diff options
| author | Vitaly Andrianov <vitalya@ti.com> | 2015-07-02 14:31:30 -0400 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2015-07-17 14:15:25 +0200 |
| commit | 3685bbce2ea6142e81c78e6f3d5b2a1cdc37660e (patch) | |
| tree | b46fda030e14ec6d6fb75ca41bbf0fd713baa46a | |
| parent | 2563606ce45314bfeae811edfa9984b1921fff06 (diff) | |
gpio/davinci: add interrupt support for GPIOs 16-31
Interrupts for GPIOs 16 through 31 are enabled by bit 1 in the
"binten" register (offset 8). Previous versions of GPIO only
used bit 0, which enables GPIO 0-15 interrupts.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| -rw-r--r-- | drivers/gpio/gpio-davinci.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c index c5e05c82d67c..86cfe1892cae 100644 --- a/drivers/gpio/gpio-davinci.c +++ b/drivers/gpio/gpio-davinci.c @@ -545,7 +545,7 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev) chips[0].chip.to_irq = gpio_to_irq_unbanked; chips[0].gpio_irq = bank_irq; chips[0].gpio_unbanked = pdata->gpio_unbanked; - binten = BIT(0); + binten = GENMASK(pdata->gpio_unbanked / 16, 0); /* AINTC handles mask/unmask; GPIO handles triggering */ irq = bank_irq; |