blob: 2cc8bbe91687415aae13549749a417810a9ede89 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
|
/*
* stmp378x: GPMI register definitions
*
* Copyright (c) 2008 Freescale Semiconductor
* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000)
#define REGS_GPMI_PHYS 0x8000C000
#define REGS_GPMI_SIZE 0x2000
#define HW_GPMI_CTRL0 0x0
#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
#define BP_GPMI_CTRL0_XFER_COUNT 0
#define BM_GPMI_CTRL0_CS 0x00300000
#define BP_GPMI_CTRL0_CS 20
#define BM_GPMI_CTRL0_LOCK_CS 0x00400000
#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
#define BM_GPMI_CTRL0_ADDRESS 0x000E0000
#define BP_GPMI_CTRL0_ADDRESS 17
#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1
#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2
#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000
#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
#define BP_GPMI_CTRL0_COMMAND_MODE 24
#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
#define BM_GPMI_CTRL0_RUN 0x20000000
#define BM_GPMI_CTRL0_CLKGATE 0x40000000
#define BM_GPMI_CTRL0_SFTRST 0x80000000
#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF
#define BP_GPMI_ECCCTRL_BUFFER_MASK 0
#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
#define BP_GPMI_ECCCTRL_ECC_CMD 13
#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0
#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 1
#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 2
#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 3
#define HW_GPMI_CTRL1 0x60
#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001
#define BP_GPMI_CTRL1_GPMI_MODE 0
#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000
#define BP_GPMI_CTRL1_RDN_DELAY 12
#define BM_GPMI_CTRL1_BCH_MODE 0x00040000
#define HW_GPMI_TIMING0 0x70
#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
#define BP_GPMI_TIMING0_DATA_SETUP 0
#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
#define BP_GPMI_TIMING0_DATA_HOLD 8
#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000
#define BP_GPMI_TIMING0_ADDRESS_SETUP 16
#define HW_GPMI_TIMING1 0x80
#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
|
