diff options
| author | Adam Thomson <Adam.Thomson.Opensource@diasemi.com> | 2016-05-10 16:11:08 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2016-05-10 19:24:19 +0100 |
| commit | abc189eadf6c12e60f95030e9c84083175526eaf (patch) | |
| tree | b20db0e344e6dbcfc06aae58e6ab6fe7014be458 /sound | |
| parent | 1e62c52ddc2d23a02ac2308cc1bb6ff18f0cf3cd (diff) | |
ASoC: da7213: Allow PLL disable/bypass when using 32KHz sysclk
Current checking for PLL 32KHz mode fails in driver code when
bypassing the PLL. This is due to an incorrect check of PLL
source type when 32KHz clock is provided. Removal of this check
resolves the issue.
Signed-off-by: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound')
| -rw-r--r-- | sound/soc/codecs/da7213.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sound/soc/codecs/da7213.c b/sound/soc/codecs/da7213.c index a233fe7f12eb..e5527bc570ae 100644 --- a/sound/soc/codecs/da7213.c +++ b/sound/soc/codecs/da7213.c @@ -1342,7 +1342,7 @@ static int da7213_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, pll_ctrl = 0; /* Workout input divider based on MCLK rate */ - if ((da7213->mclk_rate == 32768) && (source == DA7213_SYSCLK_PLL)) { + if (da7213->mclk_rate == 32768) { /* 32KHz PLL Mode */ indiv_bits = DA7213_PLL_INDIV_9_TO_18_MHZ; indiv = DA7213_PLL_INDIV_9_TO_18_MHZ_VAL; |