diff options
| author | Tony Luck <tony.luck@intel.com> | 2015-05-18 17:39:06 -0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@osg.samsung.com> | 2015-06-03 10:10:47 -0300 |
| commit | bb89e7141a4e5690a046d3bdfa57b8521aab64b0 (patch) | |
| tree | ec810474c3913f0ee0ff266c6c1da4ba0321827e /drivers/edac | |
| parent | c44696fff04ff62f65441afe9ea244b47653dd6d (diff) | |
sb_edac: Fix a typo and a thinko in address handling for Haswell
typo: "a7mode" chooses whether to use bits {8, 7, 9} or {8, 7, 6}
in the algorithm to spread access between memory resources. But
the non-a7mode path was incorrectly using GET_BITFIELD(addr, 7, 9)
and so picking bits {9, 8, 7}
thinko: BIT(1) of the dram_rule registers chooses whether to just
use the {8, 7, 6} (or {8, 7, 9}) bits mentioned above as they are,
or to XOR them with bits {18, 17, 16} but the code inverted the
test. We need the additional XOR when dram_rule{1} == 0.
Signed-off-by: Tony Luck <tony.luck@intel.com>
Acked-by: Aristeu Rozanski <aris@redhat.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
Diffstat (limited to 'drivers/edac')
| -rw-r--r-- | drivers/edac/sb_edac.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c index 1acf57ba4c86..b9648323106b 100644 --- a/drivers/edac/sb_edac.c +++ b/drivers/edac/sb_edac.c @@ -1242,9 +1242,9 @@ static int get_memory_error_data(struct mem_ctl_info *mci, bits = GET_BITFIELD(addr, 7, 8) << 1; bits |= GET_BITFIELD(addr, 9, 9); } else - bits = GET_BITFIELD(addr, 7, 9); + bits = GET_BITFIELD(addr, 6, 8); - if (interleave_mode) { + if (interleave_mode == 0) { /* interleave mode will XOR {8,7,6} with {18,17,16} */ idx = GET_BITFIELD(addr, 16, 18); idx ^= bits; |