diff options
| author | Matthias Fuchs <matthias.fuchs@esd-electronics.com> | 2007-12-07 09:23:05 +1100 |
|---|---|---|
| committer | Josh Boyer <jwboyer@linux.vnet.ibm.com> | 2008-01-08 07:58:09 -0600 |
| commit | 2af59f7d5c3e342db4bdd28c59090aee05577aef (patch) | |
| tree | 39048f450e9046bff5c76c2c97ce0c8f72c5ddba /arch/powerpc/boot/dcr.h | |
| parent | 5834584e4ea0b03c767e315a5879551b240c5652 (diff) | |
[POWERPC] 4xx: Add 405GPr and 405EP support in boot wrapper
This patch adds support for 405GPr processors with optional
new mode strapping. ibm405gp_fixup_clocks() can now be used
for 405GP and 405GPr CPUs.
This is in preparation of porting the cpci405 platform support
from arch/ppc to arch/powerpc.
This patch also adds ibm405ep_fixup_clocks() to support
405EP CPUs from the boot wrapper.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch/powerpc/boot/dcr.h')
| -rw-r--r-- | arch/powerpc/boot/dcr.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h index 55655f78505a..95b9f5344016 100644 --- a/arch/powerpc/boot/dcr.h +++ b/arch/powerpc/boot/dcr.h @@ -146,7 +146,12 @@ static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, #define DCRN_CPC0_PLLMR 0xb0 #define DCRN_405_CPC0_CR0 0xb1 #define DCRN_405_CPC0_CR1 0xb2 +#define DCRN_405_CPC0_PSR 0xb4 +/* 405EP Clocking/Power Management/Chip Control regs */ +#define DCRN_CPC0_PLLMR0 0xf0 +#define DCRN_CPC0_PLLMR1 0xf4 +#define DCRN_CPC0_UCR 0xf5 /* 440GX Clock control etc */ |