diff options
| author | Olof Johansson <olof@lixom.net> | 2012-12-17 18:40:51 -0800 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2012-12-17 18:40:51 -0800 |
| commit | 1dc1d2e9485074d5f495beb7771a3ab20eb504e9 (patch) | |
| tree | 96f5e6829816c21b6b6ad243ad26bde86abb12ed /arch/arm/mach-imx/clk-imx51-imx53.c | |
| parent | a93178a13dbd35850ec8a86b023e1f8953e80dae (diff) | |
| parent | 027c0a6af42efa4f2f6034421349bd26a3ca4923 (diff) | |
Merge tag 'imx-fixes-rc' of git://git.pengutronix.de/git/imx/linux-2.6 into fixes
From Sascha Hauer:
ARM i.MX fixes for v3.8-rc
This fixes a compile failure on imx_v4_v5_defconfig and a regression
introduced with enabling the MIPI clocks on i.MX51. Also one rather
cosmetic fix for the i.MX27 dts file.
* tag 'imx-fixes-rc' of git://git.pengutronix.de/git/imx/linux-2.6:
ARM: imx: Move platform-mx2-emma to arch/arm/mach-imx/devices
ARM i.MX51 clock: Fix regression since enabling MIPI/HSP clocks
ARM: dts: mx27: Fix the AIPI bus for FEC
Diffstat (limited to 'arch/arm/mach-imx/clk-imx51-imx53.c')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx51-imx53.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index e8c0473c7568..579023f59dc1 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c @@ -319,6 +319,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, unsigned long rate_ckih1, unsigned long rate_ckih2) { int i; + u32 val; struct device_node *np; clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE); @@ -390,6 +391,21 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc, imx_print_silicon_rev("i.MX51", mx51_revision()); clk_disable_unprepare(clk[iim_gate]); + /* + * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no + * longer supported. Set to one for better power saving. + * + * The effect of not setting these bits is that MIPI clocks can't be + * enabled without the IPU clock being enabled aswell. + */ + val = readl(MXC_CCM_CCDR); + val |= 1 << 18; + writel(val, MXC_CCM_CCDR); + + val = readl(MXC_CCM_CLPCR); + val |= 1 << 23; + writel(val, MXC_CCM_CLPCR); + return 0; } |