diff options
| author | Chris Packham <chris.packham@alliedtelesis.co.nz> | 2016-10-26 12:52:42 +1300 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2016-11-07 17:19:13 +0100 |
| commit | ad0de58bfec943cca10f808d5ddbde5e9fc24d44 (patch) | |
| tree | e4c6bf5e02257d87744fff582eadc55a5eec9af8 | |
| parent | ebbd9896a692316cf52a822d78abbace454d6bc3 (diff) | |
ARM: dts: mvebu: Update comment for main PLL frequency
The actual frequency was updated in commit ae142bd99765 ("ARM: mvebu:
Fix the main PLL frequency on Armada 375, 38x and 39x SoCs") but the
comment was not updated. Update it now.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| -rw-r--r-- | arch/arm/boot/dts/armada-375.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/armada-38x.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/armada-39x.dtsi | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index cc952cf8ec30..45fa92f9cf5c 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -65,7 +65,7 @@ }; clocks { - /* 2 GHz fixed main PLL */ + /* 1 GHz fixed main PLL */ mainpll: mainpll { compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 2d7668848c5a..7450e9fea45d 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -661,7 +661,7 @@ }; clocks { - /* 2 GHz fixed main PLL */ + /* 1 GHz fixed main PLL */ mainpll: mainpll { compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi index 34cba87f9200..de171baffcf6 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -573,7 +573,7 @@ }; clocks { - /* 2 GHz fixed main PLL */ + /* 1 GHz fixed main PLL */ mainpll: mainpll { compatible = "fixed-clock"; #clock-cells = <0>; |