diff options
author | Rob Herring <robh@kernel.org> | 2017-03-21 21:03:03 -0500 |
---|---|---|
committer | Shawn Guo <shawnguo@kernel.org> | 2017-04-10 16:16:12 +0800 |
commit | 3e1b857786f0d46a92b3a4d7878767883ed90bdc (patch) | |
tree | 9d07536fb70b84a1e9e974ed61a55e7937bc0dc0 | |
parent | d6f4996e7d69845536f5a8f8eae5caa6245d8976 (diff) |
ARM: dts: imx: fix PCI bus dtc warnings
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r-- | arch/arm/boot/dts/imx6qdl.dtsi | 3 | ||||
-rw-r--r-- | arch/arm/boot/dts/imx6sx.dtsi | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 6d7bf6496117..e426faa9c243 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -197,7 +197,7 @@ arm,shared-override; }; - pcie: pcie@0x01000000 { + pcie: pcie@1ffc000 { compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; reg = <0x01ffc000 0x04000>, <0x01f00000 0x80000>; @@ -205,6 +205,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + bus-range = <0x00 0xff>; ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ num-lanes = <1>; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index f58d7f5da977..3f1416be4c36 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -1287,7 +1287,7 @@ }; }; - pcie: pcie@0x08000000 { + pcie: pcie@8ffc000 { compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; reg = <0x08ffc000 0x4000>; /* DBI */ #address-cells = <3>; @@ -1299,6 +1299,7 @@ 0x81000000 0 0 0x08f80000 0 0x00010000 /* non-prefetchable memory */ 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; + bus-range = <0x00 0xff>; num-lanes = <1>; interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>, |