summaryrefslogtreecommitdiff
path: root/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
blob: 6fdd94c8919ec2697a81c6121c72bfe419fefabd (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
// SPDX-License-Identifier: GPL-2.0-only
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/stmmac.h>
#include <linux/clk.h>

#include "stmmac_platform.h"

static const char *const mgbe_clks[] = {
	"rx-pcs", "tx", "tx-pcs", "mac-divider", "mac", "mgbe", "ptp-ref", "mac"
};

struct tegra_mgbe {
	struct device *dev;

	struct clk_bulk_data *clks;

	struct reset_control *rst_mac;
	struct reset_control *rst_pcs;

	void __iomem *hv;
	void __iomem *regs;
	void __iomem *xpcs;

	struct mii_bus *mii;
};

#define XPCS_WRAP_UPHY_RX_CONTROL 0x801c
#define XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD BIT(31)
#define XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY BIT(10)
#define XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET BIT(9)
#define XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN BIT(8)
#define XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP (BIT(7) | BIT(6))
#define XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ BIT(5)
#define XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ BIT(4)
#define XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN BIT(0)
#define XPCS_WRAP_UPHY_HW_INIT_CTRL 0x8020
#define XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN BIT(0)
#define XPCS_WRAP_UPHY_HW_INIT_CTRL_RX_EN BIT(2)
#define XPCS_WRAP_UPHY_STATUS 0x8044
#define XPCS_WRAP_UPHY_STATUS_TX_P_UP BIT(0)
#define XPCS_WRAP_IRQ_STATUS 0x8050
#define XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS BIT(6)

#define XPCS_REG_ADDR_SHIFT 10
#define XPCS_REG_ADDR_MASK 0x1fff
#define XPCS_ADDR 0x3fc

#define MGBE_WRAP_COMMON_INTR_ENABLE	0x8704
#define MAC_SBD_INTR			BIT(2)
#define MGBE_WRAP_AXI_ASID0_CTRL	0x8400
#define MGBE_SID			0x6

static int __maybe_unused tegra_mgbe_suspend(struct device *dev)
{
	struct tegra_mgbe *mgbe = get_stmmac_bsp_priv(dev);
	int err;

	err = stmmac_suspend(dev);
	if (err)
		return err;

	clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks);

	return reset_control_assert(mgbe->rst_mac);
}

static int __maybe_unused tegra_mgbe_resume(struct device *dev)
{
	struct tegra_mgbe *mgbe = get_stmmac_bsp_priv(dev);
	u32 value;
	int err;

	err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks);
	if (err < 0)
		return err;

	err = reset_control_deassert(mgbe->rst_mac);
	if (err < 0)
		return err;

	/* Enable common interrupt at wrapper level */
	writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE);

	/* Program SID */
	writel(MGBE_SID, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL);

	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS);
	if ((value & XPCS_WRAP_UPHY_STATUS_TX_P_UP) == 0) {
		value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);
		value |= XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN;
		writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);
	}

	err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL, value,
				 (value & XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN) == 0,
				 500, 500 * 2000);
	if (err < 0) {
		dev_err(mgbe->dev, "timeout waiting for TX lane to become enabled\n");
		clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks);
		return err;
	}

	err = stmmac_resume(dev);
	if (err < 0)
		clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks);

	return err;
}

static int mgbe_uphy_lane_bringup_serdes_up(struct net_device *ndev, void *mgbe_data)
{
	struct tegra_mgbe *mgbe = (struct tegra_mgbe *)mgbe_data;
	u32 value;
	int err;

	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
	value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD;
	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);

	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
	value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ;
	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);

	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
	value &= ~XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ;
	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);

	usleep_range(10, 20);  /* 50ns min delay needed as per HW design */
	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
	value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP;
	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);

	usleep_range(10, 20);  /* 500ns min delay needed as per HW design */
	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
	value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN;
	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);

	err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL, value,
				 (value & XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN) == 0,
				 1000, 1000 * 2000);
	if (err < 0) {
		dev_err(mgbe->dev, "timeout waiting for RX calibration to become enabled\n");
		return err;
	}

	usleep_range(10, 20);  /* 50ns min delay needed as per HW design */
	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
	value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN;
	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);

	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
	value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY;
	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);

	usleep_range(10, 20);  /* 50ns min delay needed as per HW design */
	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
	value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET;
	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);

	usleep_range(10, 20);  /* 50ns min delay needed as per HW design */
	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
	value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY;
	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);

	msleep(30);  /* 30ms delay needed as per HW design */
	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
	value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET;
	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);

	err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_IRQ_STATUS, value,
				 value & XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS,
				 500, 500 * 2000);
	if (err < 0) {
		dev_err(mgbe->dev, "timeout waiting for link to become ready\n");
		return err;
	}

	/* clear status */
	writel(value, mgbe->xpcs + XPCS_WRAP_IRQ_STATUS);

	return 0;
}

static void mgbe_uphy_lane_bringup_serdes_down(struct net_device *ndev, void *mgbe_data)
{
	struct tegra_mgbe *mgbe = (struct tegra_mgbe *)mgbe_data;
	u32 value;

	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
	value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_SW_OVRD;
	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);

	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
	value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN;
	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);

	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
	value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP;
	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);

	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
	value |= XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ;
	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);

	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
	value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_IDDQ;
	writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL);
}

static int tegra_mgbe_probe(struct platform_device *pdev)
{
	struct plat_stmmacenet_data *plat;
	struct stmmac_resources res;
	struct tegra_mgbe *mgbe;
	int irq, err, i;
	u32 value;

	mgbe = devm_kzalloc(&pdev->dev, sizeof(*mgbe), GFP_KERNEL);
	if (!mgbe)
		return -ENOMEM;

	mgbe->dev = &pdev->dev;

	memset(&res, 0, sizeof(res));

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	mgbe->hv = devm_platform_ioremap_resource_byname(pdev, "hypervisor");
	if (IS_ERR(mgbe->hv))
		return PTR_ERR(mgbe->hv);

	mgbe->regs = devm_platform_ioremap_resource_byname(pdev, "mac");
	if (IS_ERR(mgbe->regs))
		return PTR_ERR(mgbe->regs);

	mgbe->xpcs = devm_platform_ioremap_resource_byname(pdev, "xpcs");
	if (IS_ERR(mgbe->xpcs))
		return PTR_ERR(mgbe->xpcs);

	res.addr = mgbe->regs;
	res.irq = irq;

	mgbe->clks = devm_kcalloc(&pdev->dev, ARRAY_SIZE(mgbe_clks),
				  sizeof(*mgbe->clks), GFP_KERNEL);
	if (!mgbe->clks)
		return -ENOMEM;

	for (i = 0; i <  ARRAY_SIZE(mgbe_clks); i++)
		mgbe->clks[i].id = mgbe_clks[i];

	err = devm_clk_bulk_get(mgbe->dev, ARRAY_SIZE(mgbe_clks), mgbe->clks);
	if (err < 0)
		return err;

	err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks);
	if (err < 0)
		return err;

	/* Perform MAC reset */
	mgbe->rst_mac = devm_reset_control_get(&pdev->dev, "mac");
	if (IS_ERR(mgbe->rst_mac)) {
		err = PTR_ERR(mgbe->rst_mac);
		goto disable_clks;
	}

	err = reset_control_assert(mgbe->rst_mac);
	if (err < 0)
		goto disable_clks;

	usleep_range(2000, 4000);

	err = reset_control_deassert(mgbe->rst_mac);
	if (err < 0)
		goto disable_clks;

	/* Perform PCS reset */
	mgbe->rst_pcs = devm_reset_control_get(&pdev->dev, "pcs");
	if (IS_ERR(mgbe->rst_pcs)) {
		err = PTR_ERR(mgbe->rst_pcs);
		goto disable_clks;
	}

	err = reset_control_assert(mgbe->rst_pcs);
	if (err < 0)
		goto disable_clks;

	usleep_range(2000, 4000);

	err = reset_control_deassert(mgbe->rst_pcs);
	if (err < 0)
		goto disable_clks;

	plat = devm_stmmac_probe_config_dt(pdev, res.mac);
	if (IS_ERR(plat)) {
		err = PTR_ERR(plat);
		goto disable_clks;
	}

	plat->has_xgmac = 1;
	plat->flags |= STMMAC_FLAG_TSO_EN;
	plat->pmt = 1;
	plat->bsp_priv = mgbe;

	if (!plat->mdio_node)
		plat->mdio_node = of_get_child_by_name(pdev->dev.of_node, "mdio");

	if (!plat->mdio_bus_data) {
		plat->mdio_bus_data = devm_kzalloc(&pdev->dev, sizeof(*plat->mdio_bus_data),
						   GFP_KERNEL);
		if (!plat->mdio_bus_data) {
			err = -ENOMEM;
			goto disable_clks;
		}
	}

	plat->mdio_bus_data->needs_reset = true;

	value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS);
	if ((value & XPCS_WRAP_UPHY_STATUS_TX_P_UP) == 0) {
		value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);
		value |= XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN;
		writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL);
	}

	err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL, value,
				 (value & XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN) == 0,
				 500, 500 * 2000);
	if (err < 0) {
		dev_err(mgbe->dev, "timeout waiting for TX lane to become enabled\n");
		goto disable_clks;
	}

	plat->serdes_powerup = mgbe_uphy_lane_bringup_serdes_up;
	plat->serdes_powerdown = mgbe_uphy_lane_bringup_serdes_down;

	/* Tx FIFO Size - 128KB */
	plat->tx_fifo_size = 131072;
	/* Rx FIFO Size - 192KB */
	plat->rx_fifo_size = 196608;

	/* Enable common interrupt at wrapper level */
	writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE);

	/* Program SID */
	writel(MGBE_SID, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL);

	plat->flags |= STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP;

	err = stmmac_dvr_probe(&pdev->dev, plat, &res);
	if (err < 0)
		goto disable_clks;

	return 0;

disable_clks:
	clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks);

	return err;
}

static void tegra_mgbe_remove(struct platform_device *pdev)
{
	struct tegra_mgbe *mgbe = get_stmmac_bsp_priv(&pdev->dev);

	clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks);

	stmmac_pltfr_remove(pdev);
}

static const struct of_device_id tegra_mgbe_match[] = {
	{ .compatible = "nvidia,tegra234-mgbe", },
	{ }
};
MODULE_DEVICE_TABLE(of, tegra_mgbe_match);

static SIMPLE_DEV_PM_OPS(tegra_mgbe_pm_ops, tegra_mgbe_suspend, tegra_mgbe_resume);

static struct platform_driver tegra_mgbe_driver = {
	.probe = tegra_mgbe_probe,
	.remove_new = tegra_mgbe_remove,
	.driver = {
		.name = "tegra-mgbe",
		.pm		= &tegra_mgbe_pm_ops,
		.of_match_table = tegra_mgbe_match,
	},
};
module_platform_driver(tegra_mgbe_driver);

MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
MODULE_DESCRIPTION("NVIDIA Tegra MGBE driver");
MODULE_LICENSE("GPL");