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path: root/drivers/gpu/drm/i915/intel_pm.c
AgeCommit message (Expand)AuthorFilesLines
2014-11-20drm/i915: remove the IRQs enabled WARN from intel_disable_gt_powersaveImre Deak1-3/+0
2014-11-20drm/i915: vlv: increase timeout when setting idle GPU freqImre Deak1-1/+1
2014-11-20drm/i915: Update ring freq for full gpu freq rangeTom O'Rourke1-2/+2
2014-11-20drm/i915: change initial rps frequency for gen8Tom O'Rourke1-1/+2
2014-11-20drm/i915: Keep min freq above floor on HSW/BDWTom O'Rourke1-1/+2
2014-11-20drm/i915: Use efficient frequency for HSW/BDWTom O'Rourke1-14/+32
2014-11-19Merge tag 'drm-intel-fixes-2014-11-19' into drm-intel-next-queuedDaniel Vetter1-5/+0
2014-11-19drm/i915: disable rps irqs earlier during suspend/unloadImre Deak1-3/+0
2014-11-19drm/i915: sanitize rps irq disablingImre Deak1-8/+9
2014-11-19drm/i915: sanitize rps irq enablingImre Deak1-8/+11
2014-11-19drm/i915: move rps irq disable one level upImre Deak1-6/+8
2014-11-19drm/i915: Extend pcode mailbox interfaceTom O'Rourke1-2/+2
2014-11-17drm/i915: Change CHV SKU400 GPU freq divider to 10Ville Syrjälä1-1/+2
2014-11-17drm/i915: Add missing newline to 'DDR speed' debug messagesVille Syrjälä1-2/+2
2014-11-17drm/i915: Refactor vlv/chv GPU frequency divider setupVille Syrjälä1-69/+35
2014-11-17drm/i915: Improve PCBR debug informationVille Syrjälä1-2/+6
2014-11-17drm/i915: Warn if GPLL isn't used on vlv/chvVille Syrjälä1-0/+6
2014-11-17drm/i915: Add a name for the Punit GPLLENABLE bitVille Syrjälä1-2/+2
2014-11-17drm/i915: Silence valleyview_set_rps()Ville Syrjälä1-7/+1
2014-11-17drm/i915: drop WaSetupGtModeTdRowDispatch:snbDaniel Vetter1-5/+0
2014-11-14drm/i915: Let's hope future platforms will use the same WM code as SKLDamien Lespiau1-1/+1
2014-11-14drm/i915: Clear PCODE_DATA1 on SNB+Damien Lespiau1-2/+1
2014-11-14drm/i915: Read the CCK fuse register from CCKVille Syrjälä1-1/+4
2014-11-14drm/i915: move rps irq enable/disable to i915_irq.cImre Deak1-41/+0
2014-11-14drm/i915: unify gen6/gen8 rps irq enable/disableImre Deak1-38/+15
2014-11-14drm/i915: unify gen6/gen8 pm irq helpersImre Deak1-1/+1
2014-11-14drm/i915/chv: Remove pre-production workaroundsArun Siluvery1-12/+0
2014-11-07drm/i915/skl: Enable Gen9 RC6Zhe Wang1-1/+51
2014-11-07drm/i915/skl: Log the order in which we flush the pipes in the WM codeDamien Lespiau1-4/+7
2014-11-07drm/i915/skl: Flush the WM configurationDamien Lespiau1-0/+135
2014-11-07drm/i915/skl: Stage the pipe DDB allocationDamien Lespiau1-7/+7
2014-11-07drm/i915/skl: Reduce the indentation level in skl_write_wm_values()Damien Lespiau1-21/+21
2014-11-07drm/i915/skl: Correctly align skl_compute_plane_wm() argumentsDamien Lespiau1-5/+5
2014-11-07drm/i915/skl: Rework when the transition WMs are computedDamien Lespiau1-15/+31
2014-11-07drm/i915/skl: Move all the WM compute functions in one placeDamien Lespiau1-22/+22
2014-11-07drm/i915/skl: Make res_blocks/lines intermediate values 32 bitsDamien Lespiau1-16/+11
2014-11-07drm/i915/skl: Use a more descriptive parameter name in skl_compute_plane_wm()Damien Lespiau1-2/+2
2014-11-07drm/i915/skl: Make 'end' of the DDB allocation entry exclusiveDamien Lespiau1-9/+19
2014-11-07drm/i915/skl: Check the DDB state at modesetDamien Lespiau1-2/+2
2014-11-07drm/i915/skl: Read back the DDB allocation hw stateDamien Lespiau1-0/+29
2014-11-07drm/i915/skl: Store the new WM state at the very end of the updateDamien Lespiau1-2/+3
2014-11-07drm/i915/gen9: Disable WM if corresponding latency is 0Vandana Kannan1-2/+12
2014-11-07drm/i915/gen9: Add 2us read latency to WM levelVandana Kannan1-0/+16
2014-11-07drm/i915/skl: Read the pipe WM HW statePradeep Bhat1-0/+104
2014-11-07drm/i915/skl: Program the DDB allocationDamien Lespiau1-0/+9
2014-11-07drm/i915/skl: Allocate DDB portions for display planesDamien Lespiau1-0/+148
2014-11-07drm/i915/skl: SKL Watermark ComputationPradeep Bhat1-0/+422
2014-11-07drm/i915/skl: Definition of SKL WM param structs for pipe/planePradeep Bhat1-0/+8
2014-11-07drm/i915/skl: Read the Memory Latency Values for WM computationPradeep Bhat1-6/+70
2014-10-24drm/i915/chv: Use 16 and 32 for low and high drain latency precision.Rodrigo Vivi1-15/+25
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