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path: root/drivers/gpu/drm/i915/icl_dsi.c
AgeCommit message (Expand)AuthorFilesLines
2018-12-03drm/i915/icl: add pll mapping for DSIJani Nikula1-0/+25
2018-12-03drm/i915/icl: Ungate DSI clocksMadhav Chauhan1-0/+19
2018-12-03drm/i915/icl: Gate clocks for DSIMadhav Chauhan1-0/+20
2018-12-03drm/i915/icl: Configure DSI Dual link modeMadhav Chauhan1-1/+41
2018-12-03drm/i915/icl: Add DSI encoder compute config hookMadhav Chauhan1-0/+31
2018-12-03drm/i915/icl: Get HW state for DSI encoderMadhav Chauhan1-0/+59
2018-12-03drm/i915/icl: Add get config functionality for DSIVandita Kulkarni1-0/+15
2018-12-03drm/i915/icl: Allocate DSI hosts and imlement host transferMadhav Chauhan1-0/+147
2018-12-03drm/i915/icl: Fill DSI ports infoMadhav Chauhan1-0/+8
2018-12-03drm/i915/icl: Use the same pll functions for dsiVandita Kulkarni1-5/+11
2018-12-03drm/i915/icl: Allocate DSI encoder/connectorMadhav Chauhan1-8/+109
2018-11-01drm/i915/icl: Find DSI presence for ICLMadhav Chauhan1-0/+8
2018-10-31drm/i915/icl: Program HS_TX_TIMEOUT/LP_RX_TIMEOUT/TA_TIMEOUT registersMadhav Chauhan1-0/+52
2018-10-31drm/i915/icl: Disable DSI IO powerMadhav Chauhan1-0/+23
2018-10-31drm/i915/icl: Disable DSI portsMadhav Chauhan1-0/+23
2018-10-31drm/i915/icl: Disable portsync modeMadhav Chauhan1-0/+10
2018-10-31drm/i915/icl: Disable DDI functionMadhav Chauhan1-0/+8
2018-10-31drm/i915/icl: Put DSI link in ULPSMadhav Chauhan1-0/+26
2018-10-31drm/i915/icl: Power down DSI panelMadhav Chauhan1-0/+15
2018-10-31drm/i915/icl: Disable DSI transcodersMadhav Chauhan1-0/+26
2018-10-31drm/i915/icl: Turn OFF panel backlightMadhav Chauhan1-0/+12
2018-10-31drm/i915/icl: Turn ON panel backlightMadhav Chauhan1-0/+6
2018-10-31drm/i915/icl: Wait for header/payload credits releaseMadhav Chauhan1-0/+74
2018-10-31drm/i915/icl: Power on DSI panelMadhav Chauhan1-0/+7
2018-10-31drm/i915/icl: Set max return packet size for DSI panelMadhav Chauhan1-0/+33
2018-10-22drm/i915/icl: Enable DSI transcodersMadhav Chauhan1-0/+25
2018-10-22drm/i915/icl: Configure DSI transcoder timingsMadhav Chauhan1-0/+118
2018-10-22drm/i915/icl: Program TRANS_DDI_FUNC_CTL registersMadhav Chauhan1-4/+60
2018-10-22drm/i915/icl: Configure DSI transcodersMadhav Chauhan1-1/+86
2018-10-22drm/i915/icl: Get DSI transcoder for a given portMadhav Chauhan1-0/+8
2018-10-22drm/i915/icl: Program TA_TIMING_PARAM registersMadhav Chauhan1-0/+21
2018-10-22drm/i915/icl: Program DSI clock and data lane timing paramsMadhav Chauhan1-0/+18
2018-09-24drm/i915/icl: Program T_INIT_MASTER registersMadhav Chauhan1-0/+19
2018-09-24drm/i915/icl: Enable DDI BufferMadhav Chauhan1-0/+22
2018-09-24drm/i915/icl: DSI vswing programming sequenceMadhav Chauhan1-0/+120
2018-09-24drm/i915/icl: Configure lane sequencing of combo phy transmitterMadhav Chauhan1-0/+39
2018-07-06drm/i915/icl: Power down unused DSI lanesMadhav Chauhan1-0/+40
2018-07-06drm/i915/icl: Enable DSI IO powerMadhav Chauhan1-0/+23
2018-07-06drm/i915/icl: Program DSI Escape clock DividerMadhav Chauhan1-0/+64
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