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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2 daysdrm/i915/reg: convert DP_TP_CTL/DP_TP_STATUS to REG_BIT() and friendsJani Nikula1-27/+29
12 daysdrm/i915/display: make CHICKEN_TRANS() display version awareJani Nikula1-2/+3
13 daysdrm/i915/crt: Extract intel_crt_regs.hVille Syrjälä1-38/+0
13 daysdrm/i915/crt: Clean up ADPA_HOTPLUG_BITS definitionsVille Syrjälä1-1/+0
13 daysdrm/i915/crt: Use REG_BIT() & co.Ville Syrjälä1-36/+33
13 daysdrm/i915/crt: Drop the unused ADPA_DPMS bit definitionsVille Syrjälä1-5/+0
13 daysdrm/i915/psr: add LATENCY_REPORTING_REMOVED() register bit helperJani Nikula1-4/+9
2024-11-05drm/i915/xe3lpd: Update HDCP rekeying bitSuraj Kandpal1-0/+1
2024-10-31drm/i915: Implement Dbuf overlap detection feature starting from LNLStanislav Lisovskiy1-0/+2
2024-10-29drm/i915/xe3lpd: Update pmdemand programmingMatt Roper1-0/+1
2024-10-17drm/i915: Remove unused underrun irq/reporting bitsSai Teja Pottumuttu1-9/+0
2024-10-03drm/i915/irq: remove GEN8_IRQ_RESET_NDX() and GEN8_IRQ_INIT_NDX() macrosJani Nikula1-0/+8
2024-10-03drm/i915/irq: remove GEN3_IRQ_RESET() and GEN3_IRQ_INIT() macrosJani Nikula1-0/+45
2024-09-11drm/i915/reg: remove superfluous whitespaceJani Nikula1-5/+0
2024-09-11drm/i915/reg: remove unused DSI register macrosJani Nikula1-19/+0
2024-09-11drm/i915/reg: fix small register style issues here and thereJani Nikula1-10/+13
2024-09-11drm/i915/reg: fix DIP CTL register styleJani Nikula1-38/+44
2024-09-11drm/i915/reg: fix PCH transcoder timing and data/link m/n styleJani Nikula1-34/+43
2024-09-11drm/i915/reg: fix PCH transcoder timing indentationJani Nikula1-7/+7
2024-09-11drm/i915/reg: fix SKL scaler register styleJani Nikula1-33/+31
2024-09-11drm/i915/reg: fix pipe data/link m/n register styleJani Nikula1-18/+21
2024-09-11drm/i915/reg: fix pipe conf, stat etc. register styleJani Nikula1-15/+17
2024-09-11drm/i915/reg: fix g4x pipe data/link m/n register styleJani Nikula1-7/+4
2024-09-11drm/i915/reg: fix transcoder timing register styleJani Nikula1-23/+28
2024-08-29drm/i915/dsb: Hook up DSB error interruptsVille Syrjälä1-0/+4
2024-08-12drm/i915/bmg: Read display register timeoutMitul Golani1-0/+2
2024-06-19drm/i915: Enable plane/pipeDMC ATS fault interrupts on mtlVille Syrjälä1-0/+2
2024-06-19drm/i915: Enable pipeDMC fault interrupts on tgl+Ville Syrjälä1-0/+2
2024-06-19drm/i915: Nuke the intermediate pipe fault bitmasksVille Syrjälä1-18/+0
2024-06-19drm/i915: Extend GEN9_PIPE_PLANE_FLIP_DONE() to cover all universal planesVille Syrjälä1-1/+5
2024-06-19drm/i915: Sort bdw+ pipe interrupt bitsVille Syrjälä1-11/+11
2024-06-19drm/i915: Document bdw+ pipe interrupt bitsVille Syrjälä1-21/+21
2024-06-19drm/i915: Use REG_BIT() for bdw+ pipe interruptsVille Syrjälä1-27/+27
2024-06-14drm/i915: remove unused pipe/plane B register macrosJani Nikula1-21/+0
2024-06-14drm/i915: relocate some DSPCNTR reg bit definitionsJani Nikula1-2/+0
2024-06-11drm/i915: Separate VRR related register definitionsMitul Golani1-100/+0
2024-06-11drm/i915: Update indentation for VRR registers and bitsMitul Golani1-87/+87
2024-06-07drm/i915: pass dev_priv explicitly to HSW_STEREO_3D_CTLJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to MTL_CLKGATE_DIS_TRANSJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_SET_CONTEXT_LATENCYJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_MSA_MISCJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to TGL_DP_TP_STATUSJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to TGL_DP_TP_CTLJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTL2Jani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTLJani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_LINK_N2Jani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_LINK_M2Jani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_LINK_N1Jani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_LINK_M1Jani Nikula1-1/+1
2024-06-07drm/i915: pass dev_priv explicitly to PIPE_DATA_N2Jani Nikula1-1/+1
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-24 16:26:07 +0000