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path: root/drivers/clk/rockchip/clk.h
AgeCommit message (Expand)AuthorFilesLines
2024-08-29clk: rockchip: Add clock controller for the RK3576Elaine Zhang1-0/+53
2024-08-29clk: rockchip: Add new pll type pll_rk3588_ddrElaine Zhang1-0/+1
2024-02-27clk: rockchip: rk3588: fix CLK_NR_CLKS usageSebastian Reichel1-0/+2
2022-11-15clk: rockchip: add clock controller for the RK3588Elaine Zhang1-1/+48
2022-11-14clk: rockchip: add lookup table supportSebastian Reichel1-6/+15
2022-11-14clk: rockchip: simplify rockchip_clk_add_lookupSebastian Reichel1-2/+0
2022-11-14clk: rockchip: allow additional mux options for cpu-clock frequency changesElaine Zhang1-0/+2
2022-11-14clk: rockchip: add pll type for RK3588Elaine Zhang1-0/+18
2022-11-14clk: rockchip: add register offset of the cores select parentElaine Zhang1-0/+3
2022-09-23clk: rockchip: Add clock controller support for RV1126 SoCJagan Teki1-0/+19
2022-09-13clk: rockchip: Add MUXTBL variantElaine Zhang1-0/+17
2021-05-11clk: rockchip: Optimize PLL table memory usageElaine Zhang1-11/+18
2021-03-21clk: rockchip: add clock controller for rk3568Elaine Zhang1-1/+29
2021-03-21clk: rockchip: support more core div settingElaine Zhang1-11/+13
2019-09-05clk: rockchip: Add clock controller for the rk3308Finley Xiao1-0/+13
2019-07-17Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds1-0/+4
2019-06-14clk: rockchip: add a type from SGRF-controlled gate clocksHeiko Stuebner1-0/+4
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157Thomas Gleixner1-10/+1
2019-04-12clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-typeFinley Xiao1-0/+23
2018-07-06clk: rockchip: add clock controller for px30Elaine Zhang1-1/+40
2018-07-06clk: rockchip: add support for half dividerElaine Zhang1-0/+85
2017-03-22clk: rockchip: rename RK1108 to RV1108Andy Yan1-14/+14
2017-01-05clk: rockchip: add clock controller for rk3328Elaine Zhang1-0/+18
2017-01-02clk: rockchip: add new pll-type for rk3328Elaine Zhang1-0/+1
2017-01-02clk: rockchip: add a clock-type for muxes based in the grfHeiko Stuebner1-0/+21
2016-11-16clk: rockchip: add clock controller for rk1108Shawn Lin1-0/+15
2016-09-01clk: rockchip: add new clock-type for the ddrclkLin Huang1-0/+33
2016-08-08clk: rockchip: use general clock flag when registering pllHeiko Stübner1-1/+1
2016-05-09clk: rockchip: simplify GRF handling in pll clocksHeiko Stuebner1-1/+0
2016-04-20clk: rockchip: fix checkpatch warning in core codeHeiko Stuebner1-1/+1
2016-04-19clk: rockchip: drop unnecessary header commentHeiko Stuebner1-1/+0
2016-03-28clk: rockchip: add clock controller for the RK3399Xing Zheng1-1/+21
2016-03-27clk: rockchip: fix warning reported by kernel-docShawn Lin1-4/+5
2016-03-27clk: rockchip: remove mux_core_reg from rockchip_cpuclk_reg_dataShawn Lin1-1/+0
2016-03-27clk: rockchip: add new pll-type for rk3399 and similar socsXing Zheng1-1/+2
2016-03-27clk: rockchip: Add support for multiple clock providersXing Zheng1-13/+38
2016-03-27clk: rockchip: allow varying mux parameters for cpuclk pll-sourcesXing Zheng1-0/+6
2016-03-27clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE typeXing Zheng1-0/+16
2016-02-04clk: rockchip: add a factor clock typeHeiko Stuebner1-0/+28
2016-01-02Merge branch 'clk-rockchip' into clk-nextMichael Turquette1-1/+1
2016-01-02clk: rockchip: fix section mismatches with new child-clocksHeiko Stübner1-1/+1
2015-12-23Merge branch 'clk-rockchip' into clk-nextMichael Turquette1-0/+19
2015-12-23clk: rockchip: handle mux dependency of fractional dividersHeiko Stuebner1-0/+19
2015-12-21clk: rockchip: only enter pll slow-mode directly before reboots on rk3288Heiko Stuebner1-1/+1
2015-12-12clk: rockchip: add clock controller for rk3228Jeffy Chen1-1/+10
2015-11-23clk: rockchip: add clock controller for rk3036Xing Zheng1-1/+8
2015-11-23clk: rockchip: add new pll-type for rk3036 and similar socsXing Zheng1-0/+23
2015-07-28clk: rockchip: Fix PLL bandwidthDouglas Anderson1-4/+4
2015-07-28Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd1-2/+2
2015-07-20clk: rockchip: Properly include clk.hStephen Boyd1-2/+2