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2018-06-16Merge tag 'riscv-for-linus-4.18-merge_window' of git://git.kernel.org/pub/scm...Linus Torvalds15-14/+626
2018-06-12Merge tag 'mips_4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/l...Linus Torvalds1-3/+3
2018-06-11RISC-V: Add CONFIG_HVC_RISCV_SBI=y to defconfigPalmer Dabbelt1-0/+1
2018-06-11RISC-V: Make our port sparse-cleanPalmer Dabbelt6-9/+14
2018-06-11RISC-V: Handle R_RISCV_32 in modulesAndreas Schwab1-0/+12
2018-06-11riscv/ftrace: Export _mcount when DYNAMIC_FTRACE isn't setAlan Kao1-1/+1
2018-06-11riscv: add riscv-specific predefines to CHECKFLAGSLuc Van Oostenryck1-0/+3
2018-06-09riscv: split the declaration of __copy_userLuc Van Oostenryck3-6/+11
2018-06-08Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a...Linus Torvalds1-1/+0
2018-06-07mm: introduce ARCH_HAS_PTE_SPECIALLaurent Dufour2-3/+1
2018-06-07riscv: no __user for probe_kernel_address()Luc Van Oostenryck1-1/+1
2018-06-07riscv: use NULL instead of a plain 0Luc Van Oostenryck2-2/+2
2018-06-04Merge branch 'siginfo-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...Linus Torvalds1-14/+2
2018-06-04RISC-V: Preliminary Perf SupportPalmer Dabbelt5-0/+586
2018-06-04perf: riscv: preliminary RISC-V supportAlan Kao5-0/+586
2018-06-04riscv: Fix the bug in memory access fixup codeAlan Kao1-4/+9
2018-05-19riscv: add swiotlb supportChristoph Hellwig3-0/+18
2018-05-19riscv: only enable ZONE_DMA32 for 64-bitChristoph Hellwig1-1/+1
2018-05-19riscv: simplify Kconfig magic for 32-bit vs 64-bit kernelsChristoph Hellwig1-25/+6
2018-05-17drivers: base: cacheinfo: setup DT cache properties earlyJeremy Linton1-1/+0
2018-05-09arch: define the ARCH_DMA_ADDR_T_64BIT config symbol in lib/KconfigChristoph Hellwig1-3/+0
2018-05-09arch: remove the ARCH_PHYS_ADDR_T_64BIT config symbolChristoph Hellwig1-4/+2
2018-05-08dma-debug: remove CONFIG_HAVE_DMA_API_DEBUGChristoph Hellwig1-1/+0
2018-05-07PCI: remove PCI_DMA_BUS_IS_PHYSChristoph Hellwig1-3/+0
2018-04-25signal/riscv: Replace do_trap_siginfo with force_sig_faultEric W. Biederman1-8/+2
2018-04-25signal/riscv: Use force_sig_fault where appropriateEric W. Biederman1-8/+1
2018-04-25signal: Ensure every siginfo we send has all bits initializedEric W. Biederman1-0/+1
2018-04-24RISC-V: build vdso-dummy.o with -no-pieAurelien Jarno1-1/+1
2018-04-24riscv: there is no <asm/handle_irq.h>Christoph Hellwig1-1/+0
2018-04-24riscv: select DMA_DIRECT_OPS instead of redefining itChristoph Hellwig1-3/+1
2018-04-23lib: Rename compiler intrinsic selects to GENERIC_LIB_*Matt Redfearn1-3/+3
2018-04-04Merge tag 'riscv-for-linus-4.17-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds19-255/+1598
2018-04-04Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kerne...Linus Torvalds4-17/+5
2018-04-03RISC-V: Rename CONFIG_CMDLINE_OVERRIDE to CONFIG_CMDLINE_FORCEPalmer Dabbelt1-2/+2
2018-04-02RISC-V: Fixes to module loadingPalmer Dabbelt9-6/+470
2018-04-02RISC-V: Assorted memory model fixesPalmer Dabbelt5-234/+630
2018-04-02RISC-V: Add definition of relocation typesZong Li1-0/+7
2018-04-02RISC-V: Enable module support in defconfigZong Li1-0/+2
2018-04-02RISC-V: Support SUB32 relocation type in kernel moduleZong Li1-0/+8
2018-04-02RISC-V: Support ADD32 relocation type in kernel moduleZong Li1-0/+8
2018-04-02RISC-V: Support ALIGN relocation type in kernel moduleZong Li1-0/+10
2018-04-02RISC-V: Support RVC_BRANCH/JUMP relocation type in kernel modulewqZong Li1-0/+35
2018-04-02RISC-V: Support HI20/LO12_I/LO12_S relocation type in kernel moduleZong Li1-0/+42
2018-04-02RISC-V: Support CALL relocation type in kernel moduleZong Li1-0/+22
2018-04-02RISC-V: Support GOT_HI20/CALL_PLT relocation type in kernel moduleZong Li1-10/+52
2018-04-02RISC-V: Add section of GOT.PLT for kernel moduleZong Li3-17/+45
2018-04-02RISC-V: Add sections of PLT and GOT for kernel moduleZong Li6-0/+260
2018-04-02riscv/atomic: Strengthen implementations with fencesAndrea Parri2-220/+588
2018-04-02riscv/spinlock: Strengthen implementations with fencesAndrea Parri2-14/+27
2018-04-02riscv/barrier: Define __smp_{store_release,load_acquire}Andrea Parri1-0/+15
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