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path: root/arch/riscv/kernel/entry.S
AgeCommit message (Expand)AuthorFilesLines
2024-09-15riscv: avoid Imbalance in RASJisheng Zhang1-2/+2
2024-09-15Merge patch series "Svvptc extension to remove preventive sfence.vma"Palmer Dabbelt1-0/+87
2024-09-15riscv: Stop emitting preventive sfence.vma for new vmalloc mappingsAlexandre Ghiti1-0/+87
2024-07-26riscv: enable HAVE_ARCH_STACKLEAKJisheng Zhang1-0/+4
2024-07-26riscv: Improve exception and system call latencyAnton Blanchard1-7/+10
2024-01-24riscv: blacklist assembly symbols for kprobeClément Léger1-0/+3
2024-01-16riscv: vector: allow kernel-mode Vector with preemptionAndy Chiu1-0/+8
2023-11-06riscv: kernel: Use correct SYM_DATA_*() macro for dataClément Léger1-5/+4
2023-11-06riscv: use ".L" local labels in assembly when applicableClément Léger1-3/+3
2023-11-02Merge patch series "riscv: SCS support"Palmer Dabbelt1-64/+60
2023-10-31riscv: put interrupt entries into .irqentry.textNam Cao1-0/+2
2023-10-27riscv: Use separate IRQ shadow call stacksSami Tolvanen1-0/+7
2023-10-27riscv: Implement Shadow Call StackSami Tolvanen1-0/+11
2023-10-27riscv: Move global pointer loading to a macroSami Tolvanen1-4/+2
2023-10-27riscv: Deduplicate IRQ stack switchingSami Tolvanen1-0/+30
2023-10-27riscv: VMAP_STACK overflow detection thread-safeDeepak Gupta1-60/+10
2023-06-20riscv: replace deprecated scall with ecallFangrui Song1-1/+1
2023-06-08riscv: Disable Vector Instructions for kernel itselfGuo Ren1-3/+3
2023-03-23riscv: entry: Consolidate general regs saving/restoringJisheng Zhang1-78/+3
2023-03-23riscv: entry: Consolidate ret_from_kernel_thread into ret_from_forkJisheng Zhang1-9/+3
2023-03-23riscv: entry: Convert to generic entryGuo Ren1-208/+34
2022-12-12Merge patch series "RISC-V: Align the shadow stack"Palmer Dabbelt1-0/+13
2022-12-08Merge patch "RISC-V: Fix unannoted hardirqs-on in return to userspace slow-path"Palmer Dabbelt1-13/+5
2022-12-08RISC-V: Fix unannoted hardirqs-on in return to userspace slow-pathAndrew Bresticker1-13/+5
2022-12-05riscv: stacktrace: Make walk_stackframe cross pt_regs frameGuo Ren1-1/+2
2022-11-29riscv: fix race when vmap stack overflowJisheng Zhang1-0/+13
2022-06-29context_tracking: Split user tracking KconfigFrederic Weisbecker1-3/+3
2022-06-29context_tracking: Rename context_tracking_user_enter/exit() to user_enter/exi...Frederic Weisbecker1-3/+3
2022-04-26riscv: compat: syscall: Add entry.S implementationGuo Ren1-2/+16
2022-03-25Merge tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds1-0/+4
2022-03-22RISC-V: Add support for restartable sequenceVincent Chen1-0/+4
2022-02-24riscv: fix oops caused by irqsoff latency tracerChangbin Du1-5/+5
2021-11-01Merge tag 'cpu-to-thread_info-v5.16-rc1' of git://git.kernel.org/pub/scm/linu...Linus Torvalds1-5/+0
2021-10-26irq: riscv: perform irqentry in entry codeMark Rutland1-2/+1
2021-09-30riscv: rely on core code to keep thread_info::cpu updatedArd Biesheuvel1-5/+0
2021-07-06riscv: add VMAP_STACK overflow detectionTong Tiangen1-0/+108
2021-05-06Merge tag 'riscv-for-linus-5.13-mw0' of git://git.kernel.org/pub/scm/linux/ke...Linus Torvalds1-2/+4
2021-04-26riscv: sifive: Apply errata "cip-453" patchVincent Chen1-2/+4
2021-04-15riscv: keep interrupts disabled for BREAKPOINT exceptionJisheng Zhang1-0/+3
2021-04-01riscv,entry: fix misaligned base for excp_vect_tableZihao Yu1-0/+1
2021-01-12riscv: Trace irq on only interrupt is enabledAtish Patra1-3/+3
2021-01-07riscv: Enable interrupts during syscalls with M-ModeDamien Le Moal1-0/+9
2021-01-07riscv: return -ENOSYS for syscall -1Andreas Schwab1-8/+1
2020-07-30riscv: Cleanup unnecessary define in asm-offset.cGuo Ren1-5/+1
2020-07-30riscv: Enable context trackingGreentime Hu1-1/+15
2020-07-30riscv: Enable LOCKDEP_SUPPORT & fixup TRACE_IRQFLAGS_SUPPORTGuo Ren1-1/+33
2020-06-09RISC-V: Remove do_IRQ() functionAnup Patel1-1/+3
2020-04-09Merge tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds1-82/+61
2020-03-05riscv: fix seccomp reject syscall code pathTycho Andersen1-8/+3
2020-03-03RISC-V: Inline the assembly register save/restore macrosPalmer Dabbelt1-82/+61