diff options
Diffstat (limited to 'arch/arm64/boot/dts/mediatek/mt8188.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8188.dtsi | 1124 |
1 files changed, 1107 insertions, 17 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index cd27966d2e3c..faccc7f16259 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/mailbox/mediatek,mt8188-gce.h> +#include <dt-bindings/memory/mediatek,mt8188-memory-port.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h> #include <dt-bindings/power/mediatek,mt8188-power.h> @@ -22,6 +23,37 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + dp-intf0 = &dp_intf0; + dp-intf1 = &dp_intf1; + ethdr0 = ðdr0; + gce0 = &gce0; + gce1 = &gce1; + merge1 = &merge1; + merge2 = &merge2; + merge3 = &merge3; + merge4 = &merge4; + merge5 = &merge5; + mutex0 = &mutex0; + mutex1 = &mutex1; + padding0 = &padding0; + padding1 = &padding1; + padding2 = &padding2; + padding3 = &padding3; + padding4 = &padding4; + padding5 = &padding5; + padding6 = &padding6; + padding7 = &padding7; + vdo1-rdma0 = &vdo1_rdma0; + vdo1-rdma1 = &vdo1_rdma1; + vdo1-rdma2 = &vdo1_rdma2; + vdo1-rdma3 = &vdo1_rdma3; + vdo1-rdma4 = &vdo1_rdma4; + vdo1-rdma5 = &vdo1_rdma5; + vdo1-rdma6 = &vdo1_rdma6; + vdo1-rdma7 = &vdo1_rdma7; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -41,6 +73,7 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; #cooling-cells = <2>; }; @@ -59,6 +92,7 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; #cooling-cells = <2>; }; @@ -77,6 +111,7 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; #cooling-cells = <2>; }; @@ -95,6 +130,7 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; #cooling-cells = <2>; }; @@ -113,6 +149,7 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; #cooling-cells = <2>; }; @@ -131,6 +168,7 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; #cooling-cells = <2>; }; @@ -149,6 +187,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; #cooling-cells = <2>; }; @@ -167,6 +206,7 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; #cooling-cells = <2>; }; @@ -420,6 +460,11 @@ method = "smc"; }; + sound: sound { + mediatek,platform = <&afe>; + status = "disabled"; + }; + thermal_zones: thermal-zones { cpu-little0-thermal { polling-delay = <1000>; @@ -878,8 +923,15 @@ #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; + dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; ranges; + performance: performance-controller@11bc10 { + compatible = "mediatek,cpufreq-hw"; + reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; + #performance-domain-cells = <1>; + }; + gic: interrupt-controller@c000000 { compatible = "arm,gic-v3"; #interrupt-cells = <4>; @@ -956,9 +1008,9 @@ #size-cells = <0>; #power-domain-cells = <1>; - power-domain@MT8188_POWER_DOMAIN_MFG1 { + mfg1: power-domain@MT8188_POWER_DOMAIN_MFG1 { reg = <MT8188_POWER_DOMAIN_MFG1>; - clocks = <&topckgen CLK_APMIXED_MFGPLL>, + clocks = <&apmixedsys CLK_APMIXED_MFGPLL>, <&topckgen CLK_TOP_MFG_CORE_TMP>; clock-names = "mfg", "alt"; mediatek,infracfg = <&infracfg_ao>; @@ -1061,20 +1113,22 @@ #power-domain-cells = <0>; }; - power-domain@MT8188_POWER_DOMAIN_VDEC1 { - reg = <MT8188_POWER_DOMAIN_VDEC1>; - clocks = <&vdecsys CLK_VDEC2_LARB1>; - clock-names = "ss-vdec"; - mediatek,infracfg = <&infracfg_ao>; - #power-domain-cells = <0>; - }; - power-domain@MT8188_POWER_DOMAIN_VDEC0 { reg = <MT8188_POWER_DOMAIN_VDEC0>; clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>; - clock-names = "ss-vdec"; + clock-names = "ss-vdec1-soc-l1"; mediatek,infracfg = <&infracfg_ao>; - #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_VDEC1 { + reg = <MT8188_POWER_DOMAIN_VDEC1>; + clocks = <&vdecsys CLK_VDEC2_LARB1>; + clock-names = "ss-vdec2-l1"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; }; cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE { @@ -1291,6 +1345,25 @@ clock-names = "spi", "wrap"; }; + spmi: spmi@10027000 { + compatible = "mediatek,mt8188-spmi", "mediatek,mt8195-spmi"; + reg = <0 0x10027000 0 0xe00>, <0 0x10029000 0 0x100>; + reg-names = "pmif", "spmimst"; + assigned-clocks = <&topckgen CLK_TOP_SPMI_M_MST>; + assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; + clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, + <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_M_MST>; + clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux"; + }; + + infra_iommu: iommu@10315000 { + compatible = "mediatek,mt8188-iommu-infra"; + reg = <0 0x10315000 0 0x1000>; + interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>; + #iommu-cells = <1>; + }; + gce0: mailbox@10320000 { compatible = "mediatek,mt8188-gce"; reg = <0 0x10320000 0 0x4000>; @@ -1315,6 +1388,97 @@ interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; }; + afe: audio-controller@10b10000 { + compatible = "mediatek,mt8188-afe"; + reg = <0 0x10b10000 0 0x10000>; + assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP>; + assigned-clock-parents = <&clk26m>; + clocks = <&clk26m>, + <&apmixedsys CLK_APMIXED_APLL1>, + <&apmixedsys CLK_APMIXED_APLL2>, + <&topckgen CLK_TOP_APLL12_CK_DIV0>, + <&topckgen CLK_TOP_APLL12_CK_DIV1>, + <&topckgen CLK_TOP_APLL12_CK_DIV2>, + <&topckgen CLK_TOP_APLL12_CK_DIV3>, + <&topckgen CLK_TOP_APLL12_CK_DIV9>, + <&topckgen CLK_TOP_A1SYS_HP>, + <&topckgen CLK_TOP_AUD_INTBUS>, + <&topckgen CLK_TOP_AUDIO_H>, + <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, + <&topckgen CLK_TOP_DPTX>, + <&topckgen CLK_TOP_I2SO1>, + <&topckgen CLK_TOP_I2SO2>, + <&topckgen CLK_TOP_I2SI1>, + <&topckgen CLK_TOP_I2SI2>, + <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>, + <&topckgen CLK_TOP_APLL1_D4>, + <&topckgen CLK_TOP_APLL2_D4>, + <&topckgen CLK_TOP_APLL12_CK_DIV4>, + <&topckgen CLK_TOP_A2SYS>, + <&topckgen CLK_TOP_AUD_IEC>; + clock-names = "clk26m", + "apll1", + "apll2", + "apll12_div0", + "apll12_div1", + "apll12_div2", + "apll12_div3", + "apll12_div9", + "top_a1sys_hp", + "top_aud_intbus", + "top_audio_h", + "top_audio_local_bus", + "top_dptx", + "top_i2so1", + "top_i2so2", + "top_i2si1", + "top_i2si2", + "adsp_audio_26m", + "apll1_d4", + "apll2_d4", + "apll12_div4", + "top_a2sys", + "top_aud_iec"; + interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_AUDIO>; + resets = <&watchdog MT8188_TOPRGU_AUDIO_SW_RST>; + reset-names = "audiosys"; + mediatek,infracfg = <&infracfg_ao>; + mediatek,topckgen = <&topckgen>; + status = "disabled"; + }; + + adsp: adsp@10b80000 { + compatible = "mediatek,mt8188-dsp"; + reg = <0 0x10b80000 0 0x2000>, + <0 0x10d00000 0 0x80000>, + <0 0x10b8b000 0 0x100>, + <0 0x10b8f000 0 0x1000>; + reg-names = "cfg", "sram", "sec", "bus"; + assigned-clocks = <&topckgen CLK_TOP_ADSP>; + clocks = <&topckgen CLK_TOP_ADSP>, + <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; + clock-names = "audiodsp", "adsp_bus"; + mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; + mbox-names = "rx", "tx"; + power-domains = <&spm MT8188_POWER_DOMAIN_ADSP>; + status = "disabled"; + }; + + adsp_mailbox0: mailbox@10b86100 { + compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox"; + reg = <0 0x10b86100 0 0x1000>; + interrupts = <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH 0>; + #mbox-cells = <0>; + }; + + adsp_mailbox1: mailbox@10b87100 { + compatible = "mediatek,mt8188-adsp-mbox", "mediatek,mt8186-adsp-mbox"; + reg = <0 0x10b87100 0 0x1000>; + interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH 0>; + #mbox-cells = <0>; + }; + adsp_audio26m: clock-controller@10b91100 { compatible = "mediatek,mt8188-adsp-audio26m"; reg = <0 0x10b91100 0 0x100>; @@ -1396,6 +1560,28 @@ #thermal-sensor-cells = <1>; }; + disp_pwm0: pwm@1100e000 { + compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + clocks = <&topckgen CLK_TOP_DISP_PWM0>, + <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; + clock-names = "main", "mm"; + interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; + #pwm-cells = <2>; + status = "disabled"; + }; + + disp_pwm1: pwm@1100f000 { + compatible = "mediatek,mt8188-disp-pwm", "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100f000 0 0x1000>; + clocks = <&topckgen CLK_TOP_DISP_PWM1>, + <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>; + clock-names = "main", "mm"; + interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>; + #pwm-cells = <2>; + status = "disabled"; + }; + spi1: spi@11010000 { compatible = "mediatek,mt8188-spi-ipm", "mediatek,spi-ipm"; #address-cells = <1>; @@ -1461,6 +1647,103 @@ status = "disabled"; }; + eth: ethernet@11021000 { + compatible = "mediatek,mt8188-gmac", "mediatek,mt8195-gmac", + "snps,dwmac-5.10a"; + reg = <0 0x11021000 0 0x4000>; + interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "macirq"; + clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, + <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; + clock-names = "axi", "apb", "mac_main", "ptp_ref", + "rmii_internal", "mac_cg"; + assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; + assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, + <&topckgen CLK_TOP_ETHPLL_D8>, + <&topckgen CLK_TOP_ETHPLL_D10>; + power-domains = <&spm MT8188_POWER_DOMAIN_ETHER>; + mediatek,pericfg = <&infracfg_ao>; + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,txpbl = <16>; + snps,rxpbl = <16>; + snps,clk-csr = <0>; + status = "disabled"; + + eth_mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-wrr; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x0>; + snps,weight = <0x10>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,weight = <0x11>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,weight = <0x12>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x3>; + snps,weight = <0x13>; + }; + }; + }; + xhci1: usb@11200000 { compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; reg = <0 0x11200000 0 0x1000>, @@ -1606,6 +1889,54 @@ status = "disabled"; }; + pcie: pcie@112f0000 { + compatible = "mediatek,mt8188-pcie", "mediatek,mt8192-pcie"; + reg = <0 0x112f0000 0 0x2000>; + reg-names = "pcie-mac"; + ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x4000000>; + bus-range = <0 0xff>; + device_type = "pci"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + + clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>; + clock-names = "pl_250m", "tl_26m", "tl_96m", "tl_32k", + "peri_26m", "peri_mem"; + + #interrupt-cells = <1>; + interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask = <0 0 0 7>; + + iommu-map = <0 &infra_iommu IFR_IOMMU_PORT_PCIE_0 0xffff>; + iommu-map-mask = <0>; + + phys = <&pcieport PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + + power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_MAC_P0>; + + resets = <&watchdog MT8188_TOPRGU_PCIE_SW_RST>; + reset-names = "mac"; + + status = "disabled"; + + pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + nor_flash: spi@1132c000 { compatible = "mediatek,mt8188-nor", "mediatek,mt8186-nor"; reg = <0 0x1132c000 0 0x1000>; @@ -1615,6 +1946,44 @@ clock-names = "spi", "sf", "axi"; assigned-clocks = <&topckgen CLK_TOP_SPINOR>; interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pciephy: t-phy@11c20700 { + compatible = "mediatek,mt8188-tphy", "mediatek,generic-tphy-v3"; + ranges = <0 0 0x11c20700 0x700>; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&spm MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>; + status = "disabled"; + + pcieport: pcie-phy@0 { + reg = <0 0x700>; + clocks = <&topckgen CLK_TOP_CFGREG_F_PCIE_PHY_REF>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + mipi_tx_config0: dsi-phy@11c80000 { + compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx"; + reg = <0 0x11c80000 0 0x1000>; + clocks = <&clk26m>; + clock-output-names = "mipi_tx0_pll"; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + + mipi_tx_config1: dsi-phy@11c90000 { + compatible = "mediatek,mt8188-mipi-tx", "mediatek,mt8183-mipi-tx"; + reg = <0 0x11c90000 0 0x1000>; + clocks = <&clk26m>; + clock-output-names = "mipi_tx0_pll"; + #clock-cells = <0>; + #phy-cells = <0>; status = "disabled"; }; @@ -1689,7 +2058,6 @@ <&clk26m>; clock-names = "ref", "da_ref"; #phy-cells = <1>; - status = "disabled"; }; }; @@ -1749,9 +2117,21 @@ #address-cells = <1>; #size-cells = <1>; + dp_calib_data: dp-calib@1a0 { + reg = <0x1a0 0xc>; + }; + lvts_efuse_data1: lvts1-calib@1ac { reg = <0x1ac 0x40>; }; + + socinfo-data1@7a0 { + reg = <0x7a0 0x4>; + }; + + socinfo-data2@7e0 { + reg = <0x7e0 0x4>; + }; }; gpu: gpu@13000000 { @@ -1778,12 +2158,43 @@ #clock-cells = <1>; }; - vppsys0: clock-controller@14000000 { - compatible = "mediatek,mt8188-vppsys0"; + vppsys0: syscon@14000000 { + compatible = "mediatek,mt8188-vppsys0", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; }; + vpp_smi_common: smi@14012000 { + compatible = "mediatek,mt8188-smi-common-vpp"; + reg = <0 0x14012000 0 0x1000>; + clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, + <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; + }; + + larb4: smi@14013000 { + compatible = "mediatek,mt8188-smi-larb"; + reg = <0 0x14013000 0 0x1000>; + clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, + <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; + mediatek,larb-id = <SMI_L4_ID>; + mediatek,smi = <&vpp_smi_common>; + }; + + vpp_iommu: iommu@14018000 { + compatible = "mediatek,mt8188-iommu-vpp"; + reg = <0 0x14018000 0 0x5000>; + clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; + clock-names = "bclk"; + interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS0>; + #iommu-cells = <1>; + mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb7 &larb23>; + }; + wpesys: clock-controller@14e00000 { compatible = "mediatek,mt8188-wpesys"; reg = <0 0x14e00000 0 0x1000>; @@ -1796,12 +2207,45 @@ #clock-cells = <1>; }; - vppsys1: clock-controller@14f00000 { - compatible = "mediatek,mt8188-vppsys1"; + larb7: smi@14e04000 { + compatible = "mediatek,mt8188-smi-larb"; + reg = <0 0x14e04000 0 0x1000>; + clocks = <&wpesys CLK_WPE_TOP_SMI_LARB7>, + <&wpesys CLK_WPE_TOP_SMI_LARB7>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8188_POWER_DOMAIN_WPE>; + mediatek,larb-id = <SMI_L7_ID>; + mediatek,smi = <&vpp_smi_common>; + }; + + vppsys1: syscon@14f00000 { + compatible = "mediatek,mt8188-vppsys1", "syscon"; reg = <0 0x14f00000 0 0x1000>; #clock-cells = <1>; }; + larb5: smi@14f02000 { + compatible = "mediatek,mt8188-smi-larb"; + reg = <0 0x14f02000 0 0x1000>; + clocks = <&vppsys1 CLK_VPP1_GALS5>, + <&vppsys1 CLK_VPP1_LARB5>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; + mediatek,larb-id = <SMI_L5_ID>; + mediatek,smi = <&vdo_smi_common>; + }; + + larb6: smi@14f03000 { + compatible = "mediatek,mt8188-smi-larb"; + reg = <0 0x14f03000 0 0x1000>; + clocks = <&vppsys1 CLK_VPP1_GALS6>, + <&vppsys1 CLK_VPP1_LARB6>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8188_POWER_DOMAIN_VPPSYS1>; + mediatek,larb-id = <SMI_L6_ID>; + mediatek,smi = <&vpp_smi_common>; + }; + imgsys: clock-controller@15000000 { compatible = "mediatek,mt8188-imgsys"; reg = <0 0x15000000 0 0x1000>; @@ -1880,12 +2324,92 @@ #clock-cells = <1>; }; + video_decoder: video-decoder@18000000 { + compatible = "mediatek,mt8188-vcodec-dec"; + reg = <0 0x18000000 0 0x1000>, <0 0x18004000 0 0x1000>; + ranges = <0 0 0 0x18000000 0 0x26000>; + iommus = <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>; + #address-cells = <2>; + #size-cells = <2>; + mediatek,scp = <&scp>; + + video-codec@10000 { + compatible = "mediatek,mtk-vcodec-lat"; + reg = <0 0x10000 0 0x800>; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys_soc CLK_VDEC1_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC1_SOC_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D6>; + clock-names = "sel", "vdec", "lat", "top"; + interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_VLD2_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_AVC_MV_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_PRED_RD_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_TILE_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_LAT0_WDMA_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_UFO_ENC_EXT_C>, + <&vpp_iommu M4U_PORT_L23_HW_VDEC_MC_EXT_C>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>; + }; + + video-codec@25000 { + compatible = "mediatek,mtk-vcodec-core"; + reg = <0 0x25000 0 0x1000>; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&vdecsys CLK_VDEC2_VDEC>, + <&vdecsys CLK_VDEC2_LAT>, + <&topckgen CLK_TOP_UNIVPLL_D6>; + clock-names = "sel", "vdec", "lat", "top"; + interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vdo_iommu M4U_PORT_L21_HW_VDEC_MC_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PP_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_RD_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PRED_WR_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_PPWRAP_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_TILE_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_VLD2_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_AVC_MV_EXT>, + <&vdo_iommu M4U_PORT_L21_HW_VDEC_UFO_EXT_C>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>; + }; + }; + + larb23: smi@1800d000 { + compatible = "mediatek,mt8188-smi-larb"; + reg = <0 0x1800d000 0 0x1000>; + clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>, + <&vdecsys_soc CLK_VDEC1_SOC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>; + mediatek,larb-id = <SMI_L23_ID>; + mediatek,smi = <&vpp_smi_common>; + }; + vdecsys_soc: clock-controller@1800f000 { compatible = "mediatek,mt8188-vdecsys-soc"; reg = <0 0x1800f000 0 0x1000>; #clock-cells = <1>; }; + larb21: smi@1802e000 { + compatible = "mediatek,mt8188-smi-larb"; + reg = <0 0x1802e000 0 0x1000>; + clocks = <&vdecsys CLK_VDEC2_LARB1>, + <&vdecsys CLK_VDEC2_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8188_POWER_DOMAIN_VDEC1>; + mediatek,larb-id = <SMI_L21_ID>; + mediatek,smi = <&vdo_smi_common>; + }; + vdecsys: clock-controller@1802f000 { compatible = "mediatek,mt8188-vdecsys"; reg = <0 0x1802f000 0 0x1000>; @@ -1898,14 +2422,249 @@ #clock-cells = <1>; }; + larb19: smi@1a010000 { + compatible = "mediatek,mt8188-smi-larb"; + reg = <0 0x1a010000 0 0x1000>; + clocks = <&vencsys CLK_VENC1_VENC>, + <&vencsys CLK_VENC1_VENC>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8188_POWER_DOMAIN_VENC>; + mediatek,larb-id = <SMI_L19_ID>; + mediatek,smi = <&vdo_smi_common>; + }; + + video_encoder: video-encoder@1a020000 { + compatible = "mediatek,mt8188-vcodec-enc"; + reg = <0 0x1a020000 0 0x10000>; + #address-cells = <2>; + #size-cells = <2>; + assigned-clocks = <&topckgen CLK_TOP_VENC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + clocks = <&vencsys CLK_VENC1_VENC>; + clock-names = "venc_sel"; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vdo_iommu M4U_PORT_L19_VENC_RCPU>, + <&vdo_iommu M4U_PORT_L19_VENC_REC>, + <&vdo_iommu M4U_PORT_L19_VENC_BSDMA>, + <&vdo_iommu M4U_PORT_L19_VENC_SV_COMV>, + <&vdo_iommu M4U_PORT_L19_VENC_RD_COMV>, + <&vdo_iommu M4U_PORT_L19_VENC_CUR_LUMA>, + <&vdo_iommu M4U_PORT_L19_VENC_CUR_CHROMA>, + <&vdo_iommu M4U_PORT_L19_VENC_REF_LUMA>, + <&vdo_iommu M4U_PORT_L19_VENC_REF_CHROMA>, + <&vdo_iommu M4U_PORT_L19_VENC_SUB_W_LUMA>, + <&vdo_iommu M4U_PORT_L19_VENC_SUB_R_LUMA>; + power-domains = <&spm MT8188_POWER_DOMAIN_VENC>; + mediatek,scp = <&scp>; + }; + + jpeg_encoder: jpeg-encoder@1a030000 { + compatible = "mediatek,mt8188-jpgenc", "mediatek,mtk-jpgenc"; + reg = <0 0x1a030000 0 0x10000>; + clocks = <&vencsys CLK_VENC1_JPGENC>; + clock-names = "jpgenc"; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vdo_iommu M4U_PORT_L19_JPGENC_Y_RDMA>, + <&vdo_iommu M4U_PORT_L19_JPGENC_C_RDMA>, + <&vdo_iommu M4U_PORT_L19_JPGENC_Q_TABLE>, + <&vdo_iommu M4U_PORT_L19_JPGENC_BSDMA>; + power-domains = <&spm MT8188_POWER_DOMAIN_VENC>; + }; + + jpeg_decoder: jpeg-decoder@1a040000 { + compatible = "mediatek,mt8188-jpgdec", "mediatek,mt2701-jpgdec"; + reg = <0 0x1a040000 0 0x10000>; + clocks = <&vencsys CLK_VENC1_LARB>, + <&vencsys CLK_VENC1_JPGDEC>; + clock-names = "jpgdec-smi", "jpgdec"; + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vdo_iommu M4U_PORT_L19_JPGDEC_WDMA_0>, + <&vdo_iommu M4U_PORT_L19_JPGDEC_BSDMA_0>, + <&vdo_iommu M4U_PORT_L19_JPGDEC_WDMA_1>, + <&vdo_iommu M4U_PORT_L19_JPGDEC_BSDMA_1>, + <&vdo_iommu M4U_PORT_L19_JPGDEC_HUFF_OFFSET_1>, + <&vdo_iommu M4U_PORT_L19_JPGDEC_HUFF_OFFSET_0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDEC0>; + }; + + ovl0: ovl@1c000000 { + compatible = "mediatek,mt8188-disp-ovl", "mediatek,mt8183-disp-ovl"; + reg = <0 0x1c000000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; + interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vdo_iommu M4U_PORT_L0_DISP_OVL0_RDMA0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; + }; + + rdma0: rdma@1c002000 { + compatible = "mediatek,mt8188-disp-rdma", "mediatek,mt8195-disp-rdma"; + reg = <0 0x1c002000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; + interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vdo_iommu M4U_PORT_L1_DISP_RDMA0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; + }; + + color0: color@1c003000 { + compatible = "mediatek,mt8188-disp-color", "mediatek,mt8173-disp-color"; + reg = <0 0x1c003000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; + interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; + }; + + ccorr0: ccorr@1c004000 { + compatible = "mediatek,mt8188-disp-ccorr", "mediatek,mt8192-disp-ccorr"; + reg = <0 0x1c004000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; + interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; + }; + + aal0: aal@1c005000 { + compatible = "mediatek,mt8188-disp-aal", "mediatek,mt8183-disp-aal"; + reg = <0 0x1c005000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; + interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; + }; + + gamma0: gamma@1c006000 { + compatible = "mediatek,mt8188-disp-gamma", "mediatek,mt8195-disp-gamma"; + reg = <0 0x1c006000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; + interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; + }; + + dither0: dither@1c007000 { + compatible = "mediatek,mt8188-disp-dither", "mediatek,mt8183-disp-dither"; + reg = <0 0x1c007000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; + interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; + }; + + disp_dsi0: dsi@1c008000 { + compatible = "mediatek,mt8188-dsi"; + reg = <0 0x1c008000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DSI0>, + <&vdosys0 CLK_VDO0_DSI0_DSI>, + <&mipi_tx_config0>; + clock-names = "engine", "digital", "hs"; + interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; + phys = <&mipi_tx_config0>; + phy-names = "dphy"; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + resets = <&vdosys0 MT8188_VDO0_RST_DSI0>; + status = "disabled"; + }; + + disp_dsi1: dsi@1c012000 { + compatible = "mediatek,mt8188-dsi"; + reg = <0 0x1c012000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DSI1>, + <&vdosys0 CLK_VDO0_DSI1_DSI>, + <&mipi_tx_config1>; + clock-names = "engine", "digital", "hs"; + interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; + phys = <&mipi_tx_config1>; + phy-names = "dphy"; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + resets = <&vdosys0 MT8188_VDO0_RST_DSI1>; + status = "disabled"; + }; + + dp_intf0: dp-intf@1c015000 { + compatible = "mediatek,mt8188-dp-intf"; + reg = <0 0x1c015000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, + <&vdosys0 CLK_VDO0_DP_INTF0>, + <&apmixedsys CLK_APMIXED_TVDPLL1>; + clock-names = "pixel", "engine", "pll"; + interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + status = "disabled"; + }; + + mutex0: mutex@1c016000 { + compatible = "mediatek,mt8188-disp-mutex"; + reg = <0 0x1c016000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; + interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; + }; + + postmask0: postmask@1c01a000 { + compatible = "mediatek,mt8188-disp-postmask", + "mediatek,mt8192-disp-postmask"; + reg = <0 0x1c01a000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DISP_POSTMASK0>; + interrupts = <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>; + }; + vdosys0: syscon@1c01d000 { compatible = "mediatek,mt8188-vdosys0", "syscon"; reg = <0 0x1c01d000 0 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>; }; + larb0: smi@1c022000 { + compatible = "mediatek,mt8188-smi-larb"; + reg = <0 0x1c022000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, + <&vdosys0 CLK_VDO0_SMI_LARB>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,larb-id = <SMI_L0_ID>; + mediatek,smi = <&vdo_smi_common>; + }; + + larb1: smi@1c023000 { + compatible = "mediatek,mt8188-smi-larb"; + reg = <0 0x1c023000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, + <&vdosys0 CLK_VDO0_SMI_LARB>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,larb-id = <SMI_L1_ID>; + mediatek,smi = <&vpp_smi_common>; + }; + + vdo_smi_common: smi@1c024000 { + compatible = "mediatek,mt8188-smi-common-vdo"; + reg = <0 0x1c024000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, + <&vdosys0 CLK_VDO0_SMI_GALS>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + }; + + vdo_iommu: iommu@1c028000 { + compatible = "mediatek,mt8188-iommu-vdo"; + reg = <0 0x1c028000 0 0x5000>; + clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; + clock-names = "bclk"; + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + #iommu-cells = <1>; + mediatek,larbs = <&larb0 &larb2 &larb5 &larb19 &larb21>; + }; + vdosys1: syscon@1c100000 { compatible = "mediatek,mt8188-vdosys1", "syscon"; reg = <0 0x1c100000 0 0x1000>; @@ -1914,5 +2673,336 @@ mboxes = <&gce0 1 CMDQ_THR_PRIO_4>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0 0x1000>; }; + + mutex1: mutex@1c101000 { + compatible = "mediatek,mt8188-disp-mutex"; + reg = <0 0x1c101000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>; + interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>; + mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>; + }; + + larb2: smi@1c102000 { + compatible = "mediatek,mt8188-smi-larb"; + reg = <0 0x1c102000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, + <&vdosys1 CLK_VDO1_SMI_LARB2>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,larb-id = <SMI_L2_ID>; + mediatek,smi = <&vdo_smi_common>; + }; + + larb3: smi@1c103000 { + compatible = "mediatek,mt8188-smi-larb"; + reg = <0 0x1c103000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, + <&vdosys1 CLK_VDO1_SMI_LARB3>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,larb-id = <SMI_L3_ID>; + mediatek,smi = <&vpp_smi_common>; + }; + + vdo1_rdma0: rdma@1c104000 { + compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c104000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; + interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells = <1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; + }; + + vdo1_rdma1: rdma@1c105000 { + compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c105000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>; + interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA1>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells = <1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; + }; + + vdo1_rdma2: rdma@1c106000 { + compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c106000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>; + interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA2>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells = <1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; + }; + + vdo1_rdma3: rdma@1c107000 { + compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c107000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>; + interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA3>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells = <1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; + }; + + vdo1_rdma4: rdma@1c108000 { + compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c108000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>; + interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA4>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells = <1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; + }; + + vdo1_rdma5: rdma@1c109000 { + compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c109000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>; + interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA5>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells = <1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; + }; + + vdo1_rdma6: rdma@1c10a000 { + compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c10a000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>; + interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vdo_iommu M4U_PORT_L2_MDP_RDMA6>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells = <1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; + }; + + vdo1_rdma7: rdma@1c10b000 { + compatible = "mediatek,mt8188-vdo1-rdma", "mediatek,mt8195-vdo1-rdma"; + reg = <0 0x1c10b000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>; + interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vpp_iommu M4U_PORT_L3_MDP_RDMA7>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + #dma-cells = <1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; + }; + + merge1: merge@1c10c000 { + compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; + reg = <0 0x1c10c000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>, + <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; + clock-names = "merge", "merge_async"; + interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets = <&vdosys1 MT8188_VDO1_RST_MERGE0_DL_ASYNC>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>; + mediatek,merge-mute; + }; + + merge2: merge@1c10d000 { + compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; + reg = <0 0x1c10d000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>, + <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>; + clock-names = "merge", "merge_async"; + interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets = <&vdosys1 MT8188_VDO1_RST_MERGE1_DL_ASYNC>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>; + mediatek,merge-mute; + }; + + merge3: merge@1c10e000 { + compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; + reg = <0 0x1c10e000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>, + <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>; + clock-names = "merge", "merge_async"; + interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets = <&vdosys1 MT8188_VDO1_RST_MERGE2_DL_ASYNC>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>; + mediatek,merge-mute; + }; + + merge4: merge@1c10f000 { + compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; + reg = <0 0x1c10f000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>, + <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; + clock-names = "merge", "merge_async"; + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets = <&vdosys1 MT8188_VDO1_RST_MERGE3_DL_ASYNC>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>; + mediatek,merge-mute; + }; + + merge5: merge@1c110000 { + compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; + reg = <0 0x1c110000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, + <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; + clock-names = "merge", "merge_async"; + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets = <&vdosys1 MT8188_VDO1_RST_MERGE4_DL_ASYNC>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>; + mediatek,merge-fifo-en; + }; + + dp_intf1: dp-intf@1c113000 { + compatible = "mediatek,mt8188-dp-intf"; + reg = <0 0x1c113000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_DPINTF>, + <&vdosys1 CLK_VDO1_DP_INTF0_MMCK>, + <&apmixedsys CLK_APMIXED_TVDPLL2>; + clock-names = "pixel", "engine", "pll"; + interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + status = "disabled"; + }; + + ethdr0: ethdr@1c114000 { + compatible = "mediatek,mt8188-disp-ethdr", "mediatek,mt8195-disp-ethdr"; + reg = <0 0x1c114000 0 0x1000>, + <0 0x1c115000 0 0x1000>, + <0 0x1c117000 0 0x1000>, + <0 0x1c119000 0 0x1000>, + <0 0x1c11a000 0 0x1000>, + <0 0x1c11b000 0 0x1000>, + <0 0x1c11c000 0 0x1000>; + reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds"; + + clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE>, + <&vdosys1 CLK_VDO1_26M_SLOW>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, + <&topckgen CLK_TOP_ETHDR>; + clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", + "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", + "gfx_fe0_async", "gfx_fe1_async", "vdo_be_async", "ethdr_top"; + + interrupts = <GIC_SPI 566 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&vpp_iommu M4U_PORT_L3_HDR_DS_SMI>, + <&vpp_iommu M4U_PORT_L3_HDR_ADL_SMI>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + resets = <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE0_DL_ASYNC>, + <&vdosys1 MT8188_VDO1_RST_HDR_VDO_FE1_DL_ASYNC>, + <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE0_DL_ASYNC>, + <&vdosys1 MT8188_VDO1_RST_HDR_GFX_FE1_DL_ASYNC>, + <&vdosys1 MT8188_VDO1_RST_HDR_VDO_BE_DL_ASYNC>; + + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, + <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; + }; + + padding0: padding@1c11d000 { + compatible = "mediatek,mt8188-disp-padding"; + reg = <0 0x1c11d000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_PADDING0>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xd000 0x1000>; + }; + + padding1: padding@1c11e000 { + compatible = "mediatek,mt8188-disp-padding"; + reg = <0 0x1c11e000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_PADDING1>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xe000 0x1000>; + }; + + padding2: padding@1c11f000 { + compatible = "mediatek,mt8188-disp-padding"; + reg = <0 0x1c11f000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_PADDING2>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0xf000 0x1000>; + }; + + padding3: padding@1c120000 { + compatible = "mediatek,mt8188-disp-padding"; + reg = <0 0x1c120000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_PADDING3>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x0000 0x1000>; + }; + + padding4: padding@1c121000 { + compatible = "mediatek,mt8188-disp-padding"; + reg = <0 0x1c121000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_PADDING4>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x1000 0x1000>; + }; + + padding5: padding@1c122000 { + compatible = "mediatek,mt8188-disp-padding"; + reg = <0 0x1c122000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_PADDING5>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x2000 0x1000>; + }; + + padding6: padding@1c123000 { + compatible = "mediatek,mt8188-disp-padding"; + reg = <0 0x1c123000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_PADDING6>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x3000 0x1000>; + }; + + padding7: padding@1c124000 { + compatible = "mediatek,mt8188-disp-padding"; + reg = <0 0x1c124000 0 0x1000>; + clocks = <&vdosys1 CLK_VDO1_PADDING7>; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS1>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c12XXXX 0x4000 0x1000>; + }; + + edp_tx: edp-tx@1c500000 { + compatible = "mediatek,mt8188-edp-tx"; + reg = <0 0x1c500000 0 0x8000>; + interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; + nvmem-cells = <&dp_calib_data>; + nvmem-cell-names = "dp_calibration_data"; + power-domains = <&spm MT8188_POWER_DOMAIN_EDP_TX>; + max-linkrate-mhz = <8100>; + status = "disabled"; + }; + + dp_tx: dp-tx@1c600000 { + compatible = "mediatek,mt8188-dp-tx"; + reg = <0 0x1c600000 0 0x8000>; + interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; + nvmem-cells = <&dp_calib_data>; + nvmem-cell-names = "dp_calibration_data"; + power-domains = <&spm MT8188_POWER_DOMAIN_DP_TX>; + max-linkrate-mhz = <5400>; + status = "disabled"; + }; }; }; |