diff options
Diffstat (limited to 'arch/arm/mach-at91/include')
| -rw-r--r-- | arch/arm/mach-at91/include/mach/cpu.h | 9 | ||||
| -rw-r--r-- | arch/arm/mach-at91/include/mach/sama5d4.h | 33 |
2 files changed, 42 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h index 86c71debab5b..d77572e8cb15 100644 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ b/arch/arm/mach-at91/include/mach/cpu.h @@ -86,6 +86,9 @@ enum at91_soc_type { /* SAMA5D3 */ AT91_SOC_SAMA5D3, + /* SAMA5D4 */ + AT91_SOC_SAMA5D4, + /* Unknown type */ AT91_SOC_UNKNOWN, }; @@ -211,6 +214,12 @@ static inline int at91_soc_is_detected(void) #define cpu_is_sama5d3() (0) #endif +#ifdef CONFIG_SOC_SAMA5D4 +#define cpu_is_sama5d4() (at91_soc_initdata.type == AT91_SOC_SAMA5D4) +#else +#define cpu_is_sama5d4() (0) +#endif + /* * Since this is ARM, we will never run on any AVR32 CPU. But these * definitions may reduce clutter in common drivers. diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h new file mode 100644 index 000000000000..f256a45d9854 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama5d4.h @@ -0,0 +1,33 @@ +/* + * Chip-specific header file for the SAMA5D4 family + * + * Copyright (C) 2013 Atmel Corporation, + * Nicolas Ferre <nicolas.ferre@atmel.com> + * + * Common definitions. + * Based on SAMA5D4 datasheet. + * + * Licensed under GPLv2 or later. + */ + +#ifndef SAMA5D4_H +#define SAMA5D4_H + +/* + * User Peripheral physical base addresses. + */ +#define SAMA5D4_BASE_USART3 0xfc00c000 /* (USART3 non-secure) Base Address */ +#define SAMA5D4_BASE_PMC 0xf0018000 /* (PMC) Base Address */ +#define SAMA5D4_BASE_MPDDRC 0xf0010000 /* (MPDDRC) Base Address */ +#define SAMA5D4_BASE_PIOD 0xfc068000 /* (PIOD) Base Address */ + +/* Some other peripherals */ +#define SAMA5D4_BASE_SYS2 SAMA5D4_BASE_PIOD + +/* + * Internal Memory. + */ +#define SAMA5D4_NS_SRAM_BASE 0x00210000 /* Internal SRAM base address Non-Secure */ +#define SAMA5D4_NS_SRAM_SIZE (64 * SZ_1K) /* Internal SRAM size Non-Secure part (64Kb) */ + +#endif |