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author | Valentin Schneider <valentin.schneider@arm.com> | 2020-07-30 18:03:20 +0100 |
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committer | Marc Zyngier <maz@kernel.org> | 2020-09-06 18:26:13 +0100 |
commit | 17f644e949ffb14e9c8870d99bc574066d8b685c (patch) | |
tree | 5b37279a9bf9925fd018893cd9fed4f1c2b57abe /lib/inflate.c | |
parent | cd1752d34ef33d68d82ef9dcc699b4eaa17c07fc (diff) |
irqchip/gic-v2, v3: Implement irq_chip->irq_retrigger()
While digging around IRQCHIP_EOI_IF_HANDLED and irq/resend.c, it has come
to my attention that the IRQ resend situation seems a bit precarious for
the GIC(s).
When marking an IRQ with IRQS_PENDING, handle_fasteoi_irq() will bail out
and issue an irq_eoi(). Should the IRQ in question be re-enabled,
check_irq_resend() will trigger a SW resend, which will go through the flow
handler again and issue *another* irq_eoi() on the *same* IRQ
activation. This is something the GIC spec clearly describes as a bad idea:
any EOI must match a previous ACK.
Implement irq_chip.irq_retrigger() for the GIC chips by setting the GIC
pending bit of the relevant IRQ. After being called by check_irq_resend(),
this will eventually trigger a *new* interrupt which we will handle as usual.
Signed-off-by: Valentin Schneider <valentin.schneider@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200730170321.31228-2-valentin.schneider@arm.com
Diffstat (limited to 'lib/inflate.c')
0 files changed, 0 insertions, 0 deletions