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authorJoerg Roedel <joerg.roedel@amd.com>2008-09-04 18:40:05 +0200
committerIngo Molnar <mingo@elte.hu>2008-09-19 12:59:07 +0200
commit1c65577398589bb44ab0980f9b9d30804b48a5db (patch)
tree4688c194c399de3a34769dbf5cd0bb31ab278d99 /include/asm-x86
parent2842e5bf3115193f05dc9dac20f940e7abf44c1a (diff)
AMD IOMMU: implement lazy IO/TLB flushing
The IO/TLB flushing on every unmaping operation is the most expensive part in AMD IOMMU code and not strictly necessary. It is sufficient to do the flush before any entries are reused. This is patch implements lazy IO/TLB flushing which does exactly this. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-x86')
-rw-r--r--include/asm-x86/amd_iommu_types.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-x86/amd_iommu_types.h b/include/asm-x86/amd_iommu_types.h
index dcc812067394..dcc472445ffd 100644
--- a/include/asm-x86/amd_iommu_types.h
+++ b/include/asm-x86/amd_iommu_types.h
@@ -196,6 +196,9 @@ struct dma_ops_domain {
* just calculate its address in constant time.
*/
u64 **pte_pages;
+
+ /* This will be set to true when TLB needs to be flushed */
+ bool need_flush;
};
/*