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authorDamien Le Moal <damien.lemoal@wdc.com>2020-12-13 22:50:35 +0900
committerPalmer Dabbelt <palmerdabbelt@google.com>2021-01-07 18:02:13 -0800
commit1f1496a923b6ba16679074fe77100e1b53cdb880 (patch)
tree268c82161fcf45e55a866d9e158ef748827214e0 /drivers/tty
parent11f4c2e940e2f317c9d8fb5a79702f2a4a02ff98 (diff)
riscv: Fix sifive serial driver
Setup the port uartclk in sifive_serial_probe() so that the base baud rate is correctly printed during device probe instead of always showing "0". I.e. the probe message is changed from 38000000.serial: ttySIF0 at MMIO 0x38000000 (irq = 1, base_baud = 0) is a SiFive UART v0 to the correct: 38000000.serial: ttySIF0 at MMIO 0x38000000 (irq = 1, base_baud = 115200) is a SiFive UART v0 Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'drivers/tty')
-rw-r--r--drivers/tty/serial/sifive.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/tty/serial/sifive.c b/drivers/tty/serial/sifive.c
index 1066eebe3b28..328d5a78792f 100644
--- a/drivers/tty/serial/sifive.c
+++ b/drivers/tty/serial/sifive.c
@@ -1000,6 +1000,7 @@ static int sifive_serial_probe(struct platform_device *pdev)
/* Set up clock divider */
ssp->clkin_rate = clk_get_rate(ssp->clk);
ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE;
+ ssp->port.uartclk = ssp->baud_rate * 16;
__ssp_update_div(ssp);
platform_set_drvdata(pdev, ssp);