diff options
| author | Argus Lin <argus.lin@mediatek.com> | 2020-02-16 14:17:22 +0800 |
|---|---|---|
| committer | Matthias Brugger <matthias.bgg@gmail.com> | 2020-02-17 11:07:24 +0100 |
| commit | adc4e8fcb23f75538d9a201b2acc56721c5c7559 (patch) | |
| tree | 979409d691e3190da1a8bf9ccb67a6df4d1952cf /drivers/soc/mediatek | |
| parent | 305ce1dce9d8046d44a322cb3ef5a6574cf86721 (diff) | |
soc: mediatek: pwrap: add pwrap driver for MT6779 SoCs
MT6779 is a highly integrated SoCs, it uses PMIC_MT6359 for
power management. This patch adds pwrap master driver to
access PMIC_MT6359.
Signed-off-by: Argus Lin <argus.lin@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'drivers/soc/mediatek')
| -rw-r--r-- | drivers/soc/mediatek/mtk-pmic-wrap.c | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c index c725315cf6a8..1f8189afaa21 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -497,6 +497,45 @@ static int mt6765_regs[] = { [PWRAP_DCM_DBC_PRD] = 0x1E0, }; +static int mt6779_regs[] = { + [PWRAP_MUX_SEL] = 0x0, + [PWRAP_WRAP_EN] = 0x4, + [PWRAP_DIO_EN] = 0x8, + [PWRAP_RDDMY] = 0x20, + [PWRAP_CSHEXT_WRITE] = 0x24, + [PWRAP_CSHEXT_READ] = 0x28, + [PWRAP_CSLEXT_WRITE] = 0x2C, + [PWRAP_CSLEXT_READ] = 0x30, + [PWRAP_EXT_CK_WRITE] = 0x34, + [PWRAP_STAUPD_CTRL] = 0x3C, + [PWRAP_STAUPD_GRPEN] = 0x40, + [PWRAP_EINT_STA0_ADR] = 0x44, + [PWRAP_HARB_HPRIO] = 0x68, + [PWRAP_HIPRIO_ARB_EN] = 0x6C, + [PWRAP_MAN_EN] = 0x7C, + [PWRAP_MAN_CMD] = 0x80, + [PWRAP_WACS0_EN] = 0x8C, + [PWRAP_INIT_DONE0] = 0x90, + [PWRAP_WACS1_EN] = 0x94, + [PWRAP_WACS2_EN] = 0x9C, + [PWRAP_INIT_DONE1] = 0x98, + [PWRAP_INIT_DONE2] = 0xA0, + [PWRAP_INT_EN] = 0xBC, + [PWRAP_INT_FLG_RAW] = 0xC0, + [PWRAP_INT_FLG] = 0xC4, + [PWRAP_INT_CLR] = 0xC8, + [PWRAP_INT1_EN] = 0xCC, + [PWRAP_INT1_FLG] = 0xD4, + [PWRAP_INT1_CLR] = 0xD8, + [PWRAP_TIMER_EN] = 0xF0, + [PWRAP_WDT_UNIT] = 0xF8, + [PWRAP_WDT_SRC_EN] = 0xFC, + [PWRAP_WDT_SRC_EN_1] = 0x100, + [PWRAP_WACS2_CMD] = 0xC20, + [PWRAP_WACS2_RDATA] = 0xC24, + [PWRAP_WACS2_VLDCLR] = 0xC28, +}; + static int mt6797_regs[] = { [PWRAP_MUX_SEL] = 0x0, [PWRAP_WRAP_EN] = 0x4, @@ -945,6 +984,7 @@ enum pmic_type { enum pwrap_type { PWRAP_MT2701, PWRAP_MT6765, + PWRAP_MT6779, PWRAP_MT6797, PWRAP_MT7622, PWRAP_MT8135, @@ -1377,6 +1417,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) break; case PWRAP_MT2701: case PWRAP_MT6765: + case PWRAP_MT6779: case PWRAP_MT6797: case PWRAP_MT8173: case PWRAP_MT8516: @@ -1783,6 +1824,19 @@ static const struct pmic_wrapper_type pwrap_mt6765 = { .init_soc_specific = NULL, }; +static const struct pmic_wrapper_type pwrap_mt6779 = { + .regs = mt6779_regs, + .type = PWRAP_MT6779, + .arb_en_all = 0xfbb7f, + .int_en_all = 0xfffffffe, + .int1_en_all = 0, + .spi_w = PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src = PWRAP_WDT_SRC_MASK_ALL, + .caps = 0, + .init_reg_clock = pwrap_common_init_reg_clock, + .init_soc_specific = NULL, +}; + static const struct pmic_wrapper_type pwrap_mt6797 = { .regs = mt6797_regs, .type = PWRAP_MT6797, @@ -1868,6 +1922,9 @@ static const struct of_device_id of_pwrap_match_tbl[] = { .compatible = "mediatek,mt6765-pwrap", .data = &pwrap_mt6765, }, { + .compatible = "mediatek,mt6779-pwrap", + .data = &pwrap_mt6779, + }, { .compatible = "mediatek,mt6797-pwrap", .data = &pwrap_mt6797, }, { |