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authorMartin Blumenstingl <martin.blumenstingl@googlemail.com>2018-11-22 22:40:15 +0100
committerNeil Armstrong <narmstrong@baylibre.com>2018-11-23 15:11:58 +0100
commit3cf94c94e81bcd5e41afcf039f98661e7698d4ca (patch)
treefb75d0b1662b2102b154d47dd6884bd43e8fadc6 /drivers/scsi/cxgbi
parent7fc1609b0c01fccf8ab7230d548fad74ab5a870a (diff)
clk: meson: clk-regmap: add read-only gate ops
Some of the gate clocks are described as "just in case" bits in the datasheet. Examples are the ABP, PERIPH, AXI and L2 DRAM clocks on Meson8b. The datasheet suggests that these bits are not touched. The full explanation is: "Set to 1 to manually disable the [...] clock when changing the mux selection. Typically this bit is set to 0 since the clock muxes can switch without glitches.". This adds new read-only ops for gate clocks so we can describe these clocks in our clock controller drivers while ensuring that we can't accidentally modify the registers. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20181122214017.25643-3-martin.blumenstingl@googlemail.com
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