diff options
| author | Fabien Parent <fparent@baylibre.com> | 2020-10-19 16:07:02 +0200 |
|---|---|---|
| committer | Thierry Reding <thierry.reding@gmail.com> | 2020-12-17 14:18:57 +0100 |
| commit | 0c0ead76235db0bcfaab83f04db546995449d002 (patch) | |
| tree | 610041bfb48bb73f1bdeb093d4ac4295aa96302b /drivers/pwm | |
| parent | ad5a228b9bad44e2a652e45fd9ac767d8880f480 (diff) | |
pwm: mediatek: Always use bus clock
The MediaTek PWM IP can sometimes use the 26 MHz source clock to
generate the PWM signal, but the driver currently assumes that we always
use the PWM bus clock to generate the PWM signal.
This commit modifies the PWM driver in order to force the PWM IP to
always use the bus clock as source clock.
I do not have the datasheet of all the MediaTek SoC, so I don't know if
the register to choose the source clock is present in all the SoCs or
only in subset. As a consequence I made this change optional by using a
platform data paremeter to says whether this register is supported or
not. On all the SoCs I don't have the datasheet (MT2712, MT7622, MT7623,
MT7628, MT7629) I kept the behavior to be the same as before this
change.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Diffstat (limited to 'drivers/pwm')
| -rw-r--r-- | drivers/pwm/pwm-mediatek.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index 6bc851cadb3e..ad3770bfc202 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -30,12 +30,14 @@ #define PWM45DWIDTH_FIXUP 0x30 #define PWMTHRES 0x30 #define PWM45THRES_FIXUP 0x34 +#define PWM_CK_26M_SEL 0x210 #define PWM_CLK_DIV_MAX 7 struct pwm_mediatek_of_data { unsigned int num_pwms; bool pwm45_fixup; + bool has_ck_26m_sel; }; /** @@ -132,6 +134,10 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, if (ret < 0) return ret; + /* Make sure we use the bus clock and not the 26MHz clock */ + if (pc->soc->has_ck_26m_sel) + writel(0, pc->regs + PWM_CK_26M_SEL); + /* Using resolution in picosecond gets accuracy higher */ resolution = (u64)NSEC_PER_SEC * 1000; do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm])); @@ -279,31 +285,37 @@ static int pwm_mediatek_remove(struct platform_device *pdev) static const struct pwm_mediatek_of_data mt2712_pwm_data = { .num_pwms = 8, .pwm45_fixup = false, + .has_ck_26m_sel = false, }; static const struct pwm_mediatek_of_data mt7622_pwm_data = { .num_pwms = 6, .pwm45_fixup = false, + .has_ck_26m_sel = false, }; static const struct pwm_mediatek_of_data mt7623_pwm_data = { .num_pwms = 5, .pwm45_fixup = true, + .has_ck_26m_sel = false, }; static const struct pwm_mediatek_of_data mt7628_pwm_data = { .num_pwms = 4, .pwm45_fixup = true, + .has_ck_26m_sel = false, }; static const struct pwm_mediatek_of_data mt7629_pwm_data = { .num_pwms = 1, .pwm45_fixup = false, + .has_ck_26m_sel = false, }; static const struct pwm_mediatek_of_data mt8516_pwm_data = { .num_pwms = 5, .pwm45_fixup = false, + .has_ck_26m_sel = true, }; static const struct of_device_id pwm_mediatek_of_match[] = { |