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authorBjorn Helgaas <bhelgaas@google.com>2017-02-21 14:59:14 -0600
committerBjorn Helgaas <bhelgaas@google.com>2017-02-21 14:59:14 -0600
commit656795c8873f93956a031d5db6fb08cf6168ebb0 (patch)
tree6daa542c4e59cd3900912bb109726c00f5ec11f8 /drivers/pci/host/pcie-designware.c
parent7ce7d89f48834cefece7804d38fc5d85382edf77 (diff)
parenta782b5f986c3fa1cfa7f2b57941200c6a5809242 (diff)
Merge branch 'for-linus' into pci/host-designware
* for-linus: PCI: designware: Check for iATU unroll only on platforms that use ATU
Diffstat (limited to 'drivers/pci/host/pcie-designware.c')
-rw-r--r--drivers/pci/host/pcie-designware.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index bed19994c1e9..af8f6e92e885 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -807,11 +807,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
{
u32 val;
- /* get iATU unroll support */
- pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp);
- dev_dbg(pp->dev, "iATU unroll: %s\n",
- pp->iatu_unroll_enabled ? "enabled" : "disabled");
-
/* set the number of lanes */
val = dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL);
val &= ~PORT_LINK_MODE_MASK;
@@ -882,6 +877,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
* we should not program the ATU here.
*/
if (!pp->ops->rd_other_conf) {
+ /* get iATU unroll support */
+ pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp);
+ dev_dbg(pp->dev, "iATU unroll: %s\n",
+ pp->iatu_unroll_enabled ? "enabled" : "disabled");
+
dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
PCIE_ATU_TYPE_MEM, pp->mem_base,
pp->mem_bus_addr, pp->mem_size);