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authorBen Skeggs <bskeggs@redhat.com>2022-06-01 20:47:38 +1000
committerBen Skeggs <bskeggs@redhat.com>2022-11-09 10:44:50 +1000
commit06db7fded6dec88772a65c5a39af12ba4dc2ad38 (patch)
treed00ff73679dd75931c7625880903e1b301184600 /drivers/gpu/drm/nouveau/include/nvif
parent7ac293328122075a2afc40a4089e7afc6cbc26eb (diff)
drm/nouveau/fifo: add new channel classes
Exposes a bunch of the new features that became possible as a result of the earlier commits. DRM will build on this in the future to add support for features such as SCG ("async compute") and multi-device rendering, as part of the work necessary to be able to write a half- decent vulkan driver - finally. For the moment, this just crudely ports DRM to the API changes. - channel class interfaces now the same for all HW classes - channel group class exposed (SCG) - channel runqueue selector exposed (SCG) - channel sub-device id control exposed (multi-device rendering) - channel names in logging will reflect creating process, not fd owner - explicit USERD allocation required by VOLTA_CHANNEL_GPFIFO_A and newer - drm is smarter about determining the appropriate channel class to use Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/include/nvif')
-rw-r--r--drivers/gpu/drm/nouveau/include/nvif/cl006b.h12
-rw-r--r--drivers/gpu/drm/nouveau/include/nvif/cl506e.h13
-rw-r--r--drivers/gpu/drm/nouveau/include/nvif/cl506f.h14
-rw-r--r--drivers/gpu/drm/nouveau/include/nvif/cl826e.h13
-rw-r--r--drivers/gpu/drm/nouveau/include/nvif/cl826f.h14
-rw-r--r--drivers/gpu/drm/nouveau/include/nvif/cl906f.h13
-rw-r--r--drivers/gpu/drm/nouveau/include/nvif/cla06f.h15
-rw-r--r--drivers/gpu/drm/nouveau/include/nvif/class.h28
-rw-r--r--drivers/gpu/drm/nouveau/include/nvif/clc36f.h16
-rw-r--r--drivers/gpu/drm/nouveau/include/nvif/if0020.h32
-rw-r--r--drivers/gpu/drm/nouveau/include/nvif/if0021.h16
11 files changed, 62 insertions, 124 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl006b.h b/drivers/gpu/drm/nouveau/include/nvif/cl006b.h
deleted file mode 100644
index c960c449e430..000000000000
--- a/drivers/gpu/drm/nouveau/include/nvif/cl006b.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-#ifndef __NVIF_CL006B_H__
-#define __NVIF_CL006B_H__
-
-struct nv03_channel_dma_v0 {
- __u8 version;
- __u8 chid;
- __u8 pad02[2];
- __u32 offset;
- __u64 pushbuf;
-};
-#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl506e.h b/drivers/gpu/drm/nouveau/include/nvif/cl506e.h
deleted file mode 100644
index 9df289c7a84f..000000000000
--- a/drivers/gpu/drm/nouveau/include/nvif/cl506e.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-#ifndef __NVIF_CL506E_H__
-#define __NVIF_CL506E_H__
-
-struct nv50_channel_dma_v0 {
- __u8 version;
- __u8 chid;
- __u8 pad02[6];
- __u64 vmm;
- __u64 pushbuf;
- __u64 offset;
-};
-#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl506f.h b/drivers/gpu/drm/nouveau/include/nvif/cl506f.h
deleted file mode 100644
index 327c96a994bb..000000000000
--- a/drivers/gpu/drm/nouveau/include/nvif/cl506f.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-#ifndef __NVIF_CL506F_H__
-#define __NVIF_CL506F_H__
-
-struct nv50_channel_gpfifo_v0 {
- __u8 version;
- __u8 chid;
- __u8 pad02[2];
- __u32 ilength;
- __u64 ioffset;
- __u64 pushbuf;
- __u64 vmm;
-};
-#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl826e.h b/drivers/gpu/drm/nouveau/include/nvif/cl826e.h
deleted file mode 100644
index ef3033b836f0..000000000000
--- a/drivers/gpu/drm/nouveau/include/nvif/cl826e.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-#ifndef __NVIF_CL826E_H__
-#define __NVIF_CL826E_H__
-
-struct g82_channel_dma_v0 {
- __u8 version;
- __u8 chid;
- __u8 pad02[6];
- __u64 vmm;
- __u64 pushbuf;
- __u64 offset;
-};
-#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl826f.h b/drivers/gpu/drm/nouveau/include/nvif/cl826f.h
deleted file mode 100644
index c5d5e56b04cc..000000000000
--- a/drivers/gpu/drm/nouveau/include/nvif/cl826f.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-#ifndef __NVIF_CL826F_H__
-#define __NVIF_CL826F_H__
-
-struct g82_channel_gpfifo_v0 {
- __u8 version;
- __u8 chid;
- __u8 pad02[2];
- __u32 ilength;
- __u64 ioffset;
- __u64 pushbuf;
- __u64 vmm;
-};
-#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl906f.h b/drivers/gpu/drm/nouveau/include/nvif/cl906f.h
deleted file mode 100644
index 5ccc8fd8c458..000000000000
--- a/drivers/gpu/drm/nouveau/include/nvif/cl906f.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-#ifndef __NVIF_CL906F_H__
-#define __NVIF_CL906F_H__
-
-struct fermi_channel_gpfifo_v0 {
- __u8 version;
- __u8 chid;
- __u8 pad02[2];
- __u32 ilength;
- __u64 ioffset;
- __u64 vmm;
-};
-#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/cla06f.h b/drivers/gpu/drm/nouveau/include/nvif/cla06f.h
deleted file mode 100644
index 10449accd3e8..000000000000
--- a/drivers/gpu/drm/nouveau/include/nvif/cla06f.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-#ifndef __NVIF_CLA06F_H__
-#define __NVIF_CLA06F_H__
-
-struct kepler_channel_gpfifo_a_v0 {
- __u8 version;
- __u8 priv;
- __u16 chid;
- __u32 ilength;
- __u64 ioffset;
- __u64 runlist;
- __u64 vmm;
- __u64 inst;
-};
-#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h
index e9d9f314a744..ceea074b064b 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/class.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/class.h
@@ -70,23 +70,23 @@
#define MAXWELL_FAULT_BUFFER_A /* clb069.h */ 0x0000b069
#define VOLTA_FAULT_BUFFER_A /* clb069.h */ 0x0000c369
-#define NV03_CHANNEL_DMA /* cl506b.h */ 0x0000006b
-#define NV10_CHANNEL_DMA /* cl506b.h */ 0x0000006e
-#define NV17_CHANNEL_DMA /* cl506b.h */ 0x0000176e
-#define NV40_CHANNEL_DMA /* cl506b.h */ 0x0000406e
+#define NV03_CHANNEL_DMA /* if0020.h */ 0x0000006b
+#define NV10_CHANNEL_DMA /* if0020.h */ 0x0000006e
+#define NV17_CHANNEL_DMA /* if0020.h */ 0x0000176e
+#define NV40_CHANNEL_DMA /* if0020.h */ 0x0000406e
#define KEPLER_CHANNEL_GROUP_A /* if0021.h */ 0x0000a06c
-#define NV50_CHANNEL_GPFIFO /* cl506f.h */ 0x0000506f
-#define G82_CHANNEL_GPFIFO /* cl826f.h */ 0x0000826f
-#define FERMI_CHANNEL_GPFIFO /* cl906f.h */ 0x0000906f
-#define KEPLER_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000a06f
-#define KEPLER_CHANNEL_GPFIFO_B /* cla06f.h */ 0x0000a16f
-#define MAXWELL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000b06f
-#define PASCAL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000c06f
-#define VOLTA_CHANNEL_GPFIFO_A /* clc36f.h */ 0x0000c36f
-#define TURING_CHANNEL_GPFIFO_A /* clc36f.h */ 0x0000c46f
-#define AMPERE_CHANNEL_GPFIFO_B /* clc36f.h */ 0x0000c76f
+#define NV50_CHANNEL_GPFIFO /* if0020.h */ 0x0000506f
+#define G82_CHANNEL_GPFIFO /* if0020.h */ 0x0000826f
+#define FERMI_CHANNEL_GPFIFO /* if0020.h */ 0x0000906f
+#define KEPLER_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000a06f
+#define KEPLER_CHANNEL_GPFIFO_B /* if0020.h */ 0x0000a16f
+#define MAXWELL_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000b06f
+#define PASCAL_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c06f
+#define VOLTA_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c36f
+#define TURING_CHANNEL_GPFIFO_A /* if0020.h */ 0x0000c46f
+#define AMPERE_CHANNEL_GPFIFO_B /* if0020.h */ 0x0000c76f
#define NV50_DISP /* if0010.h */ 0x00005070
#define G82_DISP /* if0010.h */ 0x00008270
diff --git a/drivers/gpu/drm/nouveau/include/nvif/clc36f.h b/drivers/gpu/drm/nouveau/include/nvif/clc36f.h
deleted file mode 100644
index cdf6708e1d9a..000000000000
--- a/drivers/gpu/drm/nouveau/include/nvif/clc36f.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-#ifndef __NVIF_CLC36F_H__
-#define __NVIF_CLC36F_H__
-
-struct volta_channel_gpfifo_a_v0 {
- __u8 version;
- __u8 priv;
- __u16 chid;
- __u32 ilength;
- __u64 ioffset;
- __u64 runlist;
- __u64 vmm;
- __u64 inst;
- __u32 token;
-};
-#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0020.h b/drivers/gpu/drm/nouveau/include/nvif/if0020.h
index 1893b8aa0abb..085e0ae8a450 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/if0020.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/if0020.h
@@ -2,6 +2,38 @@
#ifndef __NVIF_IF0020_H__
#define __NVIF_IF0020_H__
+union nvif_chan_args {
+ struct nvif_chan_v0 {
+ __u8 version;
+ __u8 namelen;
+ __u8 runlist;
+ __u8 runq;
+ __u8 priv;
+ __u8 pad05;
+ __u16 devm;
+ __u64 vmm;
+
+ __u64 ctxdma;
+ __u64 offset;
+ __u64 length;
+
+ __u64 huserd;
+ __u64 ouserd;
+
+ __u32 token;
+ __u16 chid;
+ __u8 pad3e;
+#define NVIF_CHAN_V0_INST_APER_VRAM 0
+#define NVIF_CHAN_V0_INST_APER_HOST 1
+#define NVIF_CHAN_V0_INST_APER_NCOH 2
+#define NVIF_CHAN_V0_INST_APER_INST 0xff
+ __u8 aper;
+ __u64 inst;
+
+ __u8 name[];
+ } v0;
+};
+
union nvif_chan_event_args {
struct nvif_chan_event_v0 {
__u8 version;
diff --git a/drivers/gpu/drm/nouveau/include/nvif/if0021.h b/drivers/gpu/drm/nouveau/include/nvif/if0021.h
new file mode 100644
index 000000000000..5013def90455
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvif/if0021.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: MIT */
+#ifndef __NVIF_IF0021_H__
+#define __NVIF_IF0021_H__
+
+union nvif_cgrp_args {
+ struct nvif_cgrp_v0 {
+ __u8 version;
+ __u8 namelen;
+ __u8 runlist;
+ __u8 pad03[3];
+ __u16 cgid;
+ __u64 vmm;
+ __u8 name[];
+ } v0;
+};
+#endif