diff options
| author | Peng Fan <peng.fan@nxp.com> | 2023-04-03 17:52:55 +0800 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@linaro.org> | 2023-04-09 16:48:54 +0300 |
| commit | 4435467b15b069e5a6f50ca9a9260e86b74dbc13 (patch) | |
| tree | d45728011d184bad51fb5adfbfa7404f754910ea /drivers/clk | |
| parent | cf8dccfedce848f67eaa42e8839305d028319161 (diff) | |
clk: imx: fracn-gppll: disable hardware select control
When programming PLL, should disable Hardware control select to make PLL
controlled by register, not hardware inputs through OSCPLL.
Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230403095300.3386988-3-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/imx/clk-fracn-gppll.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index ec50c41e2a4c..f6674110a88e 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -15,6 +15,7 @@ #include "clk.h" #define PLL_CTRL 0x0 +#define HW_CTRL_SEL BIT(16) #define CLKMUX_BYPASS BIT(2) #define CLKMUX_EN BIT(1) #define POWERUP_MASK BIT(0) @@ -193,6 +194,11 @@ static int clk_fracn_gppll_set_rate(struct clk_hw *hw, unsigned long drate, rate = imx_get_pll_settings(pll, drate); + /* Hardware control select disable. PLL is control by register */ + tmp = readl_relaxed(pll->base + PLL_CTRL); + tmp &= ~HW_CTRL_SEL; + writel_relaxed(tmp, pll->base + PLL_CTRL); + /* Disable output */ tmp = readl_relaxed(pll->base + PLL_CTRL); tmp &= ~CLKMUX_EN; |