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authorMark Zhang <markz@nvidia.com>2014-12-09 14:59:59 +0800
committerPeter De Schrijver <pdeschrijver@nvidia.com>2015-02-02 16:22:34 +0200
commitb270491eb9a033a1ab6c66e778c9dd3e3a4f7639 (patch)
tree4b0c4d9b987aa11332a5a2f774c0beb7c78f0a6e /drivers/clk/tegra/clk-id.h
parent08acae34e8dadaa8c3a0a432760555bba1db8bfb (diff)
clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
PLLD is the only parent for DSIA & DSIB on Tegra124 and Tegra132. Besides, BIT 30 in PLLD_MISC register controls the output of DSI clock. So this patch removes "dsia_mux" & "dsib_mux", and create a new clock "plld_dsi" to represent the DSI clock enable control. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mark Zhang <markz@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk-id.h')
-rw-r--r--drivers/clk/tegra/clk-id.h2
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index 0011d547a9f7..60738cc954cb 100644
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -64,10 +64,8 @@ enum clk_id {
tegra_clk_disp2,
tegra_clk_dp2,
tegra_clk_dpaux,
- tegra_clk_dsia,
tegra_clk_dsialp,
tegra_clk_dsia_mux,
- tegra_clk_dsib,
tegra_clk_dsiblp,
tegra_clk_dsib_mux,
tegra_clk_dtv,