diff options
| author | Alexey Brodkin <abrodkin@synopsys.com> | 2015-06-29 19:15:03 +0300 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2015-07-09 17:36:31 +0530 |
| commit | e2fc61f384c9224b55990a644bbcf68c25e20203 (patch) | |
| tree | b20c1c5382d9ac6ff3d35dc936dbe678cb44c884 /arch | |
| parent | 6b12ec177c410ef984d2b97717df77c9269eaeac (diff) | |
ARCv2: [axs103] bump CPU frequency from 75 to 90 MHZ
With up-to-date FPGA builds ARC cores are supposed to correctly operate
even with 90 MHz clock (which is a target frequency for AXS103 release).
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: arc-linux-dev@synopsys.com
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arc/boot/dts/axc003.dtsi | 2 | ||||
| -rw-r--r-- | arch/arc/boot/dts/axc003_idu.dtsi | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi index 15c8d6226c9d..1cd5e82f5dc2 100644 --- a/arch/arc/boot/dts/axc003.dtsi +++ b/arch/arc/boot/dts/axc003.dtsi @@ -12,7 +12,7 @@ / { compatible = "snps,arc"; - clock-frequency = <75000000>; + clock-frequency = <90000000>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arc/boot/dts/axc003_idu.dtsi b/arch/arc/boot/dts/axc003_idu.dtsi index 199d42820eca..2f0b33257db2 100644 --- a/arch/arc/boot/dts/axc003_idu.dtsi +++ b/arch/arc/boot/dts/axc003_idu.dtsi @@ -12,7 +12,7 @@ / { compatible = "snps,arc"; - clock-frequency = <75000000>; + clock-frequency = <90000000>; #address-cells = <1>; #size-cells = <1>; |