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authorKumar Gala <galak@kernel.crashing.org>2011-11-03 01:07:56 -0500
committerKumar Gala <galak@kernel.crashing.org>2011-11-24 02:01:37 -0600
commit532919592fcfb824aad0494f54e45a0acc83a776 (patch)
tree53054fb7bc0f472264db20c1399808e65413d00b /arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
parente7a7b329f2001da8fbc3a35735adf32e516b9f93 (diff)
powerpc/85xx: Rework MPC8572DS device tree
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Added GPIO controller node to MPC8572 SoC template * Dropping "fsl,mpc8572-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts487
1 files changed, 31 insertions, 456 deletions
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
index 3375c2ab0c32..d34d12712125 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
@@ -14,494 +14,69 @@
* option) any later version.
*/
-/dts-v1/;
+/include/ "mpc8572ds.dts"
+
/ {
model = "fsl,MPC8572DS";
compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
- #address-cells = <1>;
- #size-cells = <1>;
-
- aliases {
- ethernet0 = &enet0;
- ethernet1 = &enet1;
- serial0 = &serial0;
- pci0 = &pci0;
- pci1 = &pci1;
- };
cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
PowerPC,8572@0 {
- device_type = "cpu";
- reg = <0x0>;
- d-cache-line-size = <32>; // 32 bytes
- i-cache-line-size = <32>; // 32 bytes
- d-cache-size = <0x8000>; // L1, 32K
- i-cache-size = <0x8000>; // L1, 32K
- timebase-frequency = <0>;
- bus-frequency = <0>;
- clock-frequency = <0>;
- next-level-cache = <&L2>;
};
-
+ PowerPC,8572@1 {
+ status = "disabled";
+ };
};
- memory {
- device_type = "memory";
- reg = <0x0 0x0>; // Filled by U-Boot
+ localbus@ffe05000 {
+ status = "disabled";
};
soc8572@ffe00000 {
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "soc";
- compatible = "simple-bus";
- ranges = <0x0 0xffe00000 0x100000>;
- bus-frequency = <0>; // Filled out by uboot.
-
- ecm-law@0 {
- compatible = "fsl,ecm-law";
- reg = <0x0 0x1000>;
- fsl,num-laws = <12>;
+ serial@4600 {
+ status = "disabled";
};
-
- ecm@1000 {
- compatible = "fsl,mpc8572-ecm", "fsl,ecm";
- reg = <0x1000 0x1000>;
- interrupts = <17 2>;
- interrupt-parent = <&mpic>;
+ dma@c300 {
+ status = "disabled";
};
-
- memory-controller@2000 {
- compatible = "fsl,mpc8572-memory-controller";
- reg = <0x2000 0x1000>;
- interrupt-parent = <&mpic>;
- interrupts = <18 2>;
+ gpio-controller@f000 {
};
-
- memory-controller@6000 {
- compatible = "fsl,mpc8572-memory-controller";
- reg = <0x6000 0x1000>;
- interrupt-parent = <&mpic>;
- interrupts = <18 2>;
- };
-
- L2: l2-cache-controller@20000 {
- compatible = "fsl,mpc8572-l2-cache-controller";
- reg = <0x20000 0x1000>;
- cache-line-size = <32>; // 32 bytes
+ l2-cache-controller@20000 {
cache-size = <0x80000>; // L2, 512K
- interrupt-parent = <&mpic>;
- interrupts = <16 2>;
};
-
- i2c@3000 {
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <0>;
- compatible = "fsl-i2c";
- reg = <0x3000 0x100>;
- interrupts = <43 2>;
- interrupt-parent = <&mpic>;
- dfsrr;
+ ethernet@26000 {
+ status = "disabled";
};
-
- i2c@3100 {
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <1>;
- compatible = "fsl-i2c";
- reg = <0x3100 0x100>;
- interrupts = <43 2>;
- interrupt-parent = <&mpic>;
- dfsrr;
+ mdio@26520 {
+ status = "disabled";
};
-
- dma@21300 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
- reg = <0x21300 0x4>;
- ranges = <0x0 0x21100 0x200>;
- cell-index = <0>;
- dma-channel@0 {
- compatible = "fsl,mpc8572-dma-channel",
- "fsl,eloplus-dma-channel";
- reg = <0x0 0x80>;
- cell-index = <0>;
- interrupt-parent = <&mpic>;
- interrupts = <20 2>;
- };
- dma-channel@80 {
- compatible = "fsl,mpc8572-dma-channel",
- "fsl,eloplus-dma-channel";
- reg = <0x80 0x80>;
- cell-index = <1>;
- interrupt-parent = <&mpic>;
- interrupts = <21 2>;
- };
- dma-channel@100 {
- compatible = "fsl,mpc8572-dma-channel",
- "fsl,eloplus-dma-channel";
- reg = <0x100 0x80>;
- cell-index = <2>;
- interrupt-parent = <&mpic>;
- interrupts = <22 2>;
- };
- dma-channel@180 {
- compatible = "fsl,mpc8572-dma-channel",
- "fsl,eloplus-dma-channel";
- reg = <0x180 0x80>;
- cell-index = <3>;
- interrupt-parent = <&mpic>;
- interrupts = <23 2>;
- };
+ ethernet@27000 {
+ status = "disabled";
};
-
- enet0: ethernet@24000 {
- #address-cells = <1>;
- #size-cells = <1>;
- cell-index = <0>;
- device_type = "network";
- model = "eTSEC";
- compatible = "gianfar";
- reg = <0x24000 0x1000>;
- ranges = <0x0 0x24000 0x1000>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <29 2 30 2 34 2>;
- interrupt-parent = <&mpic>;
- phy-handle = <&phy0>;
- phy-connection-type = "rgmii-id";
-
- mdio@520 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,gianfar-mdio";
- reg = <0x520 0x20>;
-
- phy0: ethernet-phy@0 {
- interrupt-parent = <&mpic>;
- interrupts = <10 1>;
- reg = <0x0>;
- };
- phy1: ethernet-phy@1 {
- interrupt-parent = <&mpic>;
- interrupts = <10 1>;
- reg = <0x1>;
- };
- };
+ mdio@27520 {
+ status = "disabled";
};
-
- enet1: ethernet@25000 {
- cell-index = <1>;
- device_type = "network";
- model = "eTSEC";
- compatible = "gianfar";
- reg = <0x25000 0x1000>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <35 2 36 2 40 2>;
- interrupt-parent = <&mpic>;
- phy-handle = <&phy1>;
- phy-connection-type = "rgmii-id";
- };
-
- serial0: serial@4500 {
- cell-index = <0>;
- device_type = "serial";
- compatible = "ns16550";
- reg = <0x4500 0x100>;
- clock-frequency = <0>;
+ pic@40000 {
+ protected-sources = <
+ 31 32 33 37 38 39 /* enet2 enet3 */
+ 76 77 78 79 26 42 /* dma2 pci2 serial*/
+ 0xe4 0xe5 0xe6 0xe7 /* msi */
+ >;
};
msi@41600 {
- compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
- reg = <0x41600 0x80>;
msi-available-ranges = <0 0x80>;
interrupts = <
0xe0 0
0xe1 0
0xe2 0
0xe3 0>;
- interrupt-parent = <&mpic>;
- };
-
- global-utilities@e0000 { //global utilities block
- compatible = "fsl,mpc8572-guts";
- reg = <0xe0000 0x1000>;
- fsl,has-rstcr;
- };
-
- crypto@30000 {
- compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
- "fsl,sec2.1", "fsl,sec2.0";
- reg = <0x30000 0x10000>;
- interrupts = <45 2 58 2>;
- interrupt-parent = <&mpic>;
- fsl,num-channels = <4>;
- fsl,channel-fifo-len = <24>;
- fsl,exec-units-mask = <0x9fe>;
- fsl,descriptor-types-mask = <0x3ab0ebf>;
- };
-
- mpic: pic@40000 {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- reg = <0x40000 0x40000>;
- compatible = "chrp,open-pic";
- device_type = "open-pic";
- protected-sources = <
- 31 32 33 37 38 39 /* enet2 enet3 */
- 76 77 78 79 26 42 /* dma2 pci2 serial*/
- 0xe4 0xe5 0xe6 0xe7 /* msi */
- >;
};
- };
-
- pci0: pcie@ffe08000 {
- compatible = "fsl,mpc8548-pcie";
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <0xffe08000 0x1000>;
- bus-range = <0 255>;
- ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
- 0x1000000 0x0 0x0 0xffc00000 0x0 0x10000>;
- clock-frequency = <33333333>;
- interrupt-parent = <&mpic>;
- interrupts = <24 2>;
- interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
- interrupt-map = <
- /* IDSEL 0x11 func 0 - PCI slot 1 */
- 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
- 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
- 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
- 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
-
- /* IDSEL 0x11 func 1 - PCI slot 1 */
- 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
- 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
- 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
- 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
-
- /* IDSEL 0x11 func 2 - PCI slot 1 */
- 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
- 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
- 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
- 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
-
- /* IDSEL 0x11 func 3 - PCI slot 1 */
- 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
- 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
- 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
- 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
-
- /* IDSEL 0x11 func 4 - PCI slot 1 */
- 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
- 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
- 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
- 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
-
- /* IDSEL 0x11 func 5 - PCI slot 1 */
- 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
- 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
- 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
- 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
-
- /* IDSEL 0x11 func 6 - PCI slot 1 */
- 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
- 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
- 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
- 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
-
- /* IDSEL 0x11 func 7 - PCI slot 1 */
- 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
- 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
- 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
- 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
-
- /* IDSEL 0x12 func 0 - PCI slot 2 */
- 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
- 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
- 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
- 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
-
- /* IDSEL 0x12 func 1 - PCI slot 2 */
- 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
- 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
- 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
- 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
-
- /* IDSEL 0x12 func 2 - PCI slot 2 */
- 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
- 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
- 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
- 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
-
- /* IDSEL 0x12 func 3 - PCI slot 2 */
- 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
- 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
- 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
- 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
-
- /* IDSEL 0x12 func 4 - PCI slot 2 */
- 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
- 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
- 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
- 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
-
- /* IDSEL 0x12 func 5 - PCI slot 2 */
- 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
- 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
- 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
- 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
-
- /* IDSEL 0x12 func 6 - PCI slot 2 */
- 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
- 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
- 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
- 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
-
- /* IDSEL 0x12 func 7 - PCI slot 2 */
- 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
- 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
- 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
- 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
-
- // IDSEL 0x1c USB
- 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
- 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
- 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
- 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
-
- // IDSEL 0x1d Audio
- 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
-
- // IDSEL 0x1e Legacy
- 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
- 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
-
- // IDSEL 0x1f IDE/SATA
- 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
- 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
-
- >;
-
- pcie@0 {
- reg = <0x0 0x0 0x0 0x0 0x0>;
- #size-cells = <2>;
- #address-cells = <3>;
- device_type = "pci";
- ranges = <0x2000000 0x0 0x80000000
- 0x2000000 0x0 0x80000000
- 0x0 0x20000000
-
- 0x1000000 0x0 0x0
- 0x1000000 0x0 0x0
- 0x0 0x10000>;
- uli1575@0 {
- reg = <0x0 0x0 0x0 0x0 0x0>;
- #size-cells = <2>;
- #address-cells = <3>;
- ranges = <0x2000000 0x0 0x80000000
- 0x2000000 0x0 0x80000000
- 0x0 0x20000000
-
- 0x1000000 0x0 0x0
- 0x1000000 0x0 0x0
- 0x0 0x10000>;
- isa@1e {
- device_type = "isa";
- #interrupt-cells = <2>;
- #size-cells = <1>;
- #address-cells = <2>;
- reg = <0xf000 0x0 0x0 0x0 0x0>;
- ranges = <0x1 0x0 0x1000000 0x0 0x0
- 0x1000>;
- interrupt-parent = <&i8259>;
-
- i8259: interrupt-controller@20 {
- reg = <0x1 0x20 0x2
- 0x1 0xa0 0x2
- 0x1 0x4d0 0x2>;
- interrupt-controller;
- device_type = "interrupt-controller";
- #address-cells = <0>;
- #interrupt-cells = <2>;
- compatible = "chrp,iic";
- interrupts = <9 2>;
- interrupt-parent = <&mpic>;
- };
-
- i8042@60 {
- #size-cells = <0>;
- #address-cells = <1>;
- reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
- interrupts = <1 3 12 3>;
- interrupt-parent =
- <&i8259>;
-
- keyboard@0 {
- reg = <0x0>;
- compatible = "pnpPNP,303";
- };
-
- mouse@1 {
- reg = <0x1>;
- compatible = "pnpPNP,f03";
- };
- };
-
- rtc@70 {
- compatible = "pnpPNP,b00";
- reg = <0x1 0x70 0x2>;
- };
-
- gpio@400 {
- reg = <0x1 0x400 0x80>;
- };
- };
- };
+ timer@42100 {
+ status = "disabled";
};
-
};
-
- pci1: pcie@ffe09000 {
- compatible = "fsl,mpc8548-pcie";
- device_type = "pci";
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <0xffe09000 0x1000>;
- bus-range = <0 255>;
- ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
- 0x1000000 0x0 0x0 0xffc10000 0x0 0x10000>;
- clock-frequency = <33333333>;
- interrupt-parent = <&mpic>;
- interrupts = <25 2>;
- interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
- interrupt-map = <
- /* IDSEL 0x0 */
- 0000 0x0 0x0 0x1 &mpic 0x4 0x1
- 0000 0x0 0x0 0x2 &mpic 0x5 0x1
- 0000 0x0 0x0 0x3 &mpic 0x6 0x1
- 0000 0x0 0x0 0x4 &mpic 0x7 0x1
- >;
- pcie@0 {
- reg = <0x0 0x0 0x0 0x0 0x0>;
- #size-cells = <2>;
- #address-cells = <3>;
- device_type = "pci";
- ranges = <0x2000000 0x0 0xa0000000
- 0x2000000 0x0 0xa0000000
- 0x0 0x20000000
-
- 0x1000000 0x0 0x0
- 0x1000000 0x0 0x0
- 0x0 0x10000>;
- };
+ pcie@ffe0a000 {
+ status = "disabled";
};
};