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authorNĂ­colas F. R. A. Prado <nfraprado@collabora.com>2022-03-01 15:31:47 -0500
committerMatthias Brugger <matthias.bgg@gmail.com>2022-04-04 14:09:36 +0200
commit33c7874b44324fe9657d19ca01ef4ae4403a5a4b (patch)
tree84f47291f9e33f98ef8eba8abe1ae259334fd9d3 /arch/arm64/boot/dts/mediatek/mt2712e.dtsi
parent3123109284176b1532874591f7c81f3837bbdc17 (diff)
arm64: dts: mediatek: Format mediatek,larbs as an array of phandles
Commit 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas") updated the mediatek,larbs property in the mediatek,iommu.yaml dt-binding to make it clearer that the phandles passed to the property are independent, rather than subsequent arguments to the first phandle. Update the mediatek,larbs property in the arm64 Devicetrees to use the same formatting. This change doesn't impact any behavior: the compiled dtb is exactly the same. It does however fix the warnings generated by dtbs_check. Signed-off-by: NĂ­colas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220301203147.1143782-2-nfraprado@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch/arm64/boot/dts/mediatek/mt2712e.dtsi')
-rw-r--r--arch/arm64/boot/dts/mediatek/mt2712e.dtsi6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index a27b7628c5f7..86579330a8bd 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -329,8 +329,8 @@
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_M4U>;
clock-names = "bclk";
- mediatek,larbs = <&larb0 &larb1 &larb2
- &larb3 &larb6>;
+ mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
+ <&larb3>, <&larb6>;
#iommu-cells = <1>;
};
@@ -346,7 +346,7 @@
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_M4U>;
clock-names = "bclk";
- mediatek,larbs = <&larb4 &larb5 &larb7>;
+ mediatek,larbs = <&larb4>, <&larb5>, <&larb7>;
#iommu-cells = <1>;
};