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authorTero Kristo <t-kristo@ti.com>2014-10-27 08:39:23 -0700
committerTony Lindgren <tony@atomide.com>2014-10-27 08:39:23 -0700
commita8ae5afa5cb820afa251b9acfe3f0a938b6a6c0d (patch)
tree21d80ee4768a6ea8e9810d252a0b7e5167dc0362 /arch/arm/mach-omap2/cminst44xx.c
parent021b6ff05c4a17cb20d71c05e251ea7f80b1c516 (diff)
ARM: OMAP4+/AM33xx: CM: add common API for cm_wait_module_idle
Adds a generic CM driver API for waiting module to enter idle / standby. The SoC specific implementations are registered through cm_ll_data. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Tested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/cminst44xx.c')
-rw-r--r--arch/arm/mach-omap2/cminst44xx.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index c4f42de7f718..7ae1cc22eb5c 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -293,12 +293,14 @@ static int omap4_cminst_wait_module_ready(u8 part, s16 inst, u16 clkctrl_offs,
* @part: PRCM partition ID that the CM_CLKCTRL register exists in
* @inst: CM instance register offset (*_INST macro)
* @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ * @bit_shift: Bit shift for the register, ignored for OMAP4+
*
* Wait for the module IDLEST to be disabled. Some PRCM transition,
* like reset assertion or parent clock de-activation must wait the
* module to be fully disabled.
*/
-int omap4_cminst_wait_module_idle(u8 part, u16 inst, u16 clkctrl_offs)
+static int omap4_cminst_wait_module_idle(u8 part, s16 inst, u16 clkctrl_offs,
+ u8 bit_shift)
{
int i = 0;
@@ -510,6 +512,7 @@ struct clkdm_ops am43xx_clkdm_operations = {
static struct cm_ll_data omap4xxx_cm_ll_data = {
.wait_module_ready = &omap4_cminst_wait_module_ready,
+ .wait_module_idle = &omap4_cminst_wait_module_idle,
};
int __init omap4_cm_init(void)