diff options
| author | Victor Kamensky <victor.kamensky@linaro.org> | 2014-04-15 20:37:46 +0300 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2014-05-08 07:09:53 -0700 |
| commit | edfaf05c2fcb853fcf35f12aeb9c340f5913337f (patch) | |
| tree | f3d0d7ca941855237953f65680932a8a433b0ed4 /arch/arm/mach-omap2/clkt2xxx_dpllcore.c | |
| parent | 89ca3b881987f5a4be4c5dbaa7f0df12bbdde2fd (diff) | |
ARM: OMAP2+: raw read and write endian fix
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/mach-omap2/clkt2xxx_dpllcore.c')
| -rw-r--r-- | arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c index 3ff32543493c..59cf310bc1e9 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c @@ -138,7 +138,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate, if (!dd) return -EINVAL; - tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); + tmpset.cm_clksel1_pll = readl_relaxed(dd->mult_div1_reg); tmpset.cm_clksel1_pll &= ~(dd->mult_mask | dd->div1_mask); div = ((curr_prcm_set->xtal_speed / 1000000) - 1); |