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authorStephen Warren <swarren@nvidia.com>2012-11-16 10:53:04 -0700
committerStephen Warren <swarren@nvidia.com>2012-11-16 10:56:38 -0700
commit2658ef15b27e0fb166f4b7b997b027a223cd0793 (patch)
tree5708a4e8e7ba909dd8020f9ab34a08dffd14bd4b /arch/arm/boot/dts/tegra20-whistler.dts
parentcab2ed62fe378be22c9de12ff8a616622b68c70c (diff)
ARM: tegra: whistler: enable HDMI port
Enable host1x, and the HDMI output. Whistler also has a DSI-based LCD, and a VGA output. tegradrm doesn't support either of those output types yet. Based on work by Thierry Reding for TrimSlice. Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20-whistler.dts')
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts21
1 files changed, 19 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 94a71c91beb5..20d576ecd555 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -10,6 +10,18 @@
reg = <0x00000000 0x20000000>;
};
+ host1x {
+ hdmi {
+ status = "okay";
+
+ vdd-supply = <&hdmi_vdd_reg>;
+ pll-supply = <&hdmi_pll_reg>;
+
+ nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+ nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+ };
+ };
+
pinmux {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
@@ -246,6 +258,11 @@
clock-frequency = <216000000>;
};
+ hdmi_ddc: i2c@7000c400 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
i2c@7000d000 {
status = "okay";
clock-frequency = <100000>;
@@ -356,7 +373,7 @@
regulator-always-on;
};
- ldo6 {
+ hdmi_pll_reg: ldo6 {
regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@@ -388,7 +405,7 @@
regulator-always-on;
};
- ldo11 {
+ hdmi_vdd_reg: ldo11 {
regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;