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authorDmitry Osipenko <digetx@gmail.com>2021-12-01 02:23:43 +0300
committerThierry Reding <treding@nvidia.com>2021-12-16 14:23:17 +0100
commit83b7f0b8aeab4fc8271392fd32164efb7b3f55e9 (patch)
tree8f687f28265d496e117b0c3f9f3f56c4ca13af60 /arch/arm/boot/dts/tegra20-trimslice.dts
parent3478494dcae155f0580e8f841458905f4fc739c2 (diff)
ARM: tegra: Add OPP tables and power domains to Tegra20 device-trees
Add OPP tables and power domains to all peripheral devices which support power management on Tegra20 SoC. Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20-trimslice.dts')
-rw-r--r--arch/arm/boot/dts/tegra20-trimslice.dts9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 8bb0eaa610f2..9d0c86711de2 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -322,6 +322,7 @@
nvidia,core-pwr-good-time = <3845 3845>;
nvidia,core-pwr-off-time = <3875>;
nvidia,sys-clock-req-active-high;
+ core-supply = <&vdd_core>;
};
pcie@80003000 {
@@ -443,6 +444,14 @@
regulator-always-on;
};
+ vdd_core: regulator-core {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ };
+
sound {
compatible = "nvidia,tegra-audio-trimslice";
nvidia,i2s-controller = <&tegra_i2s1>;