diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2015-06-02 14:33:46 +0200 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-02-19 14:52:22 +0900 |
| commit | 8ffe93a5b2cb55d4da9c285d9277699bdb828b47 (patch) | |
| tree | 873ad3e0e94e30f402c550fe694fa41b6f22e407 /arch/arm/boot/dts/r8a7791.dtsi | |
| parent | fb1cecd40690e61e122d7249e7499c8d799feffb (diff) | |
ARM: dts: r8a7791: Add L2 cache-controller node
Add a device node for the L2 cache, and link the CPU nodes to it.
The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7791.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7791.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index f1732dde114b..6439f0569fe2 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -51,6 +51,7 @@ voltage-tolerance = <1>; /* 1% */ clocks = <&cpg_clocks R8A7791_CLK_Z>; clock-latency = <300000>; /* 300 us */ + next-level-cache = <&L2_CA15>; /* kHz - uV - OPPs unknown yet */ operating-points = <1500000 1000000>, @@ -66,6 +67,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1500000000>; + next-level-cache = <&L2_CA15>; }; }; @@ -88,6 +90,12 @@ }; }; + L2_CA15: cache-controller@0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + }; + gic: interrupt-controller@f1001000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; |