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author | Anson Huang <Anson.Huang@nxp.com> | 2020-04-21 22:21:25 +0800 |
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committer | Rob Herring <robh@kernel.org> | 2020-05-11 13:59:46 -0500 |
commit | 81e41fec803da7f22401fb4b2e7b61291dff8cf9 (patch) | |
tree | aa6895c8c86e252c3c8cb08a9b239ce2dba1769b /Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml | |
parent | 2c504460f502214a26b21c892bd3e5467a3bd754 (diff) |
dt-bindings: watchdog: Convert i.MX to json-schema
Convert the i.MX watchdog binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml new file mode 100644 index 000000000000..d96b93b11fad --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/fsl-imx-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX Watchdog Timer (WDT) Controller + +maintainers: + - Anson Huang <Anson.Huang@nxp.com> + +allOf: + - $ref: "watchdog.yaml#" + +properties: + compatible: + enum: + - fsl,imx21-wdt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + fsl,ext-reset-output: + $ref: /schemas/types.yaml#/definitions/flag + description: | + If present, the watchdog device is configured to assert its + external reset (WDOG_B) instead of issuing a software reset. + +required: + - compatible + - interrupts + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/imx6qdl-clock.h> + + watchdog@20bc000 { + compatible = "fsl,imx21-wdt"; + reg = <0x020bc000 0x4000>; + interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPG>; + }; + +... |