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authorRoger Quadros <rogerq@ti.com>2016-03-07 12:18:43 +0200
committerRoger Quadros <rogerq@ti.com>2016-04-15 11:54:12 +0300
commitd2d00862dfbbd22d80ee67f816cb7eeaea71f03b (patch)
tree163ba53823447c5231c372acb6b3be640b2cf453 /Documentation/devicetree/bindings/memory-controllers
parent3c76f6119a64eb8ff6d088ceb6ca03891e29a7ce (diff)
memory: omap-gpmc: Support general purpose input for WAITPINs
OMAPs can have 2 to 4 WAITPINs that can be used as general purpose input if not used for memory wait state insertion. The first user will be the OMAP NAND chip to get the NAND read/busy status using gpiolib. Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers')
-rw-r--r--Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt6
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt b/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
index 13f13786f992..97e71924dbbb 100644
--- a/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
@@ -38,6 +38,10 @@ Required properties:
0 - NAND_fifoevent
1 - NAND_termcount
- interrupt-cells: Must be set to 2
+ - gpio-controller: The GPMC driver implements a GPIO controller for the
+ GPMC WAIT pins that can be used as general purpose inputs.
+ 0 maps to GPMC_WAIT0 pin.
+ - gpio-cells: Must be set to 2
Timing properties for child nodes. All are optional and default to 0.
@@ -138,6 +142,8 @@ Example for an AM33xx board:
ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
interrupt-controller;
#interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
/* child nodes go here */
};