diff options
| author | Basavaraj Natikar <Basavaraj.Natikar@amd.com> | 2024-11-12 22:33:07 +0530 |
|---|---|---|
| committer | Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> | 2024-11-13 15:35:36 +0200 |
| commit | bd17863a708692bbd7a265212daf8a3aa4a3d0b7 (patch) | |
| tree | de099f05f400cf0e6668f825375cd7872fce72f4 /Documentation/ABI | |
| parent | 5a67c0d1c8bdcdba5dff49cfbf0d4c453b827a9d (diff) | |
platform/x86/amd: amd_3d_vcache: Add sysfs ABI documentation
Add documentation for the amd_3d_vcache sysfs bus platform driver
interface so that userspace applications can use it to change mode
preferences, either frequency or cache.
Co-developed-by: Perry Yuan <perry.yuan@amd.com>
Signed-off-by: Perry Yuan <perry.yuan@amd.com>
Co-developed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Reviewed-by: Armin Wolf <W_Armin@gmx.de>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
Link: https://lore.kernel.org/r/20241112170307.3745777-3-Basavaraj.Natikar@amd.com
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Diffstat (limited to 'Documentation/ABI')
| -rw-r--r-- | Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache b/Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache new file mode 100644 index 000000000000..ac3431736f5c --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache @@ -0,0 +1,12 @@ +What: /sys/bus/platform/drivers/amd_x3d_vcache/AMDI0101:00/amd_x3d_mode +Date: November 2024 +KernelVersion: 6.13 +Contact: Basavaraj Natikar <Basavaraj.Natikar@amd.com> +Description: (RW) AMD 3D V-Cache optimizer allows users to switch CPU core + rankings dynamically. + + This file switches between these two modes: + - "frequency" cores within the faster CCD are prioritized before + those in the slower CCD. + - "cache" cores within the larger L3 CCD are prioritized before + those in the smaller L3 CCD. |