diff options
| author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2021-10-11 14:27:11 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-10-26 18:27:42 -0700 |
| commit | f12d028b743bb6136da60b17228a1b6162886444 (patch) | |
| tree | a9836f3992618900c9818a6adb1769e8a974c180 | |
| parent | 5df4cd9099d049b1696dd4b20f1d0413ee2af93f (diff) | |
clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL
Use DIV_ROUND_CLOSEST_ULL() to avoid any inconsistency b/w the rate
computed in sam9x60_frac_pll_recalc_rate() and the one computed in
sam9x60_frac_pll_compute_mul_frac().
Fixes: 43b1bb4a9b3e1 ("clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-8-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| -rw-r--r-- | drivers/clk/at91/clk-sam9x60-pll.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c index 7020d3bf6e13..a73d7c96ce1d 100644 --- a/drivers/clk/at91/clk-sam9x60-pll.c +++ b/drivers/clk/at91/clk-sam9x60-pll.c @@ -73,8 +73,8 @@ static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw, struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); struct sam9x60_frac *frac = to_sam9x60_frac(core); - return (parent_rate * (frac->mul + 1) + - ((u64)parent_rate * frac->frac >> 22)); + return parent_rate * (frac->mul + 1) + + DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22)); } static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) |