diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2017-07-03 19:57:30 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2017-07-03 19:57:30 -0700 |
| commit | cbcd4f08aa637b74f575268770da86a00fabde6d (patch) | |
| tree | 449b5da5a05a8539b75640bcc4661147d840e053 | |
| parent | 362f6729cbb1d6bbab59e069f19441b0622ff7ec (diff) | |
| parent | 9b326dfce12afb429915c63f5a3df4afa4bea957 (diff) | |
Merge tag 'staging-4.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging
Pull staging/IIO updates from Greg KH:
"Here's the large set of staging and iio driver patches for 4.13-rc1.
After over 500 patches, we removed about 200 more lines of code than
we added, not great, but we added some new IIO drivers for unsupported
hardware, so it's an overall win.
Also here are lots of small fixes, and some tty core api additions
(with the tty maintainer's ack) for the speakup drivers, those are
finally getting some much needed cleanups and are looking much better
now than before. Full details in the shortlog.
All of these have been in linux-next for a while with no reported
issues"
* tag 'staging-4.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (529 commits)
staging: lustre: replace kmalloc with kmalloc_array
Staging: ion: fix code style warning from NULL comparisons
staging: fsl-mc: make dprc.h header private
staging: fsl-mc: move mc-cmd.h contents in the public header
staging: fsl-mc: move mc-sys.h contents in the public header
staging: fsl-mc: fix a few implicit includes
staging: fsl-mc: remove dpmng API files
staging: fsl-mc: move rest of mc-bus.h to private header
staging: fsl-mc: move couple of definitions to public header
staging: fsl-mc: move irq domain creation prototype to public header
staging: fsl-mc: turn several exported functions static
staging: fsl-mc: delete prototype of unimplemented function
staging: fsl-mc: delete duplicated function prototypes
staging: fsl-mc: decouple the mc-bus public headers from dprc.h
staging: fsl-mc: drop useless #includes
staging: fsl-mc: be consistent when checking strcmp() return
staging: fsl-mc: move comparison before strcmp() call
staging: speakup: make function ser_to_dev static
staging: ks7010: fix spelling mistake: "errror" -> "error"
staging: rtl8192e: fix spelling mistake: "respose" -> "response"
...
407 files changed, 11603 insertions, 11578 deletions
diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/testing/sysfs-bus-iio index 8c24d0892f61..2db2cdf42d54 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -1425,6 +1425,17 @@ Description: guarantees that the hardware fifo is flushed to the device buffer. +What: /sys/bus/iio/devices/iio:device*/buffer/hwfifo_timeout +KernelVersion: 4.12 +Contact: linux-iio@vger.kernel.org +Description: + A read/write property to provide capability to delay reporting of + samples till a timeout is reached. This allows host processors to + sleep, while the sensor is storing samples in its internal fifo. + The maximum timeout in seconds can be specified by setting + hwfifo_timeout.The current delay can be read by reading + hwfifo_timeout. A value of 0 means that there is no timeout. + What: /sys/bus/iio/devices/iio:deviceX/buffer/hwfifo_watermark KernelVersion: 4.2 Contact: linux-iio@vger.kernel.org diff --git a/Documentation/ABI/testing/sysfs-bus-iio-meas-spec b/Documentation/ABI/testing/sysfs-bus-iio-meas-spec index 1a6265e92e2f..6d47e548eee5 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio-meas-spec +++ b/Documentation/ABI/testing/sysfs-bus-iio-meas-spec @@ -5,4 +5,3 @@ Description: Reading returns either '1' or '0'. '1' means that the battery level supplied to sensor is below 2.25V. This ABI is available for tsys02d, htu21, ms8607 - This ABI is available for htu21, ms8607 diff --git a/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 b/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 index 230020e06677..161c147d3c40 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 +++ b/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 @@ -16,6 +16,54 @@ Description: - "OC2REF" : OC2REF signal is used as trigger output. - "OC3REF" : OC3REF signal is used as trigger output. - "OC4REF" : OC4REF signal is used as trigger output. + Additional modes (on TRGO2 only): + - "OC5REF" : OC5REF signal is used as trigger output. + - "OC6REF" : OC6REF signal is used as trigger output. + - "compare_pulse_OC4REF": + OC4REF rising or falling edges generate pulses. + - "compare_pulse_OC6REF": + OC6REF rising or falling edges generate pulses. + - "compare_pulse_OC4REF_r_or_OC6REF_r": + OC4REF or OC6REF rising edges generate pulses. + - "compare_pulse_OC4REF_r_or_OC6REF_f": + OC4REF rising or OC6REF falling edges generate pulses. + - "compare_pulse_OC5REF_r_or_OC6REF_r": + OC5REF or OC6REF rising edges generate pulses. + - "compare_pulse_OC5REF_r_or_OC6REF_f": + OC5REF rising or OC6REF falling edges generate pulses. + + +-----------+ +-------------+ +---------+ + | Prescaler +-> | Counter | +-> | Master | TRGO(2) + +-----------+ +--+--------+-+ |-> | Control +--> + | | || +---------+ + +--v--------+-+ OCxREF || +---------+ + | Chx compare +----------> | Output | ChX + +-----------+-+ | | Control +--> + . | | +---------+ + . | | . + +-----------v-+ OC6REF | . + | Ch6 compare +---------+> + +-------------+ + + Example with: "compare_pulse_OC4REF_r_or_OC6REF_r": + + X + X X + X . . X + X . . X + X . . X + count X . . . . X + . . . . + . . . . + +---------------+ + OC4REF | . . | + +-+ . . +-+ + . +---+ . + OC6REF . | | . + +-------+ +-------+ + +-+ +-+ + TRGO2 | | | | + +-+ +---+ +---------+ What: /sys/bus/iio/devices/triggerX/master_mode KernelVersion: 4.11 @@ -90,3 +138,18 @@ Description: Counting is enabled on rising edge of the connected trigger, and remains enabled for the duration of this selected mode. + +What: /sys/bus/iio/devices/iio:deviceX/in_count_trigger_mode_available +KernelVersion: 4.13 +Contact: benjamin.gaignard@st.com +Description: + Reading returns the list possible trigger modes. + +What: /sys/bus/iio/devices/iio:deviceX/in_count0_trigger_mode +KernelVersion: 4.13 +Contact: benjamin.gaignard@st.com +Description: + Configure the device counter trigger mode + counting direction is set by in_count0_count_direction + attribute and the counter is clocked by the connected trigger + rising edges. diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt index 047189192aec..f413e82c8b83 100644 --- a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt @@ -2,6 +2,8 @@ Required properties: - compatible: depending on the SoC this should be one of: + - "amlogic,meson8-saradc" for Meson8 + - "amlogic,meson8b-saradc" for Meson8b - "amlogic,meson-gxbb-saradc" for GXBB - "amlogic,meson-gxl-saradc" for GXL - "amlogic,meson-gxm-saradc" for GXM diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,gyroadc.txt b/Documentation/devicetree/bindings/iio/adc/renesas,gyroadc.txt index f5b0adae6010..df5b9f2ad8d8 100644 --- a/Documentation/devicetree/bindings/iio/adc/renesas,gyroadc.txt +++ b/Documentation/devicetree/bindings/iio/adc/renesas,gyroadc.txt @@ -1,4 +1,4 @@ -* Renesas RCar GyroADC device driver +* Renesas R-Car GyroADC device driver The GyroADC block is a reduced SPI block with up to 8 chipselect lines, which supports the SPI protocol of a selected few SPI ADCs. The SPI ADCs @@ -16,8 +16,7 @@ Required properties: - clocks: References to all the clocks specified in the clock-names property as specified in Documentation/devicetree/bindings/clock/clock-bindings.txt. -- clock-names: Shall contain "fck" and "if". The "fck" is the GyroADC block - clock, the "if" is the interface clock. +- clock-names: Shall contain "fck". The "fck" is the GyroADC block clock. - power-domains: Must contain a reference to the PM domain, if available. - #address-cells: Should be <1> (setting for the subnodes) for all ADCs except for "fujitsu,mb88101a". Should be <0> (setting for @@ -75,8 +74,8 @@ Example: adc@e6e54000 { compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc"; reg = <0 0xe6e54000 0 64>; - clocks = <&mstp9_clks R8A7791_CLK_GYROADC>, <&clk_65m>; - clock-names = "fck", "if"; + clocks = <&mstp9_clks R8A7791_CLK_GYROADC>; + clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; pinctrl-0 = <&adc_pins>; diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt index e35f9f1b3200..8310073f14e1 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt @@ -21,11 +21,19 @@ own configurable sequence and trigger: Contents of a stm32 adc root node: ----------------------------------- Required properties: -- compatible: Should be "st,stm32f4-adc-core". +- compatible: Should be one of: + "st,stm32f4-adc-core" + "st,stm32h7-adc-core" - reg: Offset and length of the ADC block register set. - interrupts: Must contain the interrupt for ADC block. -- clocks: Clock for the analog circuitry (common to all ADCs). -- clock-names: Must be "adc". +- clocks: Core can use up to two clocks, depending on part used: + - "adc" clock: for the analog circuitry, common to all ADCs. + It's required on stm32f4. + It's optional on stm32h7. + - "bus" clock: for registers access, common to all ADCs. + It's not present on stm32f4. + It's required on stm32h7. +- clock-names: Must be "adc" and/or "bus" depending on part used. - interrupt-controller: Identifies the controller node as interrupt-parent - vref-supply: Phandle to the vref input analog reference voltage. - #interrupt-cells = <1>; @@ -42,14 +50,18 @@ An ADC block node should contain at least one subnode, representing an ADC instance available on the machine. Required properties: -- compatible: Should be "st,stm32f4-adc". +- compatible: Should be one of: + "st,stm32f4-adc" + "st,stm32h7-adc" - reg: Offset of ADC instance in ADC block (e.g. may be 0x0, 0x100, 0x200). -- clocks: Input clock private to this ADC instance. +- clocks: Input clock private to this ADC instance. It's required only on + stm32f4, that has per instance clock input for registers access. - interrupt-parent: Phandle to the parent interrupt controller. - interrupts: IRQ Line for the ADC (e.g. may be 0 for adc@0, 1 for adc@100 or 2 for adc@200). - st,adc-channels: List of single-ended channels muxed for this ADC. - It can have up to 16 channels, numbered from 0 to 15 (resp. for in0..in15). + It can have up to 16 channels on stm32f4 or 20 channels on stm32h7, numbered + from 0 to 15 or 19 (resp. for in0..in15 or in0..in19). - #io-channel-cells = <1>: See the IIO bindings section "IIO consumers" in Documentation/devicetree/bindings/iio/iio-bindings.txt @@ -58,7 +70,9 @@ Optional properties: See ../../dma/dma.txt for details. - dma-names: Must be "rx" when dmas property is being used. - assigned-resolution-bits: Resolution (bits) to use for conversions. Must - match device available resolutions (e.g. can be 6, 8, 10 or 12 on stm32f4). + match device available resolutions: + * can be 6, 8, 10 or 12 on stm32f4 + * can be 8, 10, 12, 14 or 16 on stm32h7 Default is maximum resolution if unset. Example: diff --git a/Documentation/devicetree/bindings/iio/adc/ti-adc084s021.txt b/Documentation/devicetree/bindings/iio/adc/ti-adc084s021.txt new file mode 100644 index 000000000000..4259e50620bc --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/ti-adc084s021.txt @@ -0,0 +1,19 @@ +* Texas Instruments' ADC084S021 + +Required properties: + - compatible : Must be "ti,adc084s021" + - reg : SPI chip select number for the device + - vref-supply : The regulator supply for ADC reference voltage + - spi-cpol : Per spi-bus bindings + - spi-cpha : Per spi-bus bindings + - spi-max-frequency : Per spi-bus bindings + +Example: +adc@0 { + compatible = "ti,adc084s021"; + reg = <0>; + vref-supply = <&adc_vref>; + spi-cpol; + spi-cpha; + spi-max-frequency = <16000000>; +}; diff --git a/Documentation/devicetree/bindings/iio/adc/ti-adc108s102.txt b/Documentation/devicetree/bindings/iio/adc/ti-adc108s102.txt new file mode 100644 index 000000000000..bbbbb4a9f58f --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/ti-adc108s102.txt @@ -0,0 +1,18 @@ +* Texas Instruments' ADC108S102 and ADC128S102 ADC chip + +Required properties: + - compatible: Should be "ti,adc108s102" + - reg: spi chip select number for the device + - vref-supply: The regulator supply for ADC reference voltage + +Recommended properties: + - spi-max-frequency: Definition as per + Documentation/devicetree/bindings/spi/spi-bus.txt + +Example: +adc@0 { + compatible = "ti,adc108s102"; + reg = <0>; + vref-supply = <&vdd_supply>; + spi-max-frequency = <1000000>; +}; diff --git a/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt b/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt index 8305fb05ffda..6f28ff55f3ec 100644 --- a/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt +++ b/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt @@ -13,7 +13,8 @@ Optional properties: "data ready" (valid values: 1 or 2). - interrupt-parent: should be the phandle for the interrupt controller - interrupts: interrupt mapping for IRQ. It should be configured with - flags IRQ_TYPE_LEVEL_HIGH or IRQ_TYPE_EDGE_RISING. + flags IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_RISING, IRQ_TYPE_LEVEL_LOW or + IRQ_TYPE_EDGE_FALLING. Refer to interrupt-controller/interrupts.txt for generic interrupt client node bindings. diff --git a/Documentation/devicetree/bindings/trivial-devices.txt b/Documentation/devicetree/bindings/trivial-devices.txt index 3e0a34c88e07..35f406dd86b6 100644 --- a/Documentation/devicetree/bindings/trivial-devices.txt +++ b/Documentation/devicetree/bindings/trivial-devices.txt @@ -55,6 +55,7 @@ gmt,g751 G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire In infineon,slb9635tt Infineon SLB9635 (Soft-) I2C TPM (old protocol, max 100khz) infineon,slb9645tt Infineon SLB9645 I2C TPM (new protocol, max 400khz) isil,isl29028 Intersil ISL29028 Ambient Light and Proximity Sensor +isil,isl29030 Intersil ISL29030 Ambient Light and Proximity Sensor maxim,ds1050 5 Bit Programmable, Pulse-Width Modulator maxim,max1237 Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs maxim,max6625 9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface diff --git a/MAINTAINERS b/MAINTAINERS index f9c877f1ebf3..209abdaab854 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10553,6 +10553,7 @@ M: Laurentiu Tudor <laurentiu.tudor@nxp.com> L: linux-kernel@vger.kernel.org S: Maintained F: drivers/staging/fsl-mc/ +F: Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt QT1010 MEDIA DRIVER M: Antti Palosaari <crope@iki.fi> diff --git a/drivers/iio/accel/hid-sensor-accel-3d.c b/drivers/iio/accel/hid-sensor-accel-3d.c index 43a6cb078193..2238a26aba63 100644 --- a/drivers/iio/accel/hid-sensor-accel-3d.c +++ b/drivers/iio/accel/hid-sensor-accel-3d.c @@ -347,7 +347,7 @@ static int accel_3d_parse_report(struct platform_device *pdev, static int hid_accel_3d_probe(struct platform_device *pdev) { int ret = 0; - static const char *name; + const char *name; struct iio_dev *indio_dev; struct accel_3d_state *accel_state; const struct iio_chan_spec *channel_spec; diff --git a/drivers/iio/accel/mma9551.c b/drivers/iio/accel/mma9551.c index bf2704435629..1f53f08476f5 100644 --- a/drivers/iio/accel/mma9551.c +++ b/drivers/iio/accel/mma9551.c @@ -27,7 +27,6 @@ #define MMA9551_DRV_NAME "mma9551" #define MMA9551_IRQ_NAME "mma9551_event" -#define MMA9551_GPIO_NAME "mma9551_int" #define MMA9551_GPIO_COUNT 4 /* Tilt application (inclination in IIO terms). */ @@ -418,8 +417,7 @@ static int mma9551_gpio_probe(struct iio_dev *indio_dev) struct device *dev = &data->client->dev; for (i = 0; i < MMA9551_GPIO_COUNT; i++) { - gpio = devm_gpiod_get_index(dev, MMA9551_GPIO_NAME, i, - GPIOD_IN); + gpio = devm_gpiod_get_index(dev, NULL, i, GPIOD_IN); if (IS_ERR(gpio)) { dev_err(dev, "acpi gpio get index failed\n"); return PTR_ERR(gpio); diff --git a/drivers/iio/accel/st_accel_core.c b/drivers/iio/accel/st_accel_core.c index 784670e2736b..07d1489cd457 100644 --- a/drivers/iio/accel/st_accel_core.c +++ b/drivers/iio/accel/st_accel_core.c @@ -710,6 +710,8 @@ static const struct iio_trigger_ops st_accel_trigger_ops = { int st_accel_common_probe(struct iio_dev *indio_dev) { struct st_sensor_data *adata = iio_priv(indio_dev); + struct st_sensors_platform_data *pdata = + (struct st_sensors_platform_data *)adata->dev->platform_data; int irq = adata->get_irq_data_ready(indio_dev); int err; @@ -736,9 +738,8 @@ int st_accel_common_probe(struct iio_dev *indio_dev) &adata->sensor_settings->fs.fs_avl[0]; adata->odr = adata->sensor_settings->odr.odr_avl[0].hz; - if (!adata->dev->platform_data) - adata->dev->platform_data = - (struct st_sensors_platform_data *)&default_accel_pdata; + if (!pdata) + pdata = (struct st_sensors_platform_data *)&default_accel_pdata; err = st_sensors_init_sensor(indio_dev, adata->dev->platform_data); if (err < 0) diff --git a/drivers/iio/accel/st_accel_spi.c b/drivers/iio/accel/st_accel_spi.c index 29a15f27a51b..1a867f5563a4 100644 --- a/drivers/iio/accel/st_accel_spi.c +++ b/drivers/iio/accel/st_accel_spi.c @@ -47,15 +47,11 @@ static int st_accel_spi_remove(struct spi_device *spi) } static const struct spi_device_id st_accel_id_table[] = { - { LSM303DLH_ACCEL_DEV_NAME }, - { LSM303DLHC_ACCEL_DEV_NAME }, { LIS3DH_ACCEL_DEV_NAME }, { LSM330D_ACCEL_DEV_NAME }, { LSM330DL_ACCEL_DEV_NAME }, { LSM330DLC_ACCEL_DEV_NAME }, { LIS331DLH_ACCEL_DEV_NAME }, - { LSM303DL_ACCEL_DEV_NAME }, - { LSM303DLM_ACCEL_DEV_NAME }, { LSM330_ACCEL_DEV_NAME }, { LSM303AGR_ACCEL_DEV_NAME }, { LIS2DH12_ACCEL_DEV_NAME }, diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 401f47b51d83..614fa41559b1 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -679,6 +679,18 @@ config TI_ADC0832 This driver can also be built as a module. If so, the module will be called ti-adc0832. +config TI_ADC084S021 + tristate "Texas Instruments ADC084S021" + depends on SPI + select IIO_BUFFER + select IIO_TRIGGERED_BUFFER + help + If you say yes here you get support for Texas Instruments ADC084S021 + chips. + + This driver can also be built as a module. If so, the module will be + called ti-adc084s021. + config TI_ADC12138 tristate "Texas Instruments ADC12130/ADC12132/ADC12138" depends on SPI @@ -691,6 +703,18 @@ config TI_ADC12138 This driver can also be built as a module. If so, the module will be called ti-adc12138. +config TI_ADC108S102 + tristate "Texas Instruments ADC108S102 and ADC128S102 driver" + depends on SPI + select IIO_BUFFER + select IIO_TRIGGERED_BUFFER + help + Say yes here to build support for Texas Instruments ADC108S102 and + ADC128S102 ADC. + + To compile this driver as a module, choose M here: the module will + be called ti-adc108s102. + config TI_ADC128S052 tristate "Texas Instruments ADC128S052/ADC122S021/ADC124S021" depends on SPI diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 9339bec4babe..b546736a5541 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -62,7 +62,9 @@ obj-$(CONFIG_STM32_ADC_CORE) += stm32-adc-core.o obj-$(CONFIG_STM32_ADC) += stm32-adc.o obj-$(CONFIG_TI_ADC081C) += ti-adc081c.o obj-$(CONFIG_TI_ADC0832) += ti-adc0832.o +obj-$(CONFIG_TI_ADC084S021) += ti-adc084s021.o obj-$(CONFIG_TI_ADC12138) += ti-adc12138.o +obj-$(CONFIG_TI_ADC108S102) += ti-adc108s102.o obj-$(CONFIG_TI_ADC128S052) += ti-adc128s052.o obj-$(CONFIG_TI_ADC161S626) += ti-adc161s626.o obj-$(CONFIG_TI_ADS1015) += ti-ads1015.o diff --git a/drivers/iio/adc/ad7791.c b/drivers/iio/adc/ad7791.c index 1817ebf5ad84..34e353c43ac8 100644 --- a/drivers/iio/adc/ad7791.c +++ b/drivers/iio/adc/ad7791.c @@ -272,11 +272,9 @@ static ssize_t ad7791_write_frequency(struct device *dev, struct ad7791_state *st = iio_priv(indio_dev); int i, ret; - for (i = 0; i < ARRAY_SIZE(ad7791_sample_freq_avail); i++) - if (sysfs_streq(ad7791_sample_freq_avail[i], buf)) - break; - if (i == ARRAY_SIZE(ad7791_sample_freq_avail)) - return -EINVAL; + i = sysfs_match_string(ad7791_sample_freq_avail, buf); + if (i < 0) + return i; ret = iio_device_claim_direct_mode(indio_dev); if (ret) diff --git a/drivers/iio/adc/aspeed_adc.c b/drivers/iio/adc/aspeed_adc.c index 62670cbfa2bb..e0ea411a0b2d 100644 --- a/drivers/iio/adc/aspeed_adc.c +++ b/drivers/iio/adc/aspeed_adc.c @@ -212,7 +212,10 @@ static int aspeed_adc_probe(struct platform_device *pdev) } /* Start all channels in normal mode. */ - clk_prepare_enable(data->clk_scaler->clk); + ret = clk_prepare_enable(data->clk_scaler->clk); + if (ret) + goto clk_enable_error; + adc_engine_control_reg_val = GENMASK(31, 16) | ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE; writel(adc_engine_control_reg_val, @@ -236,6 +239,7 @@ iio_register_error: writel(ASPEED_OPERATION_MODE_POWER_DOWN, data->base + ASPEED_REG_ENGINE_CONTROL); clk_disable_unprepare(data->clk_scaler->clk); +clk_enable_error: clk_hw_unregister_divider(data->clk_scaler); scaler_error: diff --git a/drivers/iio/adc/cpcap-adc.c b/drivers/iio/adc/cpcap-adc.c index 62d37f8725b8..6e419d5a7c14 100644 --- a/drivers/iio/adc/cpcap-adc.c +++ b/drivers/iio/adc/cpcap-adc.c @@ -52,6 +52,10 @@ #define CPCAP_BIT_RAND0 BIT(1) /* Set with CAL_MODE */ #define CPCAP_BIT_ADEN BIT(0) /* Currently unused */ +#define CPCAP_REG_ADCC1_DEFAULTS (CPCAP_BIT_ADEN_AUTO_CLR | \ + CPCAP_BIT_ADC_CLK_SEL0 | \ + CPCAP_BIT_RAND1) + /* Register CPCAP_REG_ADCC2 bits */ #define CPCAP_BIT_CAL_FACTOR_ENABLE BIT(15) /* Currently unused */ #define CPCAP_BIT_BATDETB_EN BIT(14) /* Currently unused */ @@ -62,7 +66,7 @@ #define CPCAP_BIT_ADC_PS_FACTOR0 BIT(9) #define CPCAP_BIT_AD4_SELECT BIT(8) /* Currently unused */ #define CPCAP_BIT_ADC_BUSY BIT(7) /* Currently unused */ -#define CPCAP_BIT_THERMBIAS_EN BIT(6) /* Currently unused */ +#define CPCAP_BIT_THERMBIAS_EN BIT(6) /* Bias for AD0_BATTDETB */ #define CPCAP_BIT_ADTRIG_DIS BIT(5) /* Disable interrupt */ #define CPCAP_BIT_LIADC BIT(4) /* Currently unused */ #define CPCAP_BIT_TS_REFEN BIT(3) /* Currently unused */ @@ -70,6 +74,12 @@ #define CPCAP_BIT_TS_M1 BIT(1) /* Currently unused */ #define CPCAP_BIT_TS_M0 BIT(0) /* Currently unused */ +#define CPCAP_REG_ADCC2_DEFAULTS (CPCAP_BIT_AD4_SELECT | \ + CPCAP_BIT_ADTRIG_DIS | \ + CPCAP_BIT_LIADC | \ + CPCAP_BIT_TS_M2 | \ + CPCAP_BIT_TS_M1) + #define CPCAP_MAX_TEMP_LVL 27 #define CPCAP_FOUR_POINT_TWO_ADC 801 #define ST_ADC_CAL_CHRGI_HIGH_THRESHOLD 530 @@ -78,7 +88,7 @@ #define ST_ADC_CAL_BATTI_LOW_THRESHOLD 494 #define ST_ADC_CALIBRATE_DIFF_THRESHOLD 3 -#define CPCAP_ADC_MAX_RETRIES 5 /* Calibration and quirk */ +#define CPCAP_ADC_MAX_RETRIES 5 /* Calibration */ /** * struct cpcap_adc_ato - timing settings for cpcap adc @@ -124,10 +134,10 @@ struct cpcap_adc { */ enum cpcap_adc_channel { /* Bank0 channels */ - CPCAP_ADC_AD0_BATTDETB, /* Battery detection */ + CPCAP_ADC_AD0, /* Battery temperature */ CPCAP_ADC_BATTP, /* Battery voltage */ CPCAP_ADC_VBUS, /* USB VBUS voltage */ - CPCAP_ADC_AD3, /* Battery temperature when charging */ + CPCAP_ADC_AD3, /* Die temperature when charging */ CPCAP_ADC_BPLUS_AD4, /* Another battery or system voltage */ CPCAP_ADC_CHG_ISENSE, /* Calibrated charge current */ CPCAP_ADC_BATTI, /* Calibrated system current */ @@ -217,7 +227,7 @@ struct cpcap_adc_request { /* Phasing table for channels. Note that channels 16 & 17 use BATTP and BATTI */ static const struct cpcap_adc_phasing_tbl bank_phasing[] = { /* Bank0 */ - [CPCAP_ADC_AD0_BATTDETB] = {0, 0x80, 0x80, 0, 1023}, + [CPCAP_ADC_AD0] = {0, 0x80, 0x80, 0, 1023}, [CPCAP_ADC_BATTP] = {0, 0x80, 0x80, 0, 1023}, [CPCAP_ADC_VBUS] = {0, 0x80, 0x80, 0, 1023}, [CPCAP_ADC_AD3] = {0, 0x80, 0x80, 0, 1023}, @@ -243,7 +253,7 @@ static const struct cpcap_adc_phasing_tbl bank_phasing[] = { */ static struct cpcap_adc_conversion_tbl bank_conversion[] = { /* Bank0 */ - [CPCAP_ADC_AD0_BATTDETB] = { + [CPCAP_ADC_AD0] = { IIO_CHAN_INFO_PROCESSED, 0, 0, 0, 1, 1, }, [CPCAP_ADC_BATTP] = { @@ -541,6 +551,15 @@ static void cpcap_adc_setup_bank(struct cpcap_adc *ddata, return; switch (req->channel) { + case CPCAP_ADC_AD0: + value2 |= CPCAP_BIT_THERMBIAS_EN; + error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, + CPCAP_BIT_THERMBIAS_EN, + value2); + if (error) + return; + usleep_range(800, 1000); + break; case CPCAP_ADC_AD8 ... CPCAP_ADC_TSY2_AD15: value1 |= CPCAP_BIT_AD_SEL1; break; @@ -583,7 +602,8 @@ static void cpcap_adc_setup_bank(struct cpcap_adc *ddata, error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, CPCAP_BIT_ATOX_PS_FACTOR | CPCAP_BIT_ADC_PS_FACTOR1 | - CPCAP_BIT_ADC_PS_FACTOR0, + CPCAP_BIT_ADC_PS_FACTOR0 | + CPCAP_BIT_THERMBIAS_EN, value2); if (error) return; @@ -614,27 +634,6 @@ static void cpcap_adc_setup_bank(struct cpcap_adc *ddata, } } -/* - * Occasionally the ADC does not seem to start and there will be no - * interrupt. Let's re-init interrupt to prevent the ADC from hanging - * for the next request. It is unclear why this happens, but the next - * request will usually work after doing this. - */ -static void cpcap_adc_quirk_reset_lost_irq(struct cpcap_adc *ddata) -{ - int error; - - dev_info(ddata->dev, "lost ADC irq, attempting to reinit\n"); - disable_irq(ddata->irq); - error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, - CPCAP_BIT_ADTRIG_DIS, - CPCAP_BIT_ADTRIG_DIS); - if (error) - dev_warn(ddata->dev, "%s reset failed: %i\n", - __func__, error); - enable_irq(ddata->irq); -} - static int cpcap_adc_start_bank(struct cpcap_adc *ddata, struct cpcap_adc_request *req) { @@ -652,7 +651,6 @@ static int cpcap_adc_start_bank(struct cpcap_adc *ddata, return 0; if (error == 0) { - cpcap_adc_quirk_reset_lost_irq(ddata); error = -ETIMEDOUT; continue; } @@ -664,6 +662,21 @@ static int cpcap_adc_start_bank(struct cpcap_adc *ddata, return error; } +static int cpcap_adc_stop_bank(struct cpcap_adc *ddata) +{ + int error; + + error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1, + 0xffff, + CPCAP_REG_ADCC1_DEFAULTS); + if (error) + return error; + + return regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, + 0xffff, + CPCAP_REG_ADCC2_DEFAULTS); +} + static void cpcap_adc_phase(struct cpcap_adc_request *req) { const struct cpcap_adc_conversion_tbl *conv_tbl = req->conv_tbl; @@ -758,7 +771,7 @@ static void cpcap_adc_convert(struct cpcap_adc_request *req) return; /* Temperatures use a lookup table instead of conversion table */ - if ((req->channel == CPCAP_ADC_AD0_BATTDETB) || + if ((req->channel == CPCAP_ADC_AD0) || (req->channel == CPCAP_ADC_AD3)) { req->result = cpcap_adc_table_to_millicelcius(req->result); @@ -820,7 +833,7 @@ static int cpcap_adc_init_request(struct cpcap_adc_request *req, req->conv_tbl = bank_conversion; switch (channel) { - case CPCAP_ADC_AD0_BATTDETB ... CPCAP_ADC_USB_ID: + case CPCAP_ADC_AD0 ... CPCAP_ADC_USB_ID: req->bank_index = channel; break; case CPCAP_ADC_AD8 ... CPCAP_ADC_TSY2_AD15: @@ -839,6 +852,22 @@ static int cpcap_adc_init_request(struct cpcap_adc_request *req, return 0; } +static int cpcap_adc_read_st_die_temp(struct cpcap_adc *ddata, + int addr, int *val) +{ + int error; + + error = regmap_read(ddata->reg, addr, val); + if (error) + return error; + + *val -= 282; + *val *= 114; + *val += 25000; + + return 0; +} + static int cpcap_adc_read(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) @@ -860,6 +889,9 @@ static int cpcap_adc_read(struct iio_dev *indio_dev, error = regmap_read(ddata->reg, chan->address, val); if (error) goto err_unlock; + error = cpcap_adc_stop_bank(ddata); + if (error) + goto err_unlock; mutex_unlock(&ddata->lock); break; case IIO_CHAN_INFO_PROCESSED: @@ -867,7 +899,19 @@ static int cpcap_adc_read(struct iio_dev *indio_dev, error = cpcap_adc_start_bank(ddata, &req); if (error) goto err_unlock; - error = cpcap_adc_read_bank_scaled(ddata, &req); + if ((ddata->vendor == CPCAP_VENDOR_ST) && + (chan->channel == CPCAP_ADC_AD3)) { + error = cpcap_adc_read_st_die_temp(ddata, + chan->address, + &req.result); + if (error) + goto err_unlock; + } else { + error = cpcap_adc_read_bank_scaled(ddata, &req); + if (error) + goto err_unlock; + } + error = cpcap_adc_stop_bank(ddata); if (error) goto err_unlock; mutex_unlock(&ddata->lock); diff --git a/drivers/iio/adc/hi8435.c b/drivers/iio/adc/hi8435.c index 678e8c7ea763..adf7dc712937 100644 --- a/drivers/iio/adc/hi8435.c +++ b/drivers/iio/adc/hi8435.c @@ -105,6 +105,26 @@ static int hi8435_writew(struct hi8435_priv *priv, u8 reg, u16 val) return spi_write(priv->spi, priv->reg_buffer, 3); } +static int hi8435_read_raw(struct iio_dev *idev, + const struct iio_chan_spec *chan, + int *val, int *val2, long mask) +{ + struct hi8435_priv *priv = iio_priv(idev); + u32 tmp; + int ret; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + ret = hi8435_readl(priv, HI8435_SO31_0_REG, &tmp); + if (ret < 0) + return ret; + *val = !!(tmp & BIT(chan->channel)); + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + static int hi8435_read_event_config(struct iio_dev *idev, const struct iio_chan_spec *chan, enum iio_event_type type, @@ -121,10 +141,21 @@ static int hi8435_write_event_config(struct iio_dev *idev, enum iio_event_direction dir, int state) { struct hi8435_priv *priv = iio_priv(idev); + int ret; + u32 tmp; + + if (state) { + ret = hi8435_readl(priv, HI8435_SO31_0_REG, &tmp); + if (ret < 0) + return ret; + if (tmp & BIT(chan->channel)) + priv->event_prev_val |= BIT(chan->channel); + else + priv->event_prev_val &= ~BIT(chan->channel); - priv->event_scan_mask &= ~BIT(chan->channel); - if (state) priv->event_scan_mask |= BIT(chan->channel); + } else + priv->event_scan_mask &= ~BIT(chan->channel); return 0; } @@ -325,6 +356,7 @@ static const struct iio_enum hi8435_sensing_mode = { static const struct iio_chan_spec_ext_info hi8435_ext_info[] = { IIO_ENUM("sensing_mode", IIO_SEPARATE, &hi8435_sensing_mode), + IIO_ENUM_AVAILABLE("sensing_mode", &hi8435_sensing_mode), {}, }; @@ -333,6 +365,7 @@ static const struct iio_chan_spec_ext_info hi8435_ext_info[] = { .type = IIO_VOLTAGE, \ .indexed = 1, \ .channel = num, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ .event_spec = hi8435_events, \ .num_event_specs = ARRAY_SIZE(hi8435_events), \ .ext_info = hi8435_ext_info, \ @@ -376,11 +409,12 @@ static const struct iio_chan_spec hi8435_channels[] = { static const struct iio_info hi8435_info = { .driver_module = THIS_MODULE, - .read_event_config = &hi8435_read_event_config, + .read_raw = hi8435_read_raw, + .read_event_config = hi8435_read_event_config, .write_event_config = hi8435_write_event_config, - .read_event_value = &hi8435_read_event_value, - .write_event_value = &hi8435_write_event_value, - .debugfs_reg_access = &hi8435_debugfs_reg_access, + .read_event_value = hi8435_read_event_value, + .write_event_value = hi8435_write_event_value, + .debugfs_reg_access = hi8435_debugfs_reg_access, }; static void hi8435_iio_push_event(struct iio_dev *idev, unsigned int val) diff --git a/drivers/iio/adc/ina2xx-adc.c b/drivers/iio/adc/ina2xx-adc.c index db9838230257..232c0b80d658 100644 --- a/drivers/iio/adc/ina2xx-adc.c +++ b/drivers/iio/adc/ina2xx-adc.c @@ -42,13 +42,14 @@ #define INA2XX_CURRENT 0x04 /* readonly */ #define INA2XX_CALIBRATION 0x05 -#define INA226_ALERT_MASK GENMASK(2, 1) -#define INA266_CVRF BIT(3) +#define INA226_MASK_ENABLE 0x06 +#define INA226_CVRF BIT(3) #define INA2XX_MAX_REGISTERS 8 /* settings - depend on use case */ #define INA219_CONFIG_DEFAULT 0x399F /* PGA=8 */ +#define INA219_DEFAULT_IT 532 #define INA226_CONFIG_DEFAULT 0x4327 #define INA226_DEFAULT_AVG 4 #define INA226_DEFAULT_IT 1110 @@ -56,19 +57,24 @@ #define INA2XX_RSHUNT_DEFAULT 10000 /* - * bit mask for reading the averaging setting in the configuration register + * bit masks for reading the settings in the configuration register * FIXME: use regmap_fields. */ #define INA2XX_MODE_MASK GENMASK(3, 0) +/* Averaging for VBus/VShunt/Power */ #define INA226_AVG_MASK GENMASK(11, 9) #define INA226_SHIFT_AVG(val) ((val) << 9) /* Integration time for VBus */ +#define INA219_ITB_MASK GENMASK(10, 7) +#define INA219_SHIFT_ITB(val) ((val) << 7) #define INA226_ITB_MASK GENMASK(8, 6) #define INA226_SHIFT_ITB(val) ((val) << 6) /* Integration time for VShunt */ +#define INA219_ITS_MASK GENMASK(6, 3) +#define INA219_SHIFT_ITS(val) ((val) << 3) #define INA226_ITS_MASK GENMASK(5, 3) #define INA226_SHIFT_ITS(val) ((val) << 3) @@ -108,6 +114,7 @@ struct ina2xx_config { int bus_voltage_shift; int bus_voltage_lsb; /* uV */ int power_lsb; /* uW */ + enum ina2xx_ids chip_id; }; struct ina2xx_chip_info { @@ -130,6 +137,7 @@ static const struct ina2xx_config ina2xx_config[] = { .bus_voltage_shift = 3, .bus_voltage_lsb = 4000, .power_lsb = 20000, + .chip_id = ina219, }, [ina226] = { .config_default = INA226_CONFIG_DEFAULT, @@ -138,6 +146,7 @@ static const struct ina2xx_config ina2xx_config[] = { .bus_voltage_shift = 0, .bus_voltage_lsb = 1250, .power_lsb = 25000, + .chip_id = ina226, }, }; @@ -283,6 +292,66 @@ static int ina226_set_int_time_vshunt(struct ina2xx_chip_info *chip, return 0; } +/* Conversion times in uS. */ +static const int ina219_conv_time_tab_subsample[] = { 84, 148, 276, 532 }; +static const int ina219_conv_time_tab_average[] = { 532, 1060, 2130, 4260, + 8510, 17020, 34050, 68100}; + +static int ina219_lookup_int_time(unsigned int *val_us, int *bits) +{ + if (*val_us > 68100 || *val_us < 84) + return -EINVAL; + + if (*val_us <= 532) { + *bits = find_closest(*val_us, ina219_conv_time_tab_subsample, + ARRAY_SIZE(ina219_conv_time_tab_subsample)); + *val_us = ina219_conv_time_tab_subsample[*bits]; + } else { + *bits = find_closest(*val_us, ina219_conv_time_tab_average, + ARRAY_SIZE(ina219_conv_time_tab_average)); + *val_us = ina219_conv_time_tab_average[*bits]; + *bits |= 0x8; + } + + return 0; +} + +static int ina219_set_int_time_vbus(struct ina2xx_chip_info *chip, + unsigned int val_us, unsigned int *config) +{ + int bits, ret; + unsigned int val_us_best = val_us; + + ret = ina219_lookup_int_time(&val_us_best, &bits); + if (ret) + return ret; + + chip->int_time_vbus = val_us_best; + + *config &= ~INA219_ITB_MASK; + *config |= INA219_SHIFT_ITB(bits) & INA219_ITB_MASK; + + return 0; +} + +static int ina219_set_int_time_vshunt(struct ina2xx_chip_info *chip, + unsigned int val_us, unsigned int *config) +{ + int bits, ret; + unsigned int val_us_best = val_us; + + ret = ina219_lookup_int_time(&val_us_best, &bits); + if (ret) + return ret; + + chip->int_time_vshunt = val_us_best; + + *config &= ~INA219_ITS_MASK; + *config |= INA219_SHIFT_ITS(bits) & INA219_ITS_MASK; + + return 0; +} + static int ina2xx_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) @@ -308,10 +377,21 @@ static int ina2xx_write_raw(struct iio_dev *indio_dev, break; case IIO_CHAN_INFO_INT_TIME: - if (chan->address == INA2XX_SHUNT_VOLTAGE) - ret = ina226_set_int_time_vshunt(chip, val2, &tmp); - else - ret = ina226_set_int_time_vbus(chip, val2, &tmp); + if (chip->config->chip_id == ina226) { + if (chan->address == INA2XX_SHUNT_VOLTAGE) + ret = ina226_set_int_time_vshunt(chip, val2, + &tmp); + else + ret = ina226_set_int_time_vbus(chip, val2, + &tmp); + } else { + if (chan->address == INA2XX_SHUNT_VOLTAGE) + ret = ina219_set_int_time_vshunt(chip, val2, + &tmp); + else + ret = ina219_set_int_time_vbus(chip, val2, + &tmp); + } break; default: @@ -412,13 +492,30 @@ static ssize_t ina2xx_shunt_resistor_store(struct device *dev, return len; } -#define INA2XX_CHAN(_type, _index, _address) { \ +#define INA219_CHAN(_type, _index, _address) { \ + .type = (_type), \ + .address = (_address), \ + .indexed = 1, \ + .channel = (_index), \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_shared_by_dir = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .scan_index = (_index), \ + .scan_type = { \ + .sign = 'u', \ + .realbits = 16, \ + .storagebits = 16, \ + .endianness = IIO_CPU, \ + } \ +} + +#define INA226_CHAN(_type, _index, _address) { \ .type = (_type), \ .address = (_address), \ .indexed = 1, \ .channel = (_index), \ - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \ - | BIT(IIO_CHAN_INFO_SCALE), \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE), \ .info_mask_shared_by_dir = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .scan_index = (_index), \ @@ -434,7 +531,25 @@ static ssize_t ina2xx_shunt_resistor_store(struct device *dev, * Sampling Freq is a consequence of the integration times of * the Voltage channels. */ -#define INA2XX_CHAN_VOLTAGE(_index, _address) { \ +#define INA219_CHAN_VOLTAGE(_index, _address) { \ + .type = IIO_VOLTAGE, \ + .address = (_address), \ + .indexed = 1, \ + .channel = (_index), \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_INT_TIME), \ + .info_mask_shared_by_dir = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ + .scan_index = (_index), \ + .scan_type = { \ + .sign = 'u', \ + .realbits = 16, \ + .storagebits = 16, \ + .endianness = IIO_LE, \ + } \ +} + +#define INA226_CHAN_VOLTAGE(_index, _address) { \ .type = IIO_VOLTAGE, \ .address = (_address), \ .indexed = 1, \ @@ -442,6 +557,8 @@ static ssize_t ina2xx_shunt_resistor_store(struct device *dev, .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ BIT(IIO_CHAN_INFO_SCALE) | \ BIT(IIO_CHAN_INFO_INT_TIME), \ + .info_mask_shared_by_dir = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .scan_index = (_index), \ .scan_type = { \ .sign = 'u', \ @@ -451,11 +568,20 @@ static ssize_t ina2xx_shunt_resistor_store(struct device *dev, } \ } -static const struct iio_chan_spec ina2xx_channels[] = { - INA2XX_CHAN_VOLTAGE(0, INA2XX_SHUNT_VOLTAGE), - INA2XX_CHAN_VOLTAGE(1, INA2XX_BUS_VOLTAGE), - INA2XX_CHAN(IIO_POWER, 2, INA2XX_POWER), - INA2XX_CHAN(IIO_CURRENT, 3, INA2XX_CURRENT), + +static const struct iio_chan_spec ina226_channels[] = { + INA226_CHAN_VOLTAGE(0, INA2XX_SHUNT_VOLTAGE), + INA226_CHAN_VOLTAGE(1, INA2XX_BUS_VOLTAGE), + INA226_CHAN(IIO_POWER, 2, INA2XX_POWER), + INA226_CHAN(IIO_CURRENT, 3, INA2XX_CURRENT), + IIO_CHAN_SOFT_TIMESTAMP(4), +}; + +static const struct iio_chan_spec ina219_channels[] = { + INA219_CHAN_VOLTAGE(0, INA2XX_SHUNT_VOLTAGE), + INA219_CHAN_VOLTAGE(1, INA2XX_BUS_VOLTAGE), + INA219_CHAN(IIO_POWER, 2, INA2XX_POWER), + INA219_CHAN(IIO_CURRENT, 3, INA2XX_CURRENT), IIO_CHAN_SOFT_TIMESTAMP(4), }; @@ -481,12 +607,12 @@ static int ina2xx_work_buffer(struct iio_dev *indio_dev) */ if (!chip->allow_async_readout) do { - ret = regmap_read(chip->regmap, INA226_ALERT_MASK, + ret = regmap_read(chip->regmap, INA226_MASK_ENABLE, &alert); if (ret < 0) return ret; - alert &= INA266_CVRF; + alert &= INA226_CVRF; } while (!alert); /* @@ -590,7 +716,14 @@ static int ina2xx_debug_reg(struct iio_dev *indio_dev, } /* Possible integration times for vshunt and vbus */ -static IIO_CONST_ATTR_INT_TIME_AVAIL("0.000140 0.000204 0.000332 0.000588 0.001100 0.002116 0.004156 0.008244"); +static IIO_CONST_ATTR_NAMED(ina219_integration_time_available, + integration_time_available, + "0.000084 0.000148 0.000276 0.000532 0.001060 0.002130 0.004260 0.008510 0.017020 0.034050 0.068100"); + +static IIO_CONST_ATTR_NAMED(ina226_integration_time_available, + integration_time_available, + "0.000140 0.000204 0.000332 0.000588 0.001100 0.002116 0.004156 0.008244"); + static IIO_DEVICE_ATTR(in_allow_async_readout, S_IRUGO | S_IWUSR, ina2xx_allow_async_readout_show, @@ -600,20 +733,39 @@ static IIO_DEVICE_ATTR(in_shunt_resistor, S_IRUGO | S_IWUSR, ina2xx_shunt_resistor_show, ina2xx_shunt_resistor_store, 0); -static struct attribute *ina2xx_attributes[] = { +static struct attribute *ina219_attributes[] = { + &iio_dev_attr_in_allow_async_readout.dev_attr.attr, + &iio_const_attr_ina219_integration_time_available.dev_attr.attr, + &iio_dev_attr_in_shunt_resistor.dev_attr.attr, + NULL, +}; + +static struct attribute *ina226_attributes[] = { &iio_dev_attr_in_allow_async_readout.dev_attr.attr, - &iio_const_attr_integration_time_available.dev_attr.attr, + &iio_const_attr_ina226_integration_time_available.dev_attr.attr, &iio_dev_attr_in_shunt_resistor.dev_attr.attr, NULL, }; -static const struct attribute_group ina2xx_attribute_group = { - .attrs = ina2xx_attributes, +static const struct attribute_group ina219_attribute_group = { + .attrs = ina219_attributes, +}; + +static const struct attribute_group ina226_attribute_group = { + .attrs = ina226_attributes, }; -static const struct iio_info ina2xx_info = { +static const struct iio_info ina219_info = { .driver_module = THIS_MODULE, - .attrs = &ina2xx_attribute_group, + .attrs = &ina219_attribute_group, + .read_raw = ina2xx_read_raw, + .write_raw = ina2xx_write_raw, + .debugfs_reg_access = ina2xx_debug_reg, +}; + +static const struct iio_info ina226_info = { + .driver_module = THIS_MODULE, + .attrs = &ina226_attribute_group, .read_raw = ina2xx_read_raw, .write_raw = ina2xx_write_raw, .debugfs_reg_access = ina2xx_debug_reg, @@ -684,6 +836,10 @@ static int ina2xx_probe(struct i2c_client *client, ina226_set_average(chip, INA226_DEFAULT_AVG, &val); ina226_set_int_time_vbus(chip, INA226_DEFAULT_IT, &val); ina226_set_int_time_vshunt(chip, INA226_DEFAULT_IT, &val); + } else { + chip->avg = 1; + ina219_set_int_time_vbus(chip, INA219_DEFAULT_IT, &val); + ina219_set_int_time_vshunt(chip, INA219_DEFAULT_IT, &val); } ret = ina2xx_init(chip, val); @@ -695,10 +851,16 @@ static int ina2xx_probe(struct i2c_client *client, indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; indio_dev->dev.parent = &client->dev; indio_dev->dev.of_node = client->dev.of_node; - indio_dev->channels = ina2xx_channels; - indio_dev->num_channels = ARRAY_SIZE(ina2xx_channels); + if (id->driver_data == ina226) { + indio_dev->channels = ina226_channels; + indio_dev->num_channels = ARRAY_SIZE(ina226_channels); + indio_dev->info = &ina226_info; + } else { + indio_dev->channels = ina219_channels; + indio_dev->num_channels = ARRAY_SIZE(ina219_channels); + indio_dev->info = &ina219_info; + } indio_dev->name = id->name; - indio_dev->info = &ina2xx_info; indio_dev->setup_ops = &ina2xx_setup_ops; buffer = devm_iio_kfifo_allocate(&indio_dev->dev); diff --git a/drivers/iio/adc/lpc32xx_adc.c b/drivers/iio/adc/lpc32xx_adc.c index 0de709b4288b..6a5b9a9bc662 100644 --- a/drivers/iio/adc/lpc32xx_adc.c +++ b/drivers/iio/adc/lpc32xx_adc.c @@ -76,10 +76,14 @@ static int lpc32xx_read_raw(struct iio_dev *indio_dev, long mask) { struct lpc32xx_adc_state *st = iio_priv(indio_dev); - + int ret; if (mask == IIO_CHAN_INFO_RAW) { mutex_lock(&indio_dev->mlock); - clk_prepare_enable(st->clk); + ret = clk_prepare_enable(st->clk); + if (ret) { + mutex_unlock(&indio_dev->mlock); + return ret; + } /* Measurement setup */ __raw_writel(LPC32XXAD_INTERNAL | (chan->address) | LPC32XXAD_REFp | LPC32XXAD_REFm, diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c index 6066bbfc42fe..83da50ed73ab 100644 --- a/drivers/iio/adc/meson_saradc.c +++ b/drivers/iio/adc/meson_saradc.c @@ -220,6 +220,7 @@ enum meson_sar_adc_chan7_mux_sel { }; struct meson_sar_adc_data { + bool has_bl30_integration; unsigned int resolution; const char *name; }; @@ -437,19 +438,24 @@ static int meson_sar_adc_lock(struct iio_dev *indio_dev) mutex_lock(&indio_dev->mlock); - /* prevent BL30 from using the SAR ADC while we are using it */ - regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, - MESON_SAR_ADC_DELAY_KERNEL_BUSY, - MESON_SAR_ADC_DELAY_KERNEL_BUSY); - - /* wait until BL30 releases it's lock (so we can use the SAR ADC) */ - do { - udelay(1); - regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val); - } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--); - - if (timeout < 0) - return -ETIMEDOUT; + if (priv->data->has_bl30_integration) { + /* prevent BL30 from using the SAR ADC while we are using it */ + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, + MESON_SAR_ADC_DELAY_KERNEL_BUSY, + MESON_SAR_ADC_DELAY_KERNEL_BUSY); + + /* + * wait until BL30 releases it's lock (so we can use the SAR + * ADC) + */ + do { + udelay(1); + regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val); + } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--); + + if (timeout < 0) + return -ETIMEDOUT; + } return 0; } @@ -458,9 +464,10 @@ static void meson_sar_adc_unlock(struct iio_dev *indio_dev) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); - /* allow BL30 to use the SAR ADC again */ - regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, - MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0); + if (priv->data->has_bl30_integration) + /* allow BL30 to use the SAR ADC again */ + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, + MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0); mutex_unlock(&indio_dev->mlock); } @@ -614,14 +621,16 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev) */ meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT); - /* - * leave sampling delay and the input clocks as configured by BL30 to - * make sure BL30 gets the values it expects when reading the - * temperature sensor. - */ - regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val); - if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED) - return 0; + if (priv->data->has_bl30_integration) { + /* + * leave sampling delay and the input clocks as configured by + * BL30 to make sure BL30 gets the values it expects when + * reading the temperature sensor. + */ + regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val); + if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED) + return 0; + } meson_sar_adc_stop_sample_engine(indio_dev); @@ -834,23 +843,46 @@ static const struct iio_info meson_sar_adc_iio_info = { .driver_module = THIS_MODULE, }; -struct meson_sar_adc_data meson_sar_adc_gxbb_data = { +static const struct meson_sar_adc_data meson_sar_adc_meson8_data = { + .has_bl30_integration = false, + .resolution = 10, + .name = "meson-meson8-saradc", +}; + +static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = { + .has_bl30_integration = false, + .resolution = 10, + .name = "meson-meson8b-saradc", +}; + +static const struct meson_sar_adc_data meson_sar_adc_gxbb_data = { + .has_bl30_integration = true, .resolution = 10, .name = "meson-gxbb-saradc", }; -struct meson_sar_adc_data meson_sar_adc_gxl_data = { +static const struct meson_sar_adc_data meson_sar_adc_gxl_data = { + .has_bl30_integration = true, .resolution = 12, .name = "meson-gxl-saradc", }; -struct meson_sar_adc_data meson_sar_adc_gxm_data = { +static const struct meson_sar_adc_data meson_sar_adc_gxm_data = { + .has_bl30_integration = true, .resolution = 12, .name = "meson-gxm-saradc", }; static const struct of_device_id meson_sar_adc_of_match[] = { { + .compatible = "amlogic,meson8-saradc", + .data = &meson_sar_adc_meson8_data, + }, + { + .compatible = "amlogic,meson8b-saradc", + .data = &meson_sar_adc_meson8b_data, + }, + { .compatible = "amlogic,meson-gxbb-saradc", .data = &meson_sar_adc_gxbb_data, }, { diff --git a/drivers/iio/adc/mxs-lradc-adc.c b/drivers/iio/adc/mxs-lradc-adc.c index 6888167ca1e6..d32b34638c2f 100644 --- a/drivers/iio/adc/mxs-lradc-adc.c +++ b/drivers/iio/adc/mxs-lradc-adc.c @@ -48,7 +48,7 @@ #define VREF_MV_BASE 1850 -const char *mx23_lradc_adc_irq_names[] = { +static const char *mx23_lradc_adc_irq_names[] = { "mxs-lradc-channel0", "mxs-lradc-channel1", "mxs-lradc-channel2", @@ -57,7 +57,7 @@ const char *mx23_lradc_adc_irq_names[] = { "mxs-lradc-channel5", }; -const char *mx28_lradc_adc_irq_names[] = { +static const char *mx28_lradc_adc_irq_names[] = { "mxs-lradc-thresh0", "mxs-lradc-thresh1", "mxs-lradc-channel0", @@ -344,20 +344,20 @@ static ssize_t mxs_lradc_adc_show_scale_avail(struct device *dev, IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, 0444,\ mxs_lradc_adc_show_scale_avail, NULL, ch) -SHOW_SCALE_AVAILABLE_ATTR(0); -SHOW_SCALE_AVAILABLE_ATTR(1); -SHOW_SCALE_AVAILABLE_ATTR(2); -SHOW_SCALE_AVAILABLE_ATTR(3); -SHOW_SCALE_AVAILABLE_ATTR(4); -SHOW_SCALE_AVAILABLE_ATTR(5); -SHOW_SCALE_AVAILABLE_ATTR(6); -SHOW_SCALE_AVAILABLE_ATTR(7); -SHOW_SCALE_AVAILABLE_ATTR(10); -SHOW_SCALE_AVAILABLE_ATTR(11); -SHOW_SCALE_AVAILABLE_ATTR(12); -SHOW_SCALE_AVAILABLE_ATTR(13); -SHOW_SCALE_AVAILABLE_ATTR(14); -SHOW_SCALE_AVAILABLE_ATTR(15); +static SHOW_SCALE_AVAILABLE_ATTR(0); +static SHOW_SCALE_AVAILABLE_ATTR(1); +static SHOW_SCALE_AVAILABLE_ATTR(2); +static SHOW_SCALE_AVAILABLE_ATTR(3); +static SHOW_SCALE_AVAILABLE_ATTR(4); +static SHOW_SCALE_AVAILABLE_ATTR(5); +static SHOW_SCALE_AVAILABLE_ATTR(6); +static SHOW_SCALE_AVAILABLE_ATTR(7); +static SHOW_SCALE_AVAILABLE_ATTR(10); +static SHOW_SCALE_AVAILABLE_ATTR(11); +static SHOW_SCALE_AVAILABLE_ATTR(12); +static SHOW_SCALE_AVAILABLE_ATTR(13); +static SHOW_SCALE_AVAILABLE_ATTR(14); +static SHOW_SCALE_AVAILABLE_ATTR(15); static struct attribute *mxs_lradc_adc_attributes[] = { &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr, diff --git a/drivers/iio/adc/rcar-gyroadc.c b/drivers/iio/adc/rcar-gyroadc.c index 018ed360e717..27a318164619 100644 --- a/drivers/iio/adc/rcar-gyroadc.c +++ b/drivers/iio/adc/rcar-gyroadc.c @@ -73,7 +73,7 @@ enum rcar_gyroadc_model { struct rcar_gyroadc { struct device *dev; void __iomem *regs; - struct clk *iclk; + struct clk *clk; struct regulator *vref[8]; unsigned int num_channels; enum rcar_gyroadc_model model; @@ -83,7 +83,7 @@ struct rcar_gyroadc { static void rcar_gyroadc_hw_init(struct rcar_gyroadc *priv) { - const unsigned long clk_mhz = clk_get_rate(priv->iclk) / 1000000; + const unsigned long clk_mhz = clk_get_rate(priv->clk) / 1000000; const unsigned long clk_mul = (priv->mode == RCAR_GYROADC_MODE_SELECT_1_MB88101A) ? 10 : 5; unsigned long clk_len = clk_mhz * clk_mul; @@ -510,9 +510,9 @@ static int rcar_gyroadc_probe(struct platform_device *pdev) if (IS_ERR(priv->regs)) return PTR_ERR(priv->regs); - priv->iclk = devm_clk_get(dev, "if"); - if (IS_ERR(priv->iclk)) { - ret = PTR_ERR(priv->iclk); + priv->clk = devm_clk_get(dev, "fck"); + if (IS_ERR(priv->clk)) { + ret = PTR_ERR(priv->clk); if (ret != -EPROBE_DEFER) dev_err(dev, "Failed to get IF clock (ret=%i)\n", ret); return ret; @@ -536,7 +536,7 @@ static int rcar_gyroadc_probe(struct platform_device *pdev) indio_dev->info = &rcar_gyroadc_iio_info; indio_dev->modes = INDIO_DIRECT_MODE; - ret = clk_prepare_enable(priv->iclk); + ret = clk_prepare_enable(priv->clk); if (ret) { dev_err(dev, "Could not prepare or enable the IF clock.\n"); goto err_clk_if_enable; @@ -565,7 +565,7 @@ err_iio_device_register: pm_runtime_put_sync(dev); pm_runtime_disable(dev); pm_runtime_set_suspended(dev); - clk_disable_unprepare(priv->iclk); + clk_disable_unprepare(priv->clk); err_clk_if_enable: rcar_gyroadc_deinit_supplies(indio_dev); @@ -584,7 +584,7 @@ static int rcar_gyroadc_remove(struct platform_device *pdev) pm_runtime_put_sync(dev); pm_runtime_disable(dev); pm_runtime_set_suspended(dev); - clk_disable_unprepare(priv->iclk); + clk_disable_unprepare(priv->clk); rcar_gyroadc_deinit_supplies(indio_dev); return 0; diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c index 22b7c9321e78..e09233b03c05 100644 --- a/drivers/iio/adc/stm32-adc-core.c +++ b/drivers/iio/adc/stm32-adc-core.c @@ -49,19 +49,66 @@ /* STM32 F4 maximum analog clock rate (from datasheet) */ #define STM32F4_ADC_MAX_CLK_RATE 36000000 +/* STM32H7 - common registers for all ADC instances */ +#define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00) +#define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08) + +/* STM32H7_ADC_CSR - bit fields */ +#define STM32H7_EOC_SLV BIT(18) +#define STM32H7_EOC_MST BIT(2) + +/* STM32H7_ADC_CCR - bit fields */ +#define STM32H7_PRESC_SHIFT 18 +#define STM32H7_PRESC_MASK GENMASK(21, 18) +#define STM32H7_CKMODE_SHIFT 16 +#define STM32H7_CKMODE_MASK GENMASK(17, 16) + +/* STM32 H7 maximum analog clock rate (from datasheet) */ +#define STM32H7_ADC_MAX_CLK_RATE 72000000 + +/** + * stm32_adc_common_regs - stm32 common registers, compatible dependent data + * @csr: common status register offset + * @eoc1: adc1 end of conversion flag in @csr + * @eoc2: adc2 end of conversion flag in @csr + * @eoc3: adc3 end of conversion flag in @csr + */ +struct stm32_adc_common_regs { + u32 csr; + u32 eoc1_msk; + u32 eoc2_msk; + u32 eoc3_msk; +}; + +struct stm32_adc_priv; + +/** + * stm32_adc_priv_cfg - stm32 core compatible configuration data + * @regs: common registers for all instances + * @clk_sel: clock selection routine + */ +struct stm32_adc_priv_cfg { + const struct stm32_adc_common_regs *regs; + int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *); +}; + /** * struct stm32_adc_priv - stm32 ADC core private data * @irq: irq for ADC block * @domain: irq domain reference * @aclk: clock reference for the analog circuitry + * @bclk: bus clock common for all ADCs, depends on part used * @vref: regulator reference + * @cfg: compatible configuration data * @common: common data for all ADC instances */ struct stm32_adc_priv { int irq; struct irq_domain *domain; struct clk *aclk; + struct clk *bclk; struct regulator *vref; + const struct stm32_adc_priv_cfg *cfg; struct stm32_adc_common common; }; @@ -85,14 +132,23 @@ static int stm32f4_adc_clk_sel(struct platform_device *pdev, u32 val; int i; + /* stm32f4 has one clk input for analog (mandatory), enforce it here */ + if (!priv->aclk) { + dev_err(&pdev->dev, "No 'adc' clock found\n"); + return -ENOENT; + } + rate = clk_get_rate(priv->aclk); for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) { if ((rate / stm32f4_pclk_div[i]) <= STM32F4_ADC_MAX_CLK_RATE) break; } - if (i >= ARRAY_SIZE(stm32f4_pclk_div)) + if (i >= ARRAY_SIZE(stm32f4_pclk_div)) { + dev_err(&pdev->dev, "adc clk selection failed\n"); return -EINVAL; + } + priv->common.rate = rate; val = readl_relaxed(priv->common.base + STM32F4_ADC_CCR); val &= ~STM32F4_ADC_ADCPRE_MASK; val |= i << STM32F4_ADC_ADCPRE_SHIFT; @@ -104,6 +160,126 @@ static int stm32f4_adc_clk_sel(struct platform_device *pdev, return 0; } +/** + * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock + * @ckmode: ADC clock mode, Async or sync with prescaler. + * @presc: prescaler bitfield for async clock mode + * @div: prescaler division ratio + */ +struct stm32h7_adc_ck_spec { + u32 ckmode; + u32 presc; + int div; +}; + +const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = { + /* 00: CK_ADC[1..3]: Asynchronous clock modes */ + { 0, 0, 1 }, + { 0, 1, 2 }, + { 0, 2, 4 }, + { 0, 3, 6 }, + { 0, 4, 8 }, + { 0, 5, 10 }, + { 0, 6, 12 }, + { 0, 7, 16 }, + { 0, 8, 32 }, + { 0, 9, 64 }, + { 0, 10, 128 }, + { 0, 11, 256 }, + /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */ + { 1, 0, 1 }, + { 2, 0, 2 }, + { 3, 0, 4 }, +}; + +static int stm32h7_adc_clk_sel(struct platform_device *pdev, + struct stm32_adc_priv *priv) +{ + u32 ckmode, presc, val; + unsigned long rate; + int i, div; + + /* stm32h7 bus clock is common for all ADC instances (mandatory) */ + if (!priv->bclk) { + dev_err(&pdev->dev, "No 'bus' clock found\n"); + return -ENOENT; + } + + /* + * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry. + * So, choice is to have bus clock mandatory and adc clock optional. + * If optional 'adc' clock has been found, then try to use it first. + */ + if (priv->aclk) { + /* + * Asynchronous clock modes (e.g. ckmode == 0) + * From spec: PLL output musn't exceed max rate + */ + rate = clk_get_rate(priv->aclk); + + for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { + ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; + presc = stm32h7_adc_ckmodes_spec[i].presc; + div = stm32h7_adc_ckmodes_spec[i].div; + + if (ckmode) + continue; + + if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE) + goto out; + } + } + + /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */ + rate = clk_get_rate(priv->bclk); + + for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) { + ckmode = stm32h7_adc_ckmodes_spec[i].ckmode; + presc = stm32h7_adc_ckmodes_spec[i].presc; + div = stm32h7_adc_ckmodes_spec[i].div; + + if (!ckmode) + continue; + + if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE) + goto out; + } + + dev_err(&pdev->dev, "adc clk selection failed\n"); + return -EINVAL; + +out: + /* rate used later by each ADC instance to control BOOST mode */ + priv->common.rate = rate; + + /* Set common clock mode and prescaler */ + val = readl_relaxed(priv->common.base + STM32H7_ADC_CCR); + val &= ~(STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK); + val |= ckmode << STM32H7_CKMODE_SHIFT; + val |= presc << STM32H7_PRESC_SHIFT; + writel_relaxed(val, priv->common.base + STM32H7_ADC_CCR); + + dev_dbg(&pdev->dev, "Using %s clock/%d source at %ld kHz\n", + ckmode ? "bus" : "adc", div, rate / (div * 1000)); + + return 0; +} + +/* STM32F4 common registers definitions */ +static const struct stm32_adc_common_regs stm32f4_adc_common_regs = { + .csr = STM32F4_ADC_CSR, + .eoc1_msk = STM32F4_EOC1, + .eoc2_msk = STM32F4_EOC2, + .eoc3_msk = STM32F4_EOC3, +}; + +/* STM32H7 common registers definitions */ +static const struct stm32_adc_common_regs stm32h7_adc_common_regs = { + .csr = STM32H7_ADC_CSR, + .eoc1_msk = STM32H7_EOC_MST, + .eoc2_msk = STM32H7_EOC_SLV, +}; + /* ADC common interrupt for all instances */ static void stm32_adc_irq_handler(struct irq_desc *desc) { @@ -112,15 +288,15 @@ static void stm32_adc_irq_handler(struct irq_desc *desc) u32 status; chained_irq_enter(chip, desc); - status = readl_relaxed(priv->common.base + STM32F4_ADC_CSR); + status = readl_relaxed(priv->common.base + priv->cfg->regs->csr); - if (status & STM32F4_EOC1) + if (status & priv->cfg->regs->eoc1_msk) generic_handle_irq(irq_find_mapping(priv->domain, 0)); - if (status & STM32F4_EOC2) + if (status & priv->cfg->regs->eoc2_msk) generic_handle_irq(irq_find_mapping(priv->domain, 1)); - if (status & STM32F4_EOC3) + if (status & priv->cfg->regs->eoc3_msk) generic_handle_irq(irq_find_mapping(priv->domain, 2)); chained_irq_exit(chip, desc); @@ -186,6 +362,7 @@ static void stm32_adc_irq_remove(struct platform_device *pdev, static int stm32_adc_probe(struct platform_device *pdev) { struct stm32_adc_priv *priv; + struct device *dev = &pdev->dev; struct device_node *np = pdev->dev.of_node; struct resource *res; int ret; @@ -197,6 +374,9 @@ static int stm32_adc_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; + priv->cfg = (const struct stm32_adc_priv_cfg *) + of_match_device(dev->driver->of_match_table, dev)->data; + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); priv->common.base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(priv->common.base)) @@ -227,25 +407,48 @@ static int stm32_adc_probe(struct platform_device *pdev) priv->aclk = devm_clk_get(&pdev->dev, "adc"); if (IS_ERR(priv->aclk)) { ret = PTR_ERR(priv->aclk); - dev_err(&pdev->dev, "Can't get 'adc' clock\n"); - goto err_regulator_disable; + if (ret == -ENOENT) { + priv->aclk = NULL; + } else { + dev_err(&pdev->dev, "Can't get 'adc' clock\n"); + goto err_regulator_disable; + } } - ret = clk_prepare_enable(priv->aclk); - if (ret < 0) { - dev_err(&pdev->dev, "adc clk enable failed\n"); - goto err_regulator_disable; + if (priv->aclk) { + ret = clk_prepare_enable(priv->aclk); + if (ret < 0) { + dev_err(&pdev->dev, "adc clk enable failed\n"); + goto err_regulator_disable; + } } - ret = stm32f4_adc_clk_sel(pdev, priv); - if (ret < 0) { - dev_err(&pdev->dev, "adc clk selection failed\n"); - goto err_clk_disable; + priv->bclk = devm_clk_get(&pdev->dev, "bus"); + if (IS_ERR(priv->bclk)) { + ret = PTR_ERR(priv->bclk); + if (ret == -ENOENT) { + priv->bclk = NULL; + } else { + dev_err(&pdev->dev, "Can't get 'bus' clock\n"); + goto err_aclk_disable; + } + } + + if (priv->bclk) { + ret = clk_prepare_enable(priv->bclk); + if (ret < 0) { + dev_err(&pdev->dev, "adc clk enable failed\n"); + goto err_aclk_disable; + } } + ret = priv->cfg->clk_sel(pdev, priv); + if (ret < 0) + goto err_bclk_disable; + ret = stm32_adc_irq_probe(pdev, priv); if (ret < 0) - goto err_clk_disable; + goto err_bclk_disable; platform_set_drvdata(pdev, &priv->common); @@ -260,8 +463,13 @@ static int stm32_adc_probe(struct platform_device *pdev) err_irq_remove: stm32_adc_irq_remove(pdev, priv); -err_clk_disable: - clk_disable_unprepare(priv->aclk); +err_bclk_disable: + if (priv->bclk) + clk_disable_unprepare(priv->bclk); + +err_aclk_disable: + if (priv->aclk) + clk_disable_unprepare(priv->aclk); err_regulator_disable: regulator_disable(priv->vref); @@ -276,15 +484,34 @@ static int stm32_adc_remove(struct platform_device *pdev) of_platform_depopulate(&pdev->dev); stm32_adc_irq_remove(pdev, priv); - clk_disable_unprepare(priv->aclk); + if (priv->bclk) + clk_disable_unprepare(priv->bclk); + if (priv->aclk) + clk_disable_unprepare(priv->aclk); regulator_disable(priv->vref); return 0; } +static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = { + .regs = &stm32f4_adc_common_regs, + .clk_sel = stm32f4_adc_clk_sel, +}; + +static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = { + .regs = &stm32h7_adc_common_regs, + .clk_sel = stm32h7_adc_clk_sel, +}; + static const struct of_device_id stm32_adc_of_match[] = { - { .compatible = "st,stm32f4-adc-core" }, - {}, + { + .compatible = "st,stm32f4-adc-core", + .data = (void *)&stm32f4_adc_priv_cfg + }, { + .compatible = "st,stm32h7-adc-core", + .data = (void *)&stm32h7_adc_priv_cfg + }, { + }, }; MODULE_DEVICE_TABLE(of, stm32_adc_of_match); diff --git a/drivers/iio/adc/stm32-adc-core.h b/drivers/iio/adc/stm32-adc-core.h index 2ec7abbfbcaa..250ee958a669 100644 --- a/drivers/iio/adc/stm32-adc-core.h +++ b/drivers/iio/adc/stm32-adc-core.h @@ -43,11 +43,13 @@ * struct stm32_adc_common - stm32 ADC driver common data (for all instances) * @base: control registers base cpu addr * @phys_base: control registers base physical addr + * @rate: clock rate used for analog circuitry * @vref_mv: vref voltage (mv) */ struct stm32_adc_common { void __iomem *base; phys_addr_t phys_base; + unsigned long rate; int vref_mv; }; diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c index c28e7ff80e11..5bfcc1f13105 100644 --- a/drivers/iio/adc/stm32-adc.c +++ b/drivers/iio/adc/stm32-adc.c @@ -31,9 +31,11 @@ #include <linux/iio/triggered_buffer.h> #include <linux/interrupt.h> #include <linux/io.h> +#include <linux/iopoll.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/of.h> +#include <linux/of_device.h> #include "stm32-adc-core.h" @@ -76,6 +78,78 @@ #define STM32F4_DMA BIT(8) #define STM32F4_ADON BIT(0) +/* STM32H7 - Registers for each ADC instance */ +#define STM32H7_ADC_ISR 0x00 +#define STM32H7_ADC_IER 0x04 +#define STM32H7_ADC_CR 0x08 +#define STM32H7_ADC_CFGR 0x0C +#define STM32H7_ADC_PCSEL 0x1C +#define STM32H7_ADC_SQR1 0x30 +#define STM32H7_ADC_SQR2 0x34 +#define STM32H7_ADC_SQR3 0x38 +#define STM32H7_ADC_SQR4 0x3C +#define STM32H7_ADC_DR 0x40 +#define STM32H7_ADC_CALFACT 0xC4 +#define STM32H7_ADC_CALFACT2 0xC8 + +/* STM32H7_ADC_ISR - bit fields */ +#define STM32H7_EOC BIT(2) +#define STM32H7_ADRDY BIT(0) + +/* STM32H7_ADC_IER - bit fields */ +#define STM32H7_EOCIE STM32H7_EOC + +/* STM32H7_ADC_CR - bit fields */ +#define STM32H7_ADCAL BIT(31) +#define STM32H7_ADCALDIF BIT(30) +#define STM32H7_DEEPPWD BIT(29) +#define STM32H7_ADVREGEN BIT(28) +#define STM32H7_LINCALRDYW6 BIT(27) +#define STM32H7_LINCALRDYW5 BIT(26) +#define STM32H7_LINCALRDYW4 BIT(25) +#define STM32H7_LINCALRDYW3 BIT(24) +#define STM32H7_LINCALRDYW2 BIT(23) +#define STM32H7_LINCALRDYW1 BIT(22) +#define STM32H7_ADCALLIN BIT(16) +#define STM32H7_BOOST BIT(8) +#define STM32H7_ADSTP BIT(4) +#define STM32H7_ADSTART BIT(2) +#define STM32H7_ADDIS BIT(1) +#define STM32H7_ADEN BIT(0) + +/* STM32H7_ADC_CFGR bit fields */ +#define STM32H7_EXTEN_SHIFT 10 +#define STM32H7_EXTEN_MASK GENMASK(11, 10) +#define STM32H7_EXTSEL_SHIFT 5 +#define STM32H7_EXTSEL_MASK GENMASK(9, 5) +#define STM32H7_RES_SHIFT 2 +#define STM32H7_RES_MASK GENMASK(4, 2) +#define STM32H7_DMNGT_SHIFT 0 +#define STM32H7_DMNGT_MASK GENMASK(1, 0) + +enum stm32h7_adc_dmngt { + STM32H7_DMNGT_DR_ONLY, /* Regular data in DR only */ + STM32H7_DMNGT_DMA_ONESHOT, /* DMA one shot mode */ + STM32H7_DMNGT_DFSDM, /* DFSDM mode */ + STM32H7_DMNGT_DMA_CIRC, /* DMA circular mode */ +}; + +/* STM32H7_ADC_CALFACT - bit fields */ +#define STM32H7_CALFACT_D_SHIFT 16 +#define STM32H7_CALFACT_D_MASK GENMASK(26, 16) +#define STM32H7_CALFACT_S_SHIFT 0 +#define STM32H7_CALFACT_S_MASK GENMASK(10, 0) + +/* STM32H7_ADC_CALFACT2 - bit fields */ +#define STM32H7_LINCALFACT_SHIFT 0 +#define STM32H7_LINCALFACT_MASK GENMASK(29, 0) + +/* Number of linear calibration shadow registers / LINCALRDYW control bits */ +#define STM32H7_LINCALFACT_NUM 6 + +/* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */ +#define STM32H7_BOOST_CLKRATE 20000000UL + #define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */ #define STM32_ADC_TIMEOUT_US 100000 #define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000)) @@ -121,6 +195,18 @@ struct stm32_adc_trig_info { }; /** + * struct stm32_adc_calib - optional adc calibration data + * @calfact_s: Calibration offset for single ended channels + * @calfact_d: Calibration offset in differential + * @lincalfact: Linearity calibration factor + */ +struct stm32_adc_calib { + u32 calfact_s; + u32 calfact_d; + u32 lincalfact[STM32H7_LINCALFACT_NUM]; +}; + +/** * stm32_adc_regs - stm32 ADC misc registers & bitfield desc * @reg: register offset * @mask: bitfield mask @@ -133,9 +219,56 @@ struct stm32_adc_regs { }; /** + * stm32_adc_regspec - stm32 registers definition, compatible dependent data + * @dr: data register offset + * @ier_eoc: interrupt enable register & eocie bitfield + * @isr_eoc: interrupt status register & eoc bitfield + * @sqr: reference to sequence registers array + * @exten: trigger control register & bitfield + * @extsel: trigger selection register & bitfield + * @res: resolution selection register & bitfield + */ +struct stm32_adc_regspec { + const u32 dr; + const struct stm32_adc_regs ier_eoc; + const struct stm32_adc_regs isr_eoc; + const struct stm32_adc_regs *sqr; + const struct stm32_adc_regs exten; + const struct stm32_adc_regs extsel; + const struct stm32_adc_regs res; +}; + +struct stm32_adc; + +/** + * stm32_adc_cfg - stm32 compatible configuration data + * @regs: registers descriptions + * @adc_info: per instance input channels definitions + * @trigs: external trigger sources + * @clk_required: clock is required + * @selfcalib: optional routine for self-calibration + * @prepare: optional prepare routine (power-up, enable) + * @start_conv: routine to start conversions + * @stop_conv: routine to stop conversions + * @unprepare: optional unprepare routine (disable, power-down) + */ +struct stm32_adc_cfg { + const struct stm32_adc_regspec *regs; + const struct stm32_adc_info *adc_info; + struct stm32_adc_trig_info *trigs; + bool clk_required; + int (*selfcalib)(struct stm32_adc *); + int (*prepare)(struct stm32_adc *); + void (*start_conv)(struct stm32_adc *, bool dma); + void (*stop_conv)(struct stm32_adc *); + void (*unprepare)(struct stm32_adc *); +}; + +/** * struct stm32_adc - private data of each ADC IIO instance * @common: reference to ADC block common data * @offset: ADC instance register offset in ADC block + * @cfg: compatible configuration data * @completion: end of single conversion completion * @buffer: data buffer * @clk: clock for this adc instance @@ -149,10 +282,13 @@ struct stm32_adc_regs { * @rx_buf: dma rx buffer cpu address * @rx_dma_buf: dma rx buffer bus address * @rx_buf_sz: dma rx buffer size + * @pcsel bitmask to preselect channels on some devices + * @cal: optional calibration data on some devices */ struct stm32_adc { struct stm32_adc_common *common; u32 offset; + const struct stm32_adc_cfg *cfg; struct completion completion; u16 buffer[STM32_ADC_MAX_SQ]; struct clk *clk; @@ -166,6 +302,8 @@ struct stm32_adc { u8 *rx_buf; dma_addr_t rx_dma_buf; unsigned int rx_buf_sz; + u32 pcsel; + struct stm32_adc_calib cal; }; /** @@ -180,8 +318,26 @@ struct stm32_adc_chan_spec { const char *name; }; -/* Input definitions common for all STM32F4 instances */ -static const struct stm32_adc_chan_spec stm32f4_adc123_channels[] = { +/** + * struct stm32_adc_info - stm32 ADC, per instance config data + * @channels: Reference to stm32 channels spec + * @max_channels: Number of channels + * @resolutions: available resolutions + * @num_res: number of available resolutions + */ +struct stm32_adc_info { + const struct stm32_adc_chan_spec *channels; + int max_channels; + const unsigned int *resolutions; + const unsigned int num_res; +}; + +/* + * Input definitions common for all instances: + * stm32f4 can have up to 16 channels + * stm32h7 can have up to 20 channels + */ +static const struct stm32_adc_chan_spec stm32_adc_channels[] = { { IIO_VOLTAGE, 0, "in0" }, { IIO_VOLTAGE, 1, "in1" }, { IIO_VOLTAGE, 2, "in2" }, @@ -198,6 +354,10 @@ static const struct stm32_adc_chan_spec stm32f4_adc123_channels[] = { { IIO_VOLTAGE, 13, "in13" }, { IIO_VOLTAGE, 14, "in14" }, { IIO_VOLTAGE, 15, "in15" }, + { IIO_VOLTAGE, 16, "in16" }, + { IIO_VOLTAGE, 17, "in17" }, + { IIO_VOLTAGE, 18, "in18" }, + { IIO_VOLTAGE, 19, "in19" }, }; static const unsigned int stm32f4_adc_resolutions[] = { @@ -205,6 +365,25 @@ static const unsigned int stm32f4_adc_resolutions[] = { 12, 10, 8, 6, }; +static const struct stm32_adc_info stm32f4_adc_info = { + .channels = stm32_adc_channels, + .max_channels = 16, + .resolutions = stm32f4_adc_resolutions, + .num_res = ARRAY_SIZE(stm32f4_adc_resolutions), +}; + +static const unsigned int stm32h7_adc_resolutions[] = { + /* sorted values so the index matches RES[2:0] in STM32H7_ADC_CFGR */ + 16, 14, 12, 10, 8, +}; + +static const struct stm32_adc_info stm32h7_adc_info = { + .channels = stm32_adc_channels, + .max_channels = 20, + .resolutions = stm32h7_adc_resolutions, + .num_res = ARRAY_SIZE(stm32h7_adc_resolutions), +}; + /** * stm32f4_sq - describe regular sequence registers * - L: sequence len (register & bit field) @@ -252,6 +431,69 @@ static struct stm32_adc_trig_info stm32f4_adc_trigs[] = { {}, /* sentinel */ }; +static const struct stm32_adc_regspec stm32f4_adc_regspec = { + .dr = STM32F4_ADC_DR, + .ier_eoc = { STM32F4_ADC_CR1, STM32F4_EOCIE }, + .isr_eoc = { STM32F4_ADC_SR, STM32F4_EOC }, + .sqr = stm32f4_sq, + .exten = { STM32F4_ADC_CR2, STM32F4_EXTEN_MASK, STM32F4_EXTEN_SHIFT }, + .extsel = { STM32F4_ADC_CR2, STM32F4_EXTSEL_MASK, + STM32F4_EXTSEL_SHIFT }, + .res = { STM32F4_ADC_CR1, STM32F4_RES_MASK, STM32F4_RES_SHIFT }, +}; + +static const struct stm32_adc_regs stm32h7_sq[STM32_ADC_MAX_SQ + 1] = { + /* L: len bit field description to be kept as first element */ + { STM32H7_ADC_SQR1, GENMASK(3, 0), 0 }, + /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */ + { STM32H7_ADC_SQR1, GENMASK(10, 6), 6 }, + { STM32H7_ADC_SQR1, GENMASK(16, 12), 12 }, + { STM32H7_ADC_SQR1, GENMASK(22, 18), 18 }, + { STM32H7_ADC_SQR1, GENMASK(28, 24), 24 }, + { STM32H7_ADC_SQR2, GENMASK(4, 0), 0 }, + { STM32H7_ADC_SQR2, GENMASK(10, 6), 6 }, + { STM32H7_ADC_SQR2, GENMASK(16, 12), 12 }, + { STM32H7_ADC_SQR2, GENMASK(22, 18), 18 }, + { STM32H7_ADC_SQR2, GENMASK(28, 24), 24 }, + { STM32H7_ADC_SQR3, GENMASK(4, 0), 0 }, + { STM32H7_ADC_SQR3, GENMASK(10, 6), 6 }, + { STM32H7_ADC_SQR3, GENMASK(16, 12), 12 }, + { STM32H7_ADC_SQR3, GENMASK(22, 18), 18 }, + { STM32H7_ADC_SQR3, GENMASK(28, 24), 24 }, + { STM32H7_ADC_SQR4, GENMASK(4, 0), 0 }, + { STM32H7_ADC_SQR4, GENMASK(10, 6), 6 }, +}; + +/* STM32H7 external trigger sources for all instances */ +static struct stm32_adc_trig_info stm32h7_adc_trigs[] = { + { TIM1_CH1, STM32_EXT0 }, + { TIM1_CH2, STM32_EXT1 }, + { TIM1_CH3, STM32_EXT2 }, + { TIM2_CH2, STM32_EXT3 }, + { TIM3_TRGO, STM32_EXT4 }, + { TIM4_CH4, STM32_EXT5 }, + { TIM8_TRGO, STM32_EXT7 }, + { TIM8_TRGO2, STM32_EXT8 }, + { TIM1_TRGO, STM32_EXT9 }, + { TIM1_TRGO2, STM32_EXT10 }, + { TIM2_TRGO, STM32_EXT11 }, + { TIM4_TRGO, STM32_EXT12 }, + { TIM6_TRGO, STM32_EXT13 }, + { TIM3_CH4, STM32_EXT15 }, + {}, +}; + +static const struct stm32_adc_regspec stm32h7_adc_regspec = { + .dr = STM32H7_ADC_DR, + .ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE }, + .isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC }, + .sqr = stm32h7_sq, + .exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT }, + .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK, + STM32H7_EXTSEL_SHIFT }, + .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT }, +}; + /** * STM32 ADC registers access routines * @adc: stm32 adc instance @@ -265,6 +507,12 @@ static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg) return readl_relaxed(adc->common->base + adc->offset + reg); } +#define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr) + +#define stm32_adc_readl_poll_timeout(reg, val, cond, sleep_us, timeout_us) \ + readx_poll_timeout(stm32_adc_readl_addr, reg, val, \ + cond, sleep_us, timeout_us) + static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg) { return readw_relaxed(adc->common->base + adc->offset + reg); @@ -299,7 +547,8 @@ static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits) */ static void stm32_adc_conv_irq_enable(struct stm32_adc *adc) { - stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_EOCIE); + stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg, + adc->cfg->regs->ier_eoc.mask); }; /** @@ -308,19 +557,22 @@ static void stm32_adc_conv_irq_enable(struct stm32_adc *adc) */ static void stm32_adc_conv_irq_disable(struct stm32_adc *adc) { - stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_EOCIE); + stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg, + adc->cfg->regs->ier_eoc.mask); } static void stm32_adc_set_res(struct stm32_adc *adc) { - u32 val = stm32_adc_readl(adc, STM32F4_ADC_CR1); + const struct stm32_adc_regs *res = &adc->cfg->regs->res; + u32 val; - val = (val & ~STM32F4_RES_MASK) | (adc->res << STM32F4_RES_SHIFT); - stm32_adc_writel(adc, STM32F4_ADC_CR1, val); + val = stm32_adc_readl(adc, res->reg); + val = (val & ~res->mask) | (adc->res << res->shift); + stm32_adc_writel(adc, res->reg, val); } /** - * stm32_adc_start_conv() - Start conversions for regular channels. + * stm32f4_adc_start_conv() - Start conversions for regular channels. * @adc: stm32 adc instance * @dma: use dma to transfer conversion result * @@ -329,7 +581,7 @@ static void stm32_adc_set_res(struct stm32_adc *adc) * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct * DR read instead (e.g. read_raw, or triggered buffer mode without DMA). */ -static void stm32_adc_start_conv(struct stm32_adc *adc, bool dma) +static void stm32f4_adc_start_conv(struct stm32_adc *adc, bool dma) { stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); @@ -347,7 +599,7 @@ static void stm32_adc_start_conv(struct stm32_adc *adc, bool dma) stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART); } -static void stm32_adc_stop_conv(struct stm32_adc *adc) +static void stm32f4_adc_stop_conv(struct stm32_adc *adc) { stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK); stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT); @@ -357,6 +609,324 @@ static void stm32_adc_stop_conv(struct stm32_adc *adc) STM32F4_ADON | STM32F4_DMA | STM32F4_DDS); } +static void stm32h7_adc_start_conv(struct stm32_adc *adc, bool dma) +{ + enum stm32h7_adc_dmngt dmngt; + unsigned long flags; + u32 val; + + if (dma) + dmngt = STM32H7_DMNGT_DMA_CIRC; + else + dmngt = STM32H7_DMNGT_DR_ONLY; + + spin_lock_irqsave(&adc->lock, flags); + val = stm32_adc_readl(adc, STM32H7_ADC_CFGR); + val = (val & ~STM32H7_DMNGT_MASK) | (dmngt << STM32H7_DMNGT_SHIFT); + stm32_adc_writel(adc, STM32H7_ADC_CFGR, val); + spin_unlock_irqrestore(&adc->lock, flags); + + stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART); +} + +static void stm32h7_adc_stop_conv(struct stm32_adc *adc) +{ + struct iio_dev *indio_dev = iio_priv_to_dev(adc); + int ret; + u32 val; + + stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP); + + ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, + !(val & (STM32H7_ADSTART)), + 100, STM32_ADC_TIMEOUT_US); + if (ret) + dev_warn(&indio_dev->dev, "stop failed\n"); + + stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK); +} + +static void stm32h7_adc_exit_pwr_down(struct stm32_adc *adc) +{ + /* Exit deep power down, then enable ADC voltage regulator */ + stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); + stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN); + + if (adc->common->rate > STM32H7_BOOST_CLKRATE) + stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); + + /* Wait for startup time */ + usleep_range(10, 20); +} + +static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc) +{ + stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); + + /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */ + stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); +} + +static int stm32h7_adc_enable(struct stm32_adc *adc) +{ + struct iio_dev *indio_dev = iio_priv_to_dev(adc); + int ret; + u32 val; + + /* Clear ADRDY by writing one, then enable ADC */ + stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY); + stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN); + + /* Poll for ADRDY to be set (after adc startup time) */ + ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val, + val & STM32H7_ADRDY, + 100, STM32_ADC_TIMEOUT_US); + if (ret) { + stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN); + dev_err(&indio_dev->dev, "Failed to enable ADC\n"); + } + + return ret; +} + +static void stm32h7_adc_disable(struct stm32_adc *adc) +{ + struct iio_dev *indio_dev = iio_priv_to_dev(adc); + int ret; + u32 val; + + /* Disable ADC and wait until it's effectively disabled */ + stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); + ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, + !(val & STM32H7_ADEN), 100, + STM32_ADC_TIMEOUT_US); + if (ret) + dev_warn(&indio_dev->dev, "Failed to disable\n"); +} + +/** + * stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result + * @adc: stm32 adc instance + */ +static int stm32h7_adc_read_selfcalib(struct stm32_adc *adc) +{ + struct iio_dev *indio_dev = iio_priv_to_dev(adc); + int i, ret; + u32 lincalrdyw_mask, val; + + /* Enable adc so LINCALRDYW1..6 bits are writable */ + ret = stm32h7_adc_enable(adc); + if (ret) + return ret; + + /* Read linearity calibration */ + lincalrdyw_mask = STM32H7_LINCALRDYW6; + for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { + /* Clear STM32H7_LINCALRDYW[6..1]: transfer calib to CALFACT2 */ + stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); + + /* Poll: wait calib data to be ready in CALFACT2 register */ + ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, + !(val & lincalrdyw_mask), + 100, STM32_ADC_TIMEOUT_US); + if (ret) { + dev_err(&indio_dev->dev, "Failed to read calfact\n"); + goto disable; + } + + val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); + adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK); + adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT; + + lincalrdyw_mask >>= 1; + } + + /* Read offset calibration */ + val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT); + adc->cal.calfact_s = (val & STM32H7_CALFACT_S_MASK); + adc->cal.calfact_s >>= STM32H7_CALFACT_S_SHIFT; + adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK); + adc->cal.calfact_d >>= STM32H7_CALFACT_D_SHIFT; + +disable: + stm32h7_adc_disable(adc); + + return ret; +} + +/** + * stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result + * @adc: stm32 adc instance + * Note: ADC must be enabled, with no on-going conversions. + */ +static int stm32h7_adc_restore_selfcalib(struct stm32_adc *adc) +{ + struct iio_dev *indio_dev = iio_priv_to_dev(adc); + int i, ret; + u32 lincalrdyw_mask, val; + + val = (adc->cal.calfact_s << STM32H7_CALFACT_S_SHIFT) | + (adc->cal.calfact_d << STM32H7_CALFACT_D_SHIFT); + stm32_adc_writel(adc, STM32H7_ADC_CALFACT, val); + + lincalrdyw_mask = STM32H7_LINCALRDYW6; + for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { + /* + * Write saved calibration data to shadow registers: + * Write CALFACT2, and set LINCALRDYW[6..1] bit to trigger + * data write. Then poll to wait for complete transfer. + */ + val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT; + stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val); + stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); + ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, + val & lincalrdyw_mask, + 100, STM32_ADC_TIMEOUT_US); + if (ret) { + dev_err(&indio_dev->dev, "Failed to write calfact\n"); + return ret; + } + + /* + * Read back calibration data, has two effects: + * - It ensures bits LINCALRDYW[6..1] are kept cleared + * for next time calibration needs to be restored. + * - BTW, bit clear triggers a read, then check data has been + * correctly written. + */ + stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); + ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, + !(val & lincalrdyw_mask), + 100, STM32_ADC_TIMEOUT_US); + if (ret) { + dev_err(&indio_dev->dev, "Failed to read calfact\n"); + return ret; + } + val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); + if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) { + dev_err(&indio_dev->dev, "calfact not consistent\n"); + return -EIO; + } + + lincalrdyw_mask >>= 1; + } + + return 0; +} + +/** + * Fixed timeout value for ADC calibration. + * worst cases: + * - low clock frequency + * - maximum prescalers + * Calibration requires: + * - 131,072 ADC clock cycle for the linear calibration + * - 20 ADC clock cycle for the offset calibration + * + * Set to 100ms for now + */ +#define STM32H7_ADC_CALIB_TIMEOUT_US 100000 + +/** + * stm32h7_adc_selfcalib() - Procedure to calibrate ADC (from power down) + * @adc: stm32 adc instance + * Exit from power down, calibrate ADC, then return to power down. + */ +static int stm32h7_adc_selfcalib(struct stm32_adc *adc) +{ + struct iio_dev *indio_dev = iio_priv_to_dev(adc); + int ret; + u32 val; + + stm32h7_adc_exit_pwr_down(adc); + + /* + * Select calibration mode: + * - Offset calibration for single ended inputs + * - No linearity calibration (do it later, before reading it) + */ + stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALDIF); + stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALLIN); + + /* Start calibration, then wait for completion */ + stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); + ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, + !(val & STM32H7_ADCAL), 100, + STM32H7_ADC_CALIB_TIMEOUT_US); + if (ret) { + dev_err(&indio_dev->dev, "calibration failed\n"); + goto pwr_dwn; + } + + /* + * Select calibration mode, then start calibration: + * - Offset calibration for differential input + * - Linearity calibration (needs to be done only once for single/diff) + * will run simultaneously with offset calibration. + */ + stm32_adc_set_bits(adc, STM32H7_ADC_CR, + STM32H7_ADCALDIF | STM32H7_ADCALLIN); + stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); + ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, + !(val & STM32H7_ADCAL), 100, + STM32H7_ADC_CALIB_TIMEOUT_US); + if (ret) { + dev_err(&indio_dev->dev, "calibration failed\n"); + goto pwr_dwn; + } + + stm32_adc_clr_bits(adc, STM32H7_ADC_CR, + STM32H7_ADCALDIF | STM32H7_ADCALLIN); + + /* Read calibration result for future reference */ + ret = stm32h7_adc_read_selfcalib(adc); + +pwr_dwn: + stm32h7_adc_enter_pwr_down(adc); + + return ret; +} + +/** + * stm32h7_adc_prepare() - Leave power down mode to enable ADC. + * @adc: stm32 adc instance + * Leave power down mode. + * Enable ADC. + * Restore calibration data. + * Pre-select channels that may be used in PCSEL (required by input MUX / IO). + */ +static int stm32h7_adc_prepare(struct stm32_adc *adc) +{ + int ret; + + stm32h7_adc_exit_pwr_down(adc); + + ret = stm32h7_adc_enable(adc); + if (ret) + goto pwr_dwn; + + ret = stm32h7_adc_restore_selfcalib(adc); + if (ret) + goto disable; + + stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel); + + return 0; + +disable: + stm32h7_adc_disable(adc); +pwr_dwn: + stm32h7_adc_enter_pwr_down(adc); + + return ret; +} + +static void stm32h7_adc_unprepare(struct stm32_adc *adc) +{ + stm32h7_adc_disable(adc); + stm32h7_adc_enter_pwr_down(adc); +} + /** * stm32_adc_conf_scan_seq() - Build regular channels scan sequence * @indio_dev: IIO device @@ -371,6 +941,7 @@ static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev, const unsigned long *scan_mask) { struct stm32_adc *adc = iio_priv(indio_dev); + const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr; const struct iio_chan_spec *chan; u32 val, bit; int i = 0; @@ -388,20 +959,20 @@ static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev, dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n", __func__, chan->channel, i); - val = stm32_adc_readl(adc, stm32f4_sq[i].reg); - val &= ~stm32f4_sq[i].mask; - val |= chan->channel << stm32f4_sq[i].shift; - stm32_adc_writel(adc, stm32f4_sq[i].reg, val); + val = stm32_adc_readl(adc, sqr[i].reg); + val &= ~sqr[i].mask; + val |= chan->channel << sqr[i].shift; + stm32_adc_writel(adc, sqr[i].reg, val); } if (!i) return -EINVAL; /* Sequence len */ - val = stm32_adc_readl(adc, stm32f4_sq[0].reg); - val &= ~stm32f4_sq[0].mask; - val |= ((i - 1) << stm32f4_sq[0].shift); - stm32_adc_writel(adc, stm32f4_sq[0].reg, val); + val = stm32_adc_readl(adc, sqr[0].reg); + val &= ~sqr[0].mask; + val |= ((i - 1) << sqr[0].shift); + stm32_adc_writel(adc, sqr[0].reg, val); return 0; } @@ -412,19 +983,21 @@ static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev, * * Returns trigger extsel value, if trig matches, -EINVAL otherwise. */ -static int stm32_adc_get_trig_extsel(struct iio_trigger *trig) +static int stm32_adc_get_trig_extsel(struct iio_dev *indio_dev, + struct iio_trigger *trig) { + struct stm32_adc *adc = iio_priv(indio_dev); int i; /* lookup triggers registered by stm32 timer trigger driver */ - for (i = 0; stm32f4_adc_trigs[i].name; i++) { + for (i = 0; adc->cfg->trigs[i].name; i++) { /** * Checking both stm32 timer trigger type and trig name * should be safe against arbitrary trigger names. */ if (is_stm32_timer_trigger(trig) && - !strcmp(stm32f4_adc_trigs[i].name, trig->name)) { - return stm32f4_adc_trigs[i].extsel; + !strcmp(adc->cfg->trigs[i].name, trig->name)) { + return adc->cfg->trigs[i].extsel; } } @@ -449,7 +1022,7 @@ static int stm32_adc_set_trig(struct iio_dev *indio_dev, int ret; if (trig) { - ret = stm32_adc_get_trig_extsel(trig); + ret = stm32_adc_get_trig_extsel(indio_dev, trig); if (ret < 0) return ret; @@ -459,11 +1032,11 @@ static int stm32_adc_set_trig(struct iio_dev *indio_dev, } spin_lock_irqsave(&adc->lock, flags); - val = stm32_adc_readl(adc, STM32F4_ADC_CR2); - val &= ~(STM32F4_EXTEN_MASK | STM32F4_EXTSEL_MASK); - val |= exten << STM32F4_EXTEN_SHIFT; - val |= extsel << STM32F4_EXTSEL_SHIFT; - stm32_adc_writel(adc, STM32F4_ADC_CR2, val); + val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg); + val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask); + val |= exten << adc->cfg->regs->exten.shift; + val |= extsel << adc->cfg->regs->extsel.shift; + stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val); spin_unlock_irqrestore(&adc->lock, flags); return 0; @@ -515,6 +1088,7 @@ static int stm32_adc_single_conv(struct iio_dev *indio_dev, int *res) { struct stm32_adc *adc = iio_priv(indio_dev); + const struct stm32_adc_regspec *regs = adc->cfg->regs; long timeout; u32 val; int ret; @@ -523,21 +1097,27 @@ static int stm32_adc_single_conv(struct iio_dev *indio_dev, adc->bufi = 0; + if (adc->cfg->prepare) { + ret = adc->cfg->prepare(adc); + if (ret) + return ret; + } + /* Program chan number in regular sequence (SQ1) */ - val = stm32_adc_readl(adc, stm32f4_sq[1].reg); - val &= ~stm32f4_sq[1].mask; - val |= chan->channel << stm32f4_sq[1].shift; - stm32_adc_writel(adc, stm32f4_sq[1].reg, val); + val = stm32_adc_readl(adc, regs->sqr[1].reg); + val &= ~regs->sqr[1].mask; + val |= chan->channel << regs->sqr[1].shift; + stm32_adc_writel(adc, regs->sqr[1].reg, val); /* Set regular sequence len (0 for 1 conversion) */ - stm32_adc_clr_bits(adc, stm32f4_sq[0].reg, stm32f4_sq[0].mask); + stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask); /* Trigger detection disabled (conversion can be launched in SW) */ - stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK); + stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask); stm32_adc_conv_irq_enable(adc); - stm32_adc_start_conv(adc, false); + adc->cfg->start_conv(adc, false); timeout = wait_for_completion_interruptible_timeout( &adc->completion, STM32_ADC_TIMEOUT); @@ -550,10 +1130,13 @@ static int stm32_adc_single_conv(struct iio_dev *indio_dev, ret = IIO_VAL_INT; } - stm32_adc_stop_conv(adc); + adc->cfg->stop_conv(adc); stm32_adc_conv_irq_disable(adc); + if (adc->cfg->unprepare) + adc->cfg->unprepare(adc); + return ret; } @@ -590,11 +1173,12 @@ static irqreturn_t stm32_adc_isr(int irq, void *data) { struct stm32_adc *adc = data; struct iio_dev *indio_dev = iio_priv_to_dev(adc); - u32 status = stm32_adc_readl(adc, STM32F4_ADC_SR); + const struct stm32_adc_regspec *regs = adc->cfg->regs; + u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); - if (status & STM32F4_EOC) { + if (status & regs->isr_eoc.mask) { /* Reading DR also clears EOC status flag */ - adc->buffer[adc->bufi] = stm32_adc_readw(adc, STM32F4_ADC_DR); + adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr); if (iio_buffer_enabled(indio_dev)) { adc->bufi++; if (adc->bufi >= adc->num_conv) { @@ -621,7 +1205,7 @@ static irqreturn_t stm32_adc_isr(int irq, void *data) static int stm32_adc_validate_trigger(struct iio_dev *indio_dev, struct iio_trigger *trig) { - return stm32_adc_get_trig_extsel(trig) < 0 ? -EINVAL : 0; + return stm32_adc_get_trig_extsel(indio_dev, trig) < 0 ? -EINVAL : 0; } static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val) @@ -777,10 +1361,16 @@ static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev) struct stm32_adc *adc = iio_priv(indio_dev); int ret; + if (adc->cfg->prepare) { + ret = adc->cfg->prepare(adc); + if (ret) + return ret; + } + ret = stm32_adc_set_trig(indio_dev, indio_dev->trig); if (ret) { dev_err(&indio_dev->dev, "Can't set trigger\n"); - return ret; + goto err_unprepare; } ret = stm32_adc_dma_start(indio_dev); @@ -799,7 +1389,7 @@ static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev) if (!adc->dma_chan) stm32_adc_conv_irq_enable(adc); - stm32_adc_start_conv(adc, !!adc->dma_chan); + adc->cfg->start_conv(adc, !!adc->dma_chan); return 0; @@ -808,6 +1398,9 @@ err_stop_dma: dmaengine_terminate_all(adc->dma_chan); err_clr_trig: stm32_adc_set_trig(indio_dev, NULL); +err_unprepare: + if (adc->cfg->unprepare) + adc->cfg->unprepare(adc); return ret; } @@ -817,7 +1410,7 @@ static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev) struct stm32_adc *adc = iio_priv(indio_dev); int ret; - stm32_adc_stop_conv(adc); + adc->cfg->stop_conv(adc); if (!adc->dma_chan) stm32_adc_conv_irq_disable(adc); @@ -831,6 +1424,9 @@ static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev) if (stm32_adc_set_trig(indio_dev, NULL)) dev_err(&indio_dev->dev, "Can't clear trigger\n"); + if (adc->cfg->unprepare) + adc->cfg->unprepare(adc); + return ret; } @@ -895,12 +1491,12 @@ static int stm32_adc_of_get_resolution(struct iio_dev *indio_dev) u32 res; if (of_property_read_u32(node, "assigned-resolution-bits", &res)) - res = stm32f4_adc_resolutions[0]; + res = adc->cfg->adc_info->resolutions[0]; - for (i = 0; i < ARRAY_SIZE(stm32f4_adc_resolutions); i++) - if (res == stm32f4_adc_resolutions[i]) + for (i = 0; i < adc->cfg->adc_info->num_res; i++) + if (res == adc->cfg->adc_info->resolutions[i]) break; - if (i >= ARRAY_SIZE(stm32f4_adc_resolutions)) { + if (i >= adc->cfg->adc_info->num_res) { dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res); return -EINVAL; } @@ -926,14 +1522,19 @@ static void stm32_adc_chan_init_one(struct iio_dev *indio_dev, chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); chan->scan_type.sign = 'u'; - chan->scan_type.realbits = stm32f4_adc_resolutions[adc->res]; + chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res]; chan->scan_type.storagebits = 16; chan->ext_info = stm32_adc_ext_info; + + /* pre-build selected channels mask */ + adc->pcsel |= BIT(chan->channel); } static int stm32_adc_chan_of_init(struct iio_dev *indio_dev) { struct device_node *node = indio_dev->dev.of_node; + struct stm32_adc *adc = iio_priv(indio_dev); + const struct stm32_adc_info *adc_info = adc->cfg->adc_info; struct property *prop; const __be32 *cur; struct iio_chan_spec *channels; @@ -942,7 +1543,7 @@ static int stm32_adc_chan_of_init(struct iio_dev *indio_dev) num_channels = of_property_count_u32_elems(node, "st,adc-channels"); if (num_channels < 0 || - num_channels >= ARRAY_SIZE(stm32f4_adc123_channels)) { + num_channels >= adc_info->max_channels) { dev_err(&indio_dev->dev, "Bad st,adc-channels?\n"); return num_channels < 0 ? num_channels : -EINVAL; } @@ -953,12 +1554,12 @@ static int stm32_adc_chan_of_init(struct iio_dev *indio_dev) return -ENOMEM; of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) { - if (val >= ARRAY_SIZE(stm32f4_adc123_channels)) { + if (val >= adc_info->max_channels) { dev_err(&indio_dev->dev, "Invalid channel %d\n", val); return -EINVAL; } stm32_adc_chan_init_one(indio_dev, &channels[scan_index], - &stm32f4_adc123_channels[val], + &adc_info->channels[val], scan_index); scan_index++; } @@ -990,7 +1591,7 @@ static int stm32_adc_dma_request(struct iio_dev *indio_dev) /* Configure DMA channel to read data register */ memset(&config, 0, sizeof(config)); config.src_addr = (dma_addr_t)adc->common->phys_base; - config.src_addr += adc->offset + STM32F4_ADC_DR; + config.src_addr += adc->offset + adc->cfg->regs->dr; config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; ret = dmaengine_slave_config(adc->dma_chan, &config); @@ -1011,6 +1612,7 @@ err_release: static int stm32_adc_probe(struct platform_device *pdev) { struct iio_dev *indio_dev; + struct device *dev = &pdev->dev; struct stm32_adc *adc; int ret; @@ -1025,6 +1627,8 @@ static int stm32_adc_probe(struct platform_device *pdev) adc->common = dev_get_drvdata(pdev->dev.parent); spin_lock_init(&adc->lock); init_completion(&adc->completion); + adc->cfg = (const struct stm32_adc_cfg *) + of_match_device(dev->driver->of_match_table, dev)->data; indio_dev->name = dev_name(&pdev->dev); indio_dev->dev.parent = &pdev->dev; @@ -1055,14 +1659,21 @@ static int stm32_adc_probe(struct platform_device *pdev) adc->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(adc->clk)) { - dev_err(&pdev->dev, "Can't get clock\n"); - return PTR_ERR(adc->clk); + ret = PTR_ERR(adc->clk); + if (ret == -ENOENT && !adc->cfg->clk_required) { + adc->clk = NULL; + } else { + dev_err(&pdev->dev, "Can't get clock\n"); + return ret; + } } - ret = clk_prepare_enable(adc->clk); - if (ret < 0) { - dev_err(&pdev->dev, "clk enable failed\n"); - return ret; + if (adc->clk) { + ret = clk_prepare_enable(adc->clk); + if (ret < 0) { + dev_err(&pdev->dev, "clk enable failed\n"); + return ret; + } } ret = stm32_adc_of_get_resolution(indio_dev); @@ -1070,6 +1681,12 @@ static int stm32_adc_probe(struct platform_device *pdev) goto err_clk_disable; stm32_adc_set_res(adc); + if (adc->cfg->selfcalib) { + ret = adc->cfg->selfcalib(adc); + if (ret) + goto err_clk_disable; + } + ret = stm32_adc_chan_of_init(indio_dev); if (ret < 0) goto err_clk_disable; @@ -1106,7 +1723,8 @@ err_dma_disable: dma_release_channel(adc->dma_chan); } err_clk_disable: - clk_disable_unprepare(adc->clk); + if (adc->clk) + clk_disable_unprepare(adc->clk); return ret; } @@ -1124,13 +1742,35 @@ static int stm32_adc_remove(struct platform_device *pdev) adc->rx_buf, adc->rx_dma_buf); dma_release_channel(adc->dma_chan); } - clk_disable_unprepare(adc->clk); + if (adc->clk) + clk_disable_unprepare(adc->clk); return 0; } +static const struct stm32_adc_cfg stm32f4_adc_cfg = { + .regs = &stm32f4_adc_regspec, + .adc_info = &stm32f4_adc_info, + .trigs = stm32f4_adc_trigs, + .clk_required = true, + .start_conv = stm32f4_adc_start_conv, + .stop_conv = stm32f4_adc_stop_conv, +}; + +static const struct stm32_adc_cfg stm32h7_adc_cfg = { + .regs = &stm32h7_adc_regspec, + .adc_info = &stm32h7_adc_info, + .trigs = stm32h7_adc_trigs, + .selfcalib = stm32h7_adc_selfcalib, + .start_conv = stm32h7_adc_start_conv, + .stop_conv = stm32h7_adc_stop_conv, + .prepare = stm32h7_adc_prepare, + .unprepare = stm32h7_adc_unprepare, +}; + static const struct of_device_id stm32_adc_of_match[] = { - { .compatible = "st,stm32f4-adc" }, + { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg }, + { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg }, {}, }; MODULE_DEVICE_TABLE(of, stm32_adc_of_match); diff --git a/drivers/iio/adc/ti-adc084s021.c b/drivers/iio/adc/ti-adc084s021.c new file mode 100644 index 000000000000..a355121c11a4 --- /dev/null +++ b/drivers/iio/adc/ti-adc084s021.c @@ -0,0 +1,275 @@ +/** + * Copyright (C) 2017 Axis Communications AB + * + * Driver for Texas Instruments' ADC084S021 ADC chip. + * Datasheets can be found here: + * http://www.ti.com/lit/ds/symlink/adc084s021.pdf + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/err.h> +#include <linux/spi/spi.h> +#include <linux/module.h> +#include <linux/interrupt.h> +#include <linux/iio/iio.h> +#include <linux/iio/buffer.h> +#include <linux/iio/triggered_buffer.h> +#include <linux/iio/trigger_consumer.h> +#include <linux/regulator/consumer.h> + +#define ADC084S021_DRIVER_NAME "adc084s021" + +struct adc084s021 { + struct spi_device *spi; + struct spi_message message; + struct spi_transfer spi_trans; + struct regulator *reg; + struct mutex lock; + /* + * DMA (thus cache coherency maintenance) requires the + * transfer buffers to live in their own cache line. + */ + u16 tx_buf[4] ____cacheline_aligned; + __be16 rx_buf[5]; /* First 16-bits are trash */ +}; + +#define ADC084S021_VOLTAGE_CHANNEL(num) \ + { \ + .type = IIO_VOLTAGE, \ + .channel = (num), \ + .indexed = 1, \ + .scan_index = (num), \ + .scan_type = { \ + .sign = 'u', \ + .realbits = 8, \ + .storagebits = 16, \ + .shift = 4, \ + .endianness = IIO_BE, \ + }, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),\ + } + +static const struct iio_chan_spec adc084s021_channels[] = { + ADC084S021_VOLTAGE_CHANNEL(0), + ADC084S021_VOLTAGE_CHANNEL(1), + ADC084S021_VOLTAGE_CHANNEL(2), + ADC084S021_VOLTAGE_CHANNEL(3), + IIO_CHAN_SOFT_TIMESTAMP(4), +}; + +/** + * Read an ADC channel and return its value. + * + * @adc: The ADC SPI data. + * @data: Buffer for converted data. + */ +static int adc084s021_adc_conversion(struct adc084s021 *adc, void *data) +{ + int n_words = (adc->spi_trans.len >> 1) - 1; /* Discard first word */ + int ret, i = 0; + u16 *p = data; + + /* Do the transfer */ + ret = spi_sync(adc->spi, &adc->message); + if (ret < 0) + return ret; + + for (; i < n_words; i++) + *(p + i) = adc->rx_buf[i + 1]; + + return ret; +} + +static int adc084s021_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *channel, int *val, + int *val2, long mask) +{ + struct adc084s021 *adc = iio_priv(indio_dev); + int ret; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + ret = iio_device_claim_direct_mode(indio_dev); + if (ret < 0) + return ret; + + ret = regulator_enable(adc->reg); + if (ret) { + iio_device_release_direct_mode(indio_dev); + return ret; + } + + adc->tx_buf[0] = channel->channel << 3; + ret = adc084s021_adc_conversion(adc, val); + iio_device_release_direct_mode(indio_dev); + regulator_disable(adc->reg); + if (ret < 0) + return ret; + + *val = be16_to_cpu(*val); + *val = (*val >> channel->scan_type.shift) & 0xff; + + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + ret = regulator_enable(adc->reg); + if (ret) + return ret; + + ret = regulator_get_voltage(adc->reg); + regulator_disable(adc->reg); + if (ret < 0) + return ret; + + *val = ret / 1000; + + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +/** + * Read enabled ADC channels and push data to the buffer. + * + * @irq: The interrupt number (not used). + * @pollfunc: Pointer to the poll func. + */ +static irqreturn_t adc084s021_buffer_trigger_handler(int irq, void *pollfunc) +{ + struct iio_poll_func *pf = pollfunc; + struct iio_dev *indio_dev = pf->indio_dev; + struct adc084s021 *adc = iio_priv(indio_dev); + __be16 data[8] = {0}; /* 4 * 16-bit words of data + 8 bytes timestamp */ + + mutex_lock(&adc->lock); + + if (adc084s021_adc_conversion(adc, &data) < 0) + dev_err(&adc->spi->dev, "Failed to read data\n"); + + iio_push_to_buffers_with_timestamp(indio_dev, data, + iio_get_time_ns(indio_dev)); + mutex_unlock(&adc->lock); + iio_trigger_notify_done(indio_dev->trig); + + return IRQ_HANDLED; +} + +static int adc084s021_buffer_preenable(struct iio_dev *indio_dev) +{ + struct adc084s021 *adc = iio_priv(indio_dev); + int scan_index; + int i = 0; + + for_each_set_bit(scan_index, indio_dev->active_scan_mask, + indio_dev->masklength) { + const struct iio_chan_spec *channel = + &indio_dev->channels[scan_index]; + adc->tx_buf[i++] = channel->channel << 3; + } + adc->spi_trans.len = 2 + (i * sizeof(__be16)); /* Trash + channels */ + + return regulator_enable(adc->reg); +} + +static int adc084s021_buffer_postdisable(struct iio_dev *indio_dev) +{ + struct adc084s021 *adc = iio_priv(indio_dev); + + adc->spi_trans.len = 4; /* Trash + single channel */ + + return regulator_disable(adc->reg); +} + +static const struct iio_info adc084s021_info = { + .read_raw = adc084s021_read_raw, + .driver_module = THIS_MODULE, +}; + +static const struct iio_buffer_setup_ops adc084s021_buffer_setup_ops = { + .preenable = adc084s021_buffer_preenable, + .postenable = iio_triggered_buffer_postenable, + .predisable = iio_triggered_buffer_predisable, + .postdisable = adc084s021_buffer_postdisable, +}; + +static int adc084s021_probe(struct spi_device *spi) +{ + struct iio_dev *indio_dev; + struct adc084s021 *adc; + int ret; + + indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc)); + if (!indio_dev) { + dev_err(&spi->dev, "Failed to allocate IIO device\n"); + return -ENOMEM; + } + + adc = iio_priv(indio_dev); + adc->spi = spi; + + /* Connect the SPI device and the iio dev */ + spi_set_drvdata(spi, indio_dev); + + /* Initiate the Industrial I/O device */ + indio_dev->dev.parent = &spi->dev; + indio_dev->dev.of_node = spi->dev.of_node; + indio_dev->name = spi_get_device_id(spi)->name; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->info = &adc084s021_info; + indio_dev->channels = adc084s021_channels; + indio_dev->num_channels = ARRAY_SIZE(adc084s021_channels); + + /* Create SPI transfer for channel reads */ + adc->spi_trans.tx_buf = adc->tx_buf; + adc->spi_trans.rx_buf = adc->rx_buf; + adc->spi_trans.len = 4; /* Trash + single channel */ + spi_message_init_with_transfers(&adc->message, &adc->spi_trans, 1); + + adc->reg = devm_regulator_get(&spi->dev, "vref"); + if (IS_ERR(adc->reg)) + return PTR_ERR(adc->reg); + + mutex_init(&adc->lock); + + /* Setup triggered buffer with pollfunction */ + ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL, + adc084s021_buffer_trigger_handler, + &adc084s021_buffer_setup_ops); + if (ret) { + dev_err(&spi->dev, "Failed to setup triggered buffer\n"); + return ret; + } + + return devm_iio_device_register(&spi->dev, indio_dev); +} + +static const struct of_device_id adc084s021_of_match[] = { + { .compatible = "ti,adc084s021", }, + {}, +}; +MODULE_DEVICE_TABLE(of, adc084s021_of_match); + +static const struct spi_device_id adc084s021_id[] = { + { ADC084S021_DRIVER_NAME, 0}, + {} +}; +MODULE_DEVICE_TABLE(spi, adc084s021_id); + +static struct spi_driver adc084s021_driver = { + .driver = { + .name = ADC084S021_DRIVER_NAME, + .of_match_table = of_match_ptr(adc084s021_of_match), + }, + .probe = adc084s021_probe, + .id_table = adc084s021_id, +}; +module_spi_driver(adc084s021_driver); + +MODULE_AUTHOR("MÃ¥rten Lindahl <martenli@axis.com>"); +MODULE_DESCRIPTION("Texas Instruments ADC084S021"); +MODULE_LICENSE("GPL v2"); +MODULE_VERSION("1.0"); diff --git a/drivers/iio/adc/ti-adc108s102.c b/drivers/iio/adc/ti-adc108s102.c new file mode 100644 index 000000000000..de4e5ac98c6e --- /dev/null +++ b/drivers/iio/adc/ti-adc108s102.c @@ -0,0 +1,348 @@ +/* + * TI ADC108S102 SPI ADC driver + * + * Copyright (c) 2013-2015 Intel Corporation. + * Copyright (c) 2017 Siemens AG + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * This IIO device driver is designed to work with the following + * analog to digital converters from Texas Instruments: + * ADC108S102 + * ADC128S102 + * The communication with ADC chip is via the SPI bus (mode 3). + */ + +#include <linux/acpi.h> +#include <linux/iio/iio.h> +#include <linux/iio/buffer.h> +#include <linux/iio/types.h> +#include <linux/iio/triggered_buffer.h> +#include <linux/iio/trigger_consumer.h> +#include <linux/interrupt.h> +#include <linux/module.h> +#include <linux/property.h> +#include <linux/regulator/consumer.h> +#include <linux/spi/spi.h> + +/* + * In case of ACPI, we use the hard-wired 5000 mV of the Galileo and IOT2000 + * boards as default for the reference pin VA. Device tree users encode that + * via the vref-supply regulator. + */ +#define ADC108S102_VA_MV_ACPI_DEFAULT 5000 + +/* + * Defining the ADC resolution being 12 bits, we can use the same driver for + * both ADC108S102 (10 bits resolution) and ADC128S102 (12 bits resolution) + * chips. The ADC108S102 effectively returns a 12-bit result with the 2 + * least-significant bits unset. + */ +#define ADC108S102_BITS 12 +#define ADC108S102_MAX_CHANNELS 8 + +/* + * 16-bit SPI command format: + * [15:14] Ignored + * [13:11] 3-bit channel address + * [10:0] Ignored + */ +#define ADC108S102_CMD(ch) ((u16)(ch) << 11) + +/* + * 16-bit SPI response format: + * [15:12] Zeros + * [11:0] 12-bit ADC sample (for ADC108S102, [1:0] will always be 0). + */ +#define ADC108S102_RES_DATA(res) ((u16)res & GENMASK(11, 0)) + +struct adc108s102_state { + struct spi_device *spi; + struct regulator *reg; + u32 va_millivolt; + /* SPI transfer used by triggered buffer handler*/ + struct spi_transfer ring_xfer; + /* SPI transfer used by direct scan */ + struct spi_transfer scan_single_xfer; + /* SPI message used by ring_xfer SPI transfer */ + struct spi_message ring_msg; + /* SPI message used by scan_single_xfer SPI transfer */ + struct spi_message scan_single_msg; + + /* + * SPI message buffers: + * tx_buf: |C0|C1|C2|C3|C4|C5|C6|C7|XX| + * rx_buf: |XX|R0|R1|R2|R3|R4|R5|R6|R7|tt|tt|tt|tt| + * + * tx_buf: 8 channel read commands, plus 1 dummy command + * rx_buf: 1 dummy response, 8 channel responses, plus 64-bit timestamp + */ + __be16 rx_buf[13] ____cacheline_aligned; + __be16 tx_buf[9] ____cacheline_aligned; +}; + +#define ADC108S102_V_CHAN(index) \ + { \ + .type = IIO_VOLTAGE, \ + .indexed = 1, \ + .channel = index, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ + BIT(IIO_CHAN_INFO_SCALE), \ + .address = index, \ + .scan_index = index, \ + .scan_type = { \ + .sign = 'u', \ + .realbits = ADC108S102_BITS, \ + .storagebits = 16, \ + .endianness = IIO_BE, \ + }, \ + } + +static const struct iio_chan_spec adc108s102_channels[] = { + ADC108S102_V_CHAN(0), + ADC108S102_V_CHAN(1), + ADC108S102_V_CHAN(2), + ADC108S102_V_CHAN(3), + ADC108S102_V_CHAN(4), + ADC108S102_V_CHAN(5), + ADC108S102_V_CHAN(6), + ADC108S102_V_CHAN(7), + IIO_CHAN_SOFT_TIMESTAMP(8), +}; + +static int adc108s102_update_scan_mode(struct iio_dev *indio_dev, + unsigned long const *active_scan_mask) +{ + struct adc108s102_state *st = iio_priv(indio_dev); + unsigned int bit, cmds; + + /* + * Fill in the first x shorts of tx_buf with the number of channels + * enabled for sampling by the triggered buffer. + */ + cmds = 0; + for_each_set_bit(bit, active_scan_mask, ADC108S102_MAX_CHANNELS) + st->tx_buf[cmds++] = cpu_to_be16(ADC108S102_CMD(bit)); + + /* One dummy command added, to clock in the last response */ + st->tx_buf[cmds++] = 0x00; + + /* build SPI ring message */ + st->ring_xfer.tx_buf = &st->tx_buf[0]; + st->ring_xfer.rx_buf = &st->rx_buf[0]; + st->ring_xfer.len = cmds * sizeof(st->tx_buf[0]); + + spi_message_init_with_transfers(&st->ring_msg, &st->ring_xfer, 1); + + return 0; +} + +static irqreturn_t adc108s102_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf = p; + struct iio_dev *indio_dev = pf->indio_dev; + struct adc108s102_state *st = iio_priv(indio_dev); + int ret; + + ret = spi_sync(st->spi, &st->ring_msg); + if (ret < 0) + goto out_notify; + + /* Skip the dummy response in the first slot */ + iio_push_to_buffers_with_timestamp(indio_dev, + (u8 *)&st->rx_buf[1], + iio_get_time_ns(indio_dev)); + +out_notify: + iio_trigger_notify_done(indio_dev->trig); + + return IRQ_HANDLED; +} + +static int adc108s102_scan_direct(struct adc108s102_state *st, unsigned int ch) +{ + int ret; + + st->tx_buf[0] = cpu_to_be16(ADC108S102_CMD(ch)); + ret = spi_sync(st->spi, &st->scan_single_msg); + if (ret) + return ret; + + /* Skip the dummy response in the first slot */ + return be16_to_cpu(st->rx_buf[1]); +} + +static int adc108s102_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long m) +{ + struct adc108s102_state *st = iio_priv(indio_dev); + int ret; + + switch (m) { + case IIO_CHAN_INFO_RAW: + ret = iio_device_claim_direct_mode(indio_dev); + if (ret) + return ret; + + ret = adc108s102_scan_direct(st, chan->address); + + iio_device_release_direct_mode(indio_dev); + + if (ret < 0) + return ret; + + *val = ADC108S102_RES_DATA(ret); + + return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: + if (chan->type != IIO_VOLTAGE) + break; + + *val = st->va_millivolt; + *val2 = chan->scan_type.realbits; + + return IIO_VAL_FRACTIONAL_LOG2; + default: + break; + } + + return -EINVAL; +} + +static const struct iio_info adc108s102_info = { + .read_raw = &adc108s102_read_raw, + .update_scan_mode = &adc108s102_update_scan_mode, + .driver_module = THIS_MODULE, +}; + +static int adc108s102_probe(struct spi_device *spi) +{ + struct adc108s102_state *st; + struct iio_dev *indio_dev; + int ret; + + indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st = iio_priv(indio_dev); + + if (ACPI_COMPANION(&spi->dev)) { + st->va_millivolt = ADC108S102_VA_MV_ACPI_DEFAULT; + } else { + st->reg = devm_regulator_get(&spi->dev, "vref"); + if (IS_ERR(st->reg)) + return PTR_ERR(st->reg); + + ret = regulator_enable(st->reg); + if (ret < 0) { + dev_err(&spi->dev, "Cannot enable vref regulator\n"); + return ret; + } + + ret = regulator_get_voltage(st->reg); + if (ret < 0) { + dev_err(&spi->dev, "vref get voltage failed\n"); + return ret; + } + + st->va_millivolt = ret / 1000; + } + + spi_set_drvdata(spi, indio_dev); + st->spi = spi; + + indio_dev->name = spi->modalias; + indio_dev->dev.parent = &spi->dev; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->channels = adc108s102_channels; + indio_dev->num_channels = ARRAY_SIZE(adc108s102_channels); + indio_dev->info = &adc108s102_info; + + /* Setup default message */ + st->scan_single_xfer.tx_buf = st->tx_buf; + st->scan_single_xfer.rx_buf = st->rx_buf; + st->scan_single_xfer.len = 2 * sizeof(st->tx_buf[0]); + + spi_message_init_with_transfers(&st->scan_single_msg, + &st->scan_single_xfer, 1); + + ret = iio_triggered_buffer_setup(indio_dev, NULL, + &adc108s102_trigger_handler, NULL); + if (ret) + goto error_disable_reg; + + ret = iio_device_register(indio_dev); + if (ret) { + dev_err(&spi->dev, "Failed to register IIO device\n"); + goto error_cleanup_triggered_buffer; + } + return 0; + +error_cleanup_triggered_buffer: + iio_triggered_buffer_cleanup(indio_dev); + +error_disable_reg: + regulator_disable(st->reg); + + return ret; +} + +static int adc108s102_remove(struct spi_device *spi) +{ + struct iio_dev *indio_dev = spi_get_drvdata(spi); + struct adc108s102_state *st = iio_priv(indio_dev); + + iio_device_unregister(indio_dev); + iio_triggered_buffer_cleanup(indio_dev); + + regulator_disable(st->reg); + + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id adc108s102_of_match[] = { + { .compatible = "ti,adc108s102" }, + { } +}; +MODULE_DEVICE_TABLE(of, adc108s102_of_match); +#endif + +#ifdef CONFIG_ACPI +static const struct acpi_device_id adc108s102_acpi_ids[] = { + { "INT3495", 0 }, + { } +}; +MODULE_DEVICE_TABLE(acpi, adc108s102_acpi_ids); +#endif + +static const struct spi_device_id adc108s102_id[] = { + { "adc108s102", 0 }, + { } +}; +MODULE_DEVICE_TABLE(spi, adc108s102_id); + +static struct spi_driver adc108s102_driver = { + .driver = { + .name = "adc108s102", + .of_match_table = of_match_ptr(adc108s102_of_match), + .acpi_match_table = ACPI_PTR(adc108s102_acpi_ids), + }, + .probe = adc108s102_probe, + .remove = adc108s102_remove, + .id_table = adc108s102_id, +}; +module_spi_driver(adc108s102_driver); + +MODULE_AUTHOR("Bogdan Pricop <bogdan.pricop@emutex.com>"); +MODULE_DESCRIPTION("Texas Instruments ADC108S102 and ADC128S102 driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/iio/adc/twl4030-madc.c b/drivers/iio/adc/twl4030-madc.c index 0c74869a540a..bd3d37fc2144 100644 --- a/drivers/iio/adc/twl4030-madc.c +++ b/drivers/iio/adc/twl4030-madc.c @@ -36,7 +36,6 @@ #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/i2c/twl.h> -#include <linux/i2c/twl4030-madc.h> #include <linux/module.h> #include <linux/stddef.h> #include <linux/mutex.h> @@ -49,9 +48,121 @@ #include <linux/iio/iio.h> +#define TWL4030_MADC_MAX_CHANNELS 16 + +#define TWL4030_MADC_CTRL1 0x00 +#define TWL4030_MADC_CTRL2 0x01 + +#define TWL4030_MADC_RTSELECT_LSB 0x02 +#define TWL4030_MADC_SW1SELECT_LSB 0x06 +#define TWL4030_MADC_SW2SELECT_LSB 0x0A + +#define TWL4030_MADC_RTAVERAGE_LSB 0x04 +#define TWL4030_MADC_SW1AVERAGE_LSB 0x08 +#define TWL4030_MADC_SW2AVERAGE_LSB 0x0C + +#define TWL4030_MADC_CTRL_SW1 0x12 +#define TWL4030_MADC_CTRL_SW2 0x13 + +#define TWL4030_MADC_RTCH0_LSB 0x17 +#define TWL4030_MADC_GPCH0_LSB 0x37 + +#define TWL4030_MADC_MADCON (1 << 0) /* MADC power on */ +#define TWL4030_MADC_BUSY (1 << 0) /* MADC busy */ +/* MADC conversion completion */ +#define TWL4030_MADC_EOC_SW (1 << 1) +/* MADC SWx start conversion */ +#define TWL4030_MADC_SW_START (1 << 5) +#define TWL4030_MADC_ADCIN0 (1 << 0) +#define TWL4030_MADC_ADCIN1 (1 << 1) +#define TWL4030_MADC_ADCIN2 (1 << 2) +#define TWL4030_MADC_ADCIN3 (1 << 3) +#define TWL4030_MADC_ADCIN4 (1 << 4) +#define TWL4030_MADC_ADCIN5 (1 << 5) +#define TWL4030_MADC_ADCIN6 (1 << 6) +#define TWL4030_MADC_ADCIN7 (1 << 7) +#define TWL4030_MADC_ADCIN8 (1 << 8) +#define TWL4030_MADC_ADCIN9 (1 << 9) +#define TWL4030_MADC_ADCIN10 (1 << 10) +#define TWL4030_MADC_ADCIN11 (1 << 11) +#define TWL4030_MADC_ADCIN12 (1 << 12) +#define TWL4030_MADC_ADCIN13 (1 << 13) +#define TWL4030_MADC_ADCIN14 (1 << 14) +#define TWL4030_MADC_ADCIN15 (1 << 15) + +/* Fixed channels */ +#define TWL4030_MADC_BTEMP TWL4030_MADC_ADCIN1 +#define TWL4030_MADC_VBUS TWL4030_MADC_ADCIN8 +#define TWL4030_MADC_VBKB TWL4030_MADC_ADCIN9 +#define TWL4030_MADC_ICHG TWL4030_MADC_ADCIN10 +#define TWL4030_MADC_VCHG TWL4030_MADC_ADCIN11 +#define TWL4030_MADC_VBAT TWL4030_MADC_ADCIN12 + +/* Step size and prescaler ratio */ +#define TEMP_STEP_SIZE 147 +#define TEMP_PSR_R 100 +#define CURR_STEP_SIZE 147 +#define CURR_PSR_R1 44 +#define CURR_PSR_R2 88 + +#define TWL4030_BCI_BCICTL1 0x23 +#define TWL4030_BCI_CGAIN 0x020 +#define TWL4030_BCI_MESBAT (1 << 1) +#define TWL4030_BCI_TYPEN (1 << 4) +#define TWL4030_BCI_ITHEN (1 << 3) + +#define REG_BCICTL2 0x024 +#define TWL4030_BCI_ITHSENS 0x007 + +/* Register and bits for GPBR1 register */ +#define TWL4030_REG_GPBR1 0x0c +#define TWL4030_GPBR1_MADC_HFCLK_EN (1 << 7) + #define TWL4030_USB_SEL_MADC_MCPC (1<<3) #define TWL4030_USB_CARKIT_ANA_CTRL 0xBB +struct twl4030_madc_conversion_method { + u8 sel; + u8 avg; + u8 rbase; + u8 ctrl; +}; + +/** + * struct twl4030_madc_request - madc request packet for channel conversion + * @channels: 16 bit bitmap for individual channels + * @do_avg: sample the input channel for 4 consecutive cycles + * @method: RT, SW1, SW2 + * @type: Polling or interrupt based method + * @active: Flag if request is active + * @result_pending: Flag from irq handler, that result is ready + * @raw: Return raw value, do not convert it + * @rbuf: Result buffer + */ +struct twl4030_madc_request { + unsigned long channels; + bool do_avg; + u16 method; + u16 type; + bool active; + bool result_pending; + bool raw; + int rbuf[TWL4030_MADC_MAX_CHANNELS]; +}; + +enum conversion_methods { + TWL4030_MADC_RT, + TWL4030_MADC_SW1, + TWL4030_MADC_SW2, + TWL4030_MADC_NUM_METHODS +}; + +enum sample_type { + TWL4030_MADC_WAIT, + TWL4030_MADC_IRQ_ONESHOT, + TWL4030_MADC_IRQ_REARM +}; + /** * struct twl4030_madc_data - a container for madc info * @dev: Pointer to device structure for madc @@ -72,6 +183,8 @@ struct twl4030_madc_data { u8 isr; }; +static int twl4030_madc_conversion(struct twl4030_madc_request *req); + static int twl4030_madc_read(struct iio_dev *iio_dev, const struct iio_chan_spec *chan, int *val, int *val2, long mask) @@ -84,7 +197,6 @@ static int twl4030_madc_read(struct iio_dev *iio_dev, req.channels = BIT(chan->channel); req.active = false; - req.func_cb = NULL; req.type = TWL4030_MADC_WAIT; req.raw = !(mask == IIO_CHAN_INFO_PROCESSED); req.do_avg = (mask == IIO_CHAN_INFO_AVERAGE_RAW); @@ -341,37 +453,6 @@ static int twl4030_madc_read_channels(struct twl4030_madc_data *madc, } /* - * Enables irq. - * @madc - pointer to twl4030_madc_data struct - * @id - irq number to be enabled - * can take one of TWL4030_MADC_RT, TWL4030_MADC_SW1, TWL4030_MADC_SW2 - * corresponding to RT, SW1, SW2 conversion requests. - * If the i2c read fails it returns an error else returns 0. - */ -static int twl4030_madc_enable_irq(struct twl4030_madc_data *madc, u8 id) -{ - u8 val; - int ret; - - ret = twl_i2c_read_u8(TWL4030_MODULE_MADC, &val, madc->imr); - if (ret) { - dev_err(madc->dev, "unable to read imr register 0x%X\n", - madc->imr); - return ret; - } - - val &= ~(1 << id); - ret = twl_i2c_write_u8(TWL4030_MODULE_MADC, val, madc->imr); - if (ret) { - dev_err(madc->dev, - "unable to write imr register 0x%X\n", madc->imr); - return ret; - } - - return 0; -} - -/* * Disables irq. * @madc - pointer to twl4030_madc_data struct * @id - irq number to be disabled @@ -440,11 +521,6 @@ static irqreturn_t twl4030_madc_threaded_irq_handler(int irq, void *_madc) /* Read results */ len = twl4030_madc_read_channels(madc, method->rbase, r->channels, r->rbuf, r->raw); - /* Return results to caller */ - if (r->func_cb != NULL) { - r->func_cb(len, r->channels, r->rbuf); - r->func_cb = NULL; - } /* Free request */ r->result_pending = 0; r->active = 0; @@ -466,11 +542,6 @@ err_i2c: /* Read results */ len = twl4030_madc_read_channels(madc, method->rbase, r->channels, r->rbuf, r->raw); - /* Return results to caller */ - if (r->func_cb != NULL) { - r->func_cb(len, r->channels, r->rbuf); - r->func_cb = NULL; - } /* Free request */ r->result_pending = 0; r->active = 0; @@ -480,23 +551,6 @@ err_i2c: return IRQ_HANDLED; } -static int twl4030_madc_set_irq(struct twl4030_madc_data *madc, - struct twl4030_madc_request *req) -{ - struct twl4030_madc_request *p; - int ret; - - p = &madc->requests[req->method]; - memcpy(p, req, sizeof(*req)); - ret = twl4030_madc_enable_irq(madc, req->method); - if (ret < 0) { - dev_err(madc->dev, "enable irq failed!!\n"); - return ret; - } - - return 0; -} - /* * Function which enables the madc conversion * by writing to the control register. @@ -568,7 +622,7 @@ static int twl4030_madc_wait_conversion_ready(struct twl4030_madc_data *madc, * be a negative error value in the corresponding array element. * returns 0 if succeeds else error value */ -int twl4030_madc_conversion(struct twl4030_madc_request *req) +static int twl4030_madc_conversion(struct twl4030_madc_request *req) { const struct twl4030_madc_conversion_method *method; int ret; @@ -605,17 +659,6 @@ int twl4030_madc_conversion(struct twl4030_madc_request *req) goto out; } } - if (req->type == TWL4030_MADC_IRQ_ONESHOT && req->func_cb != NULL) { - ret = twl4030_madc_set_irq(twl4030_madc, req); - if (ret < 0) - goto out; - ret = twl4030_madc_start_conversion(twl4030_madc, req->method); - if (ret < 0) - goto out; - twl4030_madc->requests[req->method].active = 1; - ret = 0; - goto out; - } /* With RT method we should not be here anymore */ if (req->method == TWL4030_MADC_RT) { ret = -EINVAL; @@ -640,28 +683,6 @@ out: return ret; } -EXPORT_SYMBOL_GPL(twl4030_madc_conversion); - -int twl4030_get_madc_conversion(int channel_no) -{ - struct twl4030_madc_request req; - int temp = 0; - int ret; - - req.channels = (1 << channel_no); - req.method = TWL4030_MADC_SW2; - req.active = 0; - req.raw = 0; - req.func_cb = NULL; - ret = twl4030_madc_conversion(&req); - if (ret < 0) - return ret; - if (req.rbuf[channel_no] > 0) - temp = req.rbuf[channel_no]; - - return temp; -} -EXPORT_SYMBOL_GPL(twl4030_get_madc_conversion); /** * twl4030_madc_set_current_generator() - setup bias current diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c index 56cf5907a5f0..4a60497a1f19 100644 --- a/drivers/iio/adc/xilinx-xadc-core.c +++ b/drivers/iio/adc/xilinx-xadc-core.c @@ -1204,7 +1204,10 @@ static int xadc_probe(struct platform_device *pdev) ret = PTR_ERR(xadc->clk); goto err_free_samplerate_trigger; } - clk_prepare_enable(xadc->clk); + + ret = clk_prepare_enable(xadc->clk); + if (ret) + goto err_free_samplerate_trigger; ret = xadc->ops->setup(pdev, indio_dev, irq); if (ret) diff --git a/drivers/iio/common/hid-sensors/Kconfig b/drivers/iio/common/hid-sensors/Kconfig index 39188b72cd3b..80105378b0ba 100644 --- a/drivers/iio/common/hid-sensors/Kconfig +++ b/drivers/iio/common/hid-sensors/Kconfig @@ -16,7 +16,7 @@ config HID_SENSOR_IIO_COMMON config HID_SENSOR_IIO_TRIGGER tristate "Common module (trigger) for all HID Sensor IIO drivers" - depends on HID_SENSOR_HUB && HID_SENSOR_IIO_COMMON + depends on HID_SENSOR_HUB && HID_SENSOR_IIO_COMMON && IIO_BUFFER select IIO_TRIGGER help Say yes here to build trigger support for HID sensors. diff --git a/drivers/iio/common/hid-sensors/hid-sensor-attributes.c b/drivers/iio/common/hid-sensors/hid-sensor-attributes.c index 1c0874cdf665..f5d4d786e193 100644 --- a/drivers/iio/common/hid-sensors/hid-sensor-attributes.c +++ b/drivers/iio/common/hid-sensors/hid-sensor-attributes.c @@ -69,6 +69,12 @@ static struct { {HID_USAGE_SENSOR_TIME_TIMESTAMP, HID_USAGE_SENSOR_UNITS_MILLISECOND, 1000000, 0}, + {HID_USAGE_SENSOR_DEVICE_ORIENTATION, 0, 1, 0}, + + {HID_USAGE_SENSOR_RELATIVE_ORIENTATION, 0, 1, 0}, + + {HID_USAGE_SENSOR_GEOMAGNETIC_ORIENTATION, 0, 1, 0}, + {HID_USAGE_SENSOR_TEMPERATURE, 0, 1000, 0}, {HID_USAGE_SENSOR_TEMPERATURE, HID_USAGE_SENSOR_UNITS_DEGREES, 1000, 0}, @@ -230,7 +236,7 @@ int hid_sensor_write_samp_freq_value(struct hid_sensor_common *st, ret = sensor_hub_set_feature(st->hsdev, st->poll.report_id, st->poll.index, sizeof(value), &value); if (ret < 0 || value < 0) - ret = -EINVAL; + return -EINVAL; ret = sensor_hub_get_feature(st->hsdev, st->poll.report_id, @@ -283,7 +289,7 @@ int hid_sensor_write_raw_hyst_value(struct hid_sensor_common *st, st->sensitivity.index, sizeof(value), &value); if (ret < 0 || value < 0) - ret = -EINVAL; + return -EINVAL; ret = sensor_hub_get_feature(st->hsdev, st->sensitivity.report_id, @@ -404,6 +410,48 @@ int hid_sensor_get_reporting_interval(struct hid_sensor_hub_device *hsdev, } +static void hid_sensor_get_report_latency_info(struct hid_sensor_hub_device *hsdev, + u32 usage_id, + struct hid_sensor_common *st) +{ + sensor_hub_input_get_attribute_info(hsdev, HID_FEATURE_REPORT, + usage_id, + HID_USAGE_SENSOR_PROP_REPORT_LATENCY, + &st->report_latency); + + hid_dbg(hsdev->hdev, "Report latency attributes: %x:%x\n", + st->report_latency.index, st->report_latency.report_id); +} + +int hid_sensor_get_report_latency(struct hid_sensor_common *st) +{ + int ret; + int value; + + ret = sensor_hub_get_feature(st->hsdev, st->report_latency.report_id, + st->report_latency.index, sizeof(value), + &value); + if (ret < 0) + return ret; + + return value; +} +EXPORT_SYMBOL(hid_sensor_get_report_latency); + +int hid_sensor_set_report_latency(struct hid_sensor_common *st, int latency_ms) +{ + return sensor_hub_set_feature(st->hsdev, st->report_latency.report_id, + st->report_latency.index, + sizeof(latency_ms), &latency_ms); +} +EXPORT_SYMBOL(hid_sensor_set_report_latency); + +bool hid_sensor_batch_mode_supported(struct hid_sensor_common *st) +{ + return st->report_latency.index > 0 && st->report_latency.report_id > 0; +} +EXPORT_SYMBOL(hid_sensor_batch_mode_supported); + int hid_sensor_parse_common_attributes(struct hid_sensor_hub_device *hsdev, u32 usage_id, struct hid_sensor_common *st) @@ -445,6 +493,8 @@ int hid_sensor_parse_common_attributes(struct hid_sensor_hub_device *hsdev, } else st->timestamp_ns_scale = 1000000000; + hid_sensor_get_report_latency_info(hsdev, usage_id, st); + hid_dbg(hsdev->hdev, "common attributes: %x:%x, %x:%x, %x:%x %x:%x %x:%x\n", st->poll.index, st->poll.report_id, st->report_state.index, st->report_state.report_id, diff --git a/drivers/iio/common/hid-sensors/hid-sensor-trigger.c b/drivers/iio/common/hid-sensors/hid-sensor-trigger.c index 0b5dea050239..16ade0a0327b 100644 --- a/drivers/iio/common/hid-sensors/hid-sensor-trigger.c +++ b/drivers/iio/common/hid-sensors/hid-sensor-trigger.c @@ -26,9 +26,84 @@ #include <linux/hid-sensor-hub.h> #include <linux/iio/iio.h> #include <linux/iio/trigger.h> +#include <linux/iio/buffer.h> #include <linux/iio/sysfs.h> #include "hid-sensor-trigger.h" +static ssize_t _hid_sensor_set_report_latency(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); + struct hid_sensor_common *attrb = iio_device_get_drvdata(indio_dev); + int integer, fract, ret; + int latency; + + ret = iio_str_to_fixpoint(buf, 100000, &integer, &fract); + if (ret) + return ret; + + latency = integer * 1000 + fract / 1000; + ret = hid_sensor_set_report_latency(attrb, latency); + if (ret < 0) + return len; + + attrb->latency_ms = hid_sensor_get_report_latency(attrb); + + return len; +} + +static ssize_t _hid_sensor_get_report_latency(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); + struct hid_sensor_common *attrb = iio_device_get_drvdata(indio_dev); + int latency; + + latency = hid_sensor_get_report_latency(attrb); + if (latency < 0) + return latency; + + return sprintf(buf, "%d.%06u\n", latency / 1000, (latency % 1000) * 1000); +} + +static ssize_t _hid_sensor_get_fifo_state(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); + struct hid_sensor_common *attrb = iio_device_get_drvdata(indio_dev); + int latency; + + latency = hid_sensor_get_report_latency(attrb); + if (latency < 0) + return latency; + + return sprintf(buf, "%d\n", !!latency); +} + +static IIO_DEVICE_ATTR(hwfifo_timeout, 0644, + _hid_sensor_get_report_latency, + _hid_sensor_set_report_latency, 0); +static IIO_DEVICE_ATTR(hwfifo_enabled, 0444, + _hid_sensor_get_fifo_state, NULL, 0); + +static const struct attribute *hid_sensor_fifo_attributes[] = { + &iio_dev_attr_hwfifo_timeout.dev_attr.attr, + &iio_dev_attr_hwfifo_enabled.dev_attr.attr, + NULL, +}; + +static void hid_sensor_setup_batch_mode(struct iio_dev *indio_dev, + struct hid_sensor_common *st) +{ + if (!hid_sensor_batch_mode_supported(st)) + return; + + iio_buffer_set_attrs(indio_dev->buffer, hid_sensor_fifo_attributes); +} + static int _hid_sensor_power_state(struct hid_sensor_common *st, bool state) { int state_val; @@ -141,6 +216,9 @@ static void hid_sensor_set_power_work(struct work_struct *work) sizeof(attrb->raw_hystersis), &attrb->raw_hystersis); + if (attrb->latency_ms > 0) + hid_sensor_set_report_latency(attrb, attrb->latency_ms); + _hid_sensor_power_state(attrb, true); } @@ -192,6 +270,8 @@ int hid_sensor_setup_trigger(struct iio_dev *indio_dev, const char *name, attrb->trigger = trig; indio_dev->trig = iio_trigger_get(trig); + hid_sensor_setup_batch_mode(indio_dev, attrb); + ret = pm_runtime_set_active(&indio_dev->dev); if (ret) goto error_unreg_trigger; diff --git a/drivers/iio/dac/Kconfig b/drivers/iio/dac/Kconfig index df5abc46cd3f..25bed2d7d2b9 100644 --- a/drivers/iio/dac/Kconfig +++ b/drivers/iio/dac/Kconfig @@ -13,7 +13,8 @@ config AD5064 AD5045, AD5064, AD5064-1, AD5065, AD5625, AD5625R, AD5627, AD5627R, AD5628, AD5629R, AD5645R, AD5647R, AD5648, AD5665, AD5665R, AD5666, AD5667, AD5667R, AD5668, AD5669R, LTC2606, LTC2607, LTC2609, LTC2616, - LTC2617, LTC2619, LTC2626, LTC2627, LTC2629 Digital to Analog Converter. + LTC2617, LTC2619, LTC2626, LTC2627, LTC2629, LTC2631, LTC2633, LTC2635 + Digital to Analog Converter. To compile this driver as a module, choose M here: the module will be called ad5064. diff --git a/drivers/iio/dac/ad5064.c b/drivers/iio/dac/ad5064.c index 6803e4a137cd..3f9399c27869 100644 --- a/drivers/iio/dac/ad5064.c +++ b/drivers/iio/dac/ad5064.c @@ -2,8 +2,8 @@ * AD5024, AD5025, AD5044, AD5045, AD5064, AD5064-1, AD5065, AD5625, AD5625R, * AD5627, AD5627R, AD5628, AD5629R, AD5645R, AD5647R, AD5648, AD5665, AD5665R, * AD5666, AD5667, AD5667R, AD5668, AD5669R, LTC2606, LTC2607, LTC2609, LTC2616, - * LTC2617, LTC2619, LTC2626, LTC2627, LTC2629 Digital to analog converters - * driver + * LTC2617, LTC2619, LTC2626, LTC2627, LTC2629, LTC2631, LTC2633, LTC2635 + * Digital to analog converters driver * * Copyright 2011 Analog Devices Inc. * @@ -168,6 +168,24 @@ enum ad5064_type { ID_LTC2626, ID_LTC2627, ID_LTC2629, + ID_LTC2631_L12, + ID_LTC2631_H12, + ID_LTC2631_L10, + ID_LTC2631_H10, + ID_LTC2631_L8, + ID_LTC2631_H8, + ID_LTC2633_L12, + ID_LTC2633_H12, + ID_LTC2633_L10, + ID_LTC2633_H10, + ID_LTC2633_L8, + ID_LTC2633_H8, + ID_LTC2635_L12, + ID_LTC2635_H12, + ID_LTC2635_L10, + ID_LTC2635_H10, + ID_LTC2635_L8, + ID_LTC2635_H8, }; static int ad5064_write(struct ad5064_state *st, unsigned int cmd, @@ -425,6 +443,19 @@ static DECLARE_AD5064_CHANNELS(ad5669_channels, 16, 0, ad5064_ext_info); static DECLARE_AD5064_CHANNELS(ltc2607_channels, 16, 0, ltc2617_ext_info); static DECLARE_AD5064_CHANNELS(ltc2617_channels, 14, 2, ltc2617_ext_info); static DECLARE_AD5064_CHANNELS(ltc2627_channels, 12, 4, ltc2617_ext_info); +#define ltc2631_12_channels ltc2627_channels +static DECLARE_AD5064_CHANNELS(ltc2631_10_channels, 10, 6, ltc2617_ext_info); +static DECLARE_AD5064_CHANNELS(ltc2631_8_channels, 8, 8, ltc2617_ext_info); + +#define LTC2631_INFO(vref, pchannels, nchannels) \ + { \ + .shared_vref = true, \ + .internal_vref = vref, \ + .channels = pchannels, \ + .num_channels = nchannels, \ + .regmap_type = AD5064_REGMAP_LTC, \ + } + static const struct ad5064_chip_info ad5064_chip_info_tbl[] = { [ID_AD5024] = { @@ -724,6 +755,24 @@ static const struct ad5064_chip_info ad5064_chip_info_tbl[] = { .num_channels = 4, .regmap_type = AD5064_REGMAP_LTC, }, + [ID_LTC2631_L12] = LTC2631_INFO(2500000, ltc2631_12_channels, 1), + [ID_LTC2631_H12] = LTC2631_INFO(4096000, ltc2631_12_channels, 1), + [ID_LTC2631_L10] = LTC2631_INFO(2500000, ltc2631_10_channels, 1), + [ID_LTC2631_H10] = LTC2631_INFO(4096000, ltc2631_10_channels, 1), + [ID_LTC2631_L8] = LTC2631_INFO(2500000, ltc2631_8_channels, 1), + [ID_LTC2631_H8] = LTC2631_INFO(4096000, ltc2631_8_channels, 1), + [ID_LTC2633_L12] = LTC2631_INFO(2500000, ltc2631_12_channels, 2), + [ID_LTC2633_H12] = LTC2631_INFO(4096000, ltc2631_12_channels, 2), + [ID_LTC2633_L10] = LTC2631_INFO(2500000, ltc2631_10_channels, 2), + [ID_LTC2633_H10] = LTC2631_INFO(4096000, ltc2631_10_channels, 2), + [ID_LTC2633_L8] = LTC2631_INFO(2500000, ltc2631_8_channels, 2), + [ID_LTC2633_H8] = LTC2631_INFO(4096000, ltc2631_8_channels, 2), + [ID_LTC2635_L12] = LTC2631_INFO(2500000, ltc2631_12_channels, 4), + [ID_LTC2635_H12] = LTC2631_INFO(4096000, ltc2631_12_channels, 4), + [ID_LTC2635_L10] = LTC2631_INFO(2500000, ltc2631_10_channels, 4), + [ID_LTC2635_H10] = LTC2631_INFO(4096000, ltc2631_10_channels, 4), + [ID_LTC2635_L8] = LTC2631_INFO(2500000, ltc2631_8_channels, 4), + [ID_LTC2635_H8] = LTC2631_INFO(4096000, ltc2631_8_channels, 4), }; static inline unsigned int ad5064_num_vref(struct ad5064_state *st) @@ -982,6 +1031,24 @@ static const struct i2c_device_id ad5064_i2c_ids[] = { {"ltc2626", ID_LTC2626}, {"ltc2627", ID_LTC2627}, {"ltc2629", ID_LTC2629}, + {"ltc2631-l12", ID_LTC2631_L12}, + {"ltc2631-h12", ID_LTC2631_H12}, + {"ltc2631-l10", ID_LTC2631_L10}, + {"ltc2631-h10", ID_LTC2631_H10}, + {"ltc2631-l8", ID_LTC2631_L8}, + {"ltc2631-h8", ID_LTC2631_H8}, + {"ltc2633-l12", ID_LTC2633_L12}, + {"ltc2633-h12", ID_LTC2633_H12}, + {"ltc2633-l10", ID_LTC2633_L10}, + {"ltc2633-h10", ID_LTC2633_H10}, + {"ltc2633-l8", ID_LTC2633_L8}, + {"ltc2633-h8", ID_LTC2633_H8}, + {"ltc2635-l12", ID_LTC2635_L12}, + {"ltc2635-h12", ID_LTC2635_H12}, + {"ltc2635-l10", ID_LTC2635_L10}, + {"ltc2635-h10", ID_LTC2635_H10}, + {"ltc2635-l8", ID_LTC2635_L8}, + {"ltc2635-h8", ID_LTC2635_H8}, {} }; MODULE_DEVICE_TABLE(i2c, ad5064_i2c_ids); diff --git a/drivers/iio/humidity/hts221.h b/drivers/iio/humidity/hts221.h index c7154665512e..94510266e0a5 100644 --- a/drivers/iio/humidity/hts221.h +++ b/drivers/iio/humidity/hts221.h @@ -57,12 +57,15 @@ struct hts221_hw { struct hts221_sensor sensors[HTS221_SENSOR_MAX]; + bool enabled; u8 odr; const struct hts221_transfer_function *tf; struct hts221_transfer_buffer tb; }; +extern const struct dev_pm_ops hts221_pm_ops; + int hts221_config_drdy(struct hts221_hw *hw, bool enable); int hts221_probe(struct iio_dev *iio_dev); int hts221_power_on(struct hts221_hw *hw); diff --git a/drivers/iio/humidity/hts221_core.c b/drivers/iio/humidity/hts221_core.c index 3f3ef4a1a474..a56da3999e00 100644 --- a/drivers/iio/humidity/hts221_core.c +++ b/drivers/iio/humidity/hts221_core.c @@ -13,6 +13,7 @@ #include <linux/device.h> #include <linux/iio/sysfs.h> #include <linux/delay.h> +#include <linux/pm.h> #include <asm/unaligned.h> #include "hts221.h" @@ -307,15 +308,30 @@ hts221_sysfs_temp_oversampling_avail(struct device *dev, int hts221_power_on(struct hts221_hw *hw) { - return hts221_update_odr(hw, hw->odr); + int err; + + err = hts221_update_odr(hw, hw->odr); + if (err < 0) + return err; + + hw->enabled = true; + + return 0; } int hts221_power_off(struct hts221_hw *hw) { - u8 data[] = {0x00, 0x00}; + __le16 data = 0; + int err; - return hw->tf->write(hw->dev, HTS221_REG_CNTRL1_ADDR, sizeof(data), - data); + err = hw->tf->write(hw->dev, HTS221_REG_CNTRL1_ADDR, sizeof(data), + (u8 *)&data); + if (err < 0) + return err; + + hw->enabled = false; + + return 0; } static int hts221_parse_temp_caldata(struct hts221_hw *hw) @@ -682,6 +698,36 @@ int hts221_probe(struct iio_dev *iio_dev) } EXPORT_SYMBOL(hts221_probe); +static int __maybe_unused hts221_suspend(struct device *dev) +{ + struct iio_dev *iio_dev = dev_get_drvdata(dev); + struct hts221_hw *hw = iio_priv(iio_dev); + __le16 data = 0; + int err; + + err = hw->tf->write(hw->dev, HTS221_REG_CNTRL1_ADDR, sizeof(data), + (u8 *)&data); + + return err < 0 ? err : 0; +} + +static int __maybe_unused hts221_resume(struct device *dev) +{ + struct iio_dev *iio_dev = dev_get_drvdata(dev); + struct hts221_hw *hw = iio_priv(iio_dev); + int err = 0; + + if (hw->enabled) + err = hts221_update_odr(hw, hw->odr); + + return err; +} + +const struct dev_pm_ops hts221_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(hts221_suspend, hts221_resume) +}; +EXPORT_SYMBOL(hts221_pm_ops); + MODULE_AUTHOR("Lorenzo Bianconi <lorenzo.bianconi@st.com>"); MODULE_DESCRIPTION("STMicroelectronics hts221 sensor driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/iio/humidity/hts221_i2c.c b/drivers/iio/humidity/hts221_i2c.c index 8333c0296c0e..f38e4b7e0160 100644 --- a/drivers/iio/humidity/hts221_i2c.c +++ b/drivers/iio/humidity/hts221_i2c.c @@ -105,6 +105,7 @@ MODULE_DEVICE_TABLE(i2c, hts221_i2c_id_table); static struct i2c_driver hts221_driver = { .driver = { .name = "hts221_i2c", + .pm = &hts221_pm_ops, .of_match_table = of_match_ptr(hts221_i2c_of_match), .acpi_match_table = ACPI_PTR(hts221_acpi_match), }, diff --git a/drivers/iio/humidity/hts221_spi.c b/drivers/iio/humidity/hts221_spi.c index 70df5e7150c1..57cbc256771b 100644 --- a/drivers/iio/humidity/hts221_spi.c +++ b/drivers/iio/humidity/hts221_spi.c @@ -113,6 +113,7 @@ MODULE_DEVICE_TABLE(spi, hts221_spi_id_table); static struct spi_driver hts221_driver = { .driver = { .name = "hts221_spi", + .pm = &hts221_pm_ops, .of_match_table = of_match_ptr(hts221_spi_of_match), }, .probe = hts221_spi_probe, diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c index 88a7c5d4e4d2..44830bce13df 100644 --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_core.c @@ -188,7 +188,6 @@ int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on) int result = 0; if (power_on) { - /* Already under indio-dev->mlock mutex */ if (!st->powerup_count) result = regmap_write(st->map, st->reg->pwr_mgmt_1, 0); if (!result) @@ -329,50 +328,37 @@ inv_mpu6050_read_raw(struct iio_dev *indio_dev, int result; ret = IIO_VAL_INT; - result = 0; - mutex_lock(&indio_dev->mlock); - if (!st->chip_config.enable) { - result = inv_mpu6050_set_power_itg(st, true); - if (result) - goto error_read_raw; - } - /* when enable is on, power is already on */ + mutex_lock(&st->lock); + result = iio_device_claim_direct_mode(indio_dev); + if (result) + goto error_read_raw_unlock; + result = inv_mpu6050_set_power_itg(st, true); + if (result) + goto error_read_raw_release; switch (chan->type) { case IIO_ANGL_VEL: - if (!st->chip_config.gyro_fifo_enable || - !st->chip_config.enable) { - result = inv_mpu6050_switch_engine(st, true, - INV_MPU6050_BIT_PWR_GYRO_STBY); - if (result) - goto error_read_raw; - } + result = inv_mpu6050_switch_engine(st, true, + INV_MPU6050_BIT_PWR_GYRO_STBY); + if (result) + goto error_read_raw_power_off; ret = inv_mpu6050_sensor_show(st, st->reg->raw_gyro, chan->channel2, val); - if (!st->chip_config.gyro_fifo_enable || - !st->chip_config.enable) { - result = inv_mpu6050_switch_engine(st, false, - INV_MPU6050_BIT_PWR_GYRO_STBY); - if (result) - goto error_read_raw; - } + result = inv_mpu6050_switch_engine(st, false, + INV_MPU6050_BIT_PWR_GYRO_STBY); + if (result) + goto error_read_raw_power_off; break; case IIO_ACCEL: - if (!st->chip_config.accl_fifo_enable || - !st->chip_config.enable) { - result = inv_mpu6050_switch_engine(st, true, - INV_MPU6050_BIT_PWR_ACCL_STBY); - if (result) - goto error_read_raw; - } + result = inv_mpu6050_switch_engine(st, true, + INV_MPU6050_BIT_PWR_ACCL_STBY); + if (result) + goto error_read_raw_power_off; ret = inv_mpu6050_sensor_show(st, st->reg->raw_accl, chan->channel2, val); - if (!st->chip_config.accl_fifo_enable || - !st->chip_config.enable) { - result = inv_mpu6050_switch_engine(st, false, - INV_MPU6050_BIT_PWR_ACCL_STBY); - if (result) - goto error_read_raw; - } + result = inv_mpu6050_switch_engine(st, false, + INV_MPU6050_BIT_PWR_ACCL_STBY); + if (result) + goto error_read_raw_power_off; break; case IIO_TEMP: /* wait for stablization */ @@ -384,10 +370,12 @@ inv_mpu6050_read_raw(struct iio_dev *indio_dev, ret = -EINVAL; break; } -error_read_raw: - if (!st->chip_config.enable) - result |= inv_mpu6050_set_power_itg(st, false); - mutex_unlock(&indio_dev->mlock); +error_read_raw_power_off: + result |= inv_mpu6050_set_power_itg(st, false); +error_read_raw_release: + iio_device_release_direct_mode(indio_dev); +error_read_raw_unlock: + mutex_unlock(&st->lock); if (result) return result; @@ -396,13 +384,17 @@ error_read_raw: case IIO_CHAN_INFO_SCALE: switch (chan->type) { case IIO_ANGL_VEL: + mutex_lock(&st->lock); *val = 0; *val2 = gyro_scale_6050[st->chip_config.fsr]; + mutex_unlock(&st->lock); return IIO_VAL_INT_PLUS_NANO; case IIO_ACCEL: + mutex_lock(&st->lock); *val = 0; *val2 = accel_scale[st->chip_config.accl_fs]; + mutex_unlock(&st->lock); return IIO_VAL_INT_PLUS_MICRO; case IIO_TEMP: @@ -425,12 +417,16 @@ error_read_raw: case IIO_CHAN_INFO_CALIBBIAS: switch (chan->type) { case IIO_ANGL_VEL: + mutex_lock(&st->lock); ret = inv_mpu6050_sensor_show(st, st->reg->gyro_offset, chan->channel2, val); + mutex_unlock(&st->lock); return IIO_VAL_INT; case IIO_ACCEL: + mutex_lock(&st->lock); ret = inv_mpu6050_sensor_show(st, st->reg->accl_offset, chan->channel2, val); + mutex_unlock(&st->lock); return IIO_VAL_INT; default: @@ -506,18 +502,17 @@ static int inv_mpu6050_write_raw(struct iio_dev *indio_dev, struct inv_mpu6050_state *st = iio_priv(indio_dev); int result; - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); /* * we should only update scale when the chip is disabled, i.e. * not running */ - if (st->chip_config.enable) { - result = -EBUSY; - goto error_write_raw; - } + result = iio_device_claim_direct_mode(indio_dev); + if (result) + goto error_write_raw_unlock; result = inv_mpu6050_set_power_itg(st, true); if (result) - goto error_write_raw; + goto error_write_raw_release; switch (mask) { case IIO_CHAN_INFO_SCALE: @@ -553,9 +548,11 @@ static int inv_mpu6050_write_raw(struct iio_dev *indio_dev, break; } -error_write_raw: result |= inv_mpu6050_set_power_itg(st, false); - mutex_unlock(&indio_dev->mlock); +error_write_raw_release: + iio_device_release_direct_mode(indio_dev); +error_write_raw_unlock: + mutex_unlock(&st->lock); return result; } @@ -611,31 +608,35 @@ inv_mpu6050_fifo_rate_store(struct device *dev, struct device_attribute *attr, if (fifo_rate < INV_MPU6050_MIN_FIFO_RATE || fifo_rate > INV_MPU6050_MAX_FIFO_RATE) return -EINVAL; - if (fifo_rate == st->chip_config.fifo_rate) - return count; - mutex_lock(&indio_dev->mlock); - if (st->chip_config.enable) { - result = -EBUSY; - goto fifo_rate_fail; + mutex_lock(&st->lock); + if (fifo_rate == st->chip_config.fifo_rate) { + result = 0; + goto fifo_rate_fail_unlock; } + result = iio_device_claim_direct_mode(indio_dev); + if (result) + goto fifo_rate_fail_unlock; result = inv_mpu6050_set_power_itg(st, true); if (result) - goto fifo_rate_fail; + goto fifo_rate_fail_release; d = INV_MPU6050_ONE_K_HZ / fifo_rate - 1; result = regmap_write(st->map, st->reg->sample_rate_div, d); if (result) - goto fifo_rate_fail; + goto fifo_rate_fail_power_off; st->chip_config.fifo_rate = fifo_rate; result = inv_mpu6050_set_lpf(st, fifo_rate); if (result) - goto fifo_rate_fail; + goto fifo_rate_fail_power_off; -fifo_rate_fail: +fifo_rate_fail_power_off: result |= inv_mpu6050_set_power_itg(st, false); - mutex_unlock(&indio_dev->mlock); +fifo_rate_fail_release: + iio_device_release_direct_mode(indio_dev); +fifo_rate_fail_unlock: + mutex_unlock(&st->lock); if (result) return result; @@ -650,8 +651,13 @@ inv_fifo_rate_show(struct device *dev, struct device_attribute *attr, char *buf) { struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev)); + unsigned fifo_rate; + + mutex_lock(&st->lock); + fifo_rate = st->chip_config.fifo_rate; + mutex_unlock(&st->lock); - return sprintf(buf, "%d\n", st->chip_config.fifo_rate); + return scnprintf(buf, PAGE_SIZE, "%u\n", fifo_rate); } /** @@ -678,7 +684,8 @@ static ssize_t inv_attr_show(struct device *dev, struct device_attribute *attr, case ATTR_ACCL_MATRIX: m = st->plat_data.orientation; - return sprintf(buf, "%d, %d, %d; %d, %d, %d; %d, %d, %d\n", + return scnprintf(buf, PAGE_SIZE, + "%d, %d, %d; %d, %d, %d; %d, %d, %d\n", m[0], m[1], m[2], m[3], m[4], m[5], m[6], m[7], m[8]); default: return -EINVAL; @@ -803,27 +810,42 @@ static int inv_check_and_setup_chip(struct inv_mpu6050_state *st) { int result; unsigned int regval; + int i; st->hw = &hw_info[st->chip_type]; st->reg = hw_info[st->chip_type].reg; - /* reset to make sure previous state are not there */ - result = regmap_write(st->map, st->reg->pwr_mgmt_1, - INV_MPU6050_BIT_H_RESET); - if (result) - return result; - msleep(INV_MPU6050_POWER_UP_TIME); - /* check chip self-identification */ result = regmap_read(st->map, INV_MPU6050_REG_WHOAMI, ®val); if (result) return result; if (regval != st->hw->whoami) { - dev_warn(regmap_get_device(st->map), - "whoami mismatch got %#02x expected %#02hhx for %s\n", + /* check whoami against all possible values */ + for (i = 0; i < INV_NUM_PARTS; ++i) { + if (regval == hw_info[i].whoami) { + dev_warn(regmap_get_device(st->map), + "whoami mismatch got %#02x (%s)" + "expected %#02hhx (%s)\n", + regval, hw_info[i].name, + st->hw->whoami, st->hw->name); + break; + } + } + if (i >= INV_NUM_PARTS) { + dev_err(regmap_get_device(st->map), + "invalid whoami %#02x expected %#02hhx (%s)\n", regval, st->hw->whoami, st->hw->name); + return -ENODEV; + } } + /* reset to make sure previous state are not there */ + result = regmap_write(st->map, st->reg->pwr_mgmt_1, + INV_MPU6050_BIT_H_RESET); + if (result) + return result; + msleep(INV_MPU6050_POWER_UP_TIME); + /* * toggle power state. After reset, the sleep bit could be on * or off depending on the OTP settings. Toggling power would @@ -869,6 +891,7 @@ int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name, return -ENODEV; } st = iio_priv(indio_dev); + mutex_init(&st->lock); st->chip_type = chip_type; st->powerup_count = 0; st->irq = irq; @@ -962,12 +985,26 @@ EXPORT_SYMBOL_GPL(inv_mpu_core_remove); static int inv_mpu_resume(struct device *dev) { - return inv_mpu6050_set_power_itg(iio_priv(dev_get_drvdata(dev)), true); + struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(dev)); + int result; + + mutex_lock(&st->lock); + result = inv_mpu6050_set_power_itg(st, true); + mutex_unlock(&st->lock); + + return result; } static int inv_mpu_suspend(struct device *dev) { - return inv_mpu6050_set_power_itg(iio_priv(dev_get_drvdata(dev)), false); + struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(dev)); + int result; + + mutex_lock(&st->lock); + result = inv_mpu6050_set_power_itg(st, false); + mutex_unlock(&st->lock); + + return result; } #endif /* CONFIG_PM_SLEEP */ diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_i2c.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_i2c.c index 64b5f5b92200..fcd7a92b6cf8 100644 --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_i2c.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_i2c.c @@ -32,7 +32,7 @@ static int inv_mpu6050_select_bypass(struct i2c_mux_core *muxc, u32 chan_id) int ret = 0; /* Use the same mutex which was used everywhere to protect power-op */ - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); if (!st->powerup_count) { ret = regmap_write(st->map, st->reg->pwr_mgmt_1, 0); if (ret) @@ -48,7 +48,7 @@ static int inv_mpu6050_select_bypass(struct i2c_mux_core *muxc, u32 chan_id) INV_MPU6050_BIT_BYPASS_EN); } write_error: - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return ret; } @@ -58,14 +58,14 @@ static int inv_mpu6050_deselect_bypass(struct i2c_mux_core *muxc, u32 chan_id) struct iio_dev *indio_dev = i2c_mux_priv(muxc); struct inv_mpu6050_state *st = iio_priv(indio_dev); - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); /* It doesn't really mattter, if any of the calls fails */ regmap_write(st->map, st->reg->int_pin_cfg, INV_MPU6050_INT_PIN_CFG); st->powerup_count--; if (!st->powerup_count) regmap_write(st->map, st->reg->pwr_mgmt_1, INV_MPU6050_BIT_SLEEP); - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); return 0; } diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h b/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h index 953a0c09d568..065794162d65 100644 --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h @@ -14,6 +14,7 @@ #include <linux/i2c-mux.h> #include <linux/kfifo.h> #include <linux/spinlock.h> +#include <linux/mutex.h> #include <linux/iio/iio.h> #include <linux/iio/buffer.h> #include <linux/regmap.h> @@ -82,7 +83,6 @@ enum inv_devices { * @fsr: Full scale range. * @lpf: Digital low pass filter frequency. * @accl_fs: accel full scale range. - * @enable: master enable state. * @accl_fifo_enable: enable accel data output * @gyro_fifo_enable: enable gyro data output * @fifo_rate: FIFO update rate. @@ -91,7 +91,6 @@ struct inv_mpu6050_chip_config { unsigned int fsr:2; unsigned int lpf:3; unsigned int accl_fs:2; - unsigned int enable:1; unsigned int accl_fifo_enable:1; unsigned int gyro_fifo_enable:1; u16 fifo_rate; @@ -114,6 +113,7 @@ struct inv_mpu6050_hw { /* * struct inv_mpu6050_state - Driver state variables. * @TIMESTAMP_FIFO_SIZE: fifo size for timestamp. + * @lock: Chip access lock. * @trig: IIO trigger. * @chip_config: Cached attribute information. * @reg: Map of important registers. @@ -128,6 +128,7 @@ struct inv_mpu6050_hw { */ struct inv_mpu6050_state { #define TIMESTAMP_FIFO_SIZE 16 + struct mutex lock; struct iio_trigger *trig; struct inv_mpu6050_chip_config chip_config; const struct inv_mpu6050_reg_map *reg; diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c index 3a9f3eac91ab..ff81c6aa009d 100644 --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c @@ -128,7 +128,7 @@ irqreturn_t inv_mpu6050_read_fifo(int irq, void *p) u16 fifo_count; s64 timestamp; - mutex_lock(&indio_dev->mlock); + mutex_lock(&st->lock); if (!(st->chip_config.accl_fifo_enable | st->chip_config.gyro_fifo_enable)) goto end_session; @@ -178,7 +178,7 @@ irqreturn_t inv_mpu6050_read_fifo(int irq, void *p) } end_session: - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); iio_trigger_notify_done(indio_dev->trig); return IRQ_HANDLED; @@ -186,7 +186,7 @@ end_session: flush_fifo: /* Flush HW and SW FIFOs. */ inv_reset_fifo(indio_dev); - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&st->lock); iio_trigger_notify_done(indio_dev->trig); return IRQ_HANDLED; diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c index e8818d4dd4b8..540070f0a230 100644 --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_trigger.c @@ -90,7 +90,6 @@ static int inv_mpu6050_set_enable(struct iio_dev *indio_dev, bool enable) if (result) return result; } - st->chip_config.enable = enable; return 0; } @@ -103,7 +102,15 @@ static int inv_mpu6050_set_enable(struct iio_dev *indio_dev, bool enable) static int inv_mpu_data_rdy_trigger_set_state(struct iio_trigger *trig, bool state) { - return inv_mpu6050_set_enable(iio_trigger_get_drvdata(trig), state); + struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); + struct inv_mpu6050_state *st = iio_priv(indio_dev); + int result; + + mutex_lock(&st->lock); + result = inv_mpu6050_set_enable(indio_dev, state); + mutex_unlock(&st->lock); + + return result; } static const struct iio_trigger_ops inv_mpu_trigger_ops = { diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h index 4839db7b9690..46352c7bff43 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h @@ -135,6 +135,8 @@ struct st_lsm6dsx_hw { #endif /* CONFIG_SPI_MASTER */ }; +extern const struct dev_pm_ops st_lsm6dsx_pm_ops; + int st_lsm6dsx_probe(struct device *dev, int irq, int hw_id, const char *name, const struct st_lsm6dsx_transfer_function *tf_ops); int st_lsm6dsx_sensor_enable(struct st_lsm6dsx_sensor *sensor); @@ -144,5 +146,8 @@ int st_lsm6dsx_write_with_mask(struct st_lsm6dsx_hw *hw, u8 addr, u8 mask, u8 val); int st_lsm6dsx_update_watermark(struct st_lsm6dsx_sensor *sensor, u16 watermark); +int st_lsm6dsx_flush_fifo(struct st_lsm6dsx_hw *hw); +int st_lsm6dsx_set_fifo_mode(struct st_lsm6dsx_hw *hw, + enum st_lsm6dsx_fifo_mode fifo_mode); #endif /* ST_LSM6DSX_H */ diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c index c8e5cfd0ef0b..2a72acc6e049 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c @@ -37,6 +37,8 @@ #define ST_LSM6DSX_REG_FIFO_THH_ADDR 0x07 #define ST_LSM6DSX_FIFO_TH_MASK GENMASK(11, 0) #define ST_LSM6DSX_REG_FIFO_DEC_GXL_ADDR 0x08 +#define ST_LSM6DSX_REG_HLACTIVE_ADDR 0x12 +#define ST_LSM6DSX_REG_HLACTIVE_MASK BIT(5) #define ST_LSM6DSX_REG_FIFO_MODE_ADDR 0x0a #define ST_LSM6DSX_FIFO_MODE_MASK GENMASK(2, 0) #define ST_LSM6DSX_FIFO_ODR_MASK GENMASK(6, 3) @@ -130,8 +132,8 @@ static int st_lsm6dsx_update_decimators(struct st_lsm6dsx_hw *hw) return 0; } -static int st_lsm6dsx_set_fifo_mode(struct st_lsm6dsx_hw *hw, - enum st_lsm6dsx_fifo_mode fifo_mode) +int st_lsm6dsx_set_fifo_mode(struct st_lsm6dsx_hw *hw, + enum st_lsm6dsx_fifo_mode fifo_mode) { u8 data; int err; @@ -303,7 +305,7 @@ static int st_lsm6dsx_read_fifo(struct st_lsm6dsx_hw *hw) return read_len; } -static int st_lsm6dsx_flush_fifo(struct st_lsm6dsx_hw *hw) +int st_lsm6dsx_flush_fifo(struct st_lsm6dsx_hw *hw) { int err; @@ -417,6 +419,7 @@ int st_lsm6dsx_fifo_setup(struct st_lsm6dsx_hw *hw) { struct iio_buffer *buffer; unsigned long irq_type; + bool irq_active_low; int i, err; irq_type = irqd_get_trigger_type(irq_get_irq_data(hw->irq)); @@ -424,12 +427,23 @@ int st_lsm6dsx_fifo_setup(struct st_lsm6dsx_hw *hw) switch (irq_type) { case IRQF_TRIGGER_HIGH: case IRQF_TRIGGER_RISING: + irq_active_low = false; + break; + case IRQF_TRIGGER_LOW: + case IRQF_TRIGGER_FALLING: + irq_active_low = true; break; default: dev_info(hw->dev, "mode %lx unsupported\n", irq_type); return -EINVAL; } + err = st_lsm6dsx_write_with_mask(hw, ST_LSM6DSX_REG_HLACTIVE_ADDR, + ST_LSM6DSX_REG_HLACTIVE_MASK, + irq_active_low); + if (err < 0) + return err; + err = devm_request_threaded_irq(hw->dev, hw->irq, st_lsm6dsx_handler_irq, st_lsm6dsx_handler_thread, diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c index 462a27b70453..b485540da89e 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c @@ -36,6 +36,7 @@ #include <linux/delay.h> #include <linux/iio/iio.h> #include <linux/iio/sysfs.h> +#include <linux/pm.h> #include <linux/platform_data/st_sensors_pdata.h> @@ -731,6 +732,57 @@ int st_lsm6dsx_probe(struct device *dev, int irq, int hw_id, const char *name, } EXPORT_SYMBOL(st_lsm6dsx_probe); +static int __maybe_unused st_lsm6dsx_suspend(struct device *dev) +{ + struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev); + struct st_lsm6dsx_sensor *sensor; + int i, err = 0; + + for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) { + sensor = iio_priv(hw->iio_devs[i]); + if (!(hw->enable_mask & BIT(sensor->id))) + continue; + + err = st_lsm6dsx_write_with_mask(hw, + st_lsm6dsx_odr_table[sensor->id].reg.addr, + st_lsm6dsx_odr_table[sensor->id].reg.mask, 0); + if (err < 0) + return err; + } + + if (hw->fifo_mode != ST_LSM6DSX_FIFO_BYPASS) + err = st_lsm6dsx_flush_fifo(hw); + + return err; +} + +static int __maybe_unused st_lsm6dsx_resume(struct device *dev) +{ + struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev); + struct st_lsm6dsx_sensor *sensor; + int i, err = 0; + + for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) { + sensor = iio_priv(hw->iio_devs[i]); + if (!(hw->enable_mask & BIT(sensor->id))) + continue; + + err = st_lsm6dsx_set_odr(sensor, sensor->odr); + if (err < 0) + return err; + } + + if (hw->enable_mask) + err = st_lsm6dsx_set_fifo_mode(hw, ST_LSM6DSX_FIFO_CONT); + + return err; +} + +const struct dev_pm_ops st_lsm6dsx_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(st_lsm6dsx_suspend, st_lsm6dsx_resume) +}; +EXPORT_SYMBOL(st_lsm6dsx_pm_ops); + MODULE_AUTHOR("Lorenzo Bianconi <lorenzo.bianconi@st.com>"); MODULE_AUTHOR("Denis Ciocca <denis.ciocca@st.com>"); MODULE_DESCRIPTION("STMicroelectronics st_lsm6dsx driver"); diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c index 09a51cfb9b5e..305fec712ab0 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c @@ -98,6 +98,7 @@ MODULE_DEVICE_TABLE(i2c, st_lsm6dsx_i2c_id_table); static struct i2c_driver st_lsm6dsx_driver = { .driver = { .name = "st_lsm6dsx_i2c", + .pm = &st_lsm6dsx_pm_ops, .of_match_table = of_match_ptr(st_lsm6dsx_i2c_of_match), }, .probe = st_lsm6dsx_i2c_probe, diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c index f765a5058488..95472f153ad2 100644 --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c @@ -115,6 +115,7 @@ MODULE_DEVICE_TABLE(spi, st_lsm6dsx_spi_id_table); static struct spi_driver st_lsm6dsx_driver = { .driver = { .name = "st_lsm6dsx_spi", + .pm = &st_lsm6dsx_pm_ops, .of_match_table = of_match_ptr(st_lsm6dsx_spi_of_match), }, .probe = st_lsm6dsx_spi_probe, diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c index 57c14da5708f..17ec4cee51dc 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -478,21 +478,16 @@ ssize_t iio_enum_write(struct iio_dev *indio_dev, size_t len) { const struct iio_enum *e = (const struct iio_enum *)priv; - unsigned int i; int ret; if (!e->set) return -EINVAL; - for (i = 0; i < e->num_items; i++) { - if (sysfs_streq(buf, e->items[i])) - break; - } - - if (i == e->num_items) - return -EINVAL; + ret = __sysfs_match_string(e->items, e->num_items, buf); + if (ret < 0) + return ret; - ret = e->set(indio_dev, chan, i); + ret = e->set(indio_dev, chan, ret); return ret ? ret : len; } EXPORT_SYMBOL_GPL(iio_enum_write); @@ -1089,7 +1084,7 @@ static int iio_device_add_info_mask_type(struct iio_dev *indio_dev, { int i, ret, attrcount = 0; - for_each_set_bit(i, infomask, sizeof(infomask)*8) { + for_each_set_bit(i, infomask, sizeof(*infomask)*8) { if (i >= ARRAY_SIZE(iio_chan_info_postfix)) return -EINVAL; ret = __iio_add_chan_devattr(iio_chan_info_postfix[i], @@ -1118,7 +1113,7 @@ static int iio_device_add_info_mask_type_avail(struct iio_dev *indio_dev, int i, ret, attrcount = 0; char *avail_postfix; - for_each_set_bit(i, infomask, sizeof(infomask) * 8) { + for_each_set_bit(i, infomask, sizeof(*infomask) * 8) { avail_postfix = kasprintf(GFP_KERNEL, "%s_available", iio_chan_info_postfix[i]); @@ -1428,7 +1423,7 @@ static void iio_device_unregister_sysfs(struct iio_dev *indio_dev) static void iio_dev_release(struct device *device) { struct iio_dev *indio_dev = dev_to_iio_dev(device); - if (indio_dev->modes & (INDIO_BUFFER_TRIGGERED | INDIO_EVENT_TRIGGERED)) + if (indio_dev->modes & INDIO_ALL_TRIGGERED_MODES) iio_device_unregister_trigger_consumer(indio_dev); iio_device_unregister_eventset(indio_dev); iio_device_unregister_sysfs(indio_dev); @@ -1710,7 +1705,7 @@ int iio_device_register(struct iio_dev *indio_dev) "Failed to register event set\n"); goto error_free_sysfs; } - if (indio_dev->modes & (INDIO_BUFFER_TRIGGERED | INDIO_EVENT_TRIGGERED)) + if (indio_dev->modes & INDIO_ALL_TRIGGERED_MODES) iio_device_register_trigger_consumer(indio_dev); if ((indio_dev->modes & INDIO_ALL_BUFFER_MODES) && diff --git a/drivers/iio/inkern.c b/drivers/iio/inkern.c index 7a13535dc3e9..a3941bade6a7 100644 --- a/drivers/iio/inkern.c +++ b/drivers/iio/inkern.c @@ -750,11 +750,9 @@ int iio_read_avail_channel_raw(struct iio_channel *chan, err_unlock: mutex_unlock(&chan->indio_dev->info_exist_lock); - if (ret >= 0 && type != IIO_VAL_INT) { + if (ret >= 0 && type != IIO_VAL_INT) /* raw values are assumed to be IIO_VAL_INT */ ret = -EINVAL; - goto err_unlock; - } return ret; } diff --git a/drivers/iio/light/Kconfig b/drivers/iio/light/Kconfig index 33e755d8d825..2356ed9285df 100644 --- a/drivers/iio/light/Kconfig +++ b/drivers/iio/light/Kconfig @@ -172,6 +172,16 @@ config SENSORS_ISL29018 in lux, proximity infrared sensing and normal infrared sensing. Data from sensor is accessible via sysfs. +config SENSORS_ISL29028 + tristate "Intersil ISL29028 Concurrent Light and Proximity Sensor" + depends on I2C + select REGMAP_I2C + help + Provides driver for the Intersil's ISL29028 device. + This driver supports the sysfs interface to get the ALS, IR intensity, + Proximity value via iio. The ISL29028 provides the concurrent sensing + of ambient light and proximity. + config ISL29125 tristate "Intersil ISL29125 digital color light sensor" depends on I2C diff --git a/drivers/iio/light/Makefile b/drivers/iio/light/Makefile index 681363c2b298..fa32fa459e2e 100644 --- a/drivers/iio/light/Makefile +++ b/drivers/iio/light/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_GP2AP020A00F) += gp2ap020a00f.o obj-$(CONFIG_HID_SENSOR_ALS) += hid-sensor-als.o obj-$(CONFIG_HID_SENSOR_PROX) += hid-sensor-prox.o obj-$(CONFIG_SENSORS_ISL29018) += isl29018.o +obj-$(CONFIG_SENSORS_ISL29028) += isl29028.o obj-$(CONFIG_ISL29125) += isl29125.o obj-$(CONFIG_JSA1212) += jsa1212.o obj-$(CONFIG_SENSORS_LM3533) += lm3533-als.o diff --git a/drivers/iio/light/isl29018.c b/drivers/iio/light/isl29018.c index 917dd8b43e72..61f5924b472d 100644 --- a/drivers/iio/light/isl29018.c +++ b/drivers/iio/light/isl29018.c @@ -807,6 +807,7 @@ static SIMPLE_DEV_PM_OPS(isl29018_pm_ops, isl29018_suspend, isl29018_resume); #define ISL29018_PM_OPS NULL #endif +#ifdef CONFIG_ACPI static const struct acpi_device_id isl29018_acpi_match[] = { {"ISL29018", isl29018}, {"ISL29023", isl29023}, @@ -814,6 +815,7 @@ static const struct acpi_device_id isl29018_acpi_match[] = { {}, }; MODULE_DEVICE_TABLE(acpi, isl29018_acpi_match); +#endif static const struct i2c_device_id isl29018_id[] = { {"isl29018", isl29018}, diff --git a/drivers/staging/iio/light/isl29028.c b/drivers/iio/light/isl29028.c index 5375e7a81205..3d09c1fc4dad 100644 --- a/drivers/staging/iio/light/isl29028.c +++ b/drivers/iio/light/isl29028.c @@ -16,6 +16,10 @@ * * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + * Datasheets: + * - http://www.intersil.com/content/dam/Intersil/documents/isl2/isl29028.pdf + * - http://www.intersil.com/content/dam/Intersil/documents/isl2/isl29030.pdf */ #include <linux/module.h> @@ -64,8 +68,25 @@ #define ISL29028_POWER_OFF_DELAY_MS 2000 -static const unsigned int isl29028_prox_sleep_time[] = {800, 400, 200, 100, 75, - 50, 12, 0}; +struct isl29028_prox_data { + int sampling_int; + int sampling_fract; + int sleep_time; +}; + +static const struct isl29028_prox_data isl29028_prox_data[] = { + { 1, 250000, 800 }, + { 2, 500000, 400 }, + { 5, 0, 200 }, + { 10, 0, 100 }, + { 13, 300000, 75 }, + { 20, 0, 50 }, + { 80, 0, 13 }, /* + * Note: Data sheet lists 12.5 ms sleep time. + * Round up a half millisecond for msleep(). + */ + { 100, 0, 0 } +}; enum isl29028_als_ir_mode { ISL29028_MODE_NONE = 0, @@ -76,32 +97,37 @@ enum isl29028_als_ir_mode { struct isl29028_chip { struct mutex lock; struct regmap *regmap; - unsigned int prox_sampling; + int prox_sampling_int; + int prox_sampling_frac; bool enable_prox; int lux_scale; enum isl29028_als_ir_mode als_ir_mode; }; -static int isl29028_find_prox_sleep_time_index(int sampling) +static int isl29028_find_prox_sleep_index(int sampling_int, int sampling_fract) { - unsigned int period = DIV_ROUND_UP(1000, sampling); int i; - for (i = 0; i < ARRAY_SIZE(isl29028_prox_sleep_time); ++i) { - if (period >= isl29028_prox_sleep_time[i]) - break; + for (i = 0; i < ARRAY_SIZE(isl29028_prox_data); ++i) { + if (isl29028_prox_data[i].sampling_int == sampling_int && + isl29028_prox_data[i].sampling_fract == sampling_fract) + return i; } - return i; + return -EINVAL; } static int isl29028_set_proxim_sampling(struct isl29028_chip *chip, - unsigned int sampling) + int sampling_int, int sampling_fract) { struct device *dev = regmap_get_device(chip->regmap); int sleep_index, ret; - sleep_index = isl29028_find_prox_sleep_time_index(sampling); + sleep_index = isl29028_find_prox_sleep_index(sampling_int, + sampling_fract); + if (sleep_index < 0) + return sleep_index; + ret = regmap_update_bits(chip->regmap, ISL29028_REG_CONFIGURE, ISL29028_CONF_PROX_SLP_MASK, sleep_index << ISL29028_CONF_PROX_SLP_SH); @@ -112,16 +138,18 @@ static int isl29028_set_proxim_sampling(struct isl29028_chip *chip, return ret; } - chip->prox_sampling = sampling; + chip->prox_sampling_int = sampling_int; + chip->prox_sampling_frac = sampling_fract; return ret; } static int isl29028_enable_proximity(struct isl29028_chip *chip) { - int sleep_index, ret; + int prox_index, ret; - ret = isl29028_set_proxim_sampling(chip, chip->prox_sampling); + ret = isl29028_set_proxim_sampling(chip, chip->prox_sampling_int, + chip->prox_sampling_frac); if (ret < 0) return ret; @@ -132,8 +160,12 @@ static int isl29028_enable_proximity(struct isl29028_chip *chip) return ret; /* Wait for conversion to be complete for first sample */ - sleep_index = isl29028_find_prox_sleep_time_index(chip->prox_sampling); - msleep(isl29028_prox_sleep_time[sleep_index]); + prox_index = isl29028_find_prox_sleep_index(chip->prox_sampling_int, + chip->prox_sampling_frac); + if (prox_index < 0) + return prox_index; + + msleep(isl29028_prox_data[prox_index].sleep_time); return 0; } @@ -361,7 +393,7 @@ static int isl29028_write_raw(struct iio_dev *indio_dev, break; } - ret = isl29028_set_proxim_sampling(chip, val); + ret = isl29028_set_proxim_sampling(chip, val, val2); break; case IIO_LIGHT: if (mask != IIO_CHAN_INFO_SCALE) { @@ -439,7 +471,8 @@ static int isl29028_read_raw(struct iio_dev *indio_dev, if (chan->type != IIO_PROXIMITY) break; - *val = chip->prox_sampling; + *val = chip->prox_sampling_int; + *val2 = chip->prox_sampling_frac; ret = IIO_VAL_INT; break; case IIO_CHAN_INFO_SCALE: @@ -472,7 +505,7 @@ static int isl29028_read_raw(struct iio_dev *indio_dev, } static IIO_CONST_ATTR(in_proximity_sampling_frequency_available, - "1 3 5 10 13 20 83 100"); + "1.25 2.5 5 10 13.3 20 80 100"); static IIO_CONST_ATTR(in_illuminance_scale_available, "125 2000"); #define ISL29028_CONST_ATTR(name) (&iio_const_attr_##name.dev_attr.attr) @@ -571,7 +604,8 @@ static int isl29028_probe(struct i2c_client *client, } chip->enable_prox = false; - chip->prox_sampling = 20; + chip->prox_sampling_int = 20; + chip->prox_sampling_frac = 0; chip->lux_scale = 2000; ret = regmap_write(chip->regmap, ISL29028_REG_TEST1_MODE, 0x0); @@ -664,6 +698,7 @@ static const struct dev_pm_ops isl29028_pm_ops = { static const struct i2c_device_id isl29028_id[] = { {"isl29028", 0}, + {"isl29030", 0}, {} }; MODULE_DEVICE_TABLE(i2c, isl29028_id); @@ -671,6 +706,7 @@ MODULE_DEVICE_TABLE(i2c, isl29028_id); static const struct of_device_id isl29028_of_match[] = { { .compatible = "isl,isl29028", }, /* for backward compat., don't use */ { .compatible = "isil,isl29028", }, + { .compatible = "isil,isl29030", }, { }, }; MODULE_DEVICE_TABLE(of, isl29028_of_match); diff --git a/drivers/iio/light/rpr0521.c b/drivers/iio/light/rpr0521.c index 7de0f397194b..9d0c2e859bb2 100644 --- a/drivers/iio/light/rpr0521.c +++ b/drivers/iio/light/rpr0521.c @@ -9,7 +9,7 @@ * * IIO driver for RPR-0521RS (7-bit I2C slave address 0x38). * - * TODO: illuminance channel, PM support, buffer + * TODO: illuminance channel, buffer */ #include <linux/module.h> @@ -30,6 +30,7 @@ #define RPR0521_REG_PXS_DATA 0x44 /* 16-bit, little endian */ #define RPR0521_REG_ALS_DATA0 0x46 /* 16-bit, little endian */ #define RPR0521_REG_ALS_DATA1 0x48 /* 16-bit, little endian */ +#define RPR0521_REG_PS_OFFSET_LSB 0x53 #define RPR0521_REG_ID 0x92 #define RPR0521_MODE_ALS_MASK BIT(7) @@ -77,9 +78,9 @@ static const struct rpr0521_gain rpr0521_pxs_gain[3] = { }; enum rpr0521_channel { + RPR0521_CHAN_PXS, RPR0521_CHAN_ALS_DATA0, RPR0521_CHAN_ALS_DATA1, - RPR0521_CHAN_PXS, }; struct rpr0521_reg_desc { @@ -88,6 +89,10 @@ struct rpr0521_reg_desc { }; static const struct rpr0521_reg_desc rpr0521_data_reg[] = { + [RPR0521_CHAN_PXS] = { + .address = RPR0521_REG_PXS_DATA, + .device_mask = RPR0521_MODE_PXS_MASK, + }, [RPR0521_CHAN_ALS_DATA0] = { .address = RPR0521_REG_ALS_DATA0, .device_mask = RPR0521_MODE_ALS_MASK, @@ -96,10 +101,6 @@ static const struct rpr0521_reg_desc rpr0521_data_reg[] = { .address = RPR0521_REG_ALS_DATA1, .device_mask = RPR0521_MODE_ALS_MASK, }, - [RPR0521_CHAN_PXS] = { - .address = RPR0521_REG_PXS_DATA, - .device_mask = RPR0521_MODE_PXS_MASK, - }, }; static const struct rpr0521_gain_info { @@ -109,6 +110,13 @@ static const struct rpr0521_gain_info { const struct rpr0521_gain *gain; int size; } rpr0521_gain[] = { + [RPR0521_CHAN_PXS] = { + .reg = RPR0521_REG_PXS_CTRL, + .mask = RPR0521_PXS_GAIN_MASK, + .shift = RPR0521_PXS_GAIN_SHIFT, + .gain = rpr0521_pxs_gain, + .size = ARRAY_SIZE(rpr0521_pxs_gain), + }, [RPR0521_CHAN_ALS_DATA0] = { .reg = RPR0521_REG_ALS_CTRL, .mask = RPR0521_ALS_DATA0_GAIN_MASK, @@ -123,13 +131,30 @@ static const struct rpr0521_gain_info { .gain = rpr0521_als_gain, .size = ARRAY_SIZE(rpr0521_als_gain), }, - [RPR0521_CHAN_PXS] = { - .reg = RPR0521_REG_PXS_CTRL, - .mask = RPR0521_PXS_GAIN_MASK, - .shift = RPR0521_PXS_GAIN_SHIFT, - .gain = rpr0521_pxs_gain, - .size = ARRAY_SIZE(rpr0521_pxs_gain), - }, +}; + +struct rpr0521_samp_freq { + int als_hz; + int als_uhz; + int pxs_hz; + int pxs_uhz; +}; + +static const struct rpr0521_samp_freq rpr0521_samp_freq_i[13] = { +/* {ALS, PXS}, W==currently writable option */ + {0, 0, 0, 0}, /* W0000, 0=standby */ + {0, 0, 100, 0}, /* 0001 */ + {0, 0, 25, 0}, /* 0010 */ + {0, 0, 10, 0}, /* 0011 */ + {0, 0, 2, 500000}, /* 0100 */ + {10, 0, 20, 0}, /* 0101 */ + {10, 0, 10, 0}, /* W0110 */ + {10, 0, 2, 500000}, /* 0111 */ + {2, 500000, 20, 0}, /* 1000, measurement 100ms, sleep 300ms */ + {2, 500000, 10, 0}, /* 1001, measurement 100ms, sleep 300ms */ + {2, 500000, 0, 0}, /* 1010, high sensitivity mode */ + {2, 500000, 2, 500000}, /* W1011, high sensitivity mode */ + {20, 0, 20, 0} /* 1100, ALS_data x 0.5, see specification P.18 */ }; struct rpr0521_data { @@ -142,9 +167,11 @@ struct rpr0521_data { bool als_dev_en; bool pxs_dev_en; - /* optimize runtime pm ops - enable device only if needed */ + /* optimize runtime pm ops - enable/disable device only if needed */ bool als_ps_need_en; bool pxs_ps_need_en; + bool als_need_dis; + bool pxs_need_dis; struct regmap *regmap; }; @@ -152,9 +179,16 @@ struct rpr0521_data { static IIO_CONST_ATTR(in_intensity_scale_available, RPR0521_ALS_SCALE_AVAIL); static IIO_CONST_ATTR(in_proximity_scale_available, RPR0521_PXS_SCALE_AVAIL); +/* + * Start with easy freq first, whole table of freq combinations is more + * complicated. + */ +static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("2.5 10"); + static struct attribute *rpr0521_attributes[] = { &iio_const_attr_in_intensity_scale_available.dev_attr.attr, &iio_const_attr_in_proximity_scale_available.dev_attr.attr, + &iio_const_attr_sampling_frequency_available.dev_attr.attr, NULL, }; @@ -164,12 +198,21 @@ static const struct attribute_group rpr0521_attribute_group = { static const struct iio_chan_spec rpr0521_channels[] = { { + .type = IIO_PROXIMITY, + .address = RPR0521_CHAN_PXS, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_OFFSET) | + BIT(IIO_CHAN_INFO_SCALE), + .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), + }, + { .type = IIO_INTENSITY, .modified = 1, .address = RPR0521_CHAN_ALS_DATA0, .channel2 = IIO_MOD_LIGHT_BOTH, .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), + .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), }, { .type = IIO_INTENSITY, @@ -178,13 +221,8 @@ static const struct iio_chan_spec rpr0521_channels[] = { .channel2 = IIO_MOD_LIGHT_IR, .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), + .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), }, - { - .type = IIO_PROXIMITY, - .address = RPR0521_CHAN_PXS, - .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | - BIT(IIO_CHAN_INFO_SCALE), - } }; static int rpr0521_als_enable(struct rpr0521_data *data, u8 status) @@ -197,7 +235,10 @@ static int rpr0521_als_enable(struct rpr0521_data *data, u8 status) if (ret < 0) return ret; - data->als_dev_en = true; + if (status & RPR0521_MODE_ALS_MASK) + data->als_dev_en = true; + else + data->als_dev_en = false; return 0; } @@ -212,7 +253,10 @@ static int rpr0521_pxs_enable(struct rpr0521_data *data, u8 status) if (ret < 0) return ret; - data->pxs_dev_en = true; + if (status & RPR0521_MODE_PXS_MASK) + data->pxs_dev_en = true; + else + data->pxs_dev_en = false; return 0; } @@ -224,40 +268,32 @@ static int rpr0521_pxs_enable(struct rpr0521_data *data, u8 status) * @on: state to be set for devices in @device_mask * @device_mask: bitmask specifying for which device we need to update @on state * - * We rely on rpr0521_runtime_resume to enable our @device_mask devices, but - * if (for example) PXS was enabled (pxs_dev_en = true) by a previous call to - * rpr0521_runtime_resume and we want to enable ALS we MUST set ALS enable - * bit of RPR0521_REG_MODE_CTRL here because rpr0521_runtime_resume will not - * be called twice. + * Calls for this function must be balanced so that each ON should have matching + * OFF. Otherwise pm usage_count gets out of sync. */ static int rpr0521_set_power_state(struct rpr0521_data *data, bool on, u8 device_mask) { #ifdef CONFIG_PM int ret; - u8 update_mask = 0; if (device_mask & RPR0521_MODE_ALS_MASK) { - if (on && !data->als_ps_need_en && data->pxs_dev_en) - update_mask |= RPR0521_MODE_ALS_MASK; - else - data->als_ps_need_en = on; + data->als_ps_need_en = on; + data->als_need_dis = !on; } if (device_mask & RPR0521_MODE_PXS_MASK) { - if (on && !data->pxs_ps_need_en && data->als_dev_en) - update_mask |= RPR0521_MODE_PXS_MASK; - else - data->pxs_ps_need_en = on; - } - - if (update_mask) { - ret = regmap_update_bits(data->regmap, RPR0521_REG_MODE_CTRL, - update_mask, update_mask); - if (ret < 0) - return ret; + data->pxs_ps_need_en = on; + data->pxs_need_dis = !on; } + /* + * On: _resume() is called only when we are suspended + * Off: _suspend() is called after delay if _resume() is not + * called before that. + * Note: If either measurement is re-enabled before _suspend(), + * both stay enabled until _suspend(). + */ if (on) { ret = pm_runtime_get_sync(&data->client->dev); } else { @@ -273,6 +309,23 @@ static int rpr0521_set_power_state(struct rpr0521_data *data, bool on, return ret; } + + if (on) { + /* If _resume() was not called, enable measurement now. */ + if (data->als_ps_need_en) { + ret = rpr0521_als_enable(data, RPR0521_MODE_ALS_ENABLE); + if (ret) + return ret; + data->als_ps_need_en = false; + } + + if (data->pxs_ps_need_en) { + ret = rpr0521_pxs_enable(data, RPR0521_MODE_PXS_ENABLE); + if (ret) + return ret; + data->pxs_ps_need_en = false; + } + } #endif return 0; } @@ -314,6 +367,106 @@ static int rpr0521_set_gain(struct rpr0521_data *data, int chan, idx << rpr0521_gain[chan].shift); } +static int rpr0521_read_samp_freq(struct rpr0521_data *data, + enum iio_chan_type chan_type, + int *val, int *val2) +{ + int reg, ret; + + ret = regmap_read(data->regmap, RPR0521_REG_MODE_CTRL, ®); + if (ret < 0) + return ret; + + reg &= RPR0521_MODE_MEAS_TIME_MASK; + if (reg >= ARRAY_SIZE(rpr0521_samp_freq_i)) + return -EINVAL; + + switch (chan_type) { + case IIO_INTENSITY: + *val = rpr0521_samp_freq_i[reg].als_hz; + *val2 = rpr0521_samp_freq_i[reg].als_uhz; + return 0; + + case IIO_PROXIMITY: + *val = rpr0521_samp_freq_i[reg].pxs_hz; + *val2 = rpr0521_samp_freq_i[reg].pxs_uhz; + return 0; + + default: + return -EINVAL; + } +} + +static int rpr0521_write_samp_freq_common(struct rpr0521_data *data, + enum iio_chan_type chan_type, + int val, int val2) +{ + int i; + + /* + * Ignore channel + * both pxs and als are setup only to same freq because of simplicity + */ + switch (val) { + case 0: + i = 0; + break; + + case 2: + if (val2 != 500000) + return -EINVAL; + + i = 11; + break; + + case 10: + i = 6; + break; + + default: + return -EINVAL; + } + + return regmap_update_bits(data->regmap, + RPR0521_REG_MODE_CTRL, + RPR0521_MODE_MEAS_TIME_MASK, + i); +} + +static int rpr0521_read_ps_offset(struct rpr0521_data *data, int *offset) +{ + int ret; + __le16 buffer; + + ret = regmap_bulk_read(data->regmap, + RPR0521_REG_PS_OFFSET_LSB, &buffer, sizeof(buffer)); + + if (ret < 0) { + dev_err(&data->client->dev, "Failed to read PS OFFSET register\n"); + return ret; + } + *offset = le16_to_cpu(buffer); + + return ret; +} + +static int rpr0521_write_ps_offset(struct rpr0521_data *data, int offset) +{ + int ret; + __le16 buffer; + + buffer = cpu_to_le16(offset & 0x3ff); + ret = regmap_raw_write(data->regmap, + RPR0521_REG_PS_OFFSET_LSB, &buffer, sizeof(buffer)); + + if (ret < 0) { + dev_err(&data->client->dev, "Failed to write PS OFFSET register\n"); + return ret; + } + + return ret; +} + static int rpr0521_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) @@ -339,7 +492,7 @@ static int rpr0521_read_raw(struct iio_dev *indio_dev, ret = regmap_bulk_read(data->regmap, rpr0521_data_reg[chan->address].address, - &raw_data, 2); + &raw_data, sizeof(raw_data)); if (ret < 0) { rpr0521_set_power_state(data, false, device_mask); mutex_unlock(&data->lock); @@ -354,6 +507,7 @@ static int rpr0521_read_raw(struct iio_dev *indio_dev, *val = le16_to_cpu(raw_data); return IIO_VAL_INT; + case IIO_CHAN_INFO_SCALE: mutex_lock(&data->lock); ret = rpr0521_get_gain(data, chan->address, val, val2); @@ -362,6 +516,25 @@ static int rpr0521_read_raw(struct iio_dev *indio_dev, return ret; return IIO_VAL_INT_PLUS_MICRO; + + case IIO_CHAN_INFO_SAMP_FREQ: + mutex_lock(&data->lock); + ret = rpr0521_read_samp_freq(data, chan->type, val, val2); + mutex_unlock(&data->lock); + if (ret < 0) + return ret; + + return IIO_VAL_INT_PLUS_MICRO; + + case IIO_CHAN_INFO_OFFSET: + mutex_lock(&data->lock); + ret = rpr0521_read_ps_offset(data, val); + mutex_unlock(&data->lock); + if (ret < 0) + return ret; + + return IIO_VAL_INT; + default: return -EINVAL; } @@ -381,6 +554,22 @@ static int rpr0521_write_raw(struct iio_dev *indio_dev, mutex_unlock(&data->lock); return ret; + + case IIO_CHAN_INFO_SAMP_FREQ: + mutex_lock(&data->lock); + ret = rpr0521_write_samp_freq_common(data, chan->type, + val, val2); + mutex_unlock(&data->lock); + + return ret; + + case IIO_CHAN_INFO_OFFSET: + mutex_lock(&data->lock); + ret = rpr0521_write_ps_offset(data, val); + mutex_unlock(&data->lock); + + return ret; + default: return -EINVAL; } @@ -419,12 +608,14 @@ static int rpr0521_init(struct rpr0521_data *data) return ret; } +#ifndef CONFIG_PM ret = rpr0521_als_enable(data, RPR0521_MODE_ALS_ENABLE); if (ret < 0) return ret; ret = rpr0521_pxs_enable(data, RPR0521_MODE_PXS_ENABLE); if (ret < 0) return ret; +#endif return 0; } @@ -510,13 +701,26 @@ static int rpr0521_probe(struct i2c_client *client, ret = pm_runtime_set_active(&client->dev); if (ret < 0) - return ret; + goto err_poweroff; pm_runtime_enable(&client->dev); pm_runtime_set_autosuspend_delay(&client->dev, RPR0521_SLEEP_DELAY_MS); pm_runtime_use_autosuspend(&client->dev); - return iio_device_register(indio_dev); + ret = iio_device_register(indio_dev); + if (ret) + goto err_pm_disable; + + return 0; + +err_pm_disable: + pm_runtime_disable(&client->dev); + pm_runtime_set_suspended(&client->dev); + pm_runtime_put_noidle(&client->dev); +err_poweroff: + rpr0521_poweroff(data); + + return ret; } static int rpr0521_remove(struct i2c_client *client) @@ -541,9 +745,16 @@ static int rpr0521_runtime_suspend(struct device *dev) struct rpr0521_data *data = iio_priv(indio_dev); int ret; - /* disable channels and sets {als,pxs}_dev_en to false */ mutex_lock(&data->lock); + /* If measurements are enabled, enable them on resume */ + if (!data->als_need_dis) + data->als_ps_need_en = data->als_dev_en; + if (!data->pxs_need_dis) + data->pxs_ps_need_en = data->pxs_dev_en; + + /* disable channels and sets {als,pxs}_dev_en to false */ ret = rpr0521_poweroff(data); + regcache_mark_dirty(data->regmap); mutex_unlock(&data->lock); return ret; @@ -555,6 +766,7 @@ static int rpr0521_runtime_resume(struct device *dev) struct rpr0521_data *data = iio_priv(indio_dev); int ret; + regcache_sync(data->regmap); if (data->als_ps_need_en) { ret = rpr0521_als_enable(data, RPR0521_MODE_ALS_ENABLE); if (ret < 0) @@ -568,6 +780,7 @@ static int rpr0521_runtime_resume(struct device *dev) return ret; data->pxs_ps_need_en = false; } + msleep(100); //wait for first measurement result return 0; } diff --git a/drivers/iio/light/tsl2583.c b/drivers/iio/light/tsl2583.c index a78b6025c465..1679181d2bdd 100644 --- a/drivers/iio/light/tsl2583.c +++ b/drivers/iio/light/tsl2583.c @@ -3,7 +3,7 @@ * within the TAOS tsl258x family of devices (tsl2580, tsl2581, tsl2583). * * Copyright (c) 2011, TAOS Corporation. - * Copyright (c) 2016 Brian Masney <masneyb@onstation.org> + * Copyright (c) 2016-2017 Brian Masney <masneyb@onstation.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,6 +27,7 @@ #include <linux/module.h> #include <linux/iio/iio.h> #include <linux/iio/sysfs.h> +#include <linux/pm_runtime.h> /* Device Registers and Masks */ #define TSL2583_CNTRL 0x00 @@ -64,6 +65,8 @@ #define TSL2583_CHIP_ID 0x90 #define TSL2583_CHIP_ID_MASK 0xf0 +#define TSL2583_POWER_OFF_DELAY_MS 2000 + /* Per-device data */ struct tsl2583_als_info { u16 als_ch0; @@ -108,7 +111,6 @@ struct tsl2583_chip { struct tsl2583_settings als_settings; int als_time_scale; int als_saturation; - bool suspended; }; struct gainadj { @@ -460,8 +462,6 @@ static int tsl2583_chip_init_and_power_on(struct iio_dev *indio_dev) if (ret < 0) return ret; - chip->suspended = false; - return ret; } @@ -513,11 +513,6 @@ static ssize_t in_illuminance_calibrate_store(struct device *dev, mutex_lock(&chip->als_mutex); - if (chip->suspended) { - ret = -EBUSY; - goto done; - } - ret = tsl2583_als_calibrate(indio_dev); if (ret < 0) goto done; @@ -645,20 +640,36 @@ static const struct iio_chan_spec tsl2583_channels[] = { }, }; +static int tsl2583_set_pm_runtime_busy(struct tsl2583_chip *chip, bool on) +{ + int ret; + + if (on) { + ret = pm_runtime_get_sync(&chip->client->dev); + if (ret < 0) + pm_runtime_put_noidle(&chip->client->dev); + } else { + pm_runtime_mark_last_busy(&chip->client->dev); + ret = pm_runtime_put_autosuspend(&chip->client->dev); + } + + return ret; +} + static int tsl2583_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) { struct tsl2583_chip *chip = iio_priv(indio_dev); - int ret = -EINVAL; + int ret, pm_ret; - mutex_lock(&chip->als_mutex); + ret = tsl2583_set_pm_runtime_busy(chip, true); + if (ret < 0) + return ret; - if (chip->suspended) { - ret = -EBUSY; - goto read_done; - } + mutex_lock(&chip->als_mutex); + ret = -EINVAL; switch (mask) { case IIO_CHAN_INFO_RAW: if (chan->type == IIO_LIGHT) { @@ -719,6 +730,18 @@ static int tsl2583_read_raw(struct iio_dev *indio_dev, read_done: mutex_unlock(&chip->als_mutex); + if (ret < 0) + return ret; + + /* + * Preserve the ret variable if the call to + * tsl2583_set_pm_runtime_busy() is successful so the reading + * (if applicable) is returned to user space. + */ + pm_ret = tsl2583_set_pm_runtime_busy(chip, false); + if (pm_ret < 0) + return pm_ret; + return ret; } @@ -727,15 +750,15 @@ static int tsl2583_write_raw(struct iio_dev *indio_dev, int val, int val2, long mask) { struct tsl2583_chip *chip = iio_priv(indio_dev); - int ret = -EINVAL; + int ret; - mutex_lock(&chip->als_mutex); + ret = tsl2583_set_pm_runtime_busy(chip, true); + if (ret < 0) + return ret; - if (chip->suspended) { - ret = -EBUSY; - goto write_done; - } + mutex_lock(&chip->als_mutex); + ret = -EINVAL; switch (mask) { case IIO_CHAN_INFO_CALIBBIAS: if (chan->type == IIO_LIGHT) { @@ -767,9 +790,15 @@ static int tsl2583_write_raw(struct iio_dev *indio_dev, break; } -write_done: mutex_unlock(&chip->als_mutex); + if (ret < 0) + return ret; + + ret = tsl2583_set_pm_runtime_busy(chip, false); + if (ret < 0) + return ret; + return ret; } @@ -803,7 +832,6 @@ static int tsl2583_probe(struct i2c_client *clientp, i2c_set_clientdata(clientp, indio_dev); mutex_init(&chip->als_mutex); - chip->suspended = true; ret = i2c_smbus_read_byte_data(clientp, TSL2583_CMD_REG | TSL2583_CHIPID); @@ -826,6 +854,11 @@ static int tsl2583_probe(struct i2c_client *clientp, indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->name = chip->client->name; + pm_runtime_enable(&clientp->dev); + pm_runtime_set_autosuspend_delay(&clientp->dev, + TSL2583_POWER_OFF_DELAY_MS); + pm_runtime_use_autosuspend(&clientp->dev); + ret = devm_iio_device_register(indio_dev->dev.parent, indio_dev); if (ret) { dev_err(&clientp->dev, "%s: iio registration failed\n", @@ -836,16 +869,25 @@ static int tsl2583_probe(struct i2c_client *clientp, /* Load up the V2 defaults (these are hard coded defaults for now) */ tsl2583_defaults(chip); - /* Make sure the chip is on */ - ret = tsl2583_chip_init_and_power_on(indio_dev); - if (ret < 0) - return ret; - dev_info(&clientp->dev, "Light sensor found.\n"); return 0; } +static int tsl2583_remove(struct i2c_client *client) +{ + struct iio_dev *indio_dev = i2c_get_clientdata(client); + struct tsl2583_chip *chip = iio_priv(indio_dev); + + iio_device_unregister(indio_dev); + + pm_runtime_disable(&client->dev); + pm_runtime_set_suspended(&client->dev); + pm_runtime_put_noidle(&client->dev); + + return tsl2583_set_power_state(chip, TSL2583_CNTL_PWR_OFF); +} + static int __maybe_unused tsl2583_suspend(struct device *dev) { struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); @@ -855,7 +897,6 @@ static int __maybe_unused tsl2583_suspend(struct device *dev) mutex_lock(&chip->als_mutex); ret = tsl2583_set_power_state(chip, TSL2583_CNTL_PWR_OFF); - chip->suspended = true; mutex_unlock(&chip->als_mutex); @@ -877,7 +918,11 @@ static int __maybe_unused tsl2583_resume(struct device *dev) return ret; } -static SIMPLE_DEV_PM_OPS(tsl2583_pm_ops, tsl2583_suspend, tsl2583_resume); +static const struct dev_pm_ops tsl2583_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) + SET_RUNTIME_PM_OPS(tsl2583_suspend, tsl2583_resume, NULL) +}; static struct i2c_device_id tsl2583_idtable[] = { { "tsl2580", 0 }, @@ -904,6 +949,7 @@ static struct i2c_driver tsl2583_driver = { }, .id_table = tsl2583_idtable, .probe = tsl2583_probe, + .remove = tsl2583_remove, }; module_i2c_driver(tsl2583_driver); diff --git a/drivers/iio/magnetometer/st_magn_spi.c b/drivers/iio/magnetometer/st_magn_spi.c index 6325e7dc8e03..f3cb4dc05391 100644 --- a/drivers/iio/magnetometer/st_magn_spi.c +++ b/drivers/iio/magnetometer/st_magn_spi.c @@ -48,8 +48,6 @@ static int st_magn_spi_remove(struct spi_device *spi) } static const struct spi_device_id st_magn_id_table[] = { - { LSM303DLHC_MAGN_DEV_NAME }, - { LSM303DLM_MAGN_DEV_NAME }, { LIS3MDL_MAGN_DEV_NAME }, { LSM303AGR_MAGN_DEV_NAME }, {}, diff --git a/drivers/iio/orientation/hid-sensor-rotation.c b/drivers/iio/orientation/hid-sensor-rotation.c index a97e802ca523..e9fa86c87db5 100644 --- a/drivers/iio/orientation/hid-sensor-rotation.c +++ b/drivers/iio/orientation/hid-sensor-rotation.c @@ -31,6 +31,10 @@ struct dev_rot_state { struct hid_sensor_common common_attributes; struct hid_sensor_hub_attribute_info quaternion; u32 sampled_vals[4]; + int scale_pre_decml; + int scale_post_decml; + int scale_precision; + int value_offset; }; /* Channel definitions */ @@ -41,6 +45,8 @@ static const struct iio_chan_spec dev_rot_channels[] = { .channel2 = IIO_MOD_QUATERNION, .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | + BIT(IIO_CHAN_INFO_OFFSET) | + BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_HYSTERESIS) } }; @@ -80,6 +86,15 @@ static int dev_rot_read_raw(struct iio_dev *indio_dev, } else ret_type = -EINVAL; break; + case IIO_CHAN_INFO_SCALE: + vals[0] = rot_state->scale_pre_decml; + vals[1] = rot_state->scale_post_decml; + return rot_state->scale_precision; + + case IIO_CHAN_INFO_OFFSET: + *vals = rot_state->value_offset; + return IIO_VAL_INT; + case IIO_CHAN_INFO_SAMP_FREQ: ret_type = hid_sensor_read_samp_freq_value( &rot_state->common_attributes, &vals[0], &vals[1]); @@ -199,6 +214,11 @@ static int dev_rot_parse_report(struct platform_device *pdev, dev_dbg(&pdev->dev, "dev_rot: attrib size %d\n", st->quaternion.size); + st->scale_precision = hid_sensor_format_scale( + hsdev->usage, + &st->quaternion, + &st->scale_pre_decml, &st->scale_post_decml); + /* Set Sensitivity field ids, when there is no individual modifier */ if (st->common_attributes.sensitivity.index < 0) { sensor_hub_input_get_attribute_info(hsdev, @@ -218,7 +238,7 @@ static int dev_rot_parse_report(struct platform_device *pdev, static int hid_dev_rot_probe(struct platform_device *pdev) { int ret; - static char *name = "dev_rotation"; + static char *name; struct iio_dev *indio_dev; struct dev_rot_state *rot_state; struct hid_sensor_hub_device *hsdev = pdev->dev.platform_data; @@ -234,8 +254,21 @@ static int hid_dev_rot_probe(struct platform_device *pdev) rot_state->common_attributes.hsdev = hsdev; rot_state->common_attributes.pdev = pdev; - ret = hid_sensor_parse_common_attributes(hsdev, - HID_USAGE_SENSOR_DEVICE_ORIENTATION, + switch (hsdev->usage) { + case HID_USAGE_SENSOR_DEVICE_ORIENTATION: + name = "dev_rotation"; + break; + case HID_USAGE_SENSOR_RELATIVE_ORIENTATION: + name = "relative_orientation"; + break; + case HID_USAGE_SENSOR_GEOMAGNETIC_ORIENTATION: + name = "geomagnetic_orientation"; + break; + default: + return -EINVAL; + } + + ret = hid_sensor_parse_common_attributes(hsdev, hsdev->usage, &rot_state->common_attributes); if (ret) { dev_err(&pdev->dev, "failed to setup common attributes\n"); @@ -252,8 +285,7 @@ static int hid_dev_rot_probe(struct platform_device *pdev) ret = dev_rot_parse_report(pdev, hsdev, (struct iio_chan_spec *)indio_dev->channels, - HID_USAGE_SENSOR_DEVICE_ORIENTATION, - rot_state); + hsdev->usage, rot_state); if (ret) { dev_err(&pdev->dev, "failed to setup attributes\n"); return ret; @@ -288,8 +320,7 @@ static int hid_dev_rot_probe(struct platform_device *pdev) rot_state->callbacks.send_event = dev_rot_proc_event; rot_state->callbacks.capture_sample = dev_rot_capture_sample; rot_state->callbacks.pdev = pdev; - ret = sensor_hub_register_callback(hsdev, - HID_USAGE_SENSOR_DEVICE_ORIENTATION, + ret = sensor_hub_register_callback(hsdev, hsdev->usage, &rot_state->callbacks); if (ret) { dev_err(&pdev->dev, "callback reg failed\n"); @@ -314,7 +345,7 @@ static int hid_dev_rot_remove(struct platform_device *pdev) struct iio_dev *indio_dev = platform_get_drvdata(pdev); struct dev_rot_state *rot_state = iio_priv(indio_dev); - sensor_hub_remove_callback(hsdev, HID_USAGE_SENSOR_DEVICE_ORIENTATION); + sensor_hub_remove_callback(hsdev, hsdev->usage); iio_device_unregister(indio_dev); hid_sensor_remove_trigger(&rot_state->common_attributes); iio_triggered_buffer_cleanup(indio_dev); @@ -327,6 +358,14 @@ static const struct platform_device_id hid_dev_rot_ids[] = { /* Format: HID-SENSOR-usage_id_in_hex_lowercase */ .name = "HID-SENSOR-20008a", }, + { + /* Relative orientation(AG) sensor */ + .name = "HID-SENSOR-20008e", + }, + { + /* Geomagnetic orientation(AM) sensor */ + .name = "HID-SENSOR-2000c1", + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(platform, hid_dev_rot_ids); diff --git a/drivers/iio/pressure/Kconfig b/drivers/iio/pressure/Kconfig index 5d16b252ab6b..eaa7cfcb4c2a 100644 --- a/drivers/iio/pressure/Kconfig +++ b/drivers/iio/pressure/Kconfig @@ -23,7 +23,7 @@ config BMP280 select BMP280_SPI if (SPI_MASTER) help Say yes here to build support for Bosch Sensortec BMP180 and BMP280 - pressure and temperature sensors. Also supports the BE280 with + pressure and temperature sensors. Also supports the BME280 with an additional humidity sensor channel. To compile this driver as a module, choose M here: the core module diff --git a/drivers/iio/pressure/st_pressure_core.c b/drivers/iio/pressure/st_pressure_core.c index fd0edca0e656..aa61ec15c139 100644 --- a/drivers/iio/pressure/st_pressure_core.c +++ b/drivers/iio/pressure/st_pressure_core.c @@ -568,6 +568,8 @@ static const struct iio_trigger_ops st_press_trigger_ops = { int st_press_common_probe(struct iio_dev *indio_dev) { struct st_sensor_data *press_data = iio_priv(indio_dev); + struct st_sensors_platform_data *pdata = + (struct st_sensors_platform_data *)press_data->dev->platform_data; int irq = press_data->get_irq_data_ready(indio_dev); int err; @@ -603,10 +605,8 @@ int st_press_common_probe(struct iio_dev *indio_dev) press_data->odr = press_data->sensor_settings->odr.odr_avl[0].hz; /* Some devices don't support a data ready pin. */ - if (!press_data->dev->platform_data && - press_data->sensor_settings->drdy_irq.addr) - press_data->dev->platform_data = - (struct st_sensors_platform_data *)&default_press_pdata; + if (!pdata && press_data->sensor_settings->drdy_irq.addr) + pdata = (struct st_sensors_platform_data *)&default_press_pdata; err = st_sensors_init_sensor(indio_dev, press_data->dev->platform_data); if (err < 0) diff --git a/drivers/iio/pressure/zpa2326.c b/drivers/iio/pressure/zpa2326.c index e58a0ad07477..c92a95f9f52c 100644 --- a/drivers/iio/pressure/zpa2326.c +++ b/drivers/iio/pressure/zpa2326.c @@ -867,12 +867,13 @@ static int zpa2326_wait_oneshot_completion(const struct iio_dev *indio_dev, { int ret; unsigned int val; + long timeout; zpa2326_dbg(indio_dev, "waiting for one shot completion interrupt"); - ret = wait_for_completion_interruptible_timeout( + timeout = wait_for_completion_interruptible_timeout( &private->data_ready, ZPA2326_CONVERSION_JIFFIES); - if (ret > 0) + if (timeout > 0) /* * Interrupt handler completed before timeout: return operation * status. @@ -882,13 +883,16 @@ static int zpa2326_wait_oneshot_completion(const struct iio_dev *indio_dev, /* Clear all interrupts just to be sure. */ regmap_read(private->regmap, ZPA2326_INT_SOURCE_REG, &val); - if (!ret) + if (!timeout) { /* Timed out. */ + zpa2326_warn(indio_dev, "no one shot interrupt occurred (%ld)", + timeout); ret = -ETIME; - - if (ret != -ERESTARTSYS) - zpa2326_warn(indio_dev, "no one shot interrupt occurred (%d)", - ret); + } else if (timeout < 0) { + zpa2326_warn(indio_dev, + "wait for one shot interrupt cancelled"); + ret = -ERESTARTSYS; + } return ret; } diff --git a/drivers/iio/proximity/as3935.c b/drivers/iio/proximity/as3935.c index aa4df0dcc8c9..0eeff29b61be 100644 --- a/drivers/iio/proximity/as3935.c +++ b/drivers/iio/proximity/as3935.c @@ -176,13 +176,13 @@ static int as3935_read_raw(struct iio_dev *indio_dev, if (ret) return ret; - if (m == IIO_CHAN_INFO_RAW) - return IIO_VAL_INT; - /* storm out of range */ if (*val == AS3935_DATA_MASK) return -EINVAL; + if (m == IIO_CHAN_INFO_RAW) + return IIO_VAL_INT; + if (m == IIO_CHAN_INFO_PROCESSED) *val *= 1000; break; diff --git a/drivers/iio/proximity/sx9500.c b/drivers/iio/proximity/sx9500.c index 9ea147f1a50d..f42b3a1c75ff 100644 --- a/drivers/iio/proximity/sx9500.c +++ b/drivers/iio/proximity/sx9500.c @@ -878,8 +878,7 @@ static void sx9500_gpio_probe(struct i2c_client *client, dev = &client->dev; - data->gpiod_rst = devm_gpiod_get_index(dev, SX9500_GPIO_RESET, - 0, GPIOD_OUT_HIGH); + data->gpiod_rst = devm_gpiod_get(dev, SX9500_GPIO_RESET, GPIOD_OUT_HIGH); if (IS_ERR(data->gpiod_rst)) { dev_warn(dev, "gpio get reset pin failed\n"); data->gpiod_rst = NULL; diff --git a/drivers/iio/temperature/maxim_thermocouple.c b/drivers/iio/temperature/maxim_thermocouple.c index 557214202eff..d70e2e53d6a7 100644 --- a/drivers/iio/temperature/maxim_thermocouple.c +++ b/drivers/iio/temperature/maxim_thermocouple.c @@ -267,6 +267,7 @@ static int maxim_thermocouple_remove(struct spi_device *spi) static const struct spi_device_id maxim_thermocouple_id[] = { {"max6675", MAX6675}, {"max31855", MAX31855}, + {"max31856", MAX31855}, {}, }; MODULE_DEVICE_TABLE(spi, maxim_thermocouple_id); diff --git a/drivers/iio/trigger/stm32-timer-trigger.c b/drivers/iio/trigger/stm32-timer-trigger.c index 25248d644e7c..d22bc56dd9fc 100644 --- a/drivers/iio/trigger/stm32-timer-trigger.c +++ b/drivers/iio/trigger/stm32-timer-trigger.c @@ -14,19 +14,19 @@ #include <linux/module.h> #include <linux/platform_device.h> -#define MAX_TRIGGERS 6 +#define MAX_TRIGGERS 7 #define MAX_VALIDS 5 /* List the triggers created by each timer */ static const void *triggers_table[][MAX_TRIGGERS] = { - { TIM1_TRGO, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,}, + { TIM1_TRGO, TIM1_TRGO2, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,}, { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,}, { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,}, { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,}, { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,}, { TIM6_TRGO,}, { TIM7_TRGO,}, - { TIM8_TRGO, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,}, + { TIM8_TRGO, TIM8_TRGO2, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,}, { TIM9_TRGO, TIM9_CH1, TIM9_CH2,}, { }, /* timer 10 */ { }, /* timer 11 */ @@ -56,9 +56,16 @@ struct stm32_timer_trigger { u32 max_arr; const void *triggers; const void *valids; + bool has_trgo2; }; +static bool stm32_timer_is_trgo2_name(const char *name) +{ + return !!strstr(name, "trgo2"); +} + static int stm32_timer_start(struct stm32_timer_trigger *priv, + struct iio_trigger *trig, unsigned int frequency) { unsigned long long prd, div; @@ -102,7 +109,12 @@ static int stm32_timer_start(struct stm32_timer_trigger *priv, regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE); /* Force master mode to update mode */ - regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0x20); + if (stm32_timer_is_trgo2_name(trig->name)) + regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, + 0x2 << TIM_CR2_MMS2_SHIFT); + else + regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, + 0x2 << TIM_CR2_MMS_SHIFT); /* Make sure that registers are updated */ regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); @@ -150,7 +162,7 @@ static ssize_t stm32_tt_store_frequency(struct device *dev, if (freq == 0) { stm32_timer_stop(priv); } else { - ret = stm32_timer_start(priv, freq); + ret = stm32_timer_start(priv, trig, freq); if (ret) return ret; } @@ -183,6 +195,9 @@ static IIO_DEV_ATTR_SAMP_FREQ(0660, stm32_tt_read_frequency, stm32_tt_store_frequency); +#define MASTER_MODE_MAX 7 +#define MASTER_MODE2_MAX 15 + static char *master_mode_table[] = { "reset", "enable", @@ -191,7 +206,16 @@ static char *master_mode_table[] = { "OC1REF", "OC2REF", "OC3REF", - "OC4REF" + "OC4REF", + /* Master mode selection 2 only */ + "OC5REF", + "OC6REF", + "compare_pulse_OC4REF", + "compare_pulse_OC6REF", + "compare_pulse_OC4REF_r_or_OC6REF_r", + "compare_pulse_OC4REF_r_or_OC6REF_f", + "compare_pulse_OC5REF_r_or_OC6REF_r", + "compare_pulse_OC5REF_r_or_OC6REF_f", }; static ssize_t stm32_tt_show_master_mode(struct device *dev, @@ -199,10 +223,15 @@ static ssize_t stm32_tt_show_master_mode(struct device *dev, char *buf) { struct stm32_timer_trigger *priv = dev_get_drvdata(dev); + struct iio_trigger *trig = to_iio_trigger(dev); u32 cr2; regmap_read(priv->regmap, TIM_CR2, &cr2); - cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT; + + if (stm32_timer_is_trgo2_name(trig->name)) + cr2 = (cr2 & TIM_CR2_MMS2) >> TIM_CR2_MMS2_SHIFT; + else + cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT; return snprintf(buf, PAGE_SIZE, "%s\n", master_mode_table[cr2]); } @@ -212,13 +241,25 @@ static ssize_t stm32_tt_store_master_mode(struct device *dev, const char *buf, size_t len) { struct stm32_timer_trigger *priv = dev_get_drvdata(dev); + struct iio_trigger *trig = to_iio_trigger(dev); + u32 mask, shift, master_mode_max; int i; - for (i = 0; i < ARRAY_SIZE(master_mode_table); i++) { + if (stm32_timer_is_trgo2_name(trig->name)) { + mask = TIM_CR2_MMS2; + shift = TIM_CR2_MMS2_SHIFT; + master_mode_max = MASTER_MODE2_MAX; + } else { + mask = TIM_CR2_MMS; + shift = TIM_CR2_MMS_SHIFT; + master_mode_max = MASTER_MODE_MAX; + } + + for (i = 0; i <= master_mode_max; i++) { if (!strncmp(master_mode_table[i], buf, strlen(master_mode_table[i]))) { - regmap_update_bits(priv->regmap, TIM_CR2, - TIM_CR2_MMS, i << TIM_CR2_MMS_SHIFT); + regmap_update_bits(priv->regmap, TIM_CR2, mask, + i << shift); /* Make sure that registers are updated */ regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); @@ -229,8 +270,31 @@ static ssize_t stm32_tt_store_master_mode(struct device *dev, return -EINVAL; } -static IIO_CONST_ATTR(master_mode_available, - "reset enable update compare_pulse OC1REF OC2REF OC3REF OC4REF"); +static ssize_t stm32_tt_show_master_mode_avail(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_trigger *trig = to_iio_trigger(dev); + unsigned int i, master_mode_max; + size_t len = 0; + + if (stm32_timer_is_trgo2_name(trig->name)) + master_mode_max = MASTER_MODE2_MAX; + else + master_mode_max = MASTER_MODE_MAX; + + for (i = 0; i <= master_mode_max; i++) + len += scnprintf(buf + len, PAGE_SIZE - len, + "%s ", master_mode_table[i]); + + /* replace trailing space by newline */ + buf[len - 1] = '\n'; + + return len; +} + +static IIO_DEVICE_ATTR(master_mode_available, 0444, + stm32_tt_show_master_mode_avail, NULL, 0); static IIO_DEVICE_ATTR(master_mode, 0660, stm32_tt_show_master_mode, @@ -240,7 +304,7 @@ static IIO_DEVICE_ATTR(master_mode, 0660, static struct attribute *stm32_trigger_attrs[] = { &iio_dev_attr_sampling_frequency.dev_attr.attr, &iio_dev_attr_master_mode.dev_attr.attr, - &iio_const_attr_master_mode_available.dev_attr.attr, + &iio_dev_attr_master_mode_available.dev_attr.attr, NULL, }; @@ -264,6 +328,12 @@ static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv) while (cur && *cur) { struct iio_trigger *trig; + bool cur_is_trgo2 = stm32_timer_is_trgo2_name(*cur); + + if (cur_is_trgo2 && !priv->has_trgo2) { + cur++; + continue; + } trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur); if (!trig) @@ -277,7 +347,7 @@ static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv) * should only be available on trgo trigger which * is always the first in the list. */ - if (cur == priv->triggers) + if (cur == priv->triggers || cur_is_trgo2) trig->dev.groups = stm32_trigger_attr_groups; iio_trigger_set_drvdata(trig, priv); @@ -347,12 +417,70 @@ static int stm32_counter_write_raw(struct iio_dev *indio_dev, return -EINVAL; } +static int stm32_counter_validate_trigger(struct iio_dev *indio_dev, + struct iio_trigger *trig) +{ + struct stm32_timer_trigger *priv = iio_priv(indio_dev); + const char * const *cur = priv->valids; + unsigned int i = 0; + + if (!is_stm32_timer_trigger(trig)) + return -EINVAL; + + while (cur && *cur) { + if (!strncmp(trig->name, *cur, strlen(trig->name))) { + regmap_update_bits(priv->regmap, + TIM_SMCR, TIM_SMCR_TS, + i << TIM_SMCR_TS_SHIFT); + return 0; + } + cur++; + i++; + } + + return -EINVAL; +} + static const struct iio_info stm32_trigger_info = { .driver_module = THIS_MODULE, + .validate_trigger = stm32_counter_validate_trigger, .read_raw = stm32_counter_read_raw, .write_raw = stm32_counter_write_raw }; +static const char *const stm32_trigger_modes[] = { + "trigger", +}; + +static int stm32_set_trigger_mode(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int mode) +{ + struct stm32_timer_trigger *priv = iio_priv(indio_dev); + + regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, TIM_SMCR_SMS); + + return 0; +} + +static int stm32_get_trigger_mode(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct stm32_timer_trigger *priv = iio_priv(indio_dev); + u32 smcr; + + regmap_read(priv->regmap, TIM_SMCR, &smcr); + + return smcr == TIM_SMCR_SMS ? 0 : -EINVAL; +} + +static const struct iio_enum stm32_trigger_mode_enum = { + .items = stm32_trigger_modes, + .num_items = ARRAY_SIZE(stm32_trigger_modes), + .set = stm32_set_trigger_mode, + .get = stm32_get_trigger_mode +}; + static const char *const stm32_enable_modes[] = { "always", "gated", @@ -536,6 +664,8 @@ static const struct iio_chan_spec_ext_info stm32_trigger_count_info[] = { IIO_ENUM_AVAILABLE("quadrature_mode", &stm32_quadrature_mode_enum), IIO_ENUM("enable_mode", IIO_SEPARATE, &stm32_enable_mode_enum), IIO_ENUM_AVAILABLE("enable_mode", &stm32_enable_mode_enum), + IIO_ENUM("trigger_mode", IIO_SEPARATE, &stm32_trigger_mode_enum), + IIO_ENUM_AVAILABLE("trigger_mode", &stm32_trigger_mode_enum), {} }; @@ -560,6 +690,7 @@ static struct stm32_timer_trigger *stm32_setup_counter_device(struct device *dev indio_dev->name = dev_name(dev); indio_dev->dev.parent = dev; indio_dev->info = &stm32_trigger_info; + indio_dev->modes = INDIO_HARDWARE_TRIGGERED; indio_dev->num_channels = 1; indio_dev->channels = &stm32_trigger_channel; indio_dev->dev.of_node = dev->of_node; @@ -584,6 +715,20 @@ bool is_stm32_timer_trigger(struct iio_trigger *trig) } EXPORT_SYMBOL(is_stm32_timer_trigger); +static void stm32_timer_detect_trgo2(struct stm32_timer_trigger *priv) +{ + u32 val; + + /* + * Master mode selection 2 bits can only be written and read back when + * timer supports it. + */ + regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2); + regmap_read(priv->regmap, TIM_CR2, &val); + regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0); + priv->has_trgo2 = !!val; +} + static int stm32_timer_trigger_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -614,6 +759,7 @@ static int stm32_timer_trigger_probe(struct platform_device *pdev) priv->max_arr = ddata->max_arr; priv->triggers = triggers_table[index]; priv->valids = valids_table[index]; + stm32_timer_detect_trgo2(priv); ret = stm32_setup_iio_triggers(priv); if (ret) diff --git a/drivers/staging/android/ion/ion-ioctl.c b/drivers/staging/android/ion/ion-ioctl.c index 76427e4773a8..d9f8b1424da1 100644 --- a/drivers/staging/android/ion/ion-ioctl.c +++ b/drivers/staging/android/ion/ion-ioctl.c @@ -83,8 +83,8 @@ long ion_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) int fd; fd = ion_alloc(data.allocation.len, - data.allocation.heap_id_mask, - data.allocation.flags); + data.allocation.heap_id_mask, + data.allocation.flags); if (fd < 0) return fd; diff --git a/drivers/staging/android/ion/ion.c b/drivers/staging/android/ion/ion.c index 03d3a4fce0e2..93e2c90fa77d 100644 --- a/drivers/staging/android/ion/ion.c +++ b/drivers/staging/android/ion/ion.c @@ -103,7 +103,7 @@ static struct ion_buffer *ion_buffer_create(struct ion_heap *heap, goto err2; } - if (buffer->sg_table == NULL) { + if (!buffer->sg_table) { WARN_ONCE(1, "This heap needs to set the sgtable"); ret = -EINVAL; goto err1; @@ -115,7 +115,6 @@ static struct ion_buffer *ion_buffer_create(struct ion_heap *heap, buffer->dev = dev; buffer->size = len; - INIT_LIST_HEAD(&buffer->vmas); INIT_LIST_HEAD(&buffer->attachments); mutex_init(&buffer->lock); mutex_lock(&dev->buffer_lock); @@ -135,7 +134,6 @@ void ion_buffer_destroy(struct ion_buffer *buffer) if (WARN_ON(buffer->kmap_cnt > 0)) buffer->heap->ops->unmap_kernel(buffer->heap, buffer); buffer->heap->ops->free(buffer); - vfree(buffer->pages); kfree(buffer); } @@ -163,7 +161,7 @@ static void *ion_buffer_kmap_get(struct ion_buffer *buffer) return buffer->vaddr; } vaddr = buffer->heap->ops->map_kernel(buffer->heap, buffer); - if (WARN_ONCE(vaddr == NULL, + if (WARN_ONCE(!vaddr, "heap->ops->map_kernel should return ERR_PTR on error")) return ERR_PTR(-EINVAL); if (IS_ERR(vaddr)) @@ -221,7 +219,7 @@ struct ion_dma_buf_attachment { }; static int ion_dma_buf_attach(struct dma_buf *dmabuf, struct device *dev, - struct dma_buf_attachment *attachment) + struct dma_buf_attachment *attachment) { struct ion_dma_buf_attachment *a; struct sg_table *table; @@ -264,26 +262,19 @@ static void ion_dma_buf_detatch(struct dma_buf *dmabuf, kfree(a); } - static struct sg_table *ion_map_dma_buf(struct dma_buf_attachment *attachment, enum dma_data_direction direction) { struct ion_dma_buf_attachment *a = attachment->priv; struct sg_table *table; - int ret; table = a->table; if (!dma_map_sg(attachment->dev, table->sgl, table->nents, - direction)){ - ret = -ENOMEM; - goto err; - } - return table; + direction)) + return ERR_PTR(-ENOMEM); -err: - free_duped_table(table); - return ERR_PTR(ret); + return table; } static void ion_unmap_dma_buf(struct dma_buf_attachment *attachment, @@ -354,11 +345,10 @@ static int ion_dma_buf_begin_cpu_access(struct dma_buf *dmabuf, mutex_unlock(&buffer->lock); } - mutex_lock(&buffer->lock); list_for_each_entry(a, &buffer->attachments, list) { dma_sync_sg_for_cpu(a->dev, a->table->sgl, a->table->nents, - DMA_BIDIRECTIONAL); + DMA_BIDIRECTIONAL); } mutex_unlock(&buffer->lock); @@ -380,7 +370,7 @@ static int ion_dma_buf_end_cpu_access(struct dma_buf *dmabuf, mutex_lock(&buffer->lock); list_for_each_entry(a, &buffer->attachments, list) { dma_sync_sg_for_device(a->dev, a->table->sgl, a->table->nents, - DMA_BIDIRECTIONAL); + DMA_BIDIRECTIONAL); } mutex_unlock(&buffer->lock); @@ -435,7 +425,7 @@ int ion_alloc(size_t len, unsigned int heap_id_mask, unsigned int flags) } up_read(&dev->lock); - if (buffer == NULL) + if (!buffer) return -ENODEV; if (IS_ERR(buffer)) @@ -596,7 +586,7 @@ void ion_device_add_heap(struct ion_heap *heap) } EXPORT_SYMBOL(ion_device_add_heap); -int ion_device_create(void) +static int ion_device_create(void) { struct ion_device *idev; int ret; diff --git a/drivers/staging/android/ion/ion.h b/drivers/staging/android/ion/ion.h index ace8416bd509..fa9ed81ab972 100644 --- a/drivers/staging/android/ion/ion.h +++ b/drivers/staging/android/ion/ion.h @@ -68,14 +68,6 @@ struct ion_platform_heap { * @kmap_cnt: number of times the buffer is mapped to the kernel * @vaddr: the kernel mapping if kmap_cnt is not zero * @sg_table: the sg table for the buffer if dmap_cnt is not zero - * @pages: flat array of pages in the buffer -- used by fault - * handler and only valid for buffers that are faulted in - * @vmas: list of vma's mapping this buffer - * @handle_count: count of handles referencing this buffer - * @task_comm: taskcomm of last client to reference this buffer in a - * handle, used for debugging - * @pid: pid of last client to reference this buffer in a - * handle, used for debugging */ struct ion_buffer { union { @@ -92,13 +84,7 @@ struct ion_buffer { int kmap_cnt; void *vaddr; struct sg_table *sg_table; - struct page **pages; - struct list_head vmas; struct list_head attachments; - /* used to track orphaned buffers */ - int handle_count; - char task_comm[TASK_COMM_LEN]; - pid_t pid; }; void ion_buffer_destroy(struct ion_buffer *buffer); diff --git a/drivers/staging/android/ion/ion_carveout_heap.c b/drivers/staging/android/ion/ion_carveout_heap.c index 5fdc1f328f61..fee7650d6fbb 100644 --- a/drivers/staging/android/ion/ion_carveout_heap.c +++ b/drivers/staging/android/ion/ion_carveout_heap.c @@ -33,7 +33,7 @@ struct ion_carveout_heap { }; static phys_addr_t ion_carveout_allocate(struct ion_heap *heap, - unsigned long size) + unsigned long size) { struct ion_carveout_heap *carveout_heap = container_of(heap, struct ion_carveout_heap, heap); diff --git a/drivers/staging/android/ion/ion_system_heap.c b/drivers/staging/android/ion/ion_system_heap.c index c50f2d9fc58c..5964bf21fd80 100644 --- a/drivers/staging/android/ion/ion_system_heap.c +++ b/drivers/staging/android/ion/ion_system_heap.c @@ -153,7 +153,7 @@ static int ion_system_heap_allocate(struct ion_heap *heap, max_order = compound_order(page); i++; } - table = kmalloc(sizeof(struct sg_table), GFP_KERNEL); + table = kmalloc(sizeof(*table), GFP_KERNEL); if (!table) goto free_pages; @@ -383,7 +383,7 @@ static int ion_system_contig_heap_allocate(struct ion_heap *heap, for (i = len >> PAGE_SHIFT; i < (1 << order); i++) __free_page(page + i); - table = kmalloc(sizeof(struct sg_table), GFP_KERNEL); + table = kmalloc(sizeof(*table), GFP_KERNEL); if (!table) { ret = -ENOMEM; goto free_pages; @@ -433,7 +433,7 @@ static struct ion_heap *__ion_system_contig_heap_create(void) { struct ion_heap *heap; - heap = kzalloc(sizeof(struct ion_heap), GFP_KERNEL); + heap = kzalloc(sizeof(*heap), GFP_KERNEL); if (!heap) return ERR_PTR(-ENOMEM); heap->ops = &kmalloc_ops; diff --git a/drivers/staging/android/uapi/ion.h b/drivers/staging/android/uapi/ion.h index b76db1b2e197..9e21451149d0 100644 --- a/drivers/staging/android/uapi/ion.h +++ b/drivers/staging/android/uapi/ion.h @@ -57,12 +57,6 @@ enum ion_heap_type { */ #define ION_FLAG_CACHED 1 -/* - * mappings of this buffer will created at mmap time, if this is set - * caches must be managed manually - */ -#define ION_FLAG_CACHED_NEEDS_SYNC 2 - /** * DOC: Ion Userspace API * @@ -131,24 +125,6 @@ struct ion_heap_query { struct ion_allocation_data) /** - * DOC: ION_IOC_FREE - free memory - * - * Takes an ion_handle_data struct and frees the handle. - */ -#define ION_IOC_FREE _IOWR(ION_IOC_MAGIC, 1, struct ion_handle_data) - -/** - * DOC: ION_IOC_SHARE - creates a file descriptor to use to share an allocation - * - * Takes an ion_fd_data struct with the handle field populated with a valid - * opaque handle. Returns the struct with the fd field set to a file - * descriptor open in the current address space. This file descriptor - * can then be passed to another process. The corresponding opaque handle can - * be retrieved via ION_IOC_IMPORT. - */ -#define ION_IOC_SHARE _IOWR(ION_IOC_MAGIC, 4, struct ion_fd_data) - -/** * DOC: ION_IOC_HEAP_QUERY - information about available heaps * * Takes an ion_heap_query structure and populates information about diff --git a/drivers/staging/ccree/Kconfig b/drivers/staging/ccree/Kconfig index 4be87f503e3b..36a87c686a2a 100644 --- a/drivers/staging/ccree/Kconfig +++ b/drivers/staging/ccree/Kconfig @@ -18,7 +18,7 @@ config CRYPTO_DEV_CCREE select CRYPTO_CTR select CRYPTO_XTS help - Say 'Y' to enable a driver for the Arm TrustZone CryptoCell + Say 'Y' to enable a driver for the Arm TrustZone CryptoCell C7xx. Currently only the CryptoCell 712 REE is supported. Choose this if you wish to use hardware acceleration of cryptographic operations on the system REE. @@ -32,12 +32,3 @@ config CCREE_FIPS_SUPPORT Say 'Y' to enable support for FIPS compliant mode by the CCREE driver. If unsure say N. - -config CCREE_DISABLE_COHERENT_DMA_OPS - bool "Disable Coherent DMA operations for the CCREE driver" - depends on CRYPTO_DEV_CCREE - default n - help - Say 'Y' to disable the use of coherent DMA operations by the - CCREE driver for debugging purposes. - If unsure say N. diff --git a/drivers/staging/ccree/Makefile b/drivers/staging/ccree/Makefile index 44f3e3e33989..318c2b39acf6 100644 --- a/drivers/staging/ccree/Makefile +++ b/drivers/staging/ccree/Makefile @@ -1,3 +1,3 @@ obj-$(CONFIG_CRYPTO_DEV_CCREE) := ccree.o -ccree-y := ssi_driver.o ssi_sysfs.o ssi_buffer_mgr.o ssi_request_mgr.o ssi_cipher.o ssi_hash.o ssi_aead.o ssi_ivgen.o ssi_sram_mgr.o ssi_pm.o ssi_pm_ext.o +ccree-y := ssi_driver.o ssi_sysfs.o ssi_buffer_mgr.o ssi_request_mgr.o ssi_cipher.o ssi_hash.o ssi_aead.o ssi_ivgen.o ssi_sram_mgr.o ssi_pm.o ccree-$(CCREE_FIPS_SUPPORT) += ssi_fips.o ssi_fips_ll.o ssi_fips_ext.o ssi_fips_local.o diff --git a/drivers/staging/ccree/cc_bitops.h b/drivers/staging/ccree/cc_bitops.h deleted file mode 100644 index 3a39565ef73b..000000000000 --- a/drivers/staging/ccree/cc_bitops.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see <http://www.gnu.org/licenses/>. - */ - -/*! - * \file cc_bitops.h - * Bit fields operations macros. - */ -#ifndef _CC_BITOPS_H_ -#define _CC_BITOPS_H_ - -#define BITMASK(mask_size) (((mask_size) < 32) ? \ - ((1UL << (mask_size)) - 1) : 0xFFFFFFFFUL) -#define BITMASK_AT(mask_size, mask_offset) (BITMASK(mask_size) << (mask_offset)) - -#define BITFIELD_GET(word, bit_offset, bit_size) \ - (((word) >> (bit_offset)) & BITMASK(bit_size)) -#define BITFIELD_SET(word, bit_offset, bit_size, new_val) do { \ - word = ((word) & ~BITMASK_AT(bit_size, bit_offset)) | \ - (((new_val) & BITMASK(bit_size)) << (bit_offset)); \ -} while (0) - -/* Is val aligned to "align" ("align" must be power of 2) */ -#ifndef IS_ALIGNED -#define IS_ALIGNED(val, align) \ - (((uintptr_t)(val) & ((align) - 1)) == 0) -#endif - -#define SWAP_ENDIAN(word) \ - (((word) >> 24) | (((word) & 0x00FF0000) >> 8) | \ - (((word) & 0x0000FF00) << 8) | (((word) & 0x000000FF) << 24)) - -#ifdef BIG__ENDIAN -#define SWAP_TO_LE(word) SWAP_ENDIAN(word) -#define SWAP_TO_BE(word) word -#else -#define SWAP_TO_LE(word) word -#define SWAP_TO_BE(word) SWAP_ENDIAN(word) -#endif - - - -/* Is val a multiple of "mult" ("mult" must be power of 2) */ -#define IS_MULT(val, mult) \ - (((val) & ((mult) - 1)) == 0) - -#define IS_NULL_ADDR(adr) \ - (!(adr)) - -#endif /*_CC_BITOPS_H_*/ diff --git a/drivers/staging/ccree/cc_crypto_ctx.h b/drivers/staging/ccree/cc_crypto_ctx.h index 9e10b2670313..591f6fdadc59 100644 --- a/drivers/staging/ccree/cc_crypto_ctx.h +++ b/drivers/staging/ccree/cc_crypto_ctx.h @@ -1,35 +1,23 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ - #ifndef _CC_CRYPTO_CTX_H_ #define _CC_CRYPTO_CTX_H_ -#ifdef __KERNEL__ #include <linux/types.h> -#define INT32_MAX 0x7FFFFFFFL -#else -#include <stdint.h> -#endif - - -#ifndef max -#define max(a, b) ((a) > (b) ? (a) : (b)) -#define min(a, b) ((a) < (b) ? (a) : (b)) -#endif /* context size */ #ifndef CC_CTX_SIZE_LOG2 @@ -39,7 +27,7 @@ #define CC_CTX_SIZE_LOG2 7 #endif #endif -#define CC_CTX_SIZE (1<<CC_CTX_SIZE_LOG2) +#define CC_CTX_SIZE BIT(CC_CTX_SIZE_LOG2) #define CC_DRV_CTX_SIZE_WORDS (CC_CTX_SIZE >> 2) #define CC_DRV_DES_IV_SIZE 8 @@ -65,13 +53,13 @@ #define CC_AES_KEY_SIZE_MAX CC_AES_256_BIT_KEY_SIZE #define CC_AES_KEY_SIZE_WORDS_MAX (CC_AES_KEY_SIZE_MAX >> 2) -#define CC_MD5_DIGEST_SIZE 16 -#define CC_SHA1_DIGEST_SIZE 20 -#define CC_SHA224_DIGEST_SIZE 28 -#define CC_SHA256_DIGEST_SIZE 32 +#define CC_MD5_DIGEST_SIZE 16 +#define CC_SHA1_DIGEST_SIZE 20 +#define CC_SHA224_DIGEST_SIZE 28 +#define CC_SHA256_DIGEST_SIZE 32 #define CC_SHA256_DIGEST_SIZE_IN_WORDS 8 -#define CC_SHA384_DIGEST_SIZE 48 -#define CC_SHA512_DIGEST_SIZE 64 +#define CC_SHA384_DIGEST_SIZE 48 +#define CC_SHA512_DIGEST_SIZE 64 #define CC_SHA1_BLOCK_SIZE 64 #define CC_SHA1_BLOCK_SIZE_IN_WORDS 16 @@ -94,18 +82,17 @@ #define CC_HMAC_BLOCK_SIZE_MAX CC_HASH_BLOCK_SIZE_MAX -#define CC_MULTI2_SYSTEM_KEY_SIZE 32 -#define CC_MULTI2_DATA_KEY_SIZE 8 -#define CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE (CC_MULTI2_SYSTEM_KEY_SIZE + CC_MULTI2_DATA_KEY_SIZE) +#define CC_MULTI2_SYSTEM_KEY_SIZE 32 +#define CC_MULTI2_DATA_KEY_SIZE 8 +#define CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE \ + (CC_MULTI2_SYSTEM_KEY_SIZE + CC_MULTI2_DATA_KEY_SIZE) #define CC_MULTI2_BLOCK_SIZE 8 #define CC_MULTI2_IV_SIZE 8 #define CC_MULTI2_MIN_NUM_ROUNDS 8 #define CC_MULTI2_MAX_NUM_ROUNDS 128 - #define CC_DRV_ALG_MAX_BLOCK_SIZE CC_HASH_BLOCK_SIZE_MAX - enum drv_engine_type { DRV_ENGINE_NULL = 0, DRV_ENGINE_AES = 1, @@ -113,7 +100,7 @@ enum drv_engine_type { DRV_ENGINE_HASH = 3, DRV_ENGINE_RC4 = 4, DRV_ENGINE_DOUT = 5, - DRV_ENGINE_RESERVE32B = INT32_MAX, + DRV_ENGINE_RESERVE32B = S32_MAX, }; enum drv_crypto_alg { @@ -126,7 +113,7 @@ enum drv_crypto_alg { DRV_CRYPTO_ALG_AEAD = 5, DRV_CRYPTO_ALG_BYPASS = 6, DRV_CRYPTO_ALG_NUM = 7, - DRV_CRYPTO_ALG_RESERVE32B = INT32_MAX + DRV_CRYPTO_ALG_RESERVE32B = S32_MAX }; enum drv_crypto_direction { @@ -134,7 +121,7 @@ enum drv_crypto_direction { DRV_CRYPTO_DIRECTION_ENCRYPT = 0, DRV_CRYPTO_DIRECTION_DECRYPT = 1, DRV_CRYPTO_DIRECTION_DECRYPT_ENCRYPT = 3, - DRV_CRYPTO_DIRECTION_RESERVE32B = INT32_MAX + DRV_CRYPTO_DIRECTION_RESERVE32B = S32_MAX }; enum drv_cipher_mode { @@ -152,7 +139,7 @@ enum drv_cipher_mode { DRV_CIPHER_GCTR = 12, DRV_CIPHER_ESSIV = 13, DRV_CIPHER_BITLOCKER = 14, - DRV_CIPHER_RESERVE32B = INT32_MAX + DRV_CIPHER_RESERVE32B = S32_MAX }; enum drv_hash_mode { @@ -163,11 +150,11 @@ enum drv_hash_mode { DRV_HASH_SHA512 = 3, DRV_HASH_SHA384 = 4, DRV_HASH_MD5 = 5, - DRV_HASH_CBC_MAC = 6, + DRV_HASH_CBC_MAC = 6, DRV_HASH_XCBC_MAC = 7, DRV_HASH_CMAC = 8, DRV_HASH_MODE_NUM = 9, - DRV_HASH_RESERVE32B = INT32_MAX + DRV_HASH_RESERVE32B = S32_MAX }; enum drv_hash_hw_mode { @@ -178,7 +165,7 @@ enum drv_hash_hw_mode { DRV_HASH_HW_SHA512 = 4, DRV_HASH_HW_SHA384 = 12, DRV_HASH_HW_GHASH = 6, - DRV_HASH_HW_RESERVE32B = INT32_MAX + DRV_HASH_HW_RESERVE32B = S32_MAX }; enum drv_multi2_mode { @@ -186,10 +173,9 @@ enum drv_multi2_mode { DRV_MULTI2_ECB = 0, DRV_MULTI2_CBC = 1, DRV_MULTI2_OFB = 2, - DRV_MULTI2_RESERVE32B = INT32_MAX + DRV_MULTI2_RESERVE32B = S32_MAX }; - /* drv_crypto_key_type[1:0] is mapped to cipher_do[1:0] */ /* drv_crypto_key_type[2] is mapped to cipher_config2 */ enum drv_crypto_key_type { @@ -201,99 +187,14 @@ enum drv_crypto_key_type { DRV_APPLET_KEY = 4, /* NA */ DRV_PLATFORM_KEY = 5, /* 0x101 */ DRV_CUSTOMER_KEY = 6, /* 0x110 */ - DRV_END_OF_KEYS = INT32_MAX, + DRV_END_OF_KEYS = S32_MAX, }; enum drv_crypto_padding_type { DRV_PADDING_NONE = 0, DRV_PADDING_PKCS7 = 1, - DRV_PADDING_RESERVE32B = INT32_MAX + DRV_PADDING_RESERVE32B = S32_MAX }; -/*******************************************************************/ -/***************** DESCRIPTOR BASED CONTEXTS ***********************/ -/*******************************************************************/ - - /* Generic context ("super-class") */ -struct drv_ctx_generic { - enum drv_crypto_alg alg; -} __attribute__((__may_alias__)); - - -struct drv_ctx_hash { - enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_HASH */ - enum drv_hash_mode mode; - uint8_t digest[CC_DIGEST_SIZE_MAX]; - /* reserve to end of allocated context size */ - uint8_t reserved[CC_CTX_SIZE - 2 * sizeof(uint32_t) - - CC_DIGEST_SIZE_MAX]; -}; - -/* !!!! drv_ctx_hmac should have the same structure as drv_ctx_hash except - k0, k0_size fields */ -struct drv_ctx_hmac { - enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_HMAC */ - enum drv_hash_mode mode; - uint8_t digest[CC_DIGEST_SIZE_MAX]; - uint32_t k0[CC_HMAC_BLOCK_SIZE_MAX/sizeof(uint32_t)]; - uint32_t k0_size; - /* reserve to end of allocated context size */ - uint8_t reserved[CC_CTX_SIZE - 3 * sizeof(uint32_t) - - CC_DIGEST_SIZE_MAX - CC_HMAC_BLOCK_SIZE_MAX]; -}; - -struct drv_ctx_cipher { - enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_AES */ - enum drv_cipher_mode mode; - enum drv_crypto_direction direction; - enum drv_crypto_key_type crypto_key_type; - enum drv_crypto_padding_type padding_type; - uint32_t key_size; /* numeric value in bytes */ - uint32_t data_unit_size; /* required for XTS */ - /* block_state is the AES engine block state. - * It is used by the host to pass IV or counter at initialization. - * It is used by SeP for intermediate block chaining state and for - * returning MAC algorithms results. */ - uint8_t block_state[CC_AES_BLOCK_SIZE]; - uint8_t key[CC_AES_KEY_SIZE_MAX]; - uint8_t xex_key[CC_AES_KEY_SIZE_MAX]; - /* reserve to end of allocated context size */ - uint32_t reserved[CC_DRV_CTX_SIZE_WORDS - 7 - - CC_AES_BLOCK_SIZE/sizeof(uint32_t) - 2 * - (CC_AES_KEY_SIZE_MAX/sizeof(uint32_t))]; -}; - -/* authentication and encryption with associated data class */ -struct drv_ctx_aead { - enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_AES */ - enum drv_cipher_mode mode; - enum drv_crypto_direction direction; - uint32_t key_size; /* numeric value in bytes */ - uint32_t nonce_size; /* nonce size (octets) */ - uint32_t header_size; /* finit additional data size (octets) */ - uint32_t text_size; /* finit text data size (octets) */ - uint32_t tag_size; /* mac size, element of {4, 6, 8, 10, 12, 14, 16} */ - /* block_state1/2 is the AES engine block state */ - uint8_t block_state[CC_AES_BLOCK_SIZE]; - uint8_t mac_state[CC_AES_BLOCK_SIZE]; /* MAC result */ - uint8_t nonce[CC_AES_BLOCK_SIZE]; /* nonce buffer */ - uint8_t key[CC_AES_KEY_SIZE_MAX]; - /* reserve to end of allocated context size */ - uint32_t reserved[CC_DRV_CTX_SIZE_WORDS - 8 - - 3 * (CC_AES_BLOCK_SIZE/sizeof(uint32_t)) - - CC_AES_KEY_SIZE_MAX/sizeof(uint32_t)]; -}; - -/*******************************************************************/ -/***************** MESSAGE BASED CONTEXTS **************************/ -/*******************************************************************/ - - -/* Get the address of a @member within a given @ctx address - @ctx: The context address - @type: Type of context structure - @member: Associated context field */ -#define GET_CTX_FIELD_ADDR(ctx, type, member) (ctx + offsetof(type, member)) - #endif /* _CC_CRYPTO_CTX_H_ */ diff --git a/drivers/staging/ccree/cc_hal.h b/drivers/staging/ccree/cc_hal.h index 75a0ce3e80d6..eecc866dfc74 100644 --- a/drivers/staging/ccree/cc_hal.h +++ b/drivers/staging/ccree/cc_hal.h @@ -1,20 +1,22 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ -/* pseudo cc_hal.h for cc7x_perf_test_driver (to be able to include code from CC drivers) */ +/* pseudo cc_hal.h for cc7x_perf_test_driver (to be able to include code from + * CC drivers). + */ #ifndef __CC_HAL_H__ #define __CC_HAL_H__ @@ -24,7 +26,8 @@ #define READ_REGISTER(_addr) ioread32((_addr)) #define WRITE_REGISTER(_addr, _data) iowrite32((_data), (_addr)) -#define CC_HAL_WRITE_REGISTER(offset, val) WRITE_REGISTER(cc_base + offset, val) -#define CC_HAL_READ_REGISTER(offset) READ_REGISTER(cc_base + offset) +#define CC_HAL_WRITE_REGISTER(offset, val) \ + WRITE_REGISTER(cc_base + (offset), val) +#define CC_HAL_READ_REGISTER(offset) READ_REGISTER(cc_base + (offset)) #endif diff --git a/drivers/staging/ccree/cc_hw_queue_defs.h b/drivers/staging/ccree/cc_hw_queue_defs.h index fbaf1b6fcd90..e6b8cea3f88d 100644 --- a/drivers/staging/ccree/cc_hw_queue_defs.h +++ b/drivers/staging/ccree/cc_hw_queue_defs.h @@ -1,15 +1,15 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ @@ -17,63 +17,95 @@ #ifndef __CC_HW_QUEUE_DEFS_H__ #define __CC_HW_QUEUE_DEFS_H__ -#include "cc_pal_log.h" -#include "cc_regs.h" -#include "dx_crys_kernel.h" - -#ifdef __KERNEL__ #include <linux/types.h> -#define UINT32_MAX 0xFFFFFFFFL -#define INT32_MAX 0x7FFFFFFFL -#define UINT16_MAX 0xFFFFL -#else -#include <stdint.h> -#endif - -/****************************************************************************** -* DEFINITIONS -******************************************************************************/ +#include "dx_crys_kernel.h" +#include <linux/bitfield.h> -/* Dma AXI Secure bit */ -#define AXI_SECURE 0 -#define AXI_NOT_SECURE 1 +/****************************************************************************** + * DEFINITIONS + ******************************************************************************/ #define HW_DESC_SIZE_WORDS 6 #define HW_QUEUE_SLOTS_MAX 15 /* Max. available slots in HW queue */ -#define _HW_DESC_MONITOR_KICK 0x7FFFC00 +#define CC_REG_NAME(word, name) DX_DSCRPTR_QUEUE_WORD ## word ## _ ## name + +#define CC_REG_LOW(word, name) \ + (DX_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SHIFT) + +#define CC_REG_HIGH(word, name) \ + (CC_REG_LOW(word, name) + \ + DX_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SIZE - 1) + +#define CC_GENMASK(word, name) \ + GENMASK(CC_REG_HIGH(word, name), CC_REG_LOW(word, name)) + +#define WORD0_VALUE CC_GENMASK(0, VALUE) +#define WORD1_DIN_CONST_VALUE CC_GENMASK(1, DIN_CONST_VALUE) +#define WORD1_DIN_DMA_MODE CC_GENMASK(1, DIN_DMA_MODE) +#define WORD1_DIN_SIZE CC_GENMASK(1, DIN_SIZE) +#define WORD1_NOT_LAST CC_GENMASK(1, NOT_LAST) +#define WORD1_NS_BIT CC_GENMASK(1, NS_BIT) +#define WORD2_VALUE CC_GENMASK(2, VALUE) +#define WORD3_DOUT_DMA_MODE CC_GENMASK(3, DOUT_DMA_MODE) +#define WORD3_DOUT_LAST_IND CC_GENMASK(3, DOUT_LAST_IND) +#define WORD3_DOUT_SIZE CC_GENMASK(3, DOUT_SIZE) +#define WORD3_HASH_XOR_BIT CC_GENMASK(3, HASH_XOR_BIT) +#define WORD3_NS_BIT CC_GENMASK(3, NS_BIT) +#define WORD3_QUEUE_LAST_IND CC_GENMASK(3, QUEUE_LAST_IND) +#define WORD4_ACK_NEEDED CC_GENMASK(4, ACK_NEEDED) +#define WORD4_AES_SEL_N_HASH CC_GENMASK(4, AES_SEL_N_HASH) +#define WORD4_BYTES_SWAP CC_GENMASK(4, BYTES_SWAP) +#define WORD4_CIPHER_CONF0 CC_GENMASK(4, CIPHER_CONF0) +#define WORD4_CIPHER_CONF1 CC_GENMASK(4, CIPHER_CONF1) +#define WORD4_CIPHER_CONF2 CC_GENMASK(4, CIPHER_CONF2) +#define WORD4_CIPHER_DO CC_GENMASK(4, CIPHER_DO) +#define WORD4_CIPHER_MODE CC_GENMASK(4, CIPHER_MODE) +#define WORD4_CMAC_SIZE0 CC_GENMASK(4, CMAC_SIZE0) +#define WORD4_DATA_FLOW_MODE CC_GENMASK(4, DATA_FLOW_MODE) +#define WORD4_KEY_SIZE CC_GENMASK(4, KEY_SIZE) +#define WORD4_SETUP_OPERATION CC_GENMASK(4, SETUP_OPERATION) +#define WORD5_DIN_ADDR_HIGH CC_GENMASK(5, DIN_ADDR_HIGH) +#define WORD5_DOUT_ADDR_HIGH CC_GENMASK(5, DOUT_ADDR_HIGH) /****************************************************************************** -* TYPE DEFINITIONS -******************************************************************************/ + * TYPE DEFINITIONS + ******************************************************************************/ + +struct cc_hw_desc { + union { + u32 word[HW_DESC_SIZE_WORDS]; + u16 hword[HW_DESC_SIZE_WORDS * 2]; + }; +}; -typedef struct HwDesc { - uint32_t word[HW_DESC_SIZE_WORDS]; -} HwDesc_s; +enum cc_axi_sec { + AXI_SECURE = 0, + AXI_NOT_SECURE = 1 +}; -typedef enum DescDirection { +enum cc_desc_direction { DESC_DIRECTION_ILLEGAL = -1, DESC_DIRECTION_ENCRYPT_ENCRYPT = 0, DESC_DIRECTION_DECRYPT_DECRYPT = 1, DESC_DIRECTION_DECRYPT_ENCRYPT = 3, - DESC_DIRECTION_END = INT32_MAX, -}DescDirection_t; + DESC_DIRECTION_END = S32_MAX, +}; -typedef enum DmaMode { +enum cc_dma_mode { DMA_MODE_NULL = -1, - NO_DMA = 0, + NO_DMA = 0, DMA_SRAM = 1, DMA_DLLI = 2, DMA_MLLI = 3, - DmaMode_OPTIONTS, - DmaMode_END = INT32_MAX, -}DmaMode_t; + DMA_MODE_END = S32_MAX, +}; -typedef enum FlowMode { +enum cc_flow_mode { FLOW_MODE_NULL = -1, /* data flows */ - BYPASS = 0, + BYPASS = 0, DIN_AES_DOUT = 1, AES_to_HASH = 2, AES_and_HASH = 3, @@ -93,11 +125,11 @@ typedef enum FlowMode { DIN_AES_AESMAC = 17, HASH_to_DOUT = 18, /* setup flows */ - S_DIN_to_AES = 32, + S_DIN_to_AES = 32, S_DIN_to_AES2 = 33, S_DIN_to_DES = 34, S_DIN_to_RC4 = 35, - S_DIN_to_MULTI2 = 36, + S_DIN_to_MULTI2 = 36, S_DIN_to_HASH = 37, S_AES_to_DOUT = 38, S_AES2_to_DOUT = 39, @@ -105,47 +137,43 @@ typedef enum FlowMode { S_DES_to_DOUT = 42, S_HASH_to_DOUT = 43, SET_FLOW_ID = 44, - FlowMode_OPTIONTS, - FlowMode_END = INT32_MAX, -}FlowMode_t; + FLOW_MODE_END = S32_MAX, +}; -typedef enum TunnelOp { +enum cc_tunnel_op { TUNNEL_OP_INVALID = -1, TUNNEL_OFF = 0, TUNNEL_ON = 1, - TunnelOp_OPTIONS, - TunnelOp_END = INT32_MAX, -} TunnelOp_t; + TUNNEL_OP_END = S32_MAX, +}; -typedef enum SetupOp { +enum cc_setup_op { SETUP_LOAD_NOP = 0, SETUP_LOAD_STATE0 = 1, SETUP_LOAD_STATE1 = 2, SETUP_LOAD_STATE2 = 3, SETUP_LOAD_KEY0 = 4, SETUP_LOAD_XEX_KEY = 5, - SETUP_WRITE_STATE0 = 8, + SETUP_WRITE_STATE0 = 8, SETUP_WRITE_STATE1 = 9, SETUP_WRITE_STATE2 = 10, SETUP_WRITE_STATE3 = 11, - setupOp_OPTIONTS, - setupOp_END = INT32_MAX, -}SetupOp_t; + SETUP_OP_END = S32_MAX, +}; -enum AesMacSelector { +enum cc_aes_mac_selector { AES_SK = 1, AES_CMAC_INIT = 2, AES_CMAC_SIZE0 = 3, - AesMacEnd = INT32_MAX, + AES_MAC_END = S32_MAX, }; -#define HW_KEY_MASK_CIPHER_DO 0x3 +#define HW_KEY_MASK_CIPHER_DO 0x3 #define HW_KEY_SHIFT_CIPHER_CFG2 2 - /* HwCryptoKey[1:0] is mapped to cipher_do[1:0] */ /* HwCryptoKey[2:3] is mapped to cipher_config2[1:0] */ -typedef enum HwCryptoKey { +enum cc_hw_crypto_key { USER_KEY = 0, /* 0x0000 */ ROOT_KEY = 1, /* 0x0001 */ PROVISIONING_KEY = 2, /* 0x0010 */ /* ==KCP */ @@ -157,447 +185,409 @@ typedef enum HwCryptoKey { KFDE1_KEY = 9, /* 0x1001 */ KFDE2_KEY = 10, /* 0x1010 */ KFDE3_KEY = 11, /* 0x1011 */ - END_OF_KEYS = INT32_MAX, -}HwCryptoKey_t; + END_OF_KEYS = S32_MAX, +}; -typedef enum HwAesKeySize { +enum cc_hw_aes_key_size { AES_128_KEY = 0, AES_192_KEY = 1, AES_256_KEY = 2, - END_OF_AES_KEYS = INT32_MAX, -}HwAesKeySize_t; + END_OF_AES_KEYS = S32_MAX, +}; -typedef enum HwDesKeySize { +enum cc_hw_des_key_size { DES_ONE_KEY = 0, DES_TWO_KEYS = 1, DES_THREE_KEYS = 2, - END_OF_DES_KEYS = INT32_MAX, -}HwDesKeySize_t; + END_OF_DES_KEYS = S32_MAX, +}; /*****************************/ /* Descriptor packing macros */ /*****************************/ -#define GET_HW_Q_DESC_WORD_IDX(descWordIdx) (CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD ## descWordIdx) ) - -#define HW_DESC_INIT(pDesc) do { \ - (pDesc)->word[0] = 0; \ - (pDesc)->word[1] = 0; \ - (pDesc)->word[2] = 0; \ - (pDesc)->word[3] = 0; \ - (pDesc)->word[4] = 0; \ - (pDesc)->word[5] = 0; \ -} while (0) - -/* HW descriptor debug functions */ -int createDetailedDump(HwDesc_s *pDesc); -void descriptor_log(HwDesc_s *desc); - -#if defined(HW_DESCRIPTOR_LOG) || defined(HW_DESC_DUMP_HOST_BUF) -#define LOG_HW_DESC(pDesc) descriptor_log(pDesc) -#else -#define LOG_HW_DESC(pDesc) -#endif - -#if (CC_PAL_MAX_LOG_LEVEL >= CC_PAL_LOG_LEVEL_TRACE) || defined(OEMFW_LOG) - -#ifdef UART_PRINTF -#define CREATE_DETAILED_DUMP(pDesc) createDetailedDump(pDesc) -#else -#define CREATE_DETAILED_DUMP(pDesc) -#endif - -#define HW_DESC_DUMP(pDesc) do { \ - CC_PAL_LOG_TRACE("\n---------------------------------------------------\n"); \ - CREATE_DETAILED_DUMP(pDesc); \ - CC_PAL_LOG_TRACE("0x%08X, ", (unsigned int)(pDesc)->word[0]); \ - CC_PAL_LOG_TRACE("0x%08X, ", (unsigned int)(pDesc)->word[1]); \ - CC_PAL_LOG_TRACE("0x%08X, ", (unsigned int)(pDesc)->word[2]); \ - CC_PAL_LOG_TRACE("0x%08X, ", (unsigned int)(pDesc)->word[3]); \ - CC_PAL_LOG_TRACE("0x%08X, ", (unsigned int)(pDesc)->word[4]); \ - CC_PAL_LOG_TRACE("0x%08X\n", (unsigned int)(pDesc)->word[5]); \ - CC_PAL_LOG_TRACE("---------------------------------------------------\n\n"); \ -} while (0) - -#else -#define HW_DESC_DUMP(pDesc) do {} while (0) -#endif - - -/*! - * This macro indicates the end of current HW descriptors flow and release the HW engines. - * - * \param pDesc pointer HW descriptor struct - */ -#define HW_DESC_SET_QUEUE_LAST_IND(pDesc) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, QUEUE_LAST_IND, (pDesc)->word[3], 1); \ - } while (0) - -/*! - * This macro signs the end of HW descriptors flow by asking for completion ack, and release the HW engines - * - * \param pDesc pointer HW descriptor struct - */ -#define HW_DESC_SET_ACK_LAST(pDesc) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, QUEUE_LAST_IND, (pDesc)->word[3], 1); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, ACK_NEEDED, (pDesc)->word[4], 1); \ - } while (0) - - -#define MSB64(_addr) (sizeof(_addr) == 4 ? 0 : ((_addr) >> 32)&UINT16_MAX) - -/*! - * This macro sets the DIN field of a HW descriptors - * - * \param pDesc pointer HW descriptor struct - * \param dmaMode The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT - * \param dinAdr DIN address - * \param dinSize Data size in bytes - * \param axiNs AXI secure bit +/* + * Init a HW descriptor struct + * @pdesc: pointer HW descriptor struct */ -#define HW_DESC_SET_DIN_TYPE(pDesc, dmaMode, dinAdr, dinSize, axiNs) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (dinAdr)&UINT32_MAX ); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DIN_ADDR_HIGH, (pDesc)->word[5], MSB64(dinAdr) ); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_DMA_MODE, (pDesc)->word[1], (dmaMode)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_SIZE, (pDesc)->word[1], (dinSize)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, NS_BIT, (pDesc)->word[1], (axiNs)); \ - } while (0) - - -/*! - * This macro sets the DIN field of a HW descriptors to NO DMA mode. Used for NOP descriptor, register patches and - * other special modes - * - * \param pDesc pointer HW descriptor struct - * \param dinAdr DIN address - * \param dinSize Data size in bytes +static inline void hw_desc_init(struct cc_hw_desc *pdesc) +{ + memset(pdesc, 0, sizeof(struct cc_hw_desc)); +} + +/* + * Indicates the end of current HW descriptors flow and release the HW engines. + * + * @pdesc: pointer HW descriptor struct */ -#define HW_DESC_SET_DIN_NO_DMA(pDesc, dinAdr, dinSize) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (uint32_t)(dinAdr)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_SIZE, (pDesc)->word[1], (dinSize)); \ - } while (0) - -/*! - * This macro sets the DIN field of a HW descriptors to SRAM mode. - * Note: No need to check SRAM alignment since host requests do not use SRAM and - * adaptor will enforce alignment check. - * - * \param pDesc pointer HW descriptor struct - * \param dinAdr DIN address - * \param dinSize Data size in bytes +static inline void set_queue_last_ind(struct cc_hw_desc *pdesc) +{ + pdesc->word[3] |= FIELD_PREP(WORD3_QUEUE_LAST_IND, 1); +} + +/* + * Set the DIN field of a HW descriptors + * + * @pdesc: pointer HW descriptor struct + * @dma_mode: dmaMode The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT + * @addr: dinAdr DIN address + * @size: Data size in bytes + * @axi_sec: AXI secure bit */ -#define HW_DESC_SET_DIN_SRAM(pDesc, dinAdr, dinSize) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (uint32_t)(dinAdr)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_DMA_MODE, (pDesc)->word[1], DMA_SRAM); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_SIZE, (pDesc)->word[1], (dinSize)); \ - } while (0) - -/*! This macro sets the DIN field of a HW descriptors to CONST mode - * - * \param pDesc pointer HW descriptor struct - * \param val DIN const value - * \param dinSize Data size in bytes +static inline void set_din_type(struct cc_hw_desc *pdesc, + enum cc_dma_mode dma_mode, dma_addr_t addr, + u32 size, enum cc_axi_sec axi_sec) +{ + pdesc->word[0] = (u32)addr; +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + pdesc->word[5] |= FIELD_PREP(WORD5_DIN_ADDR_HIGH, ((u16)(addr >> 32))); +#endif + pdesc->word[1] |= FIELD_PREP(WORD1_DIN_DMA_MODE, dma_mode) | + FIELD_PREP(WORD1_DIN_SIZE, size) | + FIELD_PREP(WORD1_NS_BIT, axi_sec); +} + +/* + * Set the DIN field of a HW descriptors to NO DMA mode. + * Used for NOP descriptor, register patches and other special modes. + * + * @pdesc: pointer HW descriptor struct + * @addr: DIN address + * @size: Data size in bytes */ -#define HW_DESC_SET_DIN_CONST(pDesc, val, dinSize) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0, VALUE, (pDesc)->word[0], (uint32_t)(val)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_CONST_VALUE, (pDesc)->word[1], 1); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_DMA_MODE, (pDesc)->word[1], DMA_SRAM); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, DIN_SIZE, (pDesc)->word[1], (dinSize)); \ - } while (0) - -/*! - * This macro sets the DIN not last input data indicator - * - * \param pDesc pointer HW descriptor struct +static inline void set_din_no_dma(struct cc_hw_desc *pdesc, u32 addr, u32 size) +{ + pdesc->word[0] = addr; + pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size); +} + +/* + * Set the DIN field of a HW descriptors to SRAM mode. + * Note: No need to check SRAM alignment since host requests do not use SRAM and + * adaptor will enforce alignment check. + * + * @pdesc: pointer HW descriptor struct + * @addr: DIN address + * @size Data size in bytes */ -#define HW_DESC_SET_DIN_NOT_LAST_INDICATION(pDesc) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD1, NOT_LAST, (pDesc)->word[1], 1); \ - } while (0) - -/*! - * This macro sets the DOUT field of a HW descriptors - * - * \param pDesc pointer HW descriptor struct - * \param dmaMode The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT - * \param doutAdr DOUT address - * \param doutSize Data size in bytes - * \param axiNs AXI secure bit +static inline void set_din_sram(struct cc_hw_desc *pdesc, dma_addr_t addr, + u32 size) +{ + pdesc->word[0] = (u32)addr; + pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size) | + FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM); +} + +/* + * Set the DIN field of a HW descriptors to CONST mode + * + * @pdesc: pointer HW descriptor struct + * @val: DIN const value + * @size: Data size in bytes */ -#define HW_DESC_SET_DOUT_TYPE(pDesc, dmaMode, doutAdr, doutSize, axiNs) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr)&UINT32_MAX ); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DOUT_ADDR_HIGH, (pDesc)->word[5], MSB64(doutAdr) ); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], (dmaMode)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, NS_BIT, (pDesc)->word[3], (axiNs)); \ - } while (0) - -/*! - * This macro sets the DOUT field of a HW descriptors to DLLI type - * The LAST INDICATION is provided by the user - * - * \param pDesc pointer HW descriptor struct - * \param doutAdr DOUT address - * \param doutSize Data size in bytes - * \param lastInd The last indication bit - * \param axiNs AXI secure bit +static inline void set_din_const(struct cc_hw_desc *pdesc, u32 val, u32 size) +{ + pdesc->word[0] = val; + pdesc->word[1] |= FIELD_PREP(WORD1_DIN_CONST_VALUE, 1) | + FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM) | + FIELD_PREP(WORD1_DIN_SIZE, size); +} + +/* + * Set the DIN not last input data indicator + * + * @pdesc: pointer HW descriptor struct */ -#define HW_DESC_SET_DOUT_DLLI(pDesc, doutAdr, doutSize, axiNs ,lastInd) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr)&UINT32_MAX ); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DOUT_ADDR_HIGH, (pDesc)->word[5], MSB64(doutAdr) ); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], DMA_DLLI); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_LAST_IND, (pDesc)->word[3], lastInd); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, NS_BIT, (pDesc)->word[3], (axiNs)); \ - } while (0) - -/*! - * This macro sets the DOUT field of a HW descriptors to DLLI type - * The LAST INDICATION is provided by the user - * - * \param pDesc pointer HW descriptor struct - * \param doutAdr DOUT address - * \param doutSize Data size in bytes - * \param lastInd The last indication bit - * \param axiNs AXI secure bit +static inline void set_din_not_last_indication(struct cc_hw_desc *pdesc) +{ + pdesc->word[1] |= FIELD_PREP(WORD1_NOT_LAST, 1); +} + +/* + * Set the DOUT field of a HW descriptors + * + * @pdesc: pointer HW descriptor struct + * @dma_mode: The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT + * @addr: DOUT address + * @size: Data size in bytes + * @axi_sec: AXI secure bit */ -#define HW_DESC_SET_DOUT_MLLI(pDesc, doutAdr, doutSize, axiNs ,lastInd) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (doutAdr)&UINT32_MAX ); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD5, DOUT_ADDR_HIGH, (pDesc)->word[5], MSB64(doutAdr) ); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], DMA_MLLI); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_LAST_IND, (pDesc)->word[3], lastInd); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, NS_BIT, (pDesc)->word[3], (axiNs)); \ - } while (0) - -/*! - * This macro sets the DOUT field of a HW descriptors to NO DMA mode. Used for NOP descriptor, register patches and - * other special modes - * - * \param pDesc pointer HW descriptor struct - * \param doutAdr DOUT address - * \param doutSize Data size in bytes - * \param registerWriteEnable Enables a write operation to a register +static inline void set_dout_type(struct cc_hw_desc *pdesc, + enum cc_dma_mode dma_mode, dma_addr_t addr, + u32 size, enum cc_axi_sec axi_sec) +{ + pdesc->word[2] = (u32)addr; +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + pdesc->word[5] |= FIELD_PREP(WORD5_DOUT_ADDR_HIGH, ((u16)(addr >> 32))); +#endif + pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, dma_mode) | + FIELD_PREP(WORD3_DOUT_SIZE, size) | + FIELD_PREP(WORD3_NS_BIT, axi_sec); +} + +/* + * Set the DOUT field of a HW descriptors to DLLI type + * The LAST INDICATION is provided by the user + * + * @pdesc pointer HW descriptor struct + * @addr: DOUT address + * @size: Data size in bytes + * @last_ind: The last indication bit + * @axi_sec: AXI secure bit */ -#define HW_DESC_SET_DOUT_NO_DMA(pDesc, doutAdr, doutSize, registerWriteEnable) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(doutAdr)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_LAST_IND, (pDesc)->word[3], (registerWriteEnable)); \ - } while (0) - -/*! - * This macro sets the word for the XOR operation. - * - * \param pDesc pointer HW descriptor struct - * \param xorVal xor data value +static inline void set_dout_dlli(struct cc_hw_desc *pdesc, dma_addr_t addr, + u32 size, enum cc_axi_sec axi_sec, + u32 last_ind) +{ + set_dout_type(pdesc, DMA_DLLI, addr, size, axi_sec); + pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind); +} + +/* + * Set the DOUT field of a HW descriptors to DLLI type + * The LAST INDICATION is provided by the user + * + * @pdesc: pointer HW descriptor struct + * @addr: DOUT address + * @size: Data size in bytes + * @last_ind: The last indication bit + * @axi_sec: AXI secure bit */ -#define HW_DESC_SET_XOR_VAL(pDesc, xorVal) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(xorVal)); \ - } while (0) - -/*! - * This macro sets the XOR indicator bit in the descriptor - * - * \param pDesc pointer HW descriptor struct +static inline void set_dout_mlli(struct cc_hw_desc *pdesc, dma_addr_t addr, + u32 size, enum cc_axi_sec axi_sec, + bool last_ind) +{ + set_dout_type(pdesc, DMA_MLLI, addr, size, axi_sec); + pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind); +} + +/* + * Set the DOUT field of a HW descriptors to NO DMA mode. + * Used for NOP descriptor, register patches and other special modes. + * + * @pdesc: pointer HW descriptor struct + * @addr: DOUT address + * @size: Data size in bytes + * @write_enable: Enables a write operation to a register */ -#define HW_DESC_SET_XOR_ACTIVE(pDesc) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, HASH_XOR_BIT, (pDesc)->word[3], 1); \ - } while (0) - -/*! - * This macro selects the AES engine instead of HASH engine when setting up combined mode with AES XCBC MAC - * - * \param pDesc pointer HW descriptor struct +static inline void set_dout_no_dma(struct cc_hw_desc *pdesc, u32 addr, + u32 size, bool write_enable) +{ + pdesc->word[2] = addr; + pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_SIZE, size) | + FIELD_PREP(WORD3_DOUT_LAST_IND, write_enable); +} + +/* + * Set the word for the XOR operation. + * + * @pdesc: pointer HW descriptor struct + * @val: xor data value */ -#define HW_DESC_SET_AES_NOT_HASH_MODE(pDesc) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, AES_SEL_N_HASH, (pDesc)->word[4], 1); \ - } while (0) - -/*! - * This macro sets the DOUT field of a HW descriptors to SRAM mode - * Note: No need to check SRAM alignment since host requests do not use SRAM and - * adaptor will enforce alignment check. - * - * \param pDesc pointer HW descriptor struct - * \param doutAdr DOUT address - * \param doutSize Data size in bytes +static inline void set_xor_val(struct cc_hw_desc *pdesc, u32 val) +{ + pdesc->word[2] = val; +} + +/* + * Sets the XOR indicator bit in the descriptor + * + * @pdesc: pointer HW descriptor struct */ -#define HW_DESC_SET_DOUT_SRAM(pDesc, doutAdr, doutSize) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(doutAdr)); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_DMA_MODE, (pDesc)->word[3], DMA_SRAM); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD3, DOUT_SIZE, (pDesc)->word[3], (doutSize)); \ - } while (0) - - -/*! - * This macro sets the data unit size for XEX mode in data_out_addr[15:0] - * - * \param pDesc pointer HW descriptor struct - * \param dataUnitSize data unit size for XEX mode +static inline void set_xor_active(struct cc_hw_desc *pdesc) +{ + pdesc->word[3] |= FIELD_PREP(WORD3_HASH_XOR_BIT, 1); +} + +/* + * Select the AES engine instead of HASH engine when setting up combined mode + * with AES XCBC MAC + * + * @pdesc: pointer HW descriptor struct */ -#define HW_DESC_SET_XEX_DATA_UNIT_SIZE(pDesc, dataUnitSize) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(dataUnitSize)); \ - } while (0) +static inline void set_aes_not_hash_mode(struct cc_hw_desc *pdesc) +{ + pdesc->word[4] |= FIELD_PREP(WORD4_AES_SEL_N_HASH, 1); +} -/*! - * This macro sets the number of rounds for Multi2 in data_out_addr[15:0] +/* + * Set the DOUT field of a HW descriptors to SRAM mode + * Note: No need to check SRAM alignment since host requests do not use SRAM and + * adaptor will enforce alignment check. * - * \param pDesc pointer HW descriptor struct - * \param numRounds number of rounds for Multi2 -*/ -#define HW_DESC_SET_MULTI2_NUM_ROUNDS(pDesc, numRounds) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE, (pDesc)->word[2], (uint32_t)(numRounds)); \ - } while (0) - -/*! - * This macro sets the flow mode. + * @pdesc: pointer HW descriptor struct + * @addr: DOUT address + * @size: Data size in bytes + */ +static inline void set_dout_sram(struct cc_hw_desc *pdesc, u32 addr, u32 size) +{ + pdesc->word[2] = addr; + pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, DMA_SRAM) | + FIELD_PREP(WORD3_DOUT_SIZE, size); +} + +/* + * Sets the data unit size for XEX mode in data_out_addr[15:0] * - * \param pDesc pointer HW descriptor struct - * \param flowMode Any one of the modes defined in [CC7x-DESC] -*/ + * @pdesc: pDesc pointer HW descriptor struct + * @size: data unit size for XEX mode + */ +static inline void set_xex_data_unit_size(struct cc_hw_desc *pdesc, u32 size) +{ + pdesc->word[2] = size; +} -#define HW_DESC_SET_FLOW_MODE(pDesc, flowMode) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, DATA_FLOW_MODE, (pDesc)->word[4], (flowMode)); \ - } while (0) +/* + * Set the number of rounds for Multi2 in data_out_addr[15:0] + * + * @pdesc: pointer HW descriptor struct + * @num: number of rounds for Multi2 + */ +static inline void set_multi2_num_rounds(struct cc_hw_desc *pdesc, u32 num) +{ + pdesc->word[2] = num; +} -/*! - * This macro sets the cipher mode. +/* + * Set the flow mode. * - * \param pDesc pointer HW descriptor struct - * \param cipherMode Any one of the modes defined in [CC7x-DESC] -*/ -#define HW_DESC_SET_CIPHER_MODE(pDesc, cipherMode) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_MODE, (pDesc)->word[4], (cipherMode)); \ - } while (0) - -/*! - * This macro sets the cipher configuration fields. + * @pdesc: pointer HW descriptor struct + * @mode: Any one of the modes defined in [CC7x-DESC] + */ +static inline void set_flow_mode(struct cc_hw_desc *pdesc, + enum cc_flow_mode mode) +{ + pdesc->word[4] |= FIELD_PREP(WORD4_DATA_FLOW_MODE, mode); +} + +/* + * Set the cipher mode. * - * \param pDesc pointer HW descriptor struct - * \param cipherConfig Any one of the modes defined in [CC7x-DESC] -*/ -#define HW_DESC_SET_CIPHER_CONFIG0(pDesc, cipherConfig) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_CONF0, (pDesc)->word[4], (cipherConfig)); \ - } while (0) - -/*! - * This macro sets the cipher configuration fields. + * @pdesc: pointer HW descriptor struct + * @mode: Any one of the modes defined in [CC7x-DESC] + */ +static inline void set_cipher_mode(struct cc_hw_desc *pdesc, + enum drv_cipher_mode mode) +{ + pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_MODE, mode); +} + +/* + * Set the cipher configuration fields. * - * \param pDesc pointer HW descriptor struct - * \param cipherConfig Any one of the modes defined in [CC7x-DESC] -*/ -#define HW_DESC_SET_CIPHER_CONFIG1(pDesc, cipherConfig) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_CONF1, (pDesc)->word[4], (cipherConfig)); \ - } while (0) - -/*! - * This macro sets HW key configuration fields. + * @pdesc: pointer HW descriptor struct + * @mode: Any one of the modes defined in [CC7x-DESC] + */ +static inline void set_cipher_config0(struct cc_hw_desc *pdesc, + enum drv_crypto_direction mode) +{ + pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF0, mode); +} + +/* + * Set the cipher configuration fields. * - * \param pDesc pointer HW descriptor struct - * \param hwKey The hw key number as in enun HwCryptoKey -*/ -#define HW_DESC_SET_HW_CRYPTO_KEY(pDesc, hwKey) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_DO, (pDesc)->word[4], (hwKey)&HW_KEY_MASK_CIPHER_DO); \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_CONF2, (pDesc)->word[4], (hwKey>>HW_KEY_SHIFT_CIPHER_CFG2)); \ - } while (0) - -/*! - * This macro changes the bytes order of all setup-finalize descriptosets. + * @pdesc: pointer HW descriptor struct + * @config: Any one of the modes defined in [CC7x-DESC] + */ +static inline void set_cipher_config1(struct cc_hw_desc *pdesc, + enum cc_hash_conf_pad config) +{ + pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF1, config); +} + +/* + * Set HW key configuration fields. * - * \param pDesc pointer HW descriptor struct - * \param swapConfig Any one of the modes defined in [CC7x-DESC] -*/ -#define HW_DESC_SET_BYTES_SWAP(pDesc, swapConfig) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, BYTES_SWAP, (pDesc)->word[4], (swapConfig)); \ - } while (0) - -/*! - * This macro sets the CMAC_SIZE0 mode. + * @pdesc: pointer HW descriptor struct + * @hw_key: The HW key slot asdefined in enum cc_hw_crypto_key + */ +static inline void set_hw_crypto_key(struct cc_hw_desc *pdesc, + enum cc_hw_crypto_key hw_key) +{ + pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO, + (hw_key & HW_KEY_MASK_CIPHER_DO)) | + FIELD_PREP(WORD4_CIPHER_CONF2, + (hw_key >> HW_KEY_SHIFT_CIPHER_CFG2)); +} + +/* + * Set byte order of all setup-finalize descriptors. * - * \param pDesc pointer HW descriptor struct -*/ -#define HW_DESC_SET_CMAC_SIZE0_MODE(pDesc) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CMAC_SIZE0, (pDesc)->word[4], 0x1); \ - } while (0) - -/*! - * This macro sets the key size for AES engine. + * @pdesc: pointer HW descriptor struct + * @config: Any one of the modes defined in [CC7x-DESC] + */ +static inline void set_bytes_swap(struct cc_hw_desc *pdesc, bool config) +{ + pdesc->word[4] |= FIELD_PREP(WORD4_BYTES_SWAP, config); +} + +/* + * Set CMAC_SIZE0 mode. * - * \param pDesc pointer HW descriptor struct - * \param keySize key size in bytes (NOT size code) -*/ -#define HW_DESC_SET_KEY_SIZE_AES(pDesc, keySize) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, KEY_SIZE, (pDesc)->word[4], ((keySize) >> 3) - 2); \ - } while (0) - -/*! - * This macro sets the key size for DES engine. + * @pdesc: pointer HW descriptor struct + */ +static inline void set_cmac_size0_mode(struct cc_hw_desc *pdesc) +{ + pdesc->word[4] |= FIELD_PREP(WORD4_CMAC_SIZE0, 1); +} + +/* + * Set key size descriptor field. * - * \param pDesc pointer HW descriptor struct - * \param keySize key size in bytes (NOT size code) -*/ -#define HW_DESC_SET_KEY_SIZE_DES(pDesc, keySize) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, KEY_SIZE, (pDesc)->word[4], ((keySize) >> 3) - 1); \ - } while (0) - -/*! - * This macro sets the descriptor's setup mode + * @pdesc: pointer HW descriptor struct + * @size: key size in bytes (NOT size code) + */ +static inline void set_key_size(struct cc_hw_desc *pdesc, u32 size) +{ + pdesc->word[4] |= FIELD_PREP(WORD4_KEY_SIZE, size); +} + +/* + * Set AES key size. * - * \param pDesc pointer HW descriptor struct - * \param setupMode Any one of the setup modes defined in [CC7x-DESC] -*/ -#define HW_DESC_SET_SETUP_MODE(pDesc, setupMode) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, SETUP_OPERATION, (pDesc)->word[4], (setupMode)); \ - } while (0) - -/*! - * This macro sets the descriptor's cipher do + * @pdesc: pointer HW descriptor struct + * @size: key size in bytes (NOT size code) + */ +static inline void set_key_size_aes(struct cc_hw_desc *pdesc, u32 size) +{ + set_key_size(pdesc, ((size >> 3) - 2)); +} + +/* + * Set DES key size. * - * \param pDesc pointer HW descriptor struct - * \param cipherDo Any one of the cipher do defined in [CC7x-DESC] -*/ -#define HW_DESC_SET_CIPHER_DO(pDesc, cipherDo) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_DO, (pDesc)->word[4], (cipherDo)&HW_KEY_MASK_CIPHER_DO); \ - } while (0) - -/*! - * This macro sets the DIN field of a HW descriptors to star/stop monitor descriptor. - * Used for performance measurements and debug purposes. - * - * \param pDesc pointer HW descriptor struct + * @pdesc: pointer HW descriptor struct + * @size: key size in bytes (NOT size code) */ -#define HW_DESC_SET_DIN_MONITOR_CNTR(pDesc) \ - do { \ - CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_MEASURE_CNTR, VALUE, (pDesc)->word[1], _HW_DESC_MONITOR_KICK); \ - } while (0) +static inline void set_key_size_des(struct cc_hw_desc *pdesc, u32 size) +{ + set_key_size(pdesc, ((size >> 3) - 1)); +} +/* + * Set the descriptor setup mode + * + * @pdesc: pointer HW descriptor struct + * @mode: Any one of the setup modes defined in [CC7x-DESC] + */ +static inline void set_setup_mode(struct cc_hw_desc *pdesc, + enum cc_setup_op mode) +{ + pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, mode); +} +/* + * Set the descriptor cipher DO + * + * @pdesc: pointer HW descriptor struct + * @config: Any one of the cipher do defined in [CC7x-DESC] + */ +static inline void set_cipher_do(struct cc_hw_desc *pdesc, + enum cc_hash_cipher_pad config) +{ + pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO, + (config & HW_KEY_MASK_CIPHER_DO)); +} #endif /*__CC_HW_QUEUE_DEFS_H__*/ diff --git a/drivers/staging/ccree/cc_lli_defs.h b/drivers/staging/ccree/cc_lli_defs.h index 697f1ed181e0..851d3907167e 100644 --- a/drivers/staging/ccree/cc_lli_defs.h +++ b/drivers/staging/ccree/cc_lli_defs.h @@ -1,46 +1,42 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ - #ifndef _CC_LLI_DEFS_H_ #define _CC_LLI_DEFS_H_ -#ifdef __KERNEL__ -#include <linux/types.h> -#else -#include <stdint.h> -#endif -#include "cc_bitops.h" -/* Max DLLI size */ -#define DLLI_SIZE_BIT_SIZE 0x18 // DX_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE - -#define CC_MAX_MLLI_ENTRY_SIZE 0x10000 +#include <linux/types.h> -#define MSB64(_addr) (sizeof(_addr) == 4 ? 0 : ((_addr) >> 32)&UINT16_MAX) +/* Max DLLI size + * AKA DX_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE + */ +#define DLLI_SIZE_BIT_SIZE 0x18 -#define LLI_SET_ADDR(lli_p, addr) \ - BITFIELD_SET(((uint32_t *)(lli_p))[LLI_WORD0_OFFSET], LLI_LADDR_BIT_OFFSET, LLI_LADDR_BIT_SIZE, (addr & UINT32_MAX)); \ - BITFIELD_SET(((uint32_t *)(lli_p))[LLI_WORD1_OFFSET], LLI_HADDR_BIT_OFFSET, LLI_HADDR_BIT_SIZE, MSB64(addr)); +#define CC_MAX_MLLI_ENTRY_SIZE 0xFFFF -#define LLI_SET_SIZE(lli_p, size) \ - BITFIELD_SET(((uint32_t *)(lli_p))[LLI_WORD1_OFFSET], LLI_SIZE_BIT_OFFSET, LLI_SIZE_BIT_SIZE, size) +#define LLI_MAX_NUM_OF_DATA_ENTRIES 128 +#define LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES 4 +#define MLLI_TABLE_MIN_ALIGNMENT 4 /* 32 bit alignment */ +#define MAX_NUM_OF_BUFFERS_IN_MLLI 4 +#define MAX_NUM_OF_TOTAL_MLLI_ENTRIES \ + (2 * LLI_MAX_NUM_OF_DATA_ENTRIES + \ + LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES) /* Size of entry */ #define LLI_ENTRY_WORD_SIZE 2 -#define LLI_ENTRY_BYTE_SIZE (LLI_ENTRY_WORD_SIZE * sizeof(uint32_t)) +#define LLI_ENTRY_BYTE_SIZE (LLI_ENTRY_WORD_SIZE * sizeof(u32)) /* Word0[31:0] = ADDR[31:0] */ #define LLI_WORD0_OFFSET 0 @@ -53,5 +49,24 @@ #define LLI_HADDR_BIT_OFFSET 16 #define LLI_HADDR_BIT_SIZE 16 +#define LLI_SIZE_MASK GENMASK((LLI_SIZE_BIT_SIZE - 1), LLI_SIZE_BIT_OFFSET) +#define LLI_HADDR_MASK GENMASK( \ + (LLI_HADDR_BIT_OFFSET + LLI_HADDR_BIT_SIZE - 1),\ + LLI_HADDR_BIT_OFFSET) + +static inline void cc_lli_set_addr(u32 *lli_p, dma_addr_t addr) +{ + lli_p[LLI_WORD0_OFFSET] = (addr & U32_MAX); +#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT + lli_p[LLI_WORD1_OFFSET] &= ~LLI_HADDR_MASK; + lli_p[LLI_WORD1_OFFSET] |= FIELD_PREP(LLI_HADDR_MASK, (addr >> 16)); +#endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */ +} + +static inline void cc_lli_set_size(u32 *lli_p, u16 size) +{ + lli_p[LLI_WORD1_OFFSET] &= ~LLI_SIZE_MASK; + lli_p[LLI_WORD1_OFFSET] |= FIELD_PREP(LLI_SIZE_MASK, size); +} #endif /*_CC_LLI_DEFS_H_*/ diff --git a/drivers/staging/ccree/cc_pal_log.h b/drivers/staging/ccree/cc_pal_log.h deleted file mode 100644 index e5f5a8737833..000000000000 --- a/drivers/staging/ccree/cc_pal_log.h +++ /dev/null @@ -1,188 +0,0 @@ -/* - * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef _CC_PAL_LOG_H_ -#define _CC_PAL_LOG_H_ - -#include "cc_pal_types.h" -#include "cc_pal_log_plat.h" - -/*! -@file -@brief This file contains the PAL layer log definitions, by default the log is disabled. -@defgroup cc_pal_log CryptoCell PAL logging APIs and definitions -@{ -@ingroup cc_pal -*/ - -/* PAL log levels (to be used in CC_PAL_logLevel) */ -/*! PAL log level - disabled. */ -#define CC_PAL_LOG_LEVEL_NULL (-1) /*!< \internal Disable logging */ -/*! PAL log level - error. */ -#define CC_PAL_LOG_LEVEL_ERR 0 -/*! PAL log level - warning. */ -#define CC_PAL_LOG_LEVEL_WARN 1 -/*! PAL log level - info. */ -#define CC_PAL_LOG_LEVEL_INFO 2 -/*! PAL log level - debug. */ -#define CC_PAL_LOG_LEVEL_DEBUG 3 -/*! PAL log level - trace. */ -#define CC_PAL_LOG_LEVEL_TRACE 4 -/*! PAL log level - data. */ -#define CC_PAL_LOG_LEVEL_DATA 5 - -#ifndef CC_PAL_LOG_CUR_COMPONENT -/* Setting default component mask in case caller did not define */ -/* (a mask that is always on for every log mask value but full masking) */ -/*! Default log debugged component.*/ -#define CC_PAL_LOG_CUR_COMPONENT 0xFFFFFFFF -#endif -#ifndef CC_PAL_LOG_CUR_COMPONENT_NAME -/*! Default log debugged component.*/ -#define CC_PAL_LOG_CUR_COMPONENT_NAME "CC" -#endif - -/* Select compile time log level (default if not explicitly specified by caller) */ -#ifndef CC_PAL_MAX_LOG_LEVEL /* Can be overriden by external definition of this constant */ -#ifdef DEBUG -/*! Default debug log level (when debug is set to on).*/ -#define CC_PAL_MAX_LOG_LEVEL CC_PAL_LOG_LEVEL_ERR /*CC_PAL_LOG_LEVEL_DEBUG*/ -#else /* Disable logging */ -/*! Default debug log level (when debug is set to on).*/ -#define CC_PAL_MAX_LOG_LEVEL CC_PAL_LOG_LEVEL_NULL -#endif -#endif /*CC_PAL_MAX_LOG_LEVEL*/ -/*! Evaluate CC_PAL_MAX_LOG_LEVEL in case provided by caller */ -#define __CC_PAL_LOG_LEVEL_EVAL(level) level -/*! Maximal log level defintion.*/ -#define _CC_PAL_MAX_LOG_LEVEL __CC_PAL_LOG_LEVEL_EVAL(CC_PAL_MAX_LOG_LEVEL) - - -#ifdef ARM_DSM -/*! Log init function. */ -#define CC_PalLogInit() do {} while (0) -/*! Log set level function - sets the level of logging in case of debug. */ -#define CC_PalLogLevelSet(setLevel) do {} while (0) -/*! Log set mask function - sets the component masking in case of debug. */ -#define CC_PalLogMaskSet(setMask) do {} while (0) -#else -#if _CC_PAL_MAX_LOG_LEVEL > CC_PAL_LOG_LEVEL_NULL -/*! Log init function. */ -void CC_PalLogInit(void); -/*! Log set level function - sets the level of logging in case of debug. */ -void CC_PalLogLevelSet(int setLevel); -/*! Log set mask function - sets the component masking in case of debug. */ -void CC_PalLogMaskSet(uint32_t setMask); -/*! Global variable for log level */ -extern int CC_PAL_logLevel; -/*! Global variable for log mask */ -extern uint32_t CC_PAL_logMask; -#else /* No log */ -/*! Log init function. */ -static inline void CC_PalLogInit(void) {} -/*! Log set level function - sets the level of logging in case of debug. */ -static inline void CC_PalLogLevelSet(int setLevel) {CC_UNUSED_PARAM(setLevel);} -/*! Log set mask function - sets the component masking in case of debug. */ -static inline void CC_PalLogMaskSet(uint32_t setMask) {CC_UNUSED_PARAM(setMask);} -#endif -#endif - -/*! Filter logging based on logMask and dispatch to platform specific logging mechanism. */ -#define _CC_PAL_LOG(level, format, ...) \ - if (CC_PAL_logMask & CC_PAL_LOG_CUR_COMPONENT) \ - __CC_PAL_LOG_PLAT(CC_PAL_LOG_LEVEL_ ## level, "%s:%s: " format, CC_PAL_LOG_CUR_COMPONENT_NAME, __func__, ##__VA_ARGS__) - -#if (_CC_PAL_MAX_LOG_LEVEL >= CC_PAL_LOG_LEVEL_ERR) -/*! Log messages according to log level.*/ -#define CC_PAL_LOG_ERR(format, ... ) \ - _CC_PAL_LOG(ERR, format, ##__VA_ARGS__) -#else -/*! Log messages according to log level.*/ -#define CC_PAL_LOG_ERR( ... ) do {} while (0) -#endif - -#if (_CC_PAL_MAX_LOG_LEVEL >= CC_PAL_LOG_LEVEL_WARN) -/*! Log messages according to log level.*/ -#define CC_PAL_LOG_WARN(format, ... ) \ - if (CC_PAL_logLevel >= CC_PAL_LOG_LEVEL_WARN) \ - _CC_PAL_LOG(WARN, format, ##__VA_ARGS__) -#else -/*! Log messages according to log level.*/ -#define CC_PAL_LOG_WARN( ... ) do {} while (0) -#endif - -#if (_CC_PAL_MAX_LOG_LEVEL >= CC_PAL_LOG_LEVEL_INFO) -/*! Log messages according to log level.*/ -#define CC_PAL_LOG_INFO(format, ... ) \ - if (CC_PAL_logLevel >= CC_PAL_LOG_LEVEL_INFO) \ - _CC_PAL_LOG(INFO, format, ##__VA_ARGS__) -#else -/*! Log messages according to log level.*/ -#define CC_PAL_LOG_INFO( ... ) do {} while (0) -#endif - -#if (_CC_PAL_MAX_LOG_LEVEL >= CC_PAL_LOG_LEVEL_DEBUG) -/*! Log messages according to log level.*/ -#define CC_PAL_LOG_DEBUG(format, ... ) \ - if (CC_PAL_logLevel >= CC_PAL_LOG_LEVEL_DEBUG) \ - _CC_PAL_LOG(DEBUG, format, ##__VA_ARGS__) - -/*! Log message buffer.*/ -#define CC_PAL_LOG_DUMP_BUF(msg, buf, size) \ - do { \ - int i; \ - uint8_t *pData = (uint8_t*)buf; \ - \ - PRINTF("%s (%d):\n", msg, size); \ - for (i = 0; i < size; i++) { \ - PRINTF("0x%02X ", pData[i]); \ - if ((i & 0xF) == 0xF) { \ - PRINTF("\n"); \ - } \ - } \ - PRINTF("\n"); \ - } while (0) -#else -/*! Log debug messages.*/ -#define CC_PAL_LOG_DEBUG( ... ) do {} while (0) -/*! Log debug buffer.*/ -#define CC_PAL_LOG_DUMP_BUF(msg, buf, size) do {} while (0) -#endif - -#if (_CC_PAL_MAX_LOG_LEVEL >= CC_PAL_LOG_LEVEL_TRACE) -/*! Log debug trace.*/ -#define CC_PAL_LOG_TRACE(format, ... ) \ - if (CC_PAL_logLevel >= CC_PAL_LOG_LEVEL_TRACE) \ - _CC_PAL_LOG(TRACE, format, ##__VA_ARGS__) -#else -/*! Log debug trace.*/ -#define CC_PAL_LOG_TRACE(...) do {} while (0) -#endif - -#if (_CC_PAL_MAX_LOG_LEVEL >= CC_PAL_LOG_LEVEL_TRACE) -/*! Log debug data.*/ -#define CC_PAL_LOG_DATA(format, ...) \ - if (CC_PAL_logLevel >= CC_PAL_LOG_LEVEL_TRACE) \ - _CC_PAL_LOG(DATA, format, ##__VA_ARGS__) -#else -/*! Log debug data.*/ -#define CC_PAL_LOG_DATA( ...) do {} while (0) -#endif -/** -@} - */ - -#endif /*_CC_PAL_LOG_H_*/ diff --git a/drivers/staging/ccree/cc_pal_log_plat.h b/drivers/staging/ccree/cc_pal_log_plat.h deleted file mode 100644 index a05a200cf6eb..000000000000 --- a/drivers/staging/ccree/cc_pal_log_plat.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see <http://www.gnu.org/licenses/>. - */ - -/* Dummy pal_log_plat for test driver in kernel */ - -#ifndef _SSI_PAL_LOG_PLAT_H_ -#define _SSI_PAL_LOG_PLAT_H_ - -#if defined(DEBUG) - -#define __CC_PAL_LOG_PLAT(level, format, ...) printk(level "cc7x_test::" format , ##__VA_ARGS__) - -#else /* Disable all prints */ - -#define __CC_PAL_LOG_PLAT(...) do {} while (0) - -#endif - -#endif /*_SASI_PAL_LOG_PLAT_H_*/ - diff --git a/drivers/staging/ccree/cc_pal_types.h b/drivers/staging/ccree/cc_pal_types.h deleted file mode 100644 index 9b59bbb34515..000000000000 --- a/drivers/staging/ccree/cc_pal_types.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef CC_PAL_TYPES_H -#define CC_PAL_TYPES_H - -/*! -@file -@brief This file contains platform-dependent definitions and types. -@defgroup cc_pal_types CryptoCell PAL platform dependant types -@{ -@ingroup cc_pal - -*/ - -#include "cc_pal_types_plat.h" - -/*! Boolean definition.*/ -typedef enum { - /*! Boolean false definition.*/ - CC_FALSE = 0, - /*! Boolean true definition.*/ - CC_TRUE = 1 -} CCBool; - -/*! Success definition. */ -#define CC_SUCCESS 0UL -/*! Failure definition. */ -#define CC_FAIL 1UL - -/*! Defintion of 1KB in bytes. */ -#define CC_1K_SIZE_IN_BYTES 1024 -/*! Defintion of number of bits in a byte. */ -#define CC_BITS_IN_BYTE 8 -/*! Defintion of number of bits in a 32bits word. */ -#define CC_BITS_IN_32BIT_WORD 32 -/*! Defintion of number of bytes in a 32bits word. */ -#define CC_32BIT_WORD_SIZE (sizeof(uint32_t)) - -/*! Success (OK) defintion. */ -#define CC_OK 0 - -/*! Macro that handles unused parameters in the code (to avoid compilation warnings). */ -#define CC_UNUSED_PARAM(prm) ((void)prm) - -/*! Maximal uint32 value.*/ -#define CC_MAX_UINT32_VAL (0xFFFFFFFF) - - -/* Minimum and Maximum macros */ -#ifdef min -/*! Definition for minimum. */ -#define CC_MIN(a,b) min( a , b ) -#else -/*! Definition for minimum. */ -#define CC_MIN( a , b ) ( ( (a) < (b) ) ? (a) : (b) ) -#endif - -#ifdef max -/*! Definition for maximum. */ -#define CC_MAX(a,b) max( a , b ) -#else -/*! Definition for maximum. */ -#define CC_MAX( a , b ) ( ( (a) > (b) ) ? (a) : (b) ) -#endif - -/*! Macro that calculates number of full bytes from bits (i.e. 7 bits are 1 byte). */ -#define CALC_FULL_BYTES(numBits) ((numBits)/CC_BITS_IN_BYTE + (((numBits) & (CC_BITS_IN_BYTE-1)) > 0)) -/*! Macro that calculates number of full 32bits words from bits (i.e. 31 bits are 1 word). */ -#define CALC_FULL_32BIT_WORDS(numBits) ((numBits)/CC_BITS_IN_32BIT_WORD + (((numBits) & (CC_BITS_IN_32BIT_WORD-1)) > 0)) -/*! Macro that calculates number of full 32bits words from bytes (i.e. 3 bytes are 1 word). */ -#define CALC_32BIT_WORDS_FROM_BYTES(sizeBytes) ((sizeBytes)/CC_32BIT_WORD_SIZE + (((sizeBytes) & (CC_32BIT_WORD_SIZE-1)) > 0)) -/*! Macro that round up bits to 32bits words. */ -#define ROUNDUP_BITS_TO_32BIT_WORD(numBits) (CALC_FULL_32BIT_WORDS(numBits) * CC_BITS_IN_32BIT_WORD) -/*! Macro that round up bits to bytes. */ -#define ROUNDUP_BITS_TO_BYTES(numBits) (CALC_FULL_BYTES(numBits) * CC_BITS_IN_BYTE) -/*! Macro that round up bytes to 32bits words. */ -#define ROUNDUP_BYTES_TO_32BIT_WORD(sizeBytes) (CALC_32BIT_WORDS_FROM_BYTES(sizeBytes) * CC_32BIT_WORD_SIZE) - - -/** -@} - */ -#endif diff --git a/drivers/staging/ccree/cc_pal_types_plat.h b/drivers/staging/ccree/cc_pal_types_plat.h deleted file mode 100644 index 6e4211262231..000000000000 --- a/drivers/staging/ccree/cc_pal_types_plat.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef SSI_PAL_TYPES_PLAT_H -#define SSI_PAL_TYPES_PLAT_H -/* Linux kernel types */ - -#include <linux/types.h> - -#ifndef NULL /* Missing in Linux kernel */ -#define NULL (0x0L) -#endif - - -#endif /*SSI_PAL_TYPES_PLAT_H*/ diff --git a/drivers/staging/ccree/cc_regs.h b/drivers/staging/ccree/cc_regs.h index 963f8148cd28..4a893a6ba6ef 100644 --- a/drivers/staging/ccree/cc_regs.h +++ b/drivers/staging/ccree/cc_regs.h @@ -1,106 +1,42 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ - /*! - * @file - * @brief This file contains macro definitions for accessing ARM TrustZone CryptoCell register space. + * @file + * @brief This file contains macro definitions for accessing ARM TrustZone + * CryptoCell register space. */ #ifndef _CC_REGS_H_ #define _CC_REGS_H_ -#include "cc_bitops.h" +#include <linux/bitfield.h> + +#define AXIM_MON_BASE_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP) +#define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \ + DX_AXIM_MON_COMP_VALUE_BIT_SHIFT, \ + DX_AXIM_MON_COMP_VALUE_BIT_SHIFT) + +#define AXIM_MON_BASE_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP) +#define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \ + DX_AXIM_MON_COMP_VALUE_BIT_SHIFT, \ + DX_AXIM_MON_COMP_VALUE_BIT_SHIFT) /* Register Offset macro */ #define CC_REG_OFFSET(unit_name, reg_name) \ (DX_BASE_ ## unit_name + DX_ ## reg_name ## _REG_OFFSET) -#define CC_REG_BIT_SHIFT(reg_name, field_name) \ - (DX_ ## reg_name ## _ ## field_name ## _BIT_SHIFT) - -/* Register Offset macros (from registers base address in host) */ -#include "dx_reg_base_host.h" - -/* Read-Modify-Write a field of a register */ -#define MODIFY_REGISTER_FLD(unitName, regName, fldName, fldVal) \ -do { \ - uint32_t regVal; \ - regVal = READ_REGISTER(CC_REG_ADDR(unitName, regName)); \ - CC_REG_FLD_SET(unitName, regName, fldName, regVal, fldVal); \ - WRITE_REGISTER(CC_REG_ADDR(unitName, regName), regVal); \ -} while (0) - -/* Registers address macros for ENV registers (development FPGA only) */ -#ifdef DX_BASE_ENV_REGS - -/* This offset should be added to mapping address of DX_BASE_ENV_REGS */ -#define CC_ENV_REG_OFFSET(reg_name) (DX_ENV_ ## reg_name ## _REG_OFFSET) - -#endif /*DX_BASE_ENV_REGS*/ - -/*! Bit fields get */ -#define CC_REG_FLD_GET(unit_name, reg_name, fld_name, reg_val) \ - (DX_ ## reg_name ## _ ## fld_name ## _BIT_SIZE == 0x20 ? \ - reg_val /*!< \internal Optimization for 32b fields */ : \ - BITFIELD_GET(reg_val, DX_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \ - DX_ ## reg_name ## _ ## fld_name ## _BIT_SIZE)) - -/*! Bit fields access */ -#define CC_REG_FLD_GET2(unit_name, reg_name, fld_name, reg_val) \ - (CC_ ## reg_name ## _ ## fld_name ## _BIT_SIZE == 0x20 ? \ - reg_val /*!< \internal Optimization for 32b fields */ : \ - BITFIELD_GET(reg_val, CC_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \ - CC_ ## reg_name ## _ ## fld_name ## _BIT_SIZE)) - -/* yael TBD !!! - * -* all HW includes should start with CC_ and not DX_ !! */ - - -/*! Bit fields set */ -#define CC_REG_FLD_SET( \ - unit_name, reg_name, fld_name, reg_shadow_var, new_fld_val) \ -do { \ - if (DX_ ## reg_name ## _ ## fld_name ## _BIT_SIZE == 0x20) \ - reg_shadow_var = new_fld_val; /*!< \internal Optimization for 32b fields */\ - else \ - BITFIELD_SET(reg_shadow_var, \ - DX_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \ - DX_ ## reg_name ## _ ## fld_name ## _BIT_SIZE, \ - new_fld_val); \ -} while (0) - -/*! Bit fields set */ -#define CC_REG_FLD_SET2( \ - unit_name, reg_name, fld_name, reg_shadow_var, new_fld_val) \ -do { \ - if (CC_ ## reg_name ## _ ## fld_name ## _BIT_SIZE == 0x20) \ - reg_shadow_var = new_fld_val; /*!< \internal Optimization for 32b fields */\ - else \ - BITFIELD_SET(reg_shadow_var, \ - CC_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \ - CC_ ## reg_name ## _ ## fld_name ## _BIT_SIZE, \ - new_fld_val); \ -} while (0) - -/* Usage example: - uint32_t reg_shadow = READ_REGISTER(CC_REG_ADDR(CRY_KERNEL,AES_CONTROL)); - CC_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY0,reg_shadow, 3); - CC_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY1,reg_shadow, 1); - WRITE_REGISTER(CC_REG_ADDR(CRY_KERNEL,AES_CONTROL), reg_shadow); - */ - #endif /*_CC_REGS_H_*/ diff --git a/drivers/staging/ccree/dx_crys_kernel.h b/drivers/staging/ccree/dx_crys_kernel.h index 703469c4a828..219603030344 100644 --- a/drivers/staging/ccree/dx_crys_kernel.h +++ b/drivers/staging/ccree/dx_crys_kernel.h @@ -1,15 +1,15 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ @@ -20,161 +20,161 @@ // -------------------------------------- // BLOCK: DSCRPTR // -------------------------------------- -#define DX_DSCRPTR_COMPLETION_COUNTER_REG_OFFSET 0xE00UL -#define DX_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SIZE 0x6UL -#define DX_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SHIFT 0x6UL -#define DX_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SIZE 0x1UL -#define DX_DSCRPTR_SW_RESET_REG_OFFSET 0xE40UL -#define DX_DSCRPTR_SW_RESET_VALUE_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_SW_RESET_VALUE_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_SRAM_SIZE_REG_OFFSET 0xE60UL -#define DX_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SIZE 0xAUL -#define DX_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SHIFT 0xAUL -#define DX_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SIZE 0xCUL -#define DX_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SHIFT 0x16UL -#define DX_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SIZE 0x3UL -#define DX_DSCRPTR_SINGLE_ADDR_EN_REG_OFFSET 0xE64UL -#define DX_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SIZE 0x1UL -#define DX_DSCRPTR_MEASURE_CNTR_REG_OFFSET 0xE68UL -#define DX_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SIZE 0x20UL -#define DX_DSCRPTR_QUEUE_WORD0_REG_OFFSET 0xE80UL -#define DX_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SIZE 0x20UL -#define DX_DSCRPTR_QUEUE_WORD1_REG_OFFSET 0xE84UL -#define DX_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SIZE 0x2UL -#define DX_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SHIFT 0x2UL -#define DX_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE 0x18UL -#define DX_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SHIFT 0x1AUL -#define DX_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SHIFT 0x1BUL -#define DX_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SHIFT 0x1CUL -#define DX_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SHIFT 0x1DUL -#define DX_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SHIFT 0x1EUL -#define DX_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SIZE 0x2UL -#define DX_DSCRPTR_QUEUE_WORD2_REG_OFFSET 0xE88UL -#define DX_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SIZE 0x20UL -#define DX_DSCRPTR_QUEUE_WORD3_REG_OFFSET 0xE8CUL -#define DX_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SIZE 0x2UL -#define DX_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SHIFT 0x2UL -#define DX_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SIZE 0x18UL -#define DX_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SHIFT 0x1AUL -#define DX_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SHIFT 0x1BUL -#define DX_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SHIFT 0x1DUL -#define DX_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SHIFT 0x1EUL -#define DX_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SHIFT 0x1FUL -#define DX_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD4_REG_OFFSET 0xE90UL -#define DX_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SIZE 0x6UL -#define DX_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SHIFT 0x6UL -#define DX_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SHIFT 0x7UL -#define DX_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SHIFT 0x8UL -#define DX_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SIZE 0x2UL -#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SHIFT 0xAUL -#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SIZE 0x4UL -#define DX_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SHIFT 0xEUL -#define DX_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SHIFT 0xFUL -#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SIZE 0x2UL -#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SHIFT 0x11UL -#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SIZE 0x2UL -#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SHIFT 0x13UL -#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SHIFT 0x14UL -#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SIZE 0x2UL -#define DX_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SHIFT 0x16UL -#define DX_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SIZE 0x2UL -#define DX_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SHIFT 0x18UL -#define DX_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SIZE 0x4UL -#define DX_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SHIFT 0x1CUL -#define DX_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SHIFT 0x1DUL -#define DX_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SHIFT 0x1EUL -#define DX_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SHIFT 0x1FUL -#define DX_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SIZE 0x1UL -#define DX_DSCRPTR_QUEUE_WORD5_REG_OFFSET 0xE94UL -#define DX_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SIZE 0x10UL -#define DX_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SHIFT 0x10UL -#define DX_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SIZE 0x10UL -#define DX_DSCRPTR_QUEUE_WATERMARK_REG_OFFSET 0xE98UL -#define DX_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SIZE 0xAUL -#define DX_DSCRPTR_QUEUE_CONTENT_REG_OFFSET 0xE9CUL -#define DX_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SHIFT 0x0UL -#define DX_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SIZE 0xAUL +#define DX_DSCRPTR_COMPLETION_COUNTER_REG_OFFSET 0xE00UL +#define DX_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SHIFT 0x0UL +#define DX_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SIZE 0x6UL +#define DX_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SHIFT 0x6UL +#define DX_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SIZE 0x1UL +#define DX_DSCRPTR_SW_RESET_REG_OFFSET 0xE40UL +#define DX_DSCRPTR_SW_RESET_VALUE_BIT_SHIFT 0x0UL +#define DX_DSCRPTR_SW_RESET_VALUE_BIT_SIZE 0x1UL +#define DX_DSCRPTR_QUEUE_SRAM_SIZE_REG_OFFSET 0xE60UL +#define DX_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SHIFT 0x0UL +#define DX_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SIZE 0xAUL +#define DX_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SHIFT 0xAUL +#define DX_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SIZE 0xCUL +#define DX_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SHIFT 0x16UL +#define DX_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SIZE 0x3UL +#define DX_DSCRPTR_SINGLE_ADDR_EN_REG_OFFSET 0xE64UL +#define DX_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SHIFT 0x0UL +#define DX_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SIZE 0x1UL +#define DX_DSCRPTR_MEASURE_CNTR_REG_OFFSET 0xE68UL +#define DX_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SHIFT 0x0UL +#define DX_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SIZE 0x20UL +#define DX_DSCRPTR_QUEUE_WORD0_REG_OFFSET 0xE80UL +#define DX_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SHIFT 0x0UL +#define DX_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SIZE 0x20UL +#define DX_DSCRPTR_QUEUE_WORD1_REG_OFFSET 0xE84UL +#define DX_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SHIFT 0x0UL +#define DX_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SIZE 0x2UL +#define DX_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SHIFT 0x2UL +#define DX_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE 0x18UL +#define DX_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SHIFT 0x1AUL +#define DX_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SIZE 0x1UL +#define DX_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SHIFT 0x1BUL +#define DX_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SIZE 0x1UL +#define DX_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SHIFT 0x1CUL +#define DX_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SIZE 0x1UL +#define DX_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SHIFT 0x1DUL +#define DX_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SIZE 0x1UL +#define DX_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SHIFT 0x1EUL +#define DX_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SIZE 0x2UL +#define DX_DSCRPTR_QUEUE_WORD2_REG_OFFSET 0xE88UL +#define DX_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SHIFT 0x0UL +#define DX_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SIZE 0x20UL +#define DX_DSCRPTR_QUEUE_WORD3_REG_OFFSET 0xE8CUL +#define DX_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SHIFT 0x0UL +#define DX_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SIZE 0x2UL +#define DX_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SHIFT 0x2UL +#define DX_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SIZE 0x18UL +#define DX_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SHIFT 0x1AUL +#define DX_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SIZE 0x1UL +#define DX_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SHIFT 0x1BUL +#define DX_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SIZE 0x1UL +#define DX_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SHIFT 0x1DUL +#define DX_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SIZE 0x1UL +#define DX_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SHIFT 0x1EUL +#define DX_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SIZE 0x1UL +#define DX_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SHIFT 0x1FUL +#define DX_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SIZE 0x1UL +#define DX_DSCRPTR_QUEUE_WORD4_REG_OFFSET 0xE90UL +#define DX_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SHIFT 0x0UL +#define DX_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SIZE 0x6UL +#define DX_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SHIFT 0x6UL +#define DX_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SIZE 0x1UL +#define DX_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SHIFT 0x7UL +#define DX_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SIZE 0x1UL +#define DX_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SHIFT 0x8UL +#define DX_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SIZE 0x2UL +#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SHIFT 0xAUL +#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SIZE 0x4UL +#define DX_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SHIFT 0xEUL +#define DX_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SIZE 0x1UL +#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SHIFT 0xFUL +#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SIZE 0x2UL +#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SHIFT 0x11UL +#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SIZE 0x2UL +#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SHIFT 0x13UL +#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SIZE 0x1UL +#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SHIFT 0x14UL +#define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SIZE 0x2UL +#define DX_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SHIFT 0x16UL +#define DX_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SIZE 0x2UL +#define DX_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SHIFT 0x18UL +#define DX_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SIZE 0x4UL +#define DX_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SHIFT 0x1CUL +#define DX_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SIZE 0x1UL +#define DX_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SHIFT 0x1DUL +#define DX_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SIZE 0x1UL +#define DX_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SHIFT 0x1EUL +#define DX_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SIZE 0x1UL +#define DX_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SHIFT 0x1FUL +#define DX_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SIZE 0x1UL +#define DX_DSCRPTR_QUEUE_WORD5_REG_OFFSET 0xE94UL +#define DX_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SHIFT 0x0UL +#define DX_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SIZE 0x10UL +#define DX_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SHIFT 0x10UL +#define DX_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SIZE 0x10UL +#define DX_DSCRPTR_QUEUE_WATERMARK_REG_OFFSET 0xE98UL +#define DX_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SHIFT 0x0UL +#define DX_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SIZE 0xAUL +#define DX_DSCRPTR_QUEUE_CONTENT_REG_OFFSET 0xE9CUL +#define DX_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SHIFT 0x0UL +#define DX_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SIZE 0xAUL // -------------------------------------- // BLOCK: AXI_P // -------------------------------------- -#define DX_AXIM_MON_INFLIGHT_REG_OFFSET 0xB00UL -#define DX_AXIM_MON_INFLIGHT_VALUE_BIT_SHIFT 0x0UL -#define DX_AXIM_MON_INFLIGHT_VALUE_BIT_SIZE 0x8UL -#define DX_AXIM_MON_INFLIGHTLAST_REG_OFFSET 0xB40UL -#define DX_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SHIFT 0x0UL -#define DX_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SIZE 0x8UL -#define DX_AXIM_MON_COMP_REG_OFFSET 0xB80UL -#define DX_AXIM_MON_COMP_VALUE_BIT_SHIFT 0x0UL -#define DX_AXIM_MON_COMP_VALUE_BIT_SIZE 0x10UL -#define DX_AXIM_MON_ERR_REG_OFFSET 0xBC4UL -#define DX_AXIM_MON_ERR_BRESP_BIT_SHIFT 0x0UL -#define DX_AXIM_MON_ERR_BRESP_BIT_SIZE 0x2UL -#define DX_AXIM_MON_ERR_BID_BIT_SHIFT 0x2UL -#define DX_AXIM_MON_ERR_BID_BIT_SIZE 0x4UL -#define DX_AXIM_MON_ERR_RRESP_BIT_SHIFT 0x10UL -#define DX_AXIM_MON_ERR_RRESP_BIT_SIZE 0x2UL -#define DX_AXIM_MON_ERR_RID_BIT_SHIFT 0x12UL -#define DX_AXIM_MON_ERR_RID_BIT_SIZE 0x4UL -#define DX_AXIM_CFG_REG_OFFSET 0xBE8UL -#define DX_AXIM_CFG_BRESPMASK_BIT_SHIFT 0x4UL -#define DX_AXIM_CFG_BRESPMASK_BIT_SIZE 0x1UL -#define DX_AXIM_CFG_RRESPMASK_BIT_SHIFT 0x5UL -#define DX_AXIM_CFG_RRESPMASK_BIT_SIZE 0x1UL -#define DX_AXIM_CFG_INFLTMASK_BIT_SHIFT 0x6UL -#define DX_AXIM_CFG_INFLTMASK_BIT_SIZE 0x1UL -#define DX_AXIM_CFG_COMPMASK_BIT_SHIFT 0x7UL -#define DX_AXIM_CFG_COMPMASK_BIT_SIZE 0x1UL -#define DX_AXIM_ACE_CONST_REG_OFFSET 0xBECUL -#define DX_AXIM_ACE_CONST_ARDOMAIN_BIT_SHIFT 0x0UL -#define DX_AXIM_ACE_CONST_ARDOMAIN_BIT_SIZE 0x2UL -#define DX_AXIM_ACE_CONST_AWDOMAIN_BIT_SHIFT 0x2UL -#define DX_AXIM_ACE_CONST_AWDOMAIN_BIT_SIZE 0x2UL -#define DX_AXIM_ACE_CONST_ARBAR_BIT_SHIFT 0x4UL -#define DX_AXIM_ACE_CONST_ARBAR_BIT_SIZE 0x2UL -#define DX_AXIM_ACE_CONST_AWBAR_BIT_SHIFT 0x6UL -#define DX_AXIM_ACE_CONST_AWBAR_BIT_SIZE 0x2UL -#define DX_AXIM_ACE_CONST_ARSNOOP_BIT_SHIFT 0x8UL -#define DX_AXIM_ACE_CONST_ARSNOOP_BIT_SIZE 0x4UL -#define DX_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SHIFT 0xCUL -#define DX_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SIZE 0x3UL -#define DX_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SHIFT 0xFUL -#define DX_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SIZE 0x3UL -#define DX_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SHIFT 0x12UL -#define DX_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SIZE 0x7UL -#define DX_AXIM_ACE_CONST_AWLEN_VAL_BIT_SHIFT 0x19UL -#define DX_AXIM_ACE_CONST_AWLEN_VAL_BIT_SIZE 0x4UL -#define DX_AXIM_CACHE_PARAMS_REG_OFFSET 0xBF0UL -#define DX_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SHIFT 0x0UL -#define DX_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SIZE 0x4UL -#define DX_AXIM_CACHE_PARAMS_AWCACHE_BIT_SHIFT 0x4UL -#define DX_AXIM_CACHE_PARAMS_AWCACHE_BIT_SIZE 0x4UL -#define DX_AXIM_CACHE_PARAMS_ARCACHE_BIT_SHIFT 0x8UL -#define DX_AXIM_CACHE_PARAMS_ARCACHE_BIT_SIZE 0x4UL +#define DX_AXIM_MON_INFLIGHT_REG_OFFSET 0xB00UL +#define DX_AXIM_MON_INFLIGHT_VALUE_BIT_SHIFT 0x0UL +#define DX_AXIM_MON_INFLIGHT_VALUE_BIT_SIZE 0x8UL +#define DX_AXIM_MON_INFLIGHTLAST_REG_OFFSET 0xB40UL +#define DX_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SHIFT 0x0UL +#define DX_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SIZE 0x8UL +#define DX_AXIM_MON_COMP_REG_OFFSET 0xB80UL +#define DX_AXIM_MON_COMP_VALUE_BIT_SHIFT 0x0UL +#define DX_AXIM_MON_COMP_VALUE_BIT_SIZE 0x10UL +#define DX_AXIM_MON_ERR_REG_OFFSET 0xBC4UL +#define DX_AXIM_MON_ERR_BRESP_BIT_SHIFT 0x0UL +#define DX_AXIM_MON_ERR_BRESP_BIT_SIZE 0x2UL +#define DX_AXIM_MON_ERR_BID_BIT_SHIFT 0x2UL +#define DX_AXIM_MON_ERR_BID_BIT_SIZE 0x4UL +#define DX_AXIM_MON_ERR_RRESP_BIT_SHIFT 0x10UL +#define DX_AXIM_MON_ERR_RRESP_BIT_SIZE 0x2UL +#define DX_AXIM_MON_ERR_RID_BIT_SHIFT 0x12UL +#define DX_AXIM_MON_ERR_RID_BIT_SIZE 0x4UL +#define DX_AXIM_CFG_REG_OFFSET 0xBE8UL +#define DX_AXIM_CFG_BRESPMASK_BIT_SHIFT 0x4UL +#define DX_AXIM_CFG_BRESPMASK_BIT_SIZE 0x1UL +#define DX_AXIM_CFG_RRESPMASK_BIT_SHIFT 0x5UL +#define DX_AXIM_CFG_RRESPMASK_BIT_SIZE 0x1UL +#define DX_AXIM_CFG_INFLTMASK_BIT_SHIFT 0x6UL +#define DX_AXIM_CFG_INFLTMASK_BIT_SIZE 0x1UL +#define DX_AXIM_CFG_COMPMASK_BIT_SHIFT 0x7UL +#define DX_AXIM_CFG_COMPMASK_BIT_SIZE 0x1UL +#define DX_AXIM_ACE_CONST_REG_OFFSET 0xBECUL +#define DX_AXIM_ACE_CONST_ARDOMAIN_BIT_SHIFT 0x0UL +#define DX_AXIM_ACE_CONST_ARDOMAIN_BIT_SIZE 0x2UL +#define DX_AXIM_ACE_CONST_AWDOMAIN_BIT_SHIFT 0x2UL +#define DX_AXIM_ACE_CONST_AWDOMAIN_BIT_SIZE 0x2UL +#define DX_AXIM_ACE_CONST_ARBAR_BIT_SHIFT 0x4UL +#define DX_AXIM_ACE_CONST_ARBAR_BIT_SIZE 0x2UL +#define DX_AXIM_ACE_CONST_AWBAR_BIT_SHIFT 0x6UL +#define DX_AXIM_ACE_CONST_AWBAR_BIT_SIZE 0x2UL +#define DX_AXIM_ACE_CONST_ARSNOOP_BIT_SHIFT 0x8UL +#define DX_AXIM_ACE_CONST_ARSNOOP_BIT_SIZE 0x4UL +#define DX_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SHIFT 0xCUL +#define DX_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SIZE 0x3UL +#define DX_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SHIFT 0xFUL +#define DX_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SIZE 0x3UL +#define DX_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SHIFT 0x12UL +#define DX_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SIZE 0x7UL +#define DX_AXIM_ACE_CONST_AWLEN_VAL_BIT_SHIFT 0x19UL +#define DX_AXIM_ACE_CONST_AWLEN_VAL_BIT_SIZE 0x4UL +#define DX_AXIM_CACHE_PARAMS_REG_OFFSET 0xBF0UL +#define DX_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SHIFT 0x0UL +#define DX_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SIZE 0x4UL +#define DX_AXIM_CACHE_PARAMS_AWCACHE_BIT_SHIFT 0x4UL +#define DX_AXIM_CACHE_PARAMS_AWCACHE_BIT_SIZE 0x4UL +#define DX_AXIM_CACHE_PARAMS_ARCACHE_BIT_SHIFT 0x8UL +#define DX_AXIM_CACHE_PARAMS_ARCACHE_BIT_SIZE 0x4UL #endif // __DX_CRYS_KERNEL_H__ diff --git a/drivers/staging/ccree/dx_env.h b/drivers/staging/ccree/dx_env.h deleted file mode 100644 index 08040604b6da..000000000000 --- a/drivers/staging/ccree/dx_env.h +++ /dev/null @@ -1,224 +0,0 @@ -/* - * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef __DX_ENV_H__ -#define __DX_ENV_H__ - -// -------------------------------------- -// BLOCK: FPGA_ENV_REGS -// -------------------------------------- -#define DX_ENV_PKA_DEBUG_MODE_REG_OFFSET 0x024UL -#define DX_ENV_PKA_DEBUG_MODE_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_PKA_DEBUG_MODE_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_SCAN_MODE_REG_OFFSET 0x030UL -#define DX_ENV_SCAN_MODE_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_SCAN_MODE_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_CC_ALLOW_SCAN_REG_OFFSET 0x034UL -#define DX_ENV_CC_ALLOW_SCAN_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_CC_ALLOW_SCAN_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_CC_HOST_INT_REG_OFFSET 0x0A0UL -#define DX_ENV_CC_HOST_INT_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_CC_HOST_INT_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_CC_PUB_HOST_INT_REG_OFFSET 0x0A4UL -#define DX_ENV_CC_PUB_HOST_INT_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_CC_PUB_HOST_INT_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_CC_RST_N_REG_OFFSET 0x0A8UL -#define DX_ENV_CC_RST_N_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_CC_RST_N_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_RST_OVERRIDE_REG_OFFSET 0x0ACUL -#define DX_ENV_RST_OVERRIDE_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_RST_OVERRIDE_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_CC_POR_N_ADDR_REG_OFFSET 0x0E0UL -#define DX_ENV_CC_POR_N_ADDR_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_CC_POR_N_ADDR_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_CC_COLD_RST_REG_OFFSET 0x0FCUL -#define DX_ENV_CC_COLD_RST_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_CC_COLD_RST_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_DUMMY_ADDR_REG_OFFSET 0x108UL -#define DX_ENV_DUMMY_ADDR_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_DUMMY_ADDR_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_COUNTER_CLR_REG_OFFSET 0x118UL -#define DX_ENV_COUNTER_CLR_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_COUNTER_CLR_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_COUNTER_RD_REG_OFFSET 0x11CUL -#define DX_ENV_COUNTER_RD_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_COUNTER_RD_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_RNG_DEBUG_ENABLE_REG_OFFSET 0x430UL -#define DX_ENV_RNG_DEBUG_ENABLE_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_RNG_DEBUG_ENABLE_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_CC_LCS_REG_OFFSET 0x43CUL -#define DX_ENV_CC_LCS_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_CC_LCS_VALUE_BIT_SIZE 0x8UL -#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_REG_OFFSET 0x440UL -#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_CM_BIT_SHIFT 0x0UL -#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_CM_BIT_SIZE 0x1UL -#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_DM_BIT_SHIFT 0x1UL -#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_DM_BIT_SIZE 0x1UL -#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_SECURE_BIT_SHIFT 0x2UL -#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_SECURE_BIT_SIZE 0x1UL -#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_RMA_BIT_SHIFT 0x3UL -#define DX_ENV_CC_IS_CM_DM_SECURE_RMA_IS_RMA_BIT_SIZE 0x1UL -#define DX_ENV_DCU_EN_REG_OFFSET 0x444UL -#define DX_ENV_DCU_EN_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_DCU_EN_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_CC_LCS_IS_VALID_REG_OFFSET 0x448UL -#define DX_ENV_CC_LCS_IS_VALID_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_CC_LCS_IS_VALID_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_POWER_DOWN_REG_OFFSET 0x478UL -#define DX_ENV_POWER_DOWN_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_POWER_DOWN_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_DCU_H_EN_REG_OFFSET 0x484UL -#define DX_ENV_DCU_H_EN_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_DCU_H_EN_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_VERSION_REG_OFFSET 0x488UL -#define DX_ENV_VERSION_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_VERSION_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_ROSC_WRITE_REG_OFFSET 0x48CUL -#define DX_ENV_ROSC_WRITE_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_ROSC_WRITE_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_ROSC_ADDR_REG_OFFSET 0x490UL -#define DX_ENV_ROSC_ADDR_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_ROSC_ADDR_VALUE_BIT_SIZE 0x8UL -#define DX_ENV_RESET_SESSION_KEY_REG_OFFSET 0x494UL -#define DX_ENV_RESET_SESSION_KEY_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_RESET_SESSION_KEY_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_SESSION_KEY_0_REG_OFFSET 0x4A0UL -#define DX_ENV_SESSION_KEY_0_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_SESSION_KEY_0_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_SESSION_KEY_1_REG_OFFSET 0x4A4UL -#define DX_ENV_SESSION_KEY_1_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_SESSION_KEY_1_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_SESSION_KEY_2_REG_OFFSET 0x4A8UL -#define DX_ENV_SESSION_KEY_2_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_SESSION_KEY_2_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_SESSION_KEY_3_REG_OFFSET 0x4ACUL -#define DX_ENV_SESSION_KEY_3_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_SESSION_KEY_3_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_SESSION_KEY_VALID_REG_OFFSET 0x4B0UL -#define DX_ENV_SESSION_KEY_VALID_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_SESSION_KEY_VALID_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_SPIDEN_REG_OFFSET 0x4D0UL -#define DX_ENV_SPIDEN_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_SPIDEN_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_AXIM_USER_PARAMS_REG_OFFSET 0x600UL -#define DX_ENV_AXIM_USER_PARAMS_ARUSER_BIT_SHIFT 0x0UL -#define DX_ENV_AXIM_USER_PARAMS_ARUSER_BIT_SIZE 0x5UL -#define DX_ENV_AXIM_USER_PARAMS_AWUSER_BIT_SHIFT 0x5UL -#define DX_ENV_AXIM_USER_PARAMS_AWUSER_BIT_SIZE 0x5UL -#define DX_ENV_SECURITY_MODE_OVERRIDE_REG_OFFSET 0x604UL -#define DX_ENV_SECURITY_MODE_OVERRIDE_AWPROT_NS_BIT_BIT_SHIFT 0x0UL -#define DX_ENV_SECURITY_MODE_OVERRIDE_AWPROT_NS_BIT_BIT_SIZE 0x1UL -#define DX_ENV_SECURITY_MODE_OVERRIDE_AWPROT_NS_OVERRIDE_BIT_SHIFT 0x1UL -#define DX_ENV_SECURITY_MODE_OVERRIDE_AWPROT_NS_OVERRIDE_BIT_SIZE 0x1UL -#define DX_ENV_SECURITY_MODE_OVERRIDE_ARPROT_NS_BIT_BIT_SHIFT 0x2UL -#define DX_ENV_SECURITY_MODE_OVERRIDE_ARPROT_NS_BIT_BIT_SIZE 0x1UL -#define DX_ENV_SECURITY_MODE_OVERRIDE_ARPROT_NS_OVERRIDE_BIT_SHIFT 0x3UL -#define DX_ENV_SECURITY_MODE_OVERRIDE_ARPROT_NS_OVERRIDE_BIT_SIZE 0x1UL -#define DX_ENV_AO_CC_KPLT_0_REG_OFFSET 0x620UL -#define DX_ENV_AO_CC_KPLT_0_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_AO_CC_KPLT_0_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_AO_CC_KPLT_1_REG_OFFSET 0x624UL -#define DX_ENV_AO_CC_KPLT_1_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_AO_CC_KPLT_1_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_AO_CC_KPLT_2_REG_OFFSET 0x628UL -#define DX_ENV_AO_CC_KPLT_2_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_AO_CC_KPLT_2_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_AO_CC_KPLT_3_REG_OFFSET 0x62CUL -#define DX_ENV_AO_CC_KPLT_3_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_AO_CC_KPLT_3_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_AO_CC_KCST_0_REG_OFFSET 0x630UL -#define DX_ENV_AO_CC_KCST_0_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_AO_CC_KCST_0_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_AO_CC_KCST_1_REG_OFFSET 0x634UL -#define DX_ENV_AO_CC_KCST_1_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_AO_CC_KCST_1_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_AO_CC_KCST_2_REG_OFFSET 0x638UL -#define DX_ENV_AO_CC_KCST_2_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_AO_CC_KCST_2_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_AO_CC_KCST_3_REG_OFFSET 0x63CUL -#define DX_ENV_AO_CC_KCST_3_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_AO_CC_KCST_3_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_APB_FIPS_ADDR_REG_OFFSET 0x650UL -#define DX_ENV_APB_FIPS_ADDR_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APB_FIPS_ADDR_VALUE_BIT_SIZE 0xCUL -#define DX_ENV_APB_FIPS_VAL_REG_OFFSET 0x654UL -#define DX_ENV_APB_FIPS_VAL_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APB_FIPS_VAL_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_APB_FIPS_MASK_REG_OFFSET 0x658UL -#define DX_ENV_APB_FIPS_MASK_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APB_FIPS_MASK_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_APB_FIPS_CNT_REG_OFFSET 0x65CUL -#define DX_ENV_APB_FIPS_CNT_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APB_FIPS_CNT_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_APB_FIPS_NEW_ADDR_REG_OFFSET 0x660UL -#define DX_ENV_APB_FIPS_NEW_ADDR_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APB_FIPS_NEW_ADDR_VALUE_BIT_SIZE 0xCUL -#define DX_ENV_APB_FIPS_NEW_VAL_REG_OFFSET 0x664UL -#define DX_ENV_APB_FIPS_NEW_VAL_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APB_FIPS_NEW_VAL_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_APBP_FIPS_ADDR_REG_OFFSET 0x670UL -#define DX_ENV_APBP_FIPS_ADDR_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APBP_FIPS_ADDR_VALUE_BIT_SIZE 0xCUL -#define DX_ENV_APBP_FIPS_VAL_REG_OFFSET 0x674UL -#define DX_ENV_APBP_FIPS_VAL_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APBP_FIPS_VAL_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_APBP_FIPS_MASK_REG_OFFSET 0x678UL -#define DX_ENV_APBP_FIPS_MASK_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APBP_FIPS_MASK_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_APBP_FIPS_CNT_REG_OFFSET 0x67CUL -#define DX_ENV_APBP_FIPS_CNT_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APBP_FIPS_CNT_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_APBP_FIPS_NEW_ADDR_REG_OFFSET 0x680UL -#define DX_ENV_APBP_FIPS_NEW_ADDR_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APBP_FIPS_NEW_ADDR_VALUE_BIT_SIZE 0xCUL -#define DX_ENV_APBP_FIPS_NEW_VAL_REG_OFFSET 0x684UL -#define DX_ENV_APBP_FIPS_NEW_VAL_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_APBP_FIPS_NEW_VAL_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_CC_POWERDOWN_EN_REG_OFFSET 0x690UL -#define DX_ENV_CC_POWERDOWN_EN_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_CC_POWERDOWN_EN_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_CC_POWERDOWN_RST_EN_REG_OFFSET 0x694UL -#define DX_ENV_CC_POWERDOWN_RST_EN_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_CC_POWERDOWN_RST_EN_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_POWERDOWN_RST_CNTR_REG_OFFSET 0x698UL -#define DX_ENV_POWERDOWN_RST_CNTR_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_POWERDOWN_RST_CNTR_VALUE_BIT_SIZE 0x20UL -#define DX_ENV_POWERDOWN_EN_DEBUG_REG_OFFSET 0x69CUL -#define DX_ENV_POWERDOWN_EN_DEBUG_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_POWERDOWN_EN_DEBUG_VALUE_BIT_SIZE 0x1UL -// -------------------------------------- -// BLOCK: ENV_CC_MEMORIES -// -------------------------------------- -#define DX_ENV_FUSE_READY_REG_OFFSET 0x000UL -#define DX_ENV_FUSE_READY_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_FUSE_READY_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_PERF_RAM_MASTER_REG_OFFSET 0x0ECUL -#define DX_ENV_PERF_RAM_MASTER_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_PERF_RAM_MASTER_VALUE_BIT_SIZE 0x1UL -#define DX_ENV_PERF_RAM_ADDR_HIGH4_REG_OFFSET 0x0F0UL -#define DX_ENV_PERF_RAM_ADDR_HIGH4_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_PERF_RAM_ADDR_HIGH4_VALUE_BIT_SIZE 0x2UL -#define DX_ENV_FUSES_RAM_REG_OFFSET 0x3ECUL -#define DX_ENV_FUSES_RAM_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_FUSES_RAM_VALUE_BIT_SIZE 0x20UL -// -------------------------------------- -// BLOCK: ENV_PERF_RAM_BASE -// -------------------------------------- -#define DX_ENV_PERF_RAM_BASE_REG_OFFSET 0x000UL -#define DX_ENV_PERF_RAM_BASE_VALUE_BIT_SHIFT 0x0UL -#define DX_ENV_PERF_RAM_BASE_VALUE_BIT_SIZE 0x20UL - -#endif /*__DX_ENV_H__*/ diff --git a/drivers/staging/ccree/dx_host.h b/drivers/staging/ccree/dx_host.h index 4e42e748dc5f..863c2670d826 100644 --- a/drivers/staging/ccree/dx_host.h +++ b/drivers/staging/ccree/dx_host.h @@ -1,15 +1,15 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ @@ -20,136 +20,136 @@ // -------------------------------------- // BLOCK: HOST_P // -------------------------------------- -#define DX_HOST_IRR_REG_OFFSET 0xA00UL -#define DX_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SHIFT 0x2UL -#define DX_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SIZE 0x1UL -#define DX_HOST_IRR_AXI_ERR_INT_BIT_SHIFT 0x8UL -#define DX_HOST_IRR_AXI_ERR_INT_BIT_SIZE 0x1UL -#define DX_HOST_IRR_GPR0_BIT_SHIFT 0xBUL -#define DX_HOST_IRR_GPR0_BIT_SIZE 0x1UL -#define DX_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SHIFT 0x13UL -#define DX_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SIZE 0x1UL -#define DX_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT 0x17UL -#define DX_HOST_IRR_AXIM_COMP_INT_BIT_SIZE 0x1UL -#define DX_HOST_IMR_REG_OFFSET 0xA04UL -#define DX_HOST_IMR_NOT_USED_MASK_BIT_SHIFT 0x1UL -#define DX_HOST_IMR_NOT_USED_MASK_BIT_SIZE 0x1UL -#define DX_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SHIFT 0x2UL -#define DX_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SIZE 0x1UL -#define DX_HOST_IMR_AXI_ERR_MASK_BIT_SHIFT 0x8UL -#define DX_HOST_IMR_AXI_ERR_MASK_BIT_SIZE 0x1UL -#define DX_HOST_IMR_GPR0_BIT_SHIFT 0xBUL -#define DX_HOST_IMR_GPR0_BIT_SIZE 0x1UL -#define DX_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SHIFT 0x13UL -#define DX_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SIZE 0x1UL -#define DX_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SHIFT 0x17UL -#define DX_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SIZE 0x1UL -#define DX_HOST_ICR_REG_OFFSET 0xA08UL -#define DX_HOST_ICR_DSCRPTR_COMPLETION_BIT_SHIFT 0x2UL -#define DX_HOST_ICR_DSCRPTR_COMPLETION_BIT_SIZE 0x1UL -#define DX_HOST_ICR_AXI_ERR_CLEAR_BIT_SHIFT 0x8UL -#define DX_HOST_ICR_AXI_ERR_CLEAR_BIT_SIZE 0x1UL -#define DX_HOST_ICR_GPR_INT_CLEAR_BIT_SHIFT 0xBUL -#define DX_HOST_ICR_GPR_INT_CLEAR_BIT_SIZE 0x1UL -#define DX_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SHIFT 0x13UL -#define DX_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SIZE 0x1UL -#define DX_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SHIFT 0x17UL -#define DX_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SIZE 0x1UL -#define DX_HOST_SIGNATURE_REG_OFFSET 0xA24UL -#define DX_HOST_SIGNATURE_VALUE_BIT_SHIFT 0x0UL -#define DX_HOST_SIGNATURE_VALUE_BIT_SIZE 0x20UL -#define DX_HOST_BOOT_REG_OFFSET 0xA28UL -#define DX_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SHIFT 0x0UL -#define DX_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SHIFT 0x1UL -#define DX_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SHIFT 0x2UL -#define DX_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SHIFT 0x3UL -#define DX_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SHIFT 0x5UL -#define DX_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SHIFT 0x6UL -#define DX_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SIZE 0x3UL -#define DX_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SHIFT 0x9UL -#define DX_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SHIFT 0xAUL -#define DX_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SHIFT 0xBUL -#define DX_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SHIFT 0xCUL -#define DX_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SHIFT 0xDUL -#define DX_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SHIFT 0xEUL -#define DX_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SHIFT 0xFUL -#define DX_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SHIFT 0x10UL -#define DX_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SHIFT 0x11UL -#define DX_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SHIFT 0x12UL -#define DX_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SHIFT 0x13UL -#define DX_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SHIFT 0x14UL -#define DX_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SHIFT 0x15UL -#define DX_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SHIFT 0x16UL -#define DX_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SHIFT 0x17UL -#define DX_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SHIFT 0x18UL -#define DX_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SHIFT 0x19UL -#define DX_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SHIFT 0x1AUL -#define DX_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SHIFT 0x1BUL -#define DX_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SHIFT 0x1CUL -#define DX_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SHIFT 0x1DUL -#define DX_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SHIFT 0x1EUL -#define DX_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define DX_HOST_VERSION_REG_OFFSET 0xA40UL -#define DX_HOST_VERSION_VALUE_BIT_SHIFT 0x0UL -#define DX_HOST_VERSION_VALUE_BIT_SIZE 0x20UL -#define DX_HOST_KFDE0_VALID_REG_OFFSET 0xA60UL -#define DX_HOST_KFDE0_VALID_VALUE_BIT_SHIFT 0x0UL -#define DX_HOST_KFDE0_VALID_VALUE_BIT_SIZE 0x1UL -#define DX_HOST_KFDE1_VALID_REG_OFFSET 0xA64UL -#define DX_HOST_KFDE1_VALID_VALUE_BIT_SHIFT 0x0UL -#define DX_HOST_KFDE1_VALID_VALUE_BIT_SIZE 0x1UL -#define DX_HOST_KFDE2_VALID_REG_OFFSET 0xA68UL -#define DX_HOST_KFDE2_VALID_VALUE_BIT_SHIFT 0x0UL -#define DX_HOST_KFDE2_VALID_VALUE_BIT_SIZE 0x1UL -#define DX_HOST_KFDE3_VALID_REG_OFFSET 0xA6CUL -#define DX_HOST_KFDE3_VALID_VALUE_BIT_SHIFT 0x0UL -#define DX_HOST_KFDE3_VALID_VALUE_BIT_SIZE 0x1UL -#define DX_HOST_GPR0_REG_OFFSET 0xA70UL -#define DX_HOST_GPR0_VALUE_BIT_SHIFT 0x0UL -#define DX_HOST_GPR0_VALUE_BIT_SIZE 0x20UL -#define DX_GPR_HOST_REG_OFFSET 0xA74UL -#define DX_GPR_HOST_VALUE_BIT_SHIFT 0x0UL -#define DX_GPR_HOST_VALUE_BIT_SIZE 0x20UL -#define DX_HOST_POWER_DOWN_EN_REG_OFFSET 0xA78UL -#define DX_HOST_POWER_DOWN_EN_VALUE_BIT_SHIFT 0x0UL -#define DX_HOST_POWER_DOWN_EN_VALUE_BIT_SIZE 0x1UL +#define DX_HOST_IRR_REG_OFFSET 0xA00UL +#define DX_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SHIFT 0x2UL +#define DX_HOST_IRR_DSCRPTR_COMPLETION_LOW_INT_BIT_SIZE 0x1UL +#define DX_HOST_IRR_AXI_ERR_INT_BIT_SHIFT 0x8UL +#define DX_HOST_IRR_AXI_ERR_INT_BIT_SIZE 0x1UL +#define DX_HOST_IRR_GPR0_BIT_SHIFT 0xBUL +#define DX_HOST_IRR_GPR0_BIT_SIZE 0x1UL +#define DX_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SHIFT 0x13UL +#define DX_HOST_IRR_DSCRPTR_WATERMARK_INT_BIT_SIZE 0x1UL +#define DX_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT 0x17UL +#define DX_HOST_IRR_AXIM_COMP_INT_BIT_SIZE 0x1UL +#define DX_HOST_IMR_REG_OFFSET 0xA04UL +#define DX_HOST_IMR_NOT_USED_MASK_BIT_SHIFT 0x1UL +#define DX_HOST_IMR_NOT_USED_MASK_BIT_SIZE 0x1UL +#define DX_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SHIFT 0x2UL +#define DX_HOST_IMR_DSCRPTR_COMPLETION_MASK_BIT_SIZE 0x1UL +#define DX_HOST_IMR_AXI_ERR_MASK_BIT_SHIFT 0x8UL +#define DX_HOST_IMR_AXI_ERR_MASK_BIT_SIZE 0x1UL +#define DX_HOST_IMR_GPR0_BIT_SHIFT 0xBUL +#define DX_HOST_IMR_GPR0_BIT_SIZE 0x1UL +#define DX_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SHIFT 0x13UL +#define DX_HOST_IMR_DSCRPTR_WATERMARK_MASK0_BIT_SIZE 0x1UL +#define DX_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SHIFT 0x17UL +#define DX_HOST_IMR_AXIM_COMP_INT_MASK_BIT_SIZE 0x1UL +#define DX_HOST_ICR_REG_OFFSET 0xA08UL +#define DX_HOST_ICR_DSCRPTR_COMPLETION_BIT_SHIFT 0x2UL +#define DX_HOST_ICR_DSCRPTR_COMPLETION_BIT_SIZE 0x1UL +#define DX_HOST_ICR_AXI_ERR_CLEAR_BIT_SHIFT 0x8UL +#define DX_HOST_ICR_AXI_ERR_CLEAR_BIT_SIZE 0x1UL +#define DX_HOST_ICR_GPR_INT_CLEAR_BIT_SHIFT 0xBUL +#define DX_HOST_ICR_GPR_INT_CLEAR_BIT_SIZE 0x1UL +#define DX_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SHIFT 0x13UL +#define DX_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SIZE 0x1UL +#define DX_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SHIFT 0x17UL +#define DX_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SIZE 0x1UL +#define DX_HOST_SIGNATURE_REG_OFFSET 0xA24UL +#define DX_HOST_SIGNATURE_VALUE_BIT_SHIFT 0x0UL +#define DX_HOST_SIGNATURE_VALUE_BIT_SIZE 0x20UL +#define DX_HOST_BOOT_REG_OFFSET 0xA28UL +#define DX_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SHIFT 0x0UL +#define DX_HOST_BOOT_SYNTHESIS_CONFIG_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SHIFT 0x1UL +#define DX_HOST_BOOT_LARGE_RKEK_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SHIFT 0x2UL +#define DX_HOST_BOOT_HASH_IN_FUSES_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SHIFT 0x3UL +#define DX_HOST_BOOT_EXT_MEM_SECURED_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SHIFT 0x5UL +#define DX_HOST_BOOT_RKEK_ECC_EXISTS_LOCAL_N_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SHIFT 0x6UL +#define DX_HOST_BOOT_SRAM_SIZE_LOCAL_BIT_SIZE 0x3UL +#define DX_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SHIFT 0x9UL +#define DX_HOST_BOOT_DSCRPTR_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SHIFT 0xAUL +#define DX_HOST_BOOT_PAU_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SHIFT 0xBUL +#define DX_HOST_BOOT_RNG_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SHIFT 0xCUL +#define DX_HOST_BOOT_PKA_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SHIFT 0xDUL +#define DX_HOST_BOOT_RC4_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SHIFT 0xEUL +#define DX_HOST_BOOT_SHA_512_PRSNT_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SHIFT 0xFUL +#define DX_HOST_BOOT_SHA_256_PRSNT_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SHIFT 0x10UL +#define DX_HOST_BOOT_MD5_PRSNT_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SHIFT 0x11UL +#define DX_HOST_BOOT_HASH_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SHIFT 0x12UL +#define DX_HOST_BOOT_C2_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SHIFT 0x13UL +#define DX_HOST_BOOT_DES_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SHIFT 0x14UL +#define DX_HOST_BOOT_AES_XCBC_MAC_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SHIFT 0x15UL +#define DX_HOST_BOOT_AES_CMAC_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SHIFT 0x16UL +#define DX_HOST_BOOT_AES_CCM_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SHIFT 0x17UL +#define DX_HOST_BOOT_AES_XEX_HW_T_CALC_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SHIFT 0x18UL +#define DX_HOST_BOOT_AES_XEX_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SHIFT 0x19UL +#define DX_HOST_BOOT_CTR_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SHIFT 0x1AUL +#define DX_HOST_BOOT_AES_DIN_BYTE_RESOLUTION_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SHIFT 0x1BUL +#define DX_HOST_BOOT_TUNNELING_ENB_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SHIFT 0x1CUL +#define DX_HOST_BOOT_SUPPORT_256_192_KEY_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SHIFT 0x1DUL +#define DX_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SHIFT 0x1EUL +#define DX_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SIZE 0x1UL +#define DX_HOST_VERSION_REG_OFFSET 0xA40UL +#define DX_HOST_VERSION_VALUE_BIT_SHIFT 0x0UL +#define DX_HOST_VERSION_VALUE_BIT_SIZE 0x20UL +#define DX_HOST_KFDE0_VALID_REG_OFFSET 0xA60UL +#define DX_HOST_KFDE0_VALID_VALUE_BIT_SHIFT 0x0UL +#define DX_HOST_KFDE0_VALID_VALUE_BIT_SIZE 0x1UL +#define DX_HOST_KFDE1_VALID_REG_OFFSET 0xA64UL +#define DX_HOST_KFDE1_VALID_VALUE_BIT_SHIFT 0x0UL +#define DX_HOST_KFDE1_VALID_VALUE_BIT_SIZE 0x1UL +#define DX_HOST_KFDE2_VALID_REG_OFFSET 0xA68UL +#define DX_HOST_KFDE2_VALID_VALUE_BIT_SHIFT 0x0UL +#define DX_HOST_KFDE2_VALID_VALUE_BIT_SIZE 0x1UL +#define DX_HOST_KFDE3_VALID_REG_OFFSET 0xA6CUL +#define DX_HOST_KFDE3_VALID_VALUE_BIT_SHIFT 0x0UL +#define DX_HOST_KFDE3_VALID_VALUE_BIT_SIZE 0x1UL +#define DX_HOST_GPR0_REG_OFFSET 0xA70UL +#define DX_HOST_GPR0_VALUE_BIT_SHIFT 0x0UL +#define DX_HOST_GPR0_VALUE_BIT_SIZE 0x20UL +#define DX_GPR_HOST_REG_OFFSET 0xA74UL +#define DX_GPR_HOST_VALUE_BIT_SHIFT 0x0UL +#define DX_GPR_HOST_VALUE_BIT_SIZE 0x20UL +#define DX_HOST_POWER_DOWN_EN_REG_OFFSET 0xA78UL +#define DX_HOST_POWER_DOWN_EN_VALUE_BIT_SHIFT 0x0UL +#define DX_HOST_POWER_DOWN_EN_VALUE_BIT_SIZE 0x1UL // -------------------------------------- // BLOCK: HOST_SRAM // -------------------------------------- -#define DX_SRAM_DATA_REG_OFFSET 0xF00UL -#define DX_SRAM_DATA_VALUE_BIT_SHIFT 0x0UL -#define DX_SRAM_DATA_VALUE_BIT_SIZE 0x20UL -#define DX_SRAM_ADDR_REG_OFFSET 0xF04UL -#define DX_SRAM_ADDR_VALUE_BIT_SHIFT 0x0UL -#define DX_SRAM_ADDR_VALUE_BIT_SIZE 0xFUL -#define DX_SRAM_DATA_READY_REG_OFFSET 0xF08UL -#define DX_SRAM_DATA_READY_VALUE_BIT_SHIFT 0x0UL -#define DX_SRAM_DATA_READY_VALUE_BIT_SIZE 0x1UL +#define DX_SRAM_DATA_REG_OFFSET 0xF00UL +#define DX_SRAM_DATA_VALUE_BIT_SHIFT 0x0UL +#define DX_SRAM_DATA_VALUE_BIT_SIZE 0x20UL +#define DX_SRAM_ADDR_REG_OFFSET 0xF04UL +#define DX_SRAM_ADDR_VALUE_BIT_SHIFT 0x0UL +#define DX_SRAM_ADDR_VALUE_BIT_SIZE 0xFUL +#define DX_SRAM_DATA_READY_REG_OFFSET 0xF08UL +#define DX_SRAM_DATA_READY_VALUE_BIT_SHIFT 0x0UL +#define DX_SRAM_DATA_READY_VALUE_BIT_SIZE 0x1UL #endif //__DX_HOST_H__ diff --git a/drivers/staging/ccree/dx_reg_base_host.h b/drivers/staging/ccree/dx_reg_base_host.h index 58dafe05fbeb..47bbadbcd1df 100644 --- a/drivers/staging/ccree/dx_reg_base_host.h +++ b/drivers/staging/ccree/dx_reg_base_host.h @@ -1,15 +1,15 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ @@ -17,16 +17,7 @@ #ifndef __DX_REG_BASE_HOST_H__ #define __DX_REG_BASE_HOST_H__ -/* Identify platform: Xilinx Zynq7000 ZC706 */ -#define DX_PLAT_ZYNQ7000 1 -#define DX_PLAT_ZYNQ7000_ZC706 1 - #define DX_BASE_CC 0x80000000 - -#define DX_BASE_ENV_REGS 0x40008000 -#define DX_BASE_ENV_CC_MEMORIES 0x40008000 -#define DX_BASE_ENV_PERF_RAM 0x40009000 - #define DX_BASE_HOST_RGF 0x0UL #define DX_BASE_CRY_KERNEL 0x0UL #define DX_BASE_ROM 0x40000000 diff --git a/drivers/staging/ccree/dx_reg_common.h b/drivers/staging/ccree/dx_reg_common.h index 4ffed386521c..d5132ffaf6e6 100644 --- a/drivers/staging/ccree/dx_reg_common.h +++ b/drivers/staging/ccree/dx_reg_common.h @@ -1,15 +1,15 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ @@ -19,7 +19,7 @@ #define DX_DEV_SIGNATURE 0xDCC71200UL -#define CC_HW_VERSION 0xef840015UL +#define CC_HW_VERSION 0xef840015UL #define DX_DEV_SHA_MAX 512 diff --git a/drivers/staging/ccree/hash_defs.h b/drivers/staging/ccree/hash_defs.h index 5ab0861fd1bb..f52656f5a3ea 100644 --- a/drivers/staging/ccree/hash_defs.h +++ b/drivers/staging/ccree/hash_defs.h @@ -1,78 +1,36 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ -#ifndef _HASH_DEFS_H__ -#define _HASH_DEFS_H__ +#ifndef _HASH_DEFS_H_ +#define _HASH_DEFS_H_ #include "cc_crypto_ctx.h" -/* this files provides definitions required for hash engine drivers */ -#ifndef CC_CONFIG_HASH_SHA_512_SUPPORTED -#define SEP_HASH_LENGTH_WORDS 2 -#else -#define SEP_HASH_LENGTH_WORDS 4 -#endif - -#ifdef BIG__ENDIAN -#define OPAD_CURRENT_LENGTH 0x40000000, 0x00000000 , 0x00000000, 0x00000000 -#define HASH_LARVAL_MD5 0x76543210, 0xFEDCBA98, 0x89ABCDEF, 0x01234567 -#define HASH_LARVAL_SHA1 0xF0E1D2C3, 0x76543210, 0xFEDCBA98, 0x89ABCDEF, 0x01234567 -#define HASH_LARVAL_SHA224 0XA44FFABE, 0XA78FF964, 0X11155868, 0X310BC0FF, 0X39590EF7, 0X17DD7030, 0X07D57C36, 0XD89E05C1 -#define HASH_LARVAL_SHA256 0X19CDE05B, 0XABD9831F, 0X8C68059B, 0X7F520E51, 0X3AF54FA5, 0X72F36E3C, 0X85AE67BB, 0X67E6096A -#define HASH_LARVAL_SHA384 0X1D48B547, 0XA44FFABE, 0X0D2E0CDB, 0XA78FF964, 0X874AB48E, 0X11155868, 0X67263367, 0X310BC0FF, 0XD8EC2F15, 0X39590EF7, 0X5A015991, 0X17DD7030, 0X2A299A62, 0X07D57C36, 0X5D9DBBCB, 0XD89E05C1 -#define HASH_LARVAL_SHA512 0X19CDE05B, 0X79217E13, 0XABD9831F, 0X6BBD41FB, 0X8C68059B, 0X1F6C3E2B, 0X7F520E51, 0XD182E6AD, 0X3AF54FA5, 0XF1361D5F, 0X72F36E3C, 0X2BF894FE, 0X85AE67BB, 0X3BA7CA84, 0X67E6096A, 0X08C9BCF3 -#else -#define OPAD_CURRENT_LENGTH 0x00000040, 0x00000000, 0x00000000, 0x00000000 -#define HASH_LARVAL_MD5 0x10325476, 0x98BADCFE, 0xEFCDAB89, 0x67452301 -#define HASH_LARVAL_SHA1 0xC3D2E1F0, 0x10325476, 0x98BADCFE, 0xEFCDAB89, 0x67452301 -#define HASH_LARVAL_SHA224 0xbefa4fa4, 0x64f98fa7, 0x68581511, 0xffc00b31, 0xf70e5939, 0x3070dd17, 0x367cd507, 0xc1059ed8 -#define HASH_LARVAL_SHA256 0x5be0cd19, 0x1f83d9ab, 0x9b05688c, 0x510e527f, 0xa54ff53a, 0x3c6ef372, 0xbb67ae85, 0x6a09e667 -#define HASH_LARVAL_SHA384 0X47B5481D, 0XBEFA4FA4, 0XDB0C2E0D, 0X64F98FA7, 0X8EB44A87, 0X68581511, 0X67332667, 0XFFC00B31, 0X152FECD8, 0XF70E5939, 0X9159015A, 0X3070DD17, 0X629A292A, 0X367CD507, 0XCBBB9D5D, 0XC1059ED8 -#define HASH_LARVAL_SHA512 0x5be0cd19, 0x137e2179, 0x1f83d9ab, 0xfb41bd6b, 0x9b05688c, 0x2b3e6c1f, 0x510e527f, 0xade682d1, 0xa54ff53a, 0x5f1d36f1, 0x3c6ef372, 0xfe94f82b, 0xbb67ae85, 0x84caa73b, 0x6a09e667, 0xf3bcc908 -#endif - -enum HashConfig1Padding { +enum cc_hash_conf_pad { HASH_PADDING_DISABLED = 0, HASH_PADDING_ENABLED = 1, HASH_DIGEST_RESULT_LITTLE_ENDIAN = 2, - HASH_CONFIG1_PADDING_RESERVE32 = INT32_MAX, + HASH_CONFIG1_PADDING_RESERVE32 = S32_MAX, }; -enum HashCipherDoPadding { +enum cc_hash_cipher_pad { DO_NOT_PAD = 0, DO_PAD = 1, - HASH_CIPHER_DO_PADDING_RESERVE32 = INT32_MAX, + HASH_CIPHER_DO_PADDING_RESERVE32 = S32_MAX, }; -typedef struct SepHashPrivateContext { - /* The current length is placed at the end of the context buffer because the hash - context is used for all HMAC operations as well. HMAC context includes a 64 bytes - K0 field. The size of struct drv_ctx_hash reserved field is 88/184 bytes depend if t - he SHA512 is supported ( in this case teh context size is 256 bytes). - The size of struct drv_ctx_hash reseved field is 20 or 52 depend if the SHA512 is supported. - This means that this structure size (without the reserved field can be up to 20 bytes , - in case sha512 is not suppported it is 20 bytes (SEP_HASH_LENGTH_WORDS define to 2 ) and in the other - case it is 28 (SEP_HASH_LENGTH_WORDS define to 4) */ - uint32_t reserved[(sizeof(struct drv_ctx_hash)/sizeof(uint32_t)) - SEP_HASH_LENGTH_WORDS - 3]; - uint32_t CurrentDigestedLength[SEP_HASH_LENGTH_WORDS]; - uint32_t KeyType; - uint32_t dataCompleted; - uint32_t hmacFinalization; - /* no space left */ -} SepHashPrivateContext_s; - -#endif /*_HASH_DEFS_H__*/ +#endif /*_HASH_DEFS_H_*/ diff --git a/drivers/staging/ccree/hw_queue_defs_plat.h b/drivers/staging/ccree/hw_queue_defs_plat.h deleted file mode 100644 index aee02cc7588a..000000000000 --- a/drivers/staging/ccree/hw_queue_defs_plat.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef __HW_QUEUE_DEFS_PLAT_H__ -#define __HW_QUEUE_DEFS_PLAT_H__ - - -/*****************************/ -/* Descriptor packing macros */ -/*****************************/ - -#define HW_QUEUE_FREE_SLOTS_GET() (CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_CONTENT)) & HW_QUEUE_SLOTS_MAX) - -#define HW_QUEUE_POLL_QUEUE_UNTIL_FREE_SLOTS(seqLen) \ - do { \ - } while (HW_QUEUE_FREE_SLOTS_GET() < (seqLen)) - -#define HW_DESC_PUSH_TO_QUEUE(pDesc) do { \ - LOG_HW_DESC(pDesc); \ - HW_DESC_DUMP(pDesc); \ - CC_HAL_WRITE_REGISTER(GET_HW_Q_DESC_WORD_IDX(0), (pDesc)->word[0]); \ - CC_HAL_WRITE_REGISTER(GET_HW_Q_DESC_WORD_IDX(1), (pDesc)->word[1]); \ - CC_HAL_WRITE_REGISTER(GET_HW_Q_DESC_WORD_IDX(2), (pDesc)->word[2]); \ - CC_HAL_WRITE_REGISTER(GET_HW_Q_DESC_WORD_IDX(3), (pDesc)->word[3]); \ - CC_HAL_WRITE_REGISTER(GET_HW_Q_DESC_WORD_IDX(4), (pDesc)->word[4]); \ - wmb(); \ - CC_HAL_WRITE_REGISTER(GET_HW_Q_DESC_WORD_IDX(5), (pDesc)->word[5]); \ -} while (0) - -#endif /*__HW_QUEUE_DEFS_PLAT_H__*/ diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c index 038291773b59..1fc0b05ea0d5 100644 --- a/drivers/staging/ccree/ssi_aead.c +++ b/drivers/staging/ccree/ssi_aead.c @@ -1,15 +1,15 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ @@ -49,9 +49,8 @@ #define AES_CCM_RFC4309_NONCE_SIZE 3 #define MAX_NONCE_SIZE CTR_RFC3686_NONCE_SIZE - /* Value of each ICV_CMP byte (of 8) in case of success */ -#define ICV_VERIF_OK 0x01 +#define ICV_VERIF_OK 0x01 struct ssi_aead_handle { ssi_sram_addr_t sram_workspace_addr; @@ -60,18 +59,18 @@ struct ssi_aead_handle { struct ssi_aead_ctx { struct ssi_drvdata *drvdata; - uint8_t ctr_nonce[MAX_NONCE_SIZE]; /* used for ctr3686 iv and aes ccm */ - uint8_t *enckey; + u8 ctr_nonce[MAX_NONCE_SIZE]; /* used for ctr3686 iv and aes ccm */ + u8 *enckey; dma_addr_t enckey_dma_addr; union { struct { - uint8_t *padded_authkey; - uint8_t *ipad_opad; /* IPAD, OPAD*/ + u8 *padded_authkey; + u8 *ipad_opad; /* IPAD, OPAD*/ dma_addr_t padded_authkey_dma_addr; dma_addr_t ipad_opad_dma_addr; } hmac; struct { - uint8_t *xcbc_keys; /* K1,K2,K3 */ + u8 *xcbc_keys; /* K1,K2,K3 */ dma_addr_t xcbc_keys_dma_addr; } xcbc; } auth_state; @@ -79,7 +78,7 @@ struct ssi_aead_ctx { unsigned int auth_keylen; unsigned int authsize; /* Actual (reduced?) size of the MAC/ICv */ enum drv_cipher_mode cipher_mode; - enum FlowMode flow_mode; + enum cc_flow_mode flow_mode; enum drv_hash_mode auth_mode; }; @@ -96,23 +95,20 @@ static void ssi_aead_exit(struct crypto_aead *tfm) SSI_LOG_DEBUG("Clearing context @%p for %s\n", crypto_aead_ctx(tfm), crypto_tfm_alg_name(&(tfm->base))); - dev = &ctx->drvdata->plat_dev->dev; + dev = &ctx->drvdata->plat_dev->dev; /* Unmap enckey buffer */ - if (ctx->enckey != NULL) { - SSI_RESTORE_DMA_ADDR_TO_48BIT(ctx->enckey_dma_addr); + if (ctx->enckey) { dma_free_coherent(dev, AES_MAX_KEY_SIZE, ctx->enckey, ctx->enckey_dma_addr); SSI_LOG_DEBUG("Freed enckey DMA buffer enckey_dma_addr=0x%llX\n", (unsigned long long)ctx->enckey_dma_addr); ctx->enckey_dma_addr = 0; ctx->enckey = NULL; } - + if (ctx->auth_mode == DRV_HASH_XCBC_MAC) { /* XCBC authetication */ - if (ctx->auth_state.xcbc.xcbc_keys != NULL) { - SSI_RESTORE_DMA_ADDR_TO_48BIT( - ctx->auth_state.xcbc.xcbc_keys_dma_addr); + if (ctx->auth_state.xcbc.xcbc_keys) { dma_free_coherent(dev, CC_AES_128_BIT_KEY_SIZE * 3, - ctx->auth_state.xcbc.xcbc_keys, + ctx->auth_state.xcbc.xcbc_keys, ctx->auth_state.xcbc.xcbc_keys_dma_addr); } SSI_LOG_DEBUG("Freed xcbc_keys DMA buffer xcbc_keys_dma_addr=0x%llX\n", @@ -120,9 +116,7 @@ static void ssi_aead_exit(struct crypto_aead *tfm) ctx->auth_state.xcbc.xcbc_keys_dma_addr = 0; ctx->auth_state.xcbc.xcbc_keys = NULL; } else if (ctx->auth_mode != DRV_HASH_NULL) { /* HMAC auth. */ - if (ctx->auth_state.hmac.ipad_opad != NULL) { - SSI_RESTORE_DMA_ADDR_TO_48BIT( - ctx->auth_state.hmac.ipad_opad_dma_addr); + if (ctx->auth_state.hmac.ipad_opad) { dma_free_coherent(dev, 2 * MAX_HMAC_DIGEST_SIZE, ctx->auth_state.hmac.ipad_opad, ctx->auth_state.hmac.ipad_opad_dma_addr); @@ -131,9 +125,7 @@ static void ssi_aead_exit(struct crypto_aead *tfm) ctx->auth_state.hmac.ipad_opad_dma_addr = 0; ctx->auth_state.hmac.ipad_opad = NULL; } - if (ctx->auth_state.hmac.padded_authkey != NULL) { - SSI_RESTORE_DMA_ADDR_TO_48BIT( - ctx->auth_state.hmac.padded_authkey_dma_addr); + if (ctx->auth_state.hmac.padded_authkey) { dma_free_coherent(dev, MAX_HMAC_BLOCK_SIZE, ctx->auth_state.hmac.padded_authkey, ctx->auth_state.hmac.padded_authkey_dma_addr); @@ -162,16 +154,15 @@ static int ssi_aead_init(struct crypto_aead *tfm) ctx->auth_mode = ssi_alg->auth_mode; ctx->drvdata = ssi_alg->drvdata; dev = &ctx->drvdata->plat_dev->dev; - crypto_aead_set_reqsize(tfm,sizeof(struct aead_req_ctx)); + crypto_aead_set_reqsize(tfm, sizeof(struct aead_req_ctx)); /* Allocate key buffer, cache line aligned */ ctx->enckey = dma_alloc_coherent(dev, AES_MAX_KEY_SIZE, &ctx->enckey_dma_addr, GFP_KERNEL); - if (ctx->enckey == NULL) { + if (!ctx->enckey) { SSI_LOG_ERR("Failed allocating key buffer\n"); goto init_failed; } - SSI_UPDATE_DMA_ADDR_TO_48BIT(ctx->enckey_dma_addr, AES_MAX_KEY_SIZE); SSI_LOG_DEBUG("Allocated enckey buffer in context ctx->enckey=@%p\n", ctx->enckey); /* Set default authlen value */ @@ -182,38 +173,29 @@ static int ssi_aead_init(struct crypto_aead *tfm) ctx->auth_state.xcbc.xcbc_keys = dma_alloc_coherent(dev, CC_AES_128_BIT_KEY_SIZE * 3, &ctx->auth_state.xcbc.xcbc_keys_dma_addr, GFP_KERNEL); - if (ctx->auth_state.xcbc.xcbc_keys == NULL) { + if (!ctx->auth_state.xcbc.xcbc_keys) { SSI_LOG_ERR("Failed allocating buffer for XCBC keys\n"); goto init_failed; } - SSI_UPDATE_DMA_ADDR_TO_48BIT( - ctx->auth_state.xcbc.xcbc_keys_dma_addr, - CC_AES_128_BIT_KEY_SIZE * 3); } else if (ctx->auth_mode != DRV_HASH_NULL) { /* HMAC authentication */ /* Allocate dma-coherent buffer for IPAD + OPAD */ ctx->auth_state.hmac.ipad_opad = dma_alloc_coherent(dev, 2 * MAX_HMAC_DIGEST_SIZE, &ctx->auth_state.hmac.ipad_opad_dma_addr, GFP_KERNEL); - if (ctx->auth_state.hmac.ipad_opad == NULL) { + if (!ctx->auth_state.hmac.ipad_opad) { SSI_LOG_ERR("Failed allocating IPAD/OPAD buffer\n"); goto init_failed; } - SSI_UPDATE_DMA_ADDR_TO_48BIT( - ctx->auth_state.hmac.ipad_opad_dma_addr, - 2 * MAX_HMAC_DIGEST_SIZE); SSI_LOG_DEBUG("Allocated authkey buffer in context ctx->authkey=@%p\n", ctx->auth_state.hmac.ipad_opad); - + ctx->auth_state.hmac.padded_authkey = dma_alloc_coherent(dev, MAX_HMAC_BLOCK_SIZE, &ctx->auth_state.hmac.padded_authkey_dma_addr, GFP_KERNEL); - if (ctx->auth_state.hmac.padded_authkey == NULL) { + if (!ctx->auth_state.hmac.padded_authkey) { SSI_LOG_ERR("failed to allocate padded_authkey\n"); goto init_failed; - } - SSI_UPDATE_DMA_ADDR_TO_48BIT( - ctx->auth_state.hmac.padded_authkey_dma_addr, - MAX_HMAC_BLOCK_SIZE); + } } else { ctx->auth_state.hmac.ipad_opad = NULL; ctx->auth_state.hmac.padded_authkey = NULL; @@ -225,7 +207,6 @@ init_failed: ssi_aead_exit(tfm); return -ENOMEM; } - static void ssi_aead_complete(struct device *dev, void *ssi_req, void __iomem *cc_base) { @@ -234,9 +215,6 @@ static void ssi_aead_complete(struct device *dev, void *ssi_req, void __iomem *c struct crypto_aead *tfm = crypto_aead_reqtfm(ssi_req); struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); int err = 0; - DECL_CYCLE_COUNT_RESOURCES; - - START_CYCLE_COUNT(); ssi_buffer_mgr_unmap_aead_request(dev, areq); @@ -250,72 +228,75 @@ static void ssi_aead_complete(struct device *dev, void *ssi_req, void __iomem *c "(auth-size=%d, cipher=%d).\n", ctx->authsize, ctx->cipher_mode); /* In case of payload authentication failure, MUST NOT - revealed the decrypted message --> zero its memory. */ + * revealed the decrypted message --> zero its memory. + */ ssi_buffer_mgr_zero_sgl(areq->dst, areq_ctx->cryptlen); err = -EBADMSG; } } else { /*ENCRYPT*/ - if (unlikely(areq_ctx->is_icv_fragmented == true)) + if (unlikely(areq_ctx->is_icv_fragmented)) ssi_buffer_mgr_copy_scatterlist_portion( - areq_ctx->mac_buf, areq_ctx->dstSgl, areq->cryptlen+areq_ctx->dstOffset, - areq->cryptlen+areq_ctx->dstOffset + ctx->authsize, SSI_SG_FROM_BUF); + areq_ctx->mac_buf, areq_ctx->dstSgl, areq->cryptlen + areq_ctx->dstOffset, + areq->cryptlen + areq_ctx->dstOffset + ctx->authsize, SSI_SG_FROM_BUF); /* If an IV was generated, copy it back to the user provided buffer. */ - if (areq_ctx->backup_giv != NULL) { - if (ctx->cipher_mode == DRV_CIPHER_CTR) { + if (areq_ctx->backup_giv) { + if (ctx->cipher_mode == DRV_CIPHER_CTR) memcpy(areq_ctx->backup_giv, areq_ctx->ctr_iv + CTR_RFC3686_NONCE_SIZE, CTR_RFC3686_IV_SIZE); - } else if (ctx->cipher_mode == DRV_CIPHER_CCM) { + else if (ctx->cipher_mode == DRV_CIPHER_CCM) memcpy(areq_ctx->backup_giv, areq_ctx->ctr_iv + CCM_BLOCK_IV_OFFSET, CCM_BLOCK_IV_SIZE); - } } } - END_CYCLE_COUNT(STAT_OP_TYPE_GENERIC, STAT_PHASE_4); aead_request_complete(areq, err); } -static int xcbc_setkey(HwDesc_s *desc, struct ssi_aead_ctx *ctx) +static int xcbc_setkey(struct cc_hw_desc *desc, struct ssi_aead_ctx *ctx) { /* Load the AES key */ - HW_DESC_INIT(&desc[0]); + hw_desc_init(&desc[0]); /* We are using for the source/user key the same buffer as for the output keys, - because after this key loading it is not needed anymore */ - HW_DESC_SET_DIN_TYPE(&desc[0], DMA_DLLI, ctx->auth_state.xcbc.xcbc_keys_dma_addr, ctx->auth_keylen, NS_BIT); - HW_DESC_SET_CIPHER_MODE(&desc[0], DRV_CIPHER_ECB); - HW_DESC_SET_CIPHER_CONFIG0(&desc[0], DRV_CRYPTO_DIRECTION_ENCRYPT); - HW_DESC_SET_KEY_SIZE_AES(&desc[0], ctx->auth_keylen); - HW_DESC_SET_FLOW_MODE(&desc[0], S_DIN_to_AES); - HW_DESC_SET_SETUP_MODE(&desc[0], SETUP_LOAD_KEY0); - - HW_DESC_INIT(&desc[1]); - HW_DESC_SET_DIN_CONST(&desc[1], 0x01010101, CC_AES_128_BIT_KEY_SIZE); - HW_DESC_SET_FLOW_MODE(&desc[1], DIN_AES_DOUT); - HW_DESC_SET_DOUT_DLLI(&desc[1], ctx->auth_state.xcbc.xcbc_keys_dma_addr, AES_KEYSIZE_128, NS_BIT, 0); - - HW_DESC_INIT(&desc[2]); - HW_DESC_SET_DIN_CONST(&desc[2], 0x02020202, CC_AES_128_BIT_KEY_SIZE); - HW_DESC_SET_FLOW_MODE(&desc[2], DIN_AES_DOUT); - HW_DESC_SET_DOUT_DLLI(&desc[2], (ctx->auth_state.xcbc.xcbc_keys_dma_addr + * because after this key loading it is not needed anymore + */ + set_din_type(&desc[0], DMA_DLLI, + ctx->auth_state.xcbc.xcbc_keys_dma_addr, ctx->auth_keylen, + NS_BIT); + set_cipher_mode(&desc[0], DRV_CIPHER_ECB); + set_cipher_config0(&desc[0], DRV_CRYPTO_DIRECTION_ENCRYPT); + set_key_size_aes(&desc[0], ctx->auth_keylen); + set_flow_mode(&desc[0], S_DIN_to_AES); + set_setup_mode(&desc[0], SETUP_LOAD_KEY0); + + hw_desc_init(&desc[1]); + set_din_const(&desc[1], 0x01010101, CC_AES_128_BIT_KEY_SIZE); + set_flow_mode(&desc[1], DIN_AES_DOUT); + set_dout_dlli(&desc[1], ctx->auth_state.xcbc.xcbc_keys_dma_addr, + AES_KEYSIZE_128, NS_BIT, 0); + + hw_desc_init(&desc[2]); + set_din_const(&desc[2], 0x02020202, CC_AES_128_BIT_KEY_SIZE); + set_flow_mode(&desc[2], DIN_AES_DOUT); + set_dout_dlli(&desc[2], (ctx->auth_state.xcbc.xcbc_keys_dma_addr + AES_KEYSIZE_128), AES_KEYSIZE_128, NS_BIT, 0); - HW_DESC_INIT(&desc[3]); - HW_DESC_SET_DIN_CONST(&desc[3], 0x03030303, CC_AES_128_BIT_KEY_SIZE); - HW_DESC_SET_FLOW_MODE(&desc[3], DIN_AES_DOUT); - HW_DESC_SET_DOUT_DLLI(&desc[3], (ctx->auth_state.xcbc.xcbc_keys_dma_addr + hw_desc_init(&desc[3]); + set_din_const(&desc[3], 0x03030303, CC_AES_128_BIT_KEY_SIZE); + set_flow_mode(&desc[3], DIN_AES_DOUT); + set_dout_dlli(&desc[3], (ctx->auth_state.xcbc.xcbc_keys_dma_addr + 2 * AES_KEYSIZE_128), AES_KEYSIZE_128, NS_BIT, 0); return 4; } -static int hmac_setkey(HwDesc_s *desc, struct ssi_aead_ctx *ctx) +static int hmac_setkey(struct cc_hw_desc *desc, struct ssi_aead_ctx *ctx) { unsigned int hmacPadConst[2] = { HMAC_IPAD_CONST, HMAC_OPAD_CONST }; unsigned int digest_ofs = 0; - unsigned int hash_mode = (ctx->auth_mode == DRV_HASH_SHA1) ? + unsigned int hash_mode = (ctx->auth_mode == DRV_HASH_SHA1) ? DRV_HASH_HW_SHA1 : DRV_HASH_HW_SHA256; - unsigned int digest_size = (ctx->auth_mode == DRV_HASH_SHA1) ? + unsigned int digest_size = (ctx->auth_mode == DRV_HASH_SHA1) ? CC_SHA1_DIGEST_SIZE : CC_SHA256_DIGEST_SIZE; int idx = 0; @@ -324,52 +305,51 @@ static int hmac_setkey(HwDesc_s *desc, struct ssi_aead_ctx *ctx) /* calc derived HMAC key */ for (i = 0; i < 2; i++) { /* Load hash initial state */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hash_mode); - HW_DESC_SET_DIN_SRAM(&desc[idx], - ssi_ahash_get_larval_digest_sram_addr( + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], hash_mode); + set_din_sram(&desc[idx], + ssi_ahash_get_larval_digest_sram_addr( ctx->drvdata, ctx->auth_mode), - digest_size); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); + digest_size); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); idx++; /* Load the hash current length*/ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hash_mode); - HW_DESC_SET_DIN_CONST(&desc[idx], 0, HASH_LEN_SIZE); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], hash_mode); + set_din_const(&desc[idx], 0, HASH_LEN_SIZE); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; /* Prepare ipad key */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_XOR_VAL(&desc[idx], hmacPadConst[i]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hash_mode); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE1); + hw_desc_init(&desc[idx]); + set_xor_val(&desc[idx], hmacPadConst[i]); + set_cipher_mode(&desc[idx], hash_mode); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE1); idx++; /* Perform HASH update */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - ctx->auth_state.hmac.padded_authkey_dma_addr, - SHA256_BLOCK_SIZE, NS_BIT); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hash_mode); - HW_DESC_SET_XOR_ACTIVE(&desc[idx]); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_HASH); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, + ctx->auth_state.hmac.padded_authkey_dma_addr, + SHA256_BLOCK_SIZE, NS_BIT); + set_cipher_mode(&desc[idx], hash_mode); + set_xor_active(&desc[idx]); + set_flow_mode(&desc[idx], DIN_HASH); idx++; /* Get the digset */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hash_mode); - HW_DESC_SET_DOUT_DLLI(&desc[idx], - (ctx->auth_state.hmac.ipad_opad_dma_addr + - digest_ofs), - digest_size, NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_DISABLED); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], hash_mode); + set_dout_dlli(&desc[idx], + (ctx->auth_state.hmac.ipad_opad_dma_addr + + digest_ofs), digest_size, NS_BIT, 0); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); + set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); idx++; digest_ofs += digest_size; @@ -420,15 +400,17 @@ static int validate_keys_sizes(struct ssi_aead_ctx *ctx) return 0; /* All tests of keys sizes passed */ } -/*This function prepers the user key so it can pass to the hmac processing - (copy to intenral buffer or hash in case of key longer than block */ + +/* This function prepers the user key so it can pass to the hmac processing + * (copy to intenral buffer or hash in case of key longer than block + */ static int ssi_get_plain_hmac_key(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) { dma_addr_t key_dma_addr = 0; struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); struct device *dev = &ctx->drvdata->plat_dev->dev; - uint32_t larval_addr = ssi_ahash_get_larval_digest_sram_addr( + u32 larval_addr = ssi_ahash_get_larval_digest_sram_addr( ctx->drvdata, ctx->auth_mode); struct ssi_crypto_req ssi_req = {}; unsigned int blocksize; @@ -436,8 +418,8 @@ ssi_get_plain_hmac_key(struct crypto_aead *tfm, const u8 *key, unsigned int keyl unsigned int hashmode; unsigned int idx = 0; int rc = 0; - HwDesc_s desc[MAX_AEAD_SETKEY_SEQ]; - dma_addr_t padded_authkey_dma_addr = + struct cc_hw_desc desc[MAX_AEAD_SETKEY_SEQ]; + dma_addr_t padded_authkey_dma_addr = ctx->auth_state.hmac.padded_authkey_dma_addr; switch (ctx->auth_mode) { /* auth_key required and >0 */ @@ -460,107 +442,89 @@ ssi_get_plain_hmac_key(struct crypto_aead *tfm, const u8 *key, unsigned int keyl " DMA failed\n", key, keylen); return -ENOMEM; } - SSI_UPDATE_DMA_ADDR_TO_48BIT(key_dma_addr, keylen); if (keylen > blocksize) { /* Load hash initial state */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hashmode); - HW_DESC_SET_DIN_SRAM(&desc[idx], larval_addr, digestsize); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], hashmode); + set_din_sram(&desc[idx], larval_addr, digestsize); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); idx++; - + /* Load the hash current length*/ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hashmode); - HW_DESC_SET_DIN_CONST(&desc[idx], 0, HASH_LEN_SIZE); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_ENABLED); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], hashmode); + set_din_const(&desc[idx], 0, HASH_LEN_SIZE); + set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; - - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - key_dma_addr, - keylen, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_HASH); + + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, + key_dma_addr, keylen, NS_BIT); + set_flow_mode(&desc[idx], DIN_HASH); idx++; - + /* Get hashed key */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hashmode); - HW_DESC_SET_DOUT_DLLI(&desc[idx], - padded_authkey_dma_addr, - digestsize, - NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], - HASH_PADDING_DISABLED); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], - HASH_DIGEST_RESULT_LITTLE_ENDIAN); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], hashmode); + set_dout_dlli(&desc[idx], padded_authkey_dma_addr, + digestsize, NS_BIT, 0); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); + set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); + set_cipher_config0(&desc[idx], + HASH_DIGEST_RESULT_LITTLE_ENDIAN); idx++; - - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_CONST(&desc[idx], 0, (blocksize - digestsize)); - HW_DESC_SET_FLOW_MODE(&desc[idx], BYPASS); - HW_DESC_SET_DOUT_DLLI(&desc[idx], - (padded_authkey_dma_addr + digestsize), - (blocksize - digestsize), - NS_BIT, 0); + + hw_desc_init(&desc[idx]); + set_din_const(&desc[idx], 0, (blocksize - digestsize)); + set_flow_mode(&desc[idx], BYPASS); + set_dout_dlli(&desc[idx], (padded_authkey_dma_addr + + digestsize), (blocksize - digestsize), + NS_BIT, 0); idx++; } else { - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - key_dma_addr, - keylen, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], BYPASS); - HW_DESC_SET_DOUT_DLLI(&desc[idx], - (padded_authkey_dma_addr), - keylen, NS_BIT, 0); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, key_dma_addr, + keylen, NS_BIT); + set_flow_mode(&desc[idx], BYPASS); + set_dout_dlli(&desc[idx], padded_authkey_dma_addr, + keylen, NS_BIT, 0); idx++; - + if ((blocksize - keylen) != 0) { - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_CONST(&desc[idx], 0, - (blocksize - keylen)); - HW_DESC_SET_FLOW_MODE(&desc[idx], BYPASS); - HW_DESC_SET_DOUT_DLLI(&desc[idx], - (padded_authkey_dma_addr + keylen), - (blocksize - keylen), - NS_BIT, 0); + hw_desc_init(&desc[idx]); + set_din_const(&desc[idx], 0, + (blocksize - keylen)); + set_flow_mode(&desc[idx], BYPASS); + set_dout_dlli(&desc[idx], + (padded_authkey_dma_addr + + keylen), + (blocksize - keylen), NS_BIT, 0); idx++; } } } else { - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_CONST(&desc[idx], 0, - (blocksize - keylen)); - HW_DESC_SET_FLOW_MODE(&desc[idx], BYPASS); - HW_DESC_SET_DOUT_DLLI(&desc[idx], - padded_authkey_dma_addr, - blocksize, - NS_BIT, 0); + hw_desc_init(&desc[idx]); + set_din_const(&desc[idx], 0, (blocksize - keylen)); + set_flow_mode(&desc[idx], BYPASS); + set_dout_dlli(&desc[idx], padded_authkey_dma_addr, + blocksize, NS_BIT, 0); idx++; } -#ifdef ENABLE_CYCLE_COUNT - ssi_req.op_type = STAT_OP_TYPE_SETKEY; -#endif - rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0); if (unlikely(rc != 0)) SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc); - if (likely(key_dma_addr != 0)) { - SSI_RESTORE_DMA_ADDR_TO_48BIT(key_dma_addr); + if (likely(key_dma_addr != 0)) dma_unmap_single(dev, key_dma_addr, keylen, DMA_TO_DEVICE); - } return rc; } - static int ssi_aead_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) { @@ -568,16 +532,14 @@ ssi_aead_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) struct rtattr *rta = (struct rtattr *)key; struct ssi_crypto_req ssi_req = {}; struct crypto_authenc_key_param *param; - HwDesc_s desc[MAX_AEAD_SETKEY_SEQ]; + struct cc_hw_desc desc[MAX_AEAD_SETKEY_SEQ]; int seq_len = 0, rc = -EINVAL; - DECL_CYCLE_COUNT_RESOURCES; SSI_LOG_DEBUG("Setting key in context @%p for %s. key=%p keylen=%u\n", ctx, crypto_tfm_alg_name(crypto_aead_tfm(tfm)), key, keylen); CHECK_AND_RETURN_UPON_FIPS_ERROR(); /* STAT_PHASE_0: Init and sanity checks */ - START_CYCLE_COUNT(); if (ctx->auth_mode != DRV_HASH_NULL) { /* authenc() alg. */ if (!RTA_OK(rta, keylen)) @@ -600,7 +562,8 @@ ssi_aead_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) (AES_MIN_KEY_SIZE + CTR_RFC3686_NONCE_SIZE)) goto badkey; /* Copy nonce from last 4 bytes in CTR key to - * first 4 bytes in CTR IV */ + * first 4 bytes in CTR IV + */ memcpy(ctx->ctr_nonce, key + ctx->auth_keylen + ctx->enc_keylen - CTR_RFC3686_NONCE_SIZE, CTR_RFC3686_NONCE_SIZE); /* Set CTR key size */ @@ -615,9 +578,7 @@ ssi_aead_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) if (unlikely(rc != 0)) goto badkey; - END_CYCLE_COUNT(STAT_OP_TYPE_SETKEY, STAT_PHASE_0); /* STAT_PHASE_1: Copy key to ctx */ - START_CYCLE_COUNT(); /* Get key material */ memcpy(ctx->enckey, key + ctx->auth_keylen, ctx->enc_keylen); @@ -631,10 +592,7 @@ ssi_aead_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) goto badkey; } - END_CYCLE_COUNT(STAT_OP_TYPE_SETKEY, STAT_PHASE_1); - /* STAT_PHASE_2: Create sequence */ - START_CYCLE_COUNT(); switch (ctx->auth_mode) { case DRV_HASH_SHA1: @@ -652,15 +610,9 @@ ssi_aead_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) goto badkey; } - END_CYCLE_COUNT(STAT_OP_TYPE_SETKEY, STAT_PHASE_2); - /* STAT_PHASE_3: Submit sequence to HW */ - START_CYCLE_COUNT(); - + if (seq_len > 0) { /* For CCM there is no sequence to setup the key */ -#ifdef ENABLE_CYCLE_COUNT - ssi_req.op_type = STAT_OP_TYPE_SETKEY; -#endif rc = send_request(ctx->drvdata, &ssi_req, desc, seq_len, 0); if (unlikely(rc != 0)) { SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc); @@ -669,7 +621,6 @@ ssi_aead_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen) } /* Update STAT_PHASE_3 */ - END_CYCLE_COUNT(STAT_OP_TYPE_SETKEY, STAT_PHASE_3); return rc; badkey: @@ -684,7 +635,7 @@ static int ssi_rfc4309_ccm_setkey(struct crypto_aead *tfm, const u8 *key, unsign { struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); int rc = 0; - + if (keylen < 3) return -EINVAL; @@ -702,11 +653,11 @@ static int ssi_aead_setauthsize( unsigned int authsize) { struct ssi_aead_ctx *ctx = crypto_aead_ctx(authenc); - + CHECK_AND_RETURN_UPON_FIPS_ERROR(); /* Unsupported auth. sizes */ if ((authsize == 0) || - (authsize >crypto_aead_maxauthsize(authenc))) { + (authsize > crypto_aead_maxauthsize(authenc))) { return -ENOTSUPP; } @@ -752,11 +703,11 @@ static int ssi_ccm_setauthsize(struct crypto_aead *authenc, } #endif /*SSI_CC_HAS_AES_CCM*/ -static inline void +static inline void ssi_aead_create_assoc_desc( - struct aead_request *areq, + struct aead_request *areq, unsigned int flow_mode, - HwDesc_s desc[], + struct cc_hw_desc desc[], unsigned int *seq_size) { struct crypto_aead *tfm = crypto_aead_reqtfm(areq); @@ -768,24 +719,23 @@ ssi_aead_create_assoc_desc( switch (assoc_dma_type) { case SSI_DMA_BUF_DLLI: SSI_LOG_DEBUG("ASSOC buffer type DLLI\n"); - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - sg_dma_address(areq->src), - areq->assoclen, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], flow_mode); - if (ctx->auth_mode == DRV_HASH_XCBC_MAC && (areq_ctx->cryptlen > 0) ) - HW_DESC_SET_DIN_NOT_LAST_INDICATION(&desc[idx]); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, sg_dma_address(areq->src), + areq->assoclen, NS_BIT); set_flow_mode(&desc[idx], + flow_mode); + if ((ctx->auth_mode == DRV_HASH_XCBC_MAC) && + (areq_ctx->cryptlen > 0)) + set_din_not_last_indication(&desc[idx]); break; case SSI_DMA_BUF_MLLI: SSI_LOG_DEBUG("ASSOC buffer type MLLI\n"); - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_MLLI, - areq_ctx->assoc.sram_addr, - areq_ctx->assoc.mlli_nents, - NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], flow_mode); - if (ctx->auth_mode == DRV_HASH_XCBC_MAC && (areq_ctx->cryptlen > 0) ) - HW_DESC_SET_DIN_NOT_LAST_INDICATION(&desc[idx]); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_MLLI, areq_ctx->assoc.sram_addr, + areq_ctx->assoc.mlli_nents, NS_BIT); + set_flow_mode(&desc[idx], flow_mode); + if ((ctx->auth_mode == DRV_HASH_XCBC_MAC) && + (areq_ctx->cryptlen > 0)) + set_din_not_last_indication(&desc[idx]); break; case SSI_DMA_BUF_NULL: default: @@ -797,9 +747,9 @@ ssi_aead_create_assoc_desc( static inline void ssi_aead_process_authenc_data_desc( - struct aead_request *areq, + struct aead_request *areq, unsigned int flow_mode, - HwDesc_s desc[], + struct cc_hw_desc desc[], unsigned int *seq_size, int direct) { @@ -814,27 +764,28 @@ ssi_aead_process_authenc_data_desc( (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ? areq_ctx->dstSgl : areq_ctx->srcSgl; - unsigned int offset = + unsigned int offset = (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ? areq_ctx->dstOffset : areq_ctx->srcOffset; SSI_LOG_DEBUG("AUTHENC: SRC/DST buffer type DLLI\n"); - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - (sg_dma_address(cipher)+ offset), areq_ctx->cryptlen, - NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], flow_mode); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, + (sg_dma_address(cipher) + offset), + areq_ctx->cryptlen, NS_BIT); + set_flow_mode(&desc[idx], flow_mode); break; } case SSI_DMA_BUF_MLLI: { /* DOUBLE-PASS flow (as default) * assoc. + iv + data -compact in one table - * if assoclen is ZERO only IV perform */ + * if assoclen is ZERO only IV perform + */ ssi_sram_addr_t mlli_addr = areq_ctx->assoc.sram_addr; - uint32_t mlli_nents = areq_ctx->assoc.mlli_nents; + u32 mlli_nents = areq_ctx->assoc.mlli_nents; - if (likely(areq_ctx->is_single_pass == true)) { - if (direct == DRV_CRYPTO_DIRECTION_ENCRYPT){ + if (likely(areq_ctx->is_single_pass)) { + if (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) { mlli_addr = areq_ctx->dst.sram_addr; mlli_nents = areq_ctx->dst.mlli_nents; } else { @@ -844,10 +795,10 @@ ssi_aead_process_authenc_data_desc( } SSI_LOG_DEBUG("AUTHENC: SRC/DST buffer type MLLI\n"); - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_MLLI, - mlli_addr, mlli_nents, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], flow_mode); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_MLLI, mlli_addr, mlli_nents, + NS_BIT); + set_flow_mode(&desc[idx], flow_mode); break; } case SSI_DMA_BUF_NULL: @@ -860,9 +811,9 @@ ssi_aead_process_authenc_data_desc( static inline void ssi_aead_process_cipher_data_desc( - struct aead_request *areq, + struct aead_request *areq, unsigned int flow_mode, - HwDesc_s desc[], + struct cc_hw_desc desc[], unsigned int *seq_size) { unsigned int idx = *seq_size; @@ -875,25 +826,24 @@ ssi_aead_process_cipher_data_desc( switch (data_dma_type) { case SSI_DMA_BUF_DLLI: SSI_LOG_DEBUG("CIPHER: SRC/DST buffer type DLLI\n"); - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - (sg_dma_address(areq_ctx->srcSgl)+areq_ctx->srcOffset), - areq_ctx->cryptlen, NS_BIT); - HW_DESC_SET_DOUT_DLLI(&desc[idx], - (sg_dma_address(areq_ctx->dstSgl)+areq_ctx->dstOffset), - areq_ctx->cryptlen, NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&desc[idx], flow_mode); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, + (sg_dma_address(areq_ctx->srcSgl) + + areq_ctx->srcOffset), areq_ctx->cryptlen, NS_BIT); + set_dout_dlli(&desc[idx], + (sg_dma_address(areq_ctx->dstSgl) + + areq_ctx->dstOffset), + areq_ctx->cryptlen, NS_BIT, 0); + set_flow_mode(&desc[idx], flow_mode); break; case SSI_DMA_BUF_MLLI: SSI_LOG_DEBUG("CIPHER: SRC/DST buffer type MLLI\n"); - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_MLLI, - areq_ctx->src.sram_addr, - areq_ctx->src.mlli_nents, NS_BIT); - HW_DESC_SET_DOUT_MLLI(&desc[idx], - areq_ctx->dst.sram_addr, - areq_ctx->dst.mlli_nents, NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&desc[idx], flow_mode); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_MLLI, areq_ctx->src.sram_addr, + areq_ctx->src.mlli_nents, NS_BIT); + set_dout_mlli(&desc[idx], areq_ctx->dst.sram_addr, + areq_ctx->dst.mlli_nents, NS_BIT, 0); + set_flow_mode(&desc[idx], flow_mode); break; case SSI_DMA_BUF_NULL: default: @@ -905,7 +855,7 @@ ssi_aead_process_cipher_data_desc( static inline void ssi_aead_process_digest_result_desc( struct aead_request *req, - HwDesc_s desc[], + struct cc_hw_desc desc[], unsigned int *seq_size) { struct crypto_aead *tfm = crypto_aead_reqtfm(req); @@ -918,35 +868,36 @@ static inline void ssi_aead_process_digest_result_desc( /* Get final ICV result */ if (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) { - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); - HW_DESC_SET_DOUT_DLLI(&desc[idx], req_ctx->icv_dma_addr, - ctx->authsize, NS_BIT, 1); - HW_DESC_SET_QUEUE_LAST_IND(&desc[idx]); + hw_desc_init(&desc[idx]); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); + set_dout_dlli(&desc[idx], req_ctx->icv_dma_addr, ctx->authsize, + NS_BIT, 1); + set_queue_last_ind(&desc[idx]); if (ctx->auth_mode == DRV_HASH_XCBC_MAC) { - HW_DESC_SET_AES_NOT_HASH_MODE(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_XCBC_MAC); + set_aes_not_hash_mode(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC); } else { - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], - HASH_DIGEST_RESULT_LITTLE_ENDIAN); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hash_mode); + set_cipher_config0(&desc[idx], + HASH_DIGEST_RESULT_LITTLE_ENDIAN); + set_cipher_mode(&desc[idx], hash_mode); } } else { /*Decrypt*/ /* Get ICV out from hardware */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_DOUT_DLLI(&desc[idx], req_ctx->mac_buf_dma_addr, - ctx->authsize, NS_BIT, 1); - HW_DESC_SET_QUEUE_LAST_IND(&desc[idx]); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], HASH_DIGEST_RESULT_LITTLE_ENDIAN); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_DISABLED); + hw_desc_init(&desc[idx]); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_dout_dlli(&desc[idx], req_ctx->mac_buf_dma_addr, + ctx->authsize, NS_BIT, 1); + set_queue_last_ind(&desc[idx]); + set_cipher_config0(&desc[idx], + HASH_DIGEST_RESULT_LITTLE_ENDIAN); + set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); if (ctx->auth_mode == DRV_HASH_XCBC_MAC) { - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_XCBC_MAC); - HW_DESC_SET_AES_NOT_HASH_MODE(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC); + set_aes_not_hash_mode(&desc[idx]); } else { - HW_DESC_SET_CIPHER_MODE(&desc[idx], hash_mode); + set_cipher_mode(&desc[idx], hash_mode); } } @@ -955,7 +906,7 @@ static inline void ssi_aead_process_digest_result_desc( static inline void ssi_aead_setup_cipher_desc( struct aead_request *req, - HwDesc_s desc[], + struct cc_hw_desc desc[], unsigned int *seq_size) { struct crypto_aead *tfm = crypto_aead_reqtfm(req); @@ -966,35 +917,34 @@ static inline void ssi_aead_setup_cipher_desc( int direct = req_ctx->gen_ctx.op_type; /* Setup cipher state */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], direct); - HW_DESC_SET_FLOW_MODE(&desc[idx], ctx->flow_mode); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - req_ctx->gen_ctx.iv_dma_addr, hw_iv_size, NS_BIT); - if (ctx->cipher_mode == DRV_CIPHER_CTR) { - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE1); - } else { - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); - } - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->cipher_mode); + hw_desc_init(&desc[idx]); + set_cipher_config0(&desc[idx], direct); + set_flow_mode(&desc[idx], ctx->flow_mode); + set_din_type(&desc[idx], DMA_DLLI, req_ctx->gen_ctx.iv_dma_addr, + hw_iv_size, NS_BIT); + if (ctx->cipher_mode == DRV_CIPHER_CTR) + set_setup_mode(&desc[idx], SETUP_LOAD_STATE1); + else + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); + set_cipher_mode(&desc[idx], ctx->cipher_mode); idx++; /* Setup enc. key */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], direct); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); - HW_DESC_SET_FLOW_MODE(&desc[idx], ctx->flow_mode); + hw_desc_init(&desc[idx]); + set_cipher_config0(&desc[idx], direct); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); + set_flow_mode(&desc[idx], ctx->flow_mode); if (ctx->flow_mode == S_DIN_to_AES) { - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, ctx->enckey_dma_addr, - ((ctx->enc_keylen == 24) ? - CC_AES_KEY_SIZE_MAX : ctx->enc_keylen), NS_BIT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], ctx->enc_keylen); + set_din_type(&desc[idx], DMA_DLLI, ctx->enckey_dma_addr, + ((ctx->enc_keylen == 24) ? CC_AES_KEY_SIZE_MAX : + ctx->enc_keylen), NS_BIT); + set_key_size_aes(&desc[idx], ctx->enc_keylen); } else { - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, ctx->enckey_dma_addr, - ctx->enc_keylen, NS_BIT); - HW_DESC_SET_KEY_SIZE_DES(&desc[idx], ctx->enc_keylen); + set_din_type(&desc[idx], DMA_DLLI, ctx->enckey_dma_addr, + ctx->enc_keylen, NS_BIT); + set_key_size_des(&desc[idx], ctx->enc_keylen); } - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->cipher_mode); + set_cipher_mode(&desc[idx], ctx->cipher_mode); idx++; *seq_size = idx; @@ -1002,7 +952,7 @@ static inline void ssi_aead_setup_cipher_desc( static inline void ssi_aead_process_cipher( struct aead_request *req, - HwDesc_s desc[], + struct cc_hw_desc desc[], unsigned int *seq_size, unsigned int data_flow_mode) { @@ -1017,9 +967,9 @@ static inline void ssi_aead_process_cipher( ssi_aead_process_cipher_data_desc(req, data_flow_mode, desc, &idx); if (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) { /* We must wait for DMA to write all cipher */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_NO_DMA(&desc[idx], 0, 0xfffff0); - HW_DESC_SET_DOUT_NO_DMA(&desc[idx], 0, 0, 1); + hw_desc_init(&desc[idx]); + set_din_no_dma(&desc[idx], 0, 0xfffff0); + set_dout_no_dma(&desc[idx], 0, 0, 1); idx++; } @@ -1028,35 +978,36 @@ static inline void ssi_aead_process_cipher( static inline void ssi_aead_hmac_setup_digest_desc( struct aead_request *req, - HwDesc_s desc[], + struct cc_hw_desc desc[], unsigned int *seq_size) { struct crypto_aead *tfm = crypto_aead_reqtfm(req); struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); unsigned int hash_mode = (ctx->auth_mode == DRV_HASH_SHA1) ? DRV_HASH_HW_SHA1 : DRV_HASH_HW_SHA256; - unsigned int digest_size = (ctx->auth_mode == DRV_HASH_SHA1) ? + unsigned int digest_size = (ctx->auth_mode == DRV_HASH_SHA1) ? CC_SHA1_DIGEST_SIZE : CC_SHA256_DIGEST_SIZE; unsigned int idx = *seq_size; /* Loading hash ipad xor key state */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hash_mode); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - ctx->auth_state.hmac.ipad_opad_dma_addr, - digest_size, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], hash_mode); + set_din_type(&desc[idx], DMA_DLLI, + ctx->auth_state.hmac.ipad_opad_dma_addr, digest_size, + NS_BIT); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); idx++; /* Load init. digest len (64 bytes) */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hash_mode); - HW_DESC_SET_DIN_SRAM(&desc[idx], - ssi_ahash_get_initial_digest_len_sram_addr(ctx->drvdata, hash_mode), - HASH_LEN_SIZE); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], hash_mode); + set_din_sram(&desc[idx], + ssi_ahash_get_initial_digest_len_sram_addr(ctx->drvdata, + hash_mode), + HASH_LEN_SIZE); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; *seq_size = idx; @@ -1064,7 +1015,7 @@ static inline void ssi_aead_hmac_setup_digest_desc( static inline void ssi_aead_xcbc_setup_digest_desc( struct aead_request *req, - HwDesc_s desc[], + struct cc_hw_desc desc[], unsigned int *seq_size) { struct crypto_aead *tfm = crypto_aead_reqtfm(req); @@ -1072,55 +1023,53 @@ static inline void ssi_aead_xcbc_setup_digest_desc( unsigned int idx = *seq_size; /* Loading MAC state */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_CONST(&desc[idx], 0, CC_AES_BLOCK_SIZE); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_XCBC_MAC); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], CC_AES_128_BIT_KEY_SIZE); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_AES_NOT_HASH_MODE(&desc[idx]); + hw_desc_init(&desc[idx]); + set_din_const(&desc[idx], 0, CC_AES_BLOCK_SIZE); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); + set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC); + set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_aes_not_hash_mode(&desc[idx]); idx++; /* Setup XCBC MAC K1 */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - ctx->auth_state.xcbc.xcbc_keys_dma_addr, - AES_KEYSIZE_128, NS_BIT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_XCBC_MAC); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], CC_AES_128_BIT_KEY_SIZE); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_AES_NOT_HASH_MODE(&desc[idx]); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, + ctx->auth_state.xcbc.xcbc_keys_dma_addr, + AES_KEYSIZE_128, NS_BIT); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); + set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC); + set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_aes_not_hash_mode(&desc[idx]); idx++; /* Setup XCBC MAC K2 */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - (ctx->auth_state.xcbc.xcbc_keys_dma_addr + - AES_KEYSIZE_128), - AES_KEYSIZE_128, NS_BIT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE1); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_XCBC_MAC); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], CC_AES_128_BIT_KEY_SIZE); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_AES_NOT_HASH_MODE(&desc[idx]); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, + (ctx->auth_state.xcbc.xcbc_keys_dma_addr + + AES_KEYSIZE_128), AES_KEYSIZE_128, NS_BIT); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE1); + set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC); + set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_aes_not_hash_mode(&desc[idx]); idx++; /* Setup XCBC MAC K3 */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - (ctx->auth_state.xcbc.xcbc_keys_dma_addr + - 2 * AES_KEYSIZE_128), - AES_KEYSIZE_128, NS_BIT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE2); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_XCBC_MAC); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], CC_AES_128_BIT_KEY_SIZE); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_AES_NOT_HASH_MODE(&desc[idx]); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, + (ctx->auth_state.xcbc.xcbc_keys_dma_addr + + 2 * AES_KEYSIZE_128), AES_KEYSIZE_128, NS_BIT); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE2); + set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC); + set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_aes_not_hash_mode(&desc[idx]); idx++; *seq_size = idx; @@ -1128,7 +1077,7 @@ static inline void ssi_aead_xcbc_setup_digest_desc( static inline void ssi_aead_process_digest_header_desc( struct aead_request *req, - HwDesc_s desc[], + struct cc_hw_desc desc[], unsigned int *seq_size) { unsigned int idx = *seq_size; @@ -1142,7 +1091,7 @@ static inline void ssi_aead_process_digest_header_desc( static inline void ssi_aead_process_digest_scheme_desc( struct aead_request *req, - HwDesc_s desc[], + struct cc_hw_desc desc[], unsigned int *seq_size) { struct crypto_aead *tfm = crypto_aead_reqtfm(req); @@ -1150,55 +1099,56 @@ static inline void ssi_aead_process_digest_scheme_desc( struct ssi_aead_handle *aead_handle = ctx->drvdata->aead_handle; unsigned int hash_mode = (ctx->auth_mode == DRV_HASH_SHA1) ? DRV_HASH_HW_SHA1 : DRV_HASH_HW_SHA256; - unsigned int digest_size = (ctx->auth_mode == DRV_HASH_SHA1) ? + unsigned int digest_size = (ctx->auth_mode == DRV_HASH_SHA1) ? CC_SHA1_DIGEST_SIZE : CC_SHA256_DIGEST_SIZE; unsigned int idx = *seq_size; - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hash_mode); - HW_DESC_SET_DOUT_SRAM(&desc[idx], aead_handle->sram_workspace_addr, - HASH_LEN_SIZE); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE1); - HW_DESC_SET_CIPHER_DO(&desc[idx], DO_PAD); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], hash_mode); + set_dout_sram(&desc[idx], aead_handle->sram_workspace_addr, + HASH_LEN_SIZE); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE1); + set_cipher_do(&desc[idx], DO_PAD); idx++; /* Get final ICV result */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DOUT_SRAM(&desc[idx], aead_handle->sram_workspace_addr, - digest_size); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], HASH_DIGEST_RESULT_LITTLE_ENDIAN); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hash_mode); + hw_desc_init(&desc[idx]); + set_dout_sram(&desc[idx], aead_handle->sram_workspace_addr, + digest_size); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); + set_cipher_config0(&desc[idx], HASH_DIGEST_RESULT_LITTLE_ENDIAN); + set_cipher_mode(&desc[idx], hash_mode); idx++; /* Loading hash opad xor key state */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hash_mode); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - (ctx->auth_state.hmac.ipad_opad_dma_addr + digest_size), - digest_size, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], hash_mode); + set_din_type(&desc[idx], DMA_DLLI, + (ctx->auth_state.hmac.ipad_opad_dma_addr + digest_size), + digest_size, NS_BIT); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); idx++; /* Load init. digest len (64 bytes) */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hash_mode); - HW_DESC_SET_DIN_SRAM(&desc[idx], - ssi_ahash_get_initial_digest_len_sram_addr(ctx->drvdata, hash_mode), - HASH_LEN_SIZE); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_ENABLED); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], hash_mode); + set_din_sram(&desc[idx], + ssi_ahash_get_initial_digest_len_sram_addr(ctx->drvdata, + hash_mode), + HASH_LEN_SIZE); + set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; /* Perform HASH update */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_SRAM(&desc[idx], aead_handle->sram_workspace_addr, - digest_size); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_HASH); + hw_desc_init(&desc[idx]); + set_din_sram(&desc[idx], aead_handle->sram_workspace_addr, + digest_size); + set_flow_mode(&desc[idx], DIN_HASH); idx++; *seq_size = idx; @@ -1206,7 +1156,7 @@ static inline void ssi_aead_process_digest_scheme_desc( static inline void ssi_aead_load_mlli_to_sram( struct aead_request *req, - HwDesc_s desc[], + struct cc_hw_desc desc[], unsigned int *seq_size) { struct aead_req_ctx *req_ctx = aead_request_ctx(req); @@ -1216,29 +1166,29 @@ static inline void ssi_aead_load_mlli_to_sram( if (unlikely( (req_ctx->assoc_buff_type == SSI_DMA_BUF_MLLI) || (req_ctx->data_buff_type == SSI_DMA_BUF_MLLI) || - (req_ctx->is_single_pass == false))) { + !req_ctx->is_single_pass)) { SSI_LOG_DEBUG("Copy-to-sram: mlli_dma=%08x, mlli_size=%u\n", (unsigned int)ctx->drvdata->mlli_sram_addr, req_ctx->mlli_params.mlli_len); /* Copy MLLI table host-to-sram */ - HW_DESC_INIT(&desc[*seq_size]); - HW_DESC_SET_DIN_TYPE(&desc[*seq_size], DMA_DLLI, - req_ctx->mlli_params.mlli_dma_addr, - req_ctx->mlli_params.mlli_len, NS_BIT); - HW_DESC_SET_DOUT_SRAM(&desc[*seq_size], - ctx->drvdata->mlli_sram_addr, - req_ctx->mlli_params.mlli_len); - HW_DESC_SET_FLOW_MODE(&desc[*seq_size], BYPASS); + hw_desc_init(&desc[*seq_size]); + set_din_type(&desc[*seq_size], DMA_DLLI, + req_ctx->mlli_params.mlli_dma_addr, + req_ctx->mlli_params.mlli_len, NS_BIT); + set_dout_sram(&desc[*seq_size], + ctx->drvdata->mlli_sram_addr, + req_ctx->mlli_params.mlli_len); + set_flow_mode(&desc[*seq_size], BYPASS); (*seq_size)++; } } -static inline enum FlowMode ssi_aead_get_data_flow_mode( +static inline enum cc_flow_mode ssi_aead_get_data_flow_mode( enum drv_crypto_direction direct, - enum FlowMode setup_flow_mode, + enum cc_flow_mode setup_flow_mode, bool is_single_pass) { - enum FlowMode data_flow_mode; + enum cc_flow_mode data_flow_mode; if (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) { if (setup_flow_mode == S_DIN_to_AES) @@ -1261,7 +1211,7 @@ static inline enum FlowMode ssi_aead_get_data_flow_mode( static inline void ssi_aead_hmac_authenc( struct aead_request *req, - HwDesc_s desc[], + struct cc_hw_desc desc[], unsigned int *seq_size) { struct crypto_aead *tfm = crypto_aead_reqtfm(req); @@ -1271,7 +1221,7 @@ static inline void ssi_aead_hmac_authenc( unsigned int data_flow_mode = ssi_aead_get_data_flow_mode( direct, ctx->flow_mode, req_ctx->is_single_pass); - if (req_ctx->is_single_pass == true) { + if (req_ctx->is_single_pass) { /** * Single-pass flow */ @@ -1284,10 +1234,11 @@ static inline void ssi_aead_hmac_authenc( return; } - /** + /** * Double-pass flow - * Fallback for unsupported single-pass modes, - * i.e. using assoc. data of non-word-multiple */ + * Fallback for unsupported single-pass modes, + * i.e. using assoc. data of non-word-multiple + */ if (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) { /* encrypt first.. */ ssi_aead_process_cipher(req, desc, seq_size, data_flow_mode); @@ -1305,7 +1256,8 @@ static inline void ssi_aead_hmac_authenc( /* decrypt after.. */ ssi_aead_process_cipher(req, desc, seq_size, data_flow_mode); /* read the digest result with setting the completion bit - must be after the cipher operation */ + * must be after the cipher operation + */ ssi_aead_process_digest_result_desc(req, desc, seq_size); } } @@ -1313,7 +1265,7 @@ static inline void ssi_aead_hmac_authenc( static inline void ssi_aead_xcbc_authenc( struct aead_request *req, - HwDesc_s desc[], + struct cc_hw_desc desc[], unsigned int *seq_size) { struct crypto_aead *tfm = crypto_aead_reqtfm(req); @@ -1323,7 +1275,7 @@ ssi_aead_xcbc_authenc( unsigned int data_flow_mode = ssi_aead_get_data_flow_mode( direct, ctx->flow_mode, req_ctx->is_single_pass); - if (req_ctx->is_single_pass == true) { + if (req_ctx->is_single_pass) { /** * Single-pass flow */ @@ -1335,10 +1287,11 @@ ssi_aead_xcbc_authenc( return; } - /** + /** * Double-pass flow - * Fallback for unsupported single-pass modes, - * i.e. using assoc. data of non-word-multiple */ + * Fallback for unsupported single-pass modes, + * i.e. using assoc. data of non-word-multiple + */ if (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) { /* encrypt first.. */ ssi_aead_process_cipher(req, desc, seq_size, data_flow_mode); @@ -1353,7 +1306,8 @@ ssi_aead_xcbc_authenc( /* decrypt after..*/ ssi_aead_process_cipher(req, desc, seq_size, data_flow_mode); /* read the digest result with setting the completion bit - must be after the cipher operation */ + * must be after the cipher operation + */ ssi_aead_process_digest_result_desc(req, desc, seq_size); } } @@ -1379,18 +1333,17 @@ static int validate_data_size(struct ssi_aead_ctx *ctx, goto data_size_err; if (ctx->cipher_mode == DRV_CIPHER_CCM) break; - if (ctx->cipher_mode == DRV_CIPHER_GCTR) - { - if (areq_ctx->plaintext_authenticate_only == true) - areq_ctx->is_single_pass = false; + if (ctx->cipher_mode == DRV_CIPHER_GCTR) { + if (areq_ctx->plaintext_authenticate_only) + areq_ctx->is_single_pass = false; break; } - if (!IS_ALIGNED(assoclen, sizeof(uint32_t))) + if (!IS_ALIGNED(assoclen, sizeof(u32))) areq_ctx->is_single_pass = false; if ((ctx->cipher_mode == DRV_CIPHER_CTR) && - !IS_ALIGNED(cipherlen, sizeof(uint32_t))) + !IS_ALIGNED(cipherlen, sizeof(u32))) areq_ctx->is_single_pass = false; break; @@ -1412,13 +1365,14 @@ data_size_err: } #if SSI_CC_HAS_AES_CCM -static unsigned int format_ccm_a0(uint8_t *pA0Buff, uint32_t headerSize) +static unsigned int format_ccm_a0(u8 *pA0Buff, u32 headerSize) { unsigned int len = 0; - if ( headerSize == 0 ) { + + if (headerSize == 0) return 0; - } - if ( headerSize < ((1UL << 16) - (1UL << 8) )) { + + if (headerSize < ((1UL << 16) - (1UL << 8))) { len = 2; pA0Buff[0] = (headerSize >> 8) & 0xFF; @@ -1457,7 +1411,7 @@ static int set_msg_len(u8 *block, unsigned int msglen, unsigned int csize) static inline int ssi_aead_ccm( struct aead_request *req, - HwDesc_s desc[], + struct cc_hw_desc desc[], unsigned int *seq_size) { struct crypto_aead *tfm = crypto_aead_reqtfm(req); @@ -1467,7 +1421,6 @@ static inline int ssi_aead_ccm( unsigned int cipher_flow_mode; dma_addr_t mac_result; - if (req_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) { cipher_flow_mode = AES_to_HASH_and_DOUT; mac_result = req_ctx->mac_buf_dma_addr; @@ -1477,118 +1430,111 @@ static inline int ssi_aead_ccm( } /* load key */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_CTR); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, ctx->enckey_dma_addr, - ((ctx->enc_keylen == 24) ? - CC_AES_KEY_SIZE_MAX : ctx->enc_keylen), - NS_BIT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], ctx->enc_keylen); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_CTR); + set_din_type(&desc[idx], DMA_DLLI, ctx->enckey_dma_addr, + ((ctx->enc_keylen == 24) ? CC_AES_KEY_SIZE_MAX : + ctx->enc_keylen), NS_BIT); + set_key_size_aes(&desc[idx], ctx->enc_keylen); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); + set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; /* load ctr state */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_CTR); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], ctx->enc_keylen); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - req_ctx->gen_ctx.iv_dma_addr, - AES_BLOCK_SIZE, NS_BIT); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE1); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_CTR); + set_key_size_aes(&desc[idx], ctx->enc_keylen); + set_din_type(&desc[idx], DMA_DLLI, + req_ctx->gen_ctx.iv_dma_addr, AES_BLOCK_SIZE, NS_BIT); + set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE1); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; /* load MAC key */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_CBC_MAC); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, ctx->enckey_dma_addr, - ((ctx->enc_keylen == 24) ? - CC_AES_KEY_SIZE_MAX : ctx->enc_keylen), - NS_BIT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], ctx->enc_keylen); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_AES_NOT_HASH_MODE(&desc[idx]); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_CBC_MAC); + set_din_type(&desc[idx], DMA_DLLI, ctx->enckey_dma_addr, + ((ctx->enc_keylen == 24) ? CC_AES_KEY_SIZE_MAX : + ctx->enc_keylen), NS_BIT); + set_key_size_aes(&desc[idx], ctx->enc_keylen); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); + set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_aes_not_hash_mode(&desc[idx]); idx++; /* load MAC state */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_CBC_MAC); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], ctx->enc_keylen); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - req_ctx->mac_buf_dma_addr, - AES_BLOCK_SIZE, NS_BIT); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_AES_NOT_HASH_MODE(&desc[idx]); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_CBC_MAC); + set_key_size_aes(&desc[idx], ctx->enc_keylen); + set_din_type(&desc[idx], DMA_DLLI, req_ctx->mac_buf_dma_addr, + AES_BLOCK_SIZE, NS_BIT); + set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_aes_not_hash_mode(&desc[idx]); idx++; - /* process assoc data */ if (req->assoclen > 0) { ssi_aead_create_assoc_desc(req, DIN_HASH, desc, &idx); } else { - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - sg_dma_address(&req_ctx->ccm_adata_sg), - AES_BLOCK_SIZE + req_ctx->ccm_hdr_size, - NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_HASH); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, + sg_dma_address(&req_ctx->ccm_adata_sg), + AES_BLOCK_SIZE + req_ctx->ccm_hdr_size, NS_BIT); + set_flow_mode(&desc[idx], DIN_HASH); idx++; } /* process the cipher */ - if (req_ctx->cryptlen != 0) { + if (req_ctx->cryptlen != 0) ssi_aead_process_cipher_data_desc(req, cipher_flow_mode, desc, &idx); - } /* Read temporal MAC */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_CBC_MAC); - HW_DESC_SET_DOUT_DLLI(&desc[idx], req_ctx->mac_buf_dma_addr, - ctx->authsize, NS_BIT, 0); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], HASH_DIGEST_RESULT_LITTLE_ENDIAN); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_AES_NOT_HASH_MODE(&desc[idx]); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_CBC_MAC); + set_dout_dlli(&desc[idx], req_ctx->mac_buf_dma_addr, ctx->authsize, + NS_BIT, 0); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); + set_cipher_config0(&desc[idx], HASH_DIGEST_RESULT_LITTLE_ENDIAN); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_aes_not_hash_mode(&desc[idx]); idx++; /* load AES-CTR state (for last MAC calculation)*/ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_CTR); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - req_ctx->ccm_iv0_dma_addr , - AES_BLOCK_SIZE, NS_BIT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], ctx->enc_keylen); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE1); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_CTR); + set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); + set_din_type(&desc[idx], DMA_DLLI, req_ctx->ccm_iv0_dma_addr, + AES_BLOCK_SIZE, NS_BIT); + set_key_size_aes(&desc[idx], ctx->enc_keylen); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE1); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_NO_DMA(&desc[idx], 0, 0xfffff0); - HW_DESC_SET_DOUT_NO_DMA(&desc[idx], 0, 0, 1); + hw_desc_init(&desc[idx]); + set_din_no_dma(&desc[idx], 0, 0xfffff0); + set_dout_no_dma(&desc[idx], 0, 0, 1); idx++; /* encrypt the "T" value and store MAC in mac_state */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - req_ctx->mac_buf_dma_addr , ctx->authsize, NS_BIT); - HW_DESC_SET_DOUT_DLLI(&desc[idx], mac_result , ctx->authsize, NS_BIT, 1); - HW_DESC_SET_QUEUE_LAST_IND(&desc[idx]); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_AES_DOUT); - idx++; + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, req_ctx->mac_buf_dma_addr, + ctx->authsize, NS_BIT); + set_dout_dlli(&desc[idx], mac_result, ctx->authsize, NS_BIT, 1); + set_queue_last_ind(&desc[idx]); + set_flow_mode(&desc[idx], DIN_AES_DOUT); + idx++; *seq_size = idx; return 0; } -static int config_ccm_adata(struct aead_request *req) { +static int config_ccm_adata(struct aead_request *req) +{ struct crypto_aead *tfm = crypto_aead_reqtfm(req); struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); struct aead_req_ctx *req_ctx = aead_request_ctx(req); @@ -1597,21 +1543,22 @@ static int config_ccm_adata(struct aead_request *req) { /* Note: The code assume that req->iv[0] already contains the value of L' of RFC3610 */ unsigned int l = lp + 1; /* This is L' of RFC 3610. */ unsigned int m = ctx->authsize; /* This is M' of RFC 3610. */ - uint8_t *b0 = req_ctx->ccm_config + CCM_B0_OFFSET; - uint8_t *a0 = req_ctx->ccm_config + CCM_A0_OFFSET; - uint8_t *ctr_count_0 = req_ctx->ccm_config + CCM_CTR_COUNT_0_OFFSET; - unsigned int cryptlen = (req_ctx->gen_ctx.op_type == - DRV_CRYPTO_DIRECTION_ENCRYPT) ? - req->cryptlen : + u8 *b0 = req_ctx->ccm_config + CCM_B0_OFFSET; + u8 *a0 = req_ctx->ccm_config + CCM_A0_OFFSET; + u8 *ctr_count_0 = req_ctx->ccm_config + CCM_CTR_COUNT_0_OFFSET; + unsigned int cryptlen = (req_ctx->gen_ctx.op_type == + DRV_CRYPTO_DIRECTION_ENCRYPT) ? + req->cryptlen : (req->cryptlen - ctx->authsize); int rc; + memset(req_ctx->mac_buf, 0, AES_BLOCK_SIZE); - memset(req_ctx->ccm_config, 0, AES_BLOCK_SIZE*3); + memset(req_ctx->ccm_config, 0, AES_BLOCK_SIZE * 3); /* taken from crypto/ccm.c */ /* 2 <= L <= 8, so 1 <= L' <= 7. */ if (2 > l || l > 8) { - SSI_LOG_ERR("illegal iv value %X\n",req->iv[0]); + SSI_LOG_ERR("illegal iv value %X\n", req->iv[0]); return -EINVAL; } memcpy(b0, req->iv, AES_BLOCK_SIZE); @@ -1622,20 +1569,19 @@ static int config_ccm_adata(struct aead_request *req) { *b0 |= (8 * ((m - 2) / 2)); if (req->assoclen > 0) *b0 |= 64; /* Enable bit 6 if Adata exists. */ - + rc = set_msg_len(b0 + 16 - l, cryptlen, l); /* Write L'. */ - if (rc != 0) { + if (rc != 0) return rc; - } /* END of "taken from crypto/ccm.c" */ - + /* l(a) - size of associated data. */ - req_ctx->ccm_hdr_size = format_ccm_a0 (a0, req->assoclen); + req_ctx->ccm_hdr_size = format_ccm_a0(a0, req->assoclen); memset(req->iv + 15 - req->iv[0], 0, req->iv[0] + 1); - req->iv [15] = 1; + req->iv[15] = 1; - memcpy(ctr_count_0, req->iv, AES_BLOCK_SIZE) ; + memcpy(ctr_count_0, req->iv, AES_BLOCK_SIZE); ctr_count_0[15] = 0; return 0; @@ -1654,7 +1600,7 @@ static void ssi_rfc4309_ccm_process(struct aead_request *req) /* In RFC 4309 there is an 11-bytes nonce+IV part, that we build here. */ memcpy(areq_ctx->ctr_iv + CCM_BLOCK_NONCE_OFFSET, ctx->ctr_nonce, CCM_BLOCK_NONCE_SIZE); memcpy(areq_ctx->ctr_iv + CCM_BLOCK_IV_OFFSET, req->iv, CCM_BLOCK_IV_SIZE); - req->iv = areq_ctx->ctr_iv; + req->iv = areq_ctx->ctr_iv; req->assoclen -= CCM_BLOCK_IV_SIZE; } #endif /*SSI_CC_HAS_AES_CCM*/ @@ -1663,7 +1609,7 @@ static void ssi_rfc4309_ccm_process(struct aead_request *req) static inline void ssi_aead_gcm_setup_ghash_desc( struct aead_request *req, - HwDesc_s desc[], + struct cc_hw_desc desc[], unsigned int *seq_size) { struct crypto_aead *tfm = crypto_aead_reqtfm(req); @@ -1672,69 +1618,68 @@ static inline void ssi_aead_gcm_setup_ghash_desc( unsigned int idx = *seq_size; /* load key to AES*/ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_ECB); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, ctx->enckey_dma_addr, - ctx->enc_keylen, NS_BIT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], ctx->enc_keylen); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_ECB); + set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); + set_din_type(&desc[idx], DMA_DLLI, ctx->enckey_dma_addr, + ctx->enc_keylen, NS_BIT); + set_key_size_aes(&desc[idx], ctx->enc_keylen); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; /* process one zero block to generate hkey */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_CONST(&desc[idx], 0x0, AES_BLOCK_SIZE); - HW_DESC_SET_DOUT_DLLI(&desc[idx], - req_ctx->hkey_dma_addr, - AES_BLOCK_SIZE, - NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_AES_DOUT); + hw_desc_init(&desc[idx]); + set_din_const(&desc[idx], 0x0, AES_BLOCK_SIZE); + set_dout_dlli(&desc[idx], req_ctx->hkey_dma_addr, AES_BLOCK_SIZE, + NS_BIT, 0); + set_flow_mode(&desc[idx], DIN_AES_DOUT); idx++; /* Memory Barrier */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_NO_DMA(&desc[idx], 0, 0xfffff0); - HW_DESC_SET_DOUT_NO_DMA(&desc[idx], 0, 0, 1); + hw_desc_init(&desc[idx]); + set_din_no_dma(&desc[idx], 0, 0xfffff0); + set_dout_no_dma(&desc[idx], 0, 0, 1); idx++; /* Load GHASH subkey */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - req_ctx->hkey_dma_addr, - AES_BLOCK_SIZE, NS_BIT); - HW_DESC_SET_DOUT_NO_DMA(&desc[idx], 0, 0, 1); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_AES_NOT_HASH_MODE(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_HASH_HW_GHASH); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_ENABLED); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, req_ctx->hkey_dma_addr, + AES_BLOCK_SIZE, NS_BIT); + set_dout_no_dma(&desc[idx], 0, 0, 1); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_aes_not_hash_mode(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_HASH_HW_GHASH); + set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; /* Configure Hash Engine to work with GHASH. - Since it was not possible to extend HASH submodes to add GHASH, - The following command is necessary in order to select GHASH (according to HW designers)*/ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_NO_DMA(&desc[idx], 0, 0xfffff0); - HW_DESC_SET_DOUT_NO_DMA(&desc[idx], 0, 0, 1); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_AES_NOT_HASH_MODE(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_HASH_HW_GHASH); - HW_DESC_SET_CIPHER_DO(&desc[idx], 1); //1=AES_SK RKEK - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_ENABLED); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + * Since it was not possible to extend HASH submodes to add GHASH, + * The following command is necessary in order to + * select GHASH (according to HW designers) + */ + hw_desc_init(&desc[idx]); + set_din_no_dma(&desc[idx], 0, 0xfffff0); + set_dout_no_dma(&desc[idx], 0, 0, 1); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_aes_not_hash_mode(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_HASH_HW_GHASH); + set_cipher_do(&desc[idx], 1); //1=AES_SK RKEK + set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); + set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; /* Load GHASH initial STATE (which is 0). (for any hash there is an initial state) */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_CONST(&desc[idx], 0x0, AES_BLOCK_SIZE); - HW_DESC_SET_DOUT_NO_DMA(&desc[idx], 0, 0, 1); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_AES_NOT_HASH_MODE(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_HASH_HW_GHASH); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_ENABLED); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); + hw_desc_init(&desc[idx]); + set_din_const(&desc[idx], 0x0, AES_BLOCK_SIZE); + set_dout_no_dma(&desc[idx], 0, 0, 1); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_aes_not_hash_mode(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_HASH_HW_GHASH); + set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); idx++; *seq_size = idx; @@ -1742,7 +1687,7 @@ static inline void ssi_aead_gcm_setup_ghash_desc( static inline void ssi_aead_gcm_setup_gctr_desc( struct aead_request *req, - HwDesc_s desc[], + struct cc_hw_desc desc[], unsigned int *seq_size) { struct crypto_aead *tfm = crypto_aead_reqtfm(req); @@ -1751,27 +1696,27 @@ static inline void ssi_aead_gcm_setup_gctr_desc( unsigned int idx = *seq_size; /* load key to AES*/ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_GCTR); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, ctx->enckey_dma_addr, - ctx->enc_keylen, NS_BIT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], ctx->enc_keylen); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_GCTR); + set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); + set_din_type(&desc[idx], DMA_DLLI, ctx->enckey_dma_addr, + ctx->enc_keylen, NS_BIT); + set_key_size_aes(&desc[idx], ctx->enc_keylen); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; - if ((req_ctx->cryptlen != 0) && (req_ctx->plaintext_authenticate_only==false)){ + if ((req_ctx->cryptlen != 0) && (!req_ctx->plaintext_authenticate_only)) { /* load AES/CTR initial CTR value inc by 2*/ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_GCTR); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], ctx->enc_keylen); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - req_ctx->gcm_iv_inc2_dma_addr, - AES_BLOCK_SIZE, NS_BIT); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE1); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_GCTR); + set_key_size_aes(&desc[idx], ctx->enc_keylen); + set_din_type(&desc[idx], DMA_DLLI, + req_ctx->gcm_iv_inc2_dma_addr, AES_BLOCK_SIZE, + NS_BIT); + set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE1); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; } @@ -1780,13 +1725,13 @@ static inline void ssi_aead_gcm_setup_gctr_desc( static inline void ssi_aead_process_gcm_result_desc( struct aead_request *req, - HwDesc_s desc[], + struct cc_hw_desc desc[], unsigned int *seq_size) { struct crypto_aead *tfm = crypto_aead_reqtfm(req); struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); struct aead_req_ctx *req_ctx = aead_request_ctx(req); - dma_addr_t mac_result; + dma_addr_t mac_result; unsigned int idx = *seq_size; if (req_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) { @@ -1796,60 +1741,57 @@ static inline void ssi_aead_process_gcm_result_desc( } /* process(ghash) gcm_block_len */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - req_ctx->gcm_block_len_dma_addr, - AES_BLOCK_SIZE, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_HASH); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, req_ctx->gcm_block_len_dma_addr, + AES_BLOCK_SIZE, NS_BIT); + set_flow_mode(&desc[idx], DIN_HASH); idx++; /* Store GHASH state after GHASH(Associated Data + Cipher +LenBlock) */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_HASH_HW_GHASH); - HW_DESC_SET_DIN_NO_DMA(&desc[idx], 0, 0xfffff0); - HW_DESC_SET_DOUT_DLLI(&desc[idx], req_ctx->mac_buf_dma_addr, - AES_BLOCK_SIZE, NS_BIT, 0); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_AES_NOT_HASH_MODE(&desc[idx]); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_HASH_HW_GHASH); + set_din_no_dma(&desc[idx], 0, 0xfffff0); + set_dout_dlli(&desc[idx], req_ctx->mac_buf_dma_addr, AES_BLOCK_SIZE, + NS_BIT, 0); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_aes_not_hash_mode(&desc[idx]); - idx++; + idx++; /* load AES/CTR initial CTR value inc by 1*/ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_GCTR); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], ctx->enc_keylen); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - req_ctx->gcm_iv_inc1_dma_addr, - AES_BLOCK_SIZE, NS_BIT); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE1); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_GCTR); + set_key_size_aes(&desc[idx], ctx->enc_keylen); + set_din_type(&desc[idx], DMA_DLLI, req_ctx->gcm_iv_inc1_dma_addr, + AES_BLOCK_SIZE, NS_BIT); + set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE1); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; /* Memory Barrier */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_NO_DMA(&desc[idx], 0, 0xfffff0); - HW_DESC_SET_DOUT_NO_DMA(&desc[idx], 0, 0, 1); + hw_desc_init(&desc[idx]); + set_din_no_dma(&desc[idx], 0, 0xfffff0); + set_dout_no_dma(&desc[idx], 0, 0, 1); idx++; /* process GCTR on stored GHASH and store MAC in mac_state*/ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_GCTR); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - req_ctx->mac_buf_dma_addr, - AES_BLOCK_SIZE, NS_BIT); - HW_DESC_SET_DOUT_DLLI(&desc[idx], mac_result, ctx->authsize, NS_BIT, 1); - HW_DESC_SET_QUEUE_LAST_IND(&desc[idx]); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_AES_DOUT); - idx++; + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_GCTR); + set_din_type(&desc[idx], DMA_DLLI, req_ctx->mac_buf_dma_addr, + AES_BLOCK_SIZE, NS_BIT); + set_dout_dlli(&desc[idx], mac_result, ctx->authsize, NS_BIT, 1); + set_queue_last_ind(&desc[idx]); + set_flow_mode(&desc[idx], DIN_AES_DOUT); + idx++; *seq_size = idx; } static inline int ssi_aead_gcm( struct aead_request *req, - HwDesc_s desc[], + struct cc_hw_desc desc[], unsigned int *seq_size) { struct aead_req_ctx *req_ctx = aead_request_ctx(req); @@ -1862,9 +1804,8 @@ static inline int ssi_aead_gcm( cipher_flow_mode = AES_to_HASH_and_DOUT; } - //in RFC4543 no data to encrypt. just copy data from src to dest. - if (req_ctx->plaintext_authenticate_only==true){ + if (req_ctx->plaintext_authenticate_only) { ssi_aead_process_cipher_data_desc(req, BYPASS, desc, seq_size); ssi_aead_gcm_setup_ghash_desc(req, desc, seq_size); /* process(ghash) assoc data */ @@ -1883,7 +1824,7 @@ static inline int ssi_aead_gcm( ssi_aead_gcm_setup_gctr_desc(req, desc, seq_size); /* process(gctr+ghash) */ if (req_ctx->cryptlen != 0) - ssi_aead_process_cipher_data_desc(req, cipher_flow_mode, desc, seq_size); + ssi_aead_process_cipher_data_desc(req, cipher_flow_mode, desc, seq_size); ssi_aead_process_gcm_result_desc(req, desc, seq_size); idx = *seq_size; @@ -1892,7 +1833,7 @@ static inline int ssi_aead_gcm( #ifdef CC_DEBUG static inline void ssi_aead_dump_gcm( - const char* title, + const char *title, struct aead_request *req) { struct crypto_aead *tfm = crypto_aead_reqtfm(req); @@ -1902,52 +1843,50 @@ static inline void ssi_aead_dump_gcm( if (ctx->cipher_mode != DRV_CIPHER_GCTR) return; - if (title != NULL) { + if (title) { SSI_LOG_DEBUG("----------------------------------------------------------------------------------"); SSI_LOG_DEBUG("%s\n", title); } - SSI_LOG_DEBUG("cipher_mode %d, authsize %d, enc_keylen %d, assoclen %d, cryptlen %d \n", \ - ctx->cipher_mode, ctx->authsize, ctx->enc_keylen, req->assoclen, req_ctx->cryptlen ); + SSI_LOG_DEBUG("cipher_mode %d, authsize %d, enc_keylen %d, assoclen %d, cryptlen %d\n", \ + ctx->cipher_mode, ctx->authsize, ctx->enc_keylen, req->assoclen, req_ctx->cryptlen); - if ( ctx->enckey != NULL ) { - dump_byte_array("mac key",ctx->enckey, 16); - } + if (ctx->enckey) + dump_byte_array("mac key", ctx->enckey, 16); - dump_byte_array("req->iv",req->iv, AES_BLOCK_SIZE); + dump_byte_array("req->iv", req->iv, AES_BLOCK_SIZE); - dump_byte_array("gcm_iv_inc1",req_ctx->gcm_iv_inc1, AES_BLOCK_SIZE); + dump_byte_array("gcm_iv_inc1", req_ctx->gcm_iv_inc1, AES_BLOCK_SIZE); - dump_byte_array("gcm_iv_inc2",req_ctx->gcm_iv_inc2, AES_BLOCK_SIZE); + dump_byte_array("gcm_iv_inc2", req_ctx->gcm_iv_inc2, AES_BLOCK_SIZE); - dump_byte_array("hkey",req_ctx->hkey, AES_BLOCK_SIZE); + dump_byte_array("hkey", req_ctx->hkey, AES_BLOCK_SIZE); - dump_byte_array("mac_buf",req_ctx->mac_buf, AES_BLOCK_SIZE); + dump_byte_array("mac_buf", req_ctx->mac_buf, AES_BLOCK_SIZE); - dump_byte_array("gcm_len_block",req_ctx->gcm_len_block.lenA, AES_BLOCK_SIZE); + dump_byte_array("gcm_len_block", req_ctx->gcm_len_block.lenA, AES_BLOCK_SIZE); - if (req->src!=NULL && req->cryptlen) { - dump_byte_array("req->src",sg_virt(req->src), req->cryptlen+req->assoclen); - } + if (req->src && req->cryptlen) + dump_byte_array("req->src", sg_virt(req->src), req->cryptlen + req->assoclen); - if (req->dst!=NULL) { - dump_byte_array("req->dst",sg_virt(req->dst), req->cryptlen+ctx->authsize+req->assoclen); - } + if (req->dst) + dump_byte_array("req->dst", sg_virt(req->dst), req->cryptlen + ctx->authsize + req->assoclen); } #endif -static int config_gcm_context(struct aead_request *req) { +static int config_gcm_context(struct aead_request *req) +{ struct crypto_aead *tfm = crypto_aead_reqtfm(req); struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); struct aead_req_ctx *req_ctx = aead_request_ctx(req); - - unsigned int cryptlen = (req_ctx->gen_ctx.op_type == - DRV_CRYPTO_DIRECTION_ENCRYPT) ? - req->cryptlen : + + unsigned int cryptlen = (req_ctx->gen_ctx.op_type == + DRV_CRYPTO_DIRECTION_ENCRYPT) ? + req->cryptlen : (req->cryptlen - ctx->authsize); __be32 counter = cpu_to_be32(2); - SSI_LOG_DEBUG("config_gcm_context() cryptlen = %d, req->assoclen = %d ctx->authsize = %d \n", cryptlen, req->assoclen, ctx->authsize); + SSI_LOG_DEBUG("config_gcm_context() cryptlen = %d, req->assoclen = %d ctx->authsize = %d\n", cryptlen, req->assoclen, ctx->authsize); memset(req_ctx->hkey, 0, AES_BLOCK_SIZE); @@ -1960,21 +1899,20 @@ static int config_gcm_context(struct aead_request *req) { memcpy(req->iv + 12, &counter, 4); memcpy(req_ctx->gcm_iv_inc1, req->iv, 16); - - if (req_ctx->plaintext_authenticate_only == false) - { + if (!req_ctx->plaintext_authenticate_only) { __be64 temp64; + temp64 = cpu_to_be64(req->assoclen * 8); - memcpy ( &req_ctx->gcm_len_block.lenA , &temp64, sizeof(temp64) ); + memcpy(&req_ctx->gcm_len_block.lenA, &temp64, sizeof(temp64)); temp64 = cpu_to_be64(cryptlen * 8); - memcpy ( &req_ctx->gcm_len_block.lenC , &temp64, 8 ); - } - else { //rfc4543=> all data(AAD,IV,Plain) are considered additional data that is nothing is encrypted. + memcpy(&req_ctx->gcm_len_block.lenC, &temp64, 8); + } else { //rfc4543=> all data(AAD,IV,Plain) are considered additional data that is nothing is encrypted. __be64 temp64; - temp64 = cpu_to_be64((req->assoclen+GCM_BLOCK_RFC4_IV_SIZE+cryptlen) * 8); - memcpy ( &req_ctx->gcm_len_block.lenA , &temp64, sizeof(temp64) ); + + temp64 = cpu_to_be64((req->assoclen + GCM_BLOCK_RFC4_IV_SIZE + cryptlen) * 8); + memcpy(&req_ctx->gcm_len_block.lenA, &temp64, sizeof(temp64)); temp64 = 0; - memcpy ( &req_ctx->gcm_len_block.lenC , &temp64, 8 ); + memcpy(&req_ctx->gcm_len_block.lenC, &temp64, 8); } return 0; @@ -1988,34 +1926,30 @@ static void ssi_rfc4_gcm_process(struct aead_request *req) memcpy(areq_ctx->ctr_iv + GCM_BLOCK_RFC4_NONCE_OFFSET, ctx->ctr_nonce, GCM_BLOCK_RFC4_NONCE_SIZE); memcpy(areq_ctx->ctr_iv + GCM_BLOCK_RFC4_IV_OFFSET, req->iv, GCM_BLOCK_RFC4_IV_SIZE); - req->iv = areq_ctx->ctr_iv; + req->iv = areq_ctx->ctr_iv; req->assoclen -= GCM_BLOCK_RFC4_IV_SIZE; } - #endif /*SSI_CC_HAS_AES_GCM*/ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction direct) { int rc = 0; int seq_len = 0; - HwDesc_s desc[MAX_AEAD_PROCESS_SEQ]; + struct cc_hw_desc desc[MAX_AEAD_PROCESS_SEQ]; struct crypto_aead *tfm = crypto_aead_reqtfm(req); struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); struct aead_req_ctx *areq_ctx = aead_request_ctx(req); struct device *dev = &ctx->drvdata->plat_dev->dev; struct ssi_crypto_req ssi_req = {}; - DECL_CYCLE_COUNT_RESOURCES; - SSI_LOG_DEBUG("%s context=%p req=%p iv=%p src=%p src_ofs=%d dst=%p dst_ofs=%d cryptolen=%d\n", - ((direct==DRV_CRYPTO_DIRECTION_ENCRYPT)?"Encrypt":"Decrypt"), ctx, req, req->iv, + ((direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ? "Encrypt" : "Decrypt"), ctx, req, req->iv, sg_virt(req->src), req->src->offset, sg_virt(req->dst), req->dst->offset, req->cryptlen); CHECK_AND_RETURN_UPON_FIPS_ERROR(); /* STAT_PHASE_0: Init and sanity checks */ - START_CYCLE_COUNT(); - + /* Check data length according to mode */ if (unlikely(validate_data_size(ctx, direct, req) != 0)) { SSI_LOG_ERR("Unsupported crypt/assoc len %d/%d.\n", @@ -2028,25 +1962,19 @@ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction ssi_req.user_cb = (void *)ssi_aead_complete; ssi_req.user_arg = (void *)req; -#ifdef ENABLE_CYCLE_COUNT - ssi_req.op_type = (direct == DRV_CRYPTO_DIRECTION_DECRYPT) ? - STAT_OP_TYPE_DECODE : STAT_OP_TYPE_ENCODE; -#endif /* Setup request context */ areq_ctx->gen_ctx.op_type = direct; areq_ctx->req_authsize = ctx->authsize; areq_ctx->cipher_mode = ctx->cipher_mode; - END_CYCLE_COUNT(ssi_req.op_type, STAT_PHASE_0); - /* STAT_PHASE_1: Map buffers */ - START_CYCLE_COUNT(); - + if (ctx->cipher_mode == DRV_CIPHER_CTR) { /* Build CTR IV - Copy nonce from last 4 bytes in - * CTR key to first 4 bytes in CTR IV */ + * CTR key to first 4 bytes in CTR IV + */ memcpy(areq_ctx->ctr_iv, ctx->ctr_nonce, CTR_RFC3686_NONCE_SIZE); - if (areq_ctx->backup_giv == NULL) /*User none-generated IV*/ + if (!areq_ctx->backup_giv) /*User none-generated IV*/ memcpy(areq_ctx->ctr_iv + CTR_RFC3686_NONCE_SIZE, req->iv, CTR_RFC3686_IV_SIZE); /* Initialize counter portion of counter block */ @@ -2056,8 +1984,8 @@ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction /* Replace with counter iv */ req->iv = areq_ctx->ctr_iv; areq_ctx->hw_iv_size = CTR_RFC3686_BLOCK_SIZE; - } else if ((ctx->cipher_mode == DRV_CIPHER_CCM) || - (ctx->cipher_mode == DRV_CIPHER_GCTR) ) { + } else if ((ctx->cipher_mode == DRV_CIPHER_CCM) || + (ctx->cipher_mode == DRV_CIPHER_GCTR)) { areq_ctx->hw_iv_size = AES_BLOCK_SIZE; if (areq_ctx->ctr_iv != req->iv) { memcpy(areq_ctx->ctr_iv, req->iv, crypto_aead_ivsize(tfm)); @@ -2072,23 +2000,23 @@ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction rc = config_ccm_adata(req); if (unlikely(rc != 0)) { SSI_LOG_ERR("config_ccm_adata() returned with a failure %d!", rc); - goto exit; + goto exit; } } else { - areq_ctx->ccm_hdr_size = ccm_header_size_null; + areq_ctx->ccm_hdr_size = ccm_header_size_null; } #else - areq_ctx->ccm_hdr_size = ccm_header_size_null; + areq_ctx->ccm_hdr_size = ccm_header_size_null; #endif /*SSI_CC_HAS_AES_CCM*/ -#if SSI_CC_HAS_AES_GCM +#if SSI_CC_HAS_AES_GCM if (ctx->cipher_mode == DRV_CIPHER_GCTR) { rc = config_gcm_context(req); if (unlikely(rc != 0)) { SSI_LOG_ERR("config_gcm_context() returned with a failure %d!", rc); - goto exit; + goto exit; } - } + } #endif /*SSI_CC_HAS_AES_GCM*/ rc = ssi_buffer_mgr_map_aead_request(ctx->drvdata, req); @@ -2098,17 +2026,17 @@ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction } /* do we need to generate IV? */ - if (areq_ctx->backup_giv != NULL) { - + if (areq_ctx->backup_giv) { /* set the DMA mapped IV address*/ if (ctx->cipher_mode == DRV_CIPHER_CTR) { ssi_req.ivgen_dma_addr[0] = areq_ctx->gen_ctx.iv_dma_addr + CTR_RFC3686_NONCE_SIZE; ssi_req.ivgen_dma_addr_len = 1; } else if (ctx->cipher_mode == DRV_CIPHER_CCM) { /* In ccm, the IV needs to exist both inside B0 and inside the counter. - It is also copied to iv_dma_addr for other reasons (like returning - it to the user). - So, using 3 (identical) IV outputs. */ + * It is also copied to iv_dma_addr for other reasons (like returning + * it to the user). + * So, using 3 (identical) IV outputs. + */ ssi_req.ivgen_dma_addr[0] = areq_ctx->gen_ctx.iv_dma_addr + CCM_BLOCK_IV_OFFSET; ssi_req.ivgen_dma_addr[1] = sg_dma_address(&areq_ctx->ccm_adata_sg) + CCM_B0_OFFSET + CCM_BLOCK_IV_OFFSET; ssi_req.ivgen_dma_addr[2] = sg_dma_address(&areq_ctx->ccm_adata_sg) + CCM_CTR_COUNT_0_OFFSET + CCM_BLOCK_IV_OFFSET; @@ -2122,10 +2050,7 @@ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction ssi_req.ivgen_size = crypto_aead_ivsize(tfm); } - END_CYCLE_COUNT(ssi_req.op_type, STAT_PHASE_1); - /* STAT_PHASE_2: Create sequence */ - START_CYCLE_COUNT(); /* Load MLLI tables to SRAM if necessary */ ssi_aead_load_mlli_to_sram(req, desc, &seq_len); @@ -2139,31 +2064,26 @@ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction case DRV_HASH_XCBC_MAC: ssi_aead_xcbc_authenc(req, desc, &seq_len); break; -#if ( SSI_CC_HAS_AES_CCM || SSI_CC_HAS_AES_GCM ) +#if (SSI_CC_HAS_AES_CCM || SSI_CC_HAS_AES_GCM) case DRV_HASH_NULL: #if SSI_CC_HAS_AES_CCM - if (ctx->cipher_mode == DRV_CIPHER_CCM) { + if (ctx->cipher_mode == DRV_CIPHER_CCM) ssi_aead_ccm(req, desc, &seq_len); - } #endif /*SSI_CC_HAS_AES_CCM*/ #if SSI_CC_HAS_AES_GCM - if (ctx->cipher_mode == DRV_CIPHER_GCTR) { + if (ctx->cipher_mode == DRV_CIPHER_GCTR) ssi_aead_gcm(req, desc, &seq_len); - } #endif /*SSI_CC_HAS_AES_GCM*/ break; #endif - default: + default: SSI_LOG_ERR("Unsupported authenc (%d)\n", ctx->auth_mode); ssi_buffer_mgr_unmap_aead_request(dev, req); rc = -ENOTSUPP; goto exit; } - END_CYCLE_COUNT(ssi_req.op_type, STAT_PHASE_2); - /* STAT_PHASE_3: Lock HW and push sequence */ - START_CYCLE_COUNT(); rc = send_request(ctx->drvdata, &ssi_req, desc, seq_len, 1); @@ -2172,8 +2092,6 @@ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction ssi_buffer_mgr_unmap_aead_request(dev, req); } - - END_CYCLE_COUNT(ssi_req.op_type, STAT_PHASE_3); exit: return rc; } @@ -2206,7 +2124,7 @@ static int ssi_rfc4309_ccm_encrypt(struct aead_request *req) int rc = -EINVAL; if (!valid_assoclen(req)) { - SSI_LOG_ERR("invalid Assoclen:%u\n", req->assoclen ); + SSI_LOG_ERR("invalid Assoclen:%u\n", req->assoclen); goto out; } @@ -2214,9 +2132,9 @@ static int ssi_rfc4309_ccm_encrypt(struct aead_request *req) areq_ctx->backup_iv = req->iv; areq_ctx->backup_giv = NULL; areq_ctx->is_gcm4543 = true; - + ssi_rfc4309_ccm_process(req); - + rc = ssi_aead_process(req, DRV_CRYPTO_DIRECTION_ENCRYPT); if (rc != -EINPROGRESS) req->iv = areq_ctx->backup_iv; @@ -2242,7 +2160,6 @@ static int ssi_aead_decrypt(struct aead_request *req) req->iv = areq_ctx->backup_iv; return rc; - } #if SSI_CC_HAS_AES_CCM @@ -2261,10 +2178,10 @@ static int ssi_rfc4309_ccm_decrypt(struct aead_request *req) /* No generated IV required */ areq_ctx->backup_iv = req->iv; areq_ctx->backup_giv = NULL; - + areq_ctx->is_gcm4543 = true; ssi_rfc4309_ccm_process(req); - + rc = ssi_aead_process(req, DRV_CRYPTO_DIRECTION_DECRYPT); if (rc != -EINPROGRESS) req->iv = areq_ctx->backup_iv; @@ -2280,8 +2197,8 @@ static int ssi_rfc4106_gcm_setkey(struct crypto_aead *tfm, const u8 *key, unsign { struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); int rc = 0; - - SSI_LOG_DEBUG("ssi_rfc4106_gcm_setkey() keylen %d, key %p \n", keylen, key ); + + SSI_LOG_DEBUG("ssi_rfc4106_gcm_setkey() keylen %d, key %p\n", keylen, key); if (keylen < 4) return -EINVAL; @@ -2298,8 +2215,8 @@ static int ssi_rfc4543_gcm_setkey(struct crypto_aead *tfm, const u8 *key, unsign { struct ssi_aead_ctx *ctx = crypto_aead_ctx(tfm); int rc = 0; - - SSI_LOG_DEBUG("ssi_rfc4543_gcm_setkey() keylen %d, key %p \n", keylen, key ); + + SSI_LOG_DEBUG("ssi_rfc4543_gcm_setkey() keylen %d, key %p\n", keylen, key); if (keylen < 4) return -EINVAL; @@ -2334,24 +2251,24 @@ static int ssi_gcm_setauthsize(struct crypto_aead *authenc, static int ssi_rfc4106_gcm_setauthsize(struct crypto_aead *authenc, unsigned int authsize) { - SSI_LOG_DEBUG("ssi_rfc4106_gcm_setauthsize() authsize %d \n", authsize ); - - switch (authsize) { - case 8: - case 12: - case 16: - break; - default: - return -EINVAL; - } - - return ssi_aead_setauthsize(authenc, authsize); + SSI_LOG_DEBUG("ssi_rfc4106_gcm_setauthsize() authsize %d\n", authsize); + + switch (authsize) { + case 8: + case 12: + case 16: + break; + default: + return -EINVAL; + } + + return ssi_aead_setauthsize(authenc, authsize); } static int ssi_rfc4543_gcm_setauthsize(struct crypto_aead *authenc, - unsigned int authsize) + unsigned int authsize) { - SSI_LOG_DEBUG("ssi_rfc4543_gcm_setauthsize() authsize %d \n", authsize ); + SSI_LOG_DEBUG("ssi_rfc4543_gcm_setauthsize() authsize %d\n", authsize); if (authsize != 16) return -EINVAL; @@ -2364,7 +2281,7 @@ static int ssi_rfc4106_gcm_encrypt(struct aead_request *req) /* Very similar to ssi_aead_encrypt() above. */ struct aead_req_ctx *areq_ctx = aead_request_ctx(req); - int rc = -EINVAL; + int rc = -EINVAL; if (!valid_assoclen(req)) { SSI_LOG_ERR("invalid Assoclen:%u\n", req->assoclen); @@ -2374,7 +2291,7 @@ static int ssi_rfc4106_gcm_encrypt(struct aead_request *req) /* No generated IV required */ areq_ctx->backup_iv = req->iv; areq_ctx->backup_giv = NULL; - + areq_ctx->plaintext_authenticate_only = false; ssi_rfc4_gcm_process(req); @@ -2393,14 +2310,14 @@ static int ssi_rfc4543_gcm_encrypt(struct aead_request *req) struct aead_req_ctx *areq_ctx = aead_request_ctx(req); int rc; - + //plaintext is not encryped with rfc4543 areq_ctx->plaintext_authenticate_only = true; /* No generated IV required */ areq_ctx->backup_iv = req->iv; areq_ctx->backup_giv = NULL; - + ssi_rfc4_gcm_process(req); areq_ctx->is_gcm4543 = true; @@ -2416,7 +2333,7 @@ static int ssi_rfc4106_gcm_decrypt(struct aead_request *req) /* Very similar to ssi_aead_decrypt() above. */ struct aead_req_ctx *areq_ctx = aead_request_ctx(req); - int rc = -EINVAL; + int rc = -EINVAL; if (!valid_assoclen(req)) { SSI_LOG_ERR("invalid Assoclen:%u\n", req->assoclen); @@ -2426,7 +2343,7 @@ static int ssi_rfc4106_gcm_decrypt(struct aead_request *req) /* No generated IV required */ areq_ctx->backup_iv = req->iv; areq_ctx->backup_giv = NULL; - + areq_ctx->plaintext_authenticate_only = false; ssi_rfc4_gcm_process(req); @@ -2452,7 +2369,7 @@ static int ssi_rfc4543_gcm_decrypt(struct aead_request *req) /* No generated IV required */ areq_ctx->backup_iv = req->iv; areq_ctx->backup_giv = NULL; - + ssi_rfc4_gcm_process(req); areq_ctx->is_gcm4543 = true; @@ -2715,7 +2632,7 @@ static struct ssi_alg_template aead_algs[] = { .cipher_mode = DRV_CIPHER_GCTR, .flow_mode = S_DIN_to_AES, .auth_mode = DRV_HASH_NULL, - }, + }, #endif /*SSI_CC_HAS_AES_GCM*/ }; @@ -2758,7 +2675,7 @@ int ssi_aead_free(struct ssi_drvdata *drvdata) struct ssi_aead_handle *aead_handle = (struct ssi_aead_handle *)drvdata->aead_handle; - if (aead_handle != NULL) { + if (aead_handle) { /* Remove registered algs */ list_for_each_entry_safe(t_alg, n, &aead_handle->aead_list, entry) { crypto_unregister_aead(&t_alg->aead_alg); @@ -2780,7 +2697,7 @@ int ssi_aead_alloc(struct ssi_drvdata *drvdata) int alg; aead_handle = kmalloc(sizeof(struct ssi_aead_handle), GFP_KERNEL); - if (aead_handle == NULL) { + if (!aead_handle) { rc = -ENOMEM; goto fail0; } @@ -2827,6 +2744,3 @@ fail1: fail0: return rc; } - - - diff --git a/drivers/staging/ccree/ssi_aead.h b/drivers/staging/ccree/ssi_aead.h index fe88c9e04f88..39cc633a3ffa 100644 --- a/drivers/staging/ccree/ssi_aead.h +++ b/drivers/staging/ccree/ssi_aead.h @@ -1,21 +1,21 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ /* \file ssi_aead.h - ARM CryptoCell AEAD Crypto API + * ARM CryptoCell AEAD Crypto API */ #ifndef __SSI_AEAD_H__ @@ -25,22 +25,18 @@ #include <crypto/algapi.h> #include <crypto/ctr.h> - /* mac_cmp - HW writes 8 B but all bytes hold the same value */ #define ICV_CMP_SIZE 8 -#define CCM_CONFIG_BUF_SIZE (AES_BLOCK_SIZE*3) +#define CCM_CONFIG_BUF_SIZE (AES_BLOCK_SIZE * 3) #define MAX_MAC_SIZE MAX(SHA256_DIGEST_SIZE, AES_BLOCK_SIZE) - /* defines for AES GCM configuration buffer */ #define GCM_BLOCK_LEN_SIZE 8 -#define GCM_BLOCK_RFC4_IV_OFFSET 4 -#define GCM_BLOCK_RFC4_IV_SIZE 8 /* IV size for rfc's */ -#define GCM_BLOCK_RFC4_NONCE_OFFSET 0 -#define GCM_BLOCK_RFC4_NONCE_SIZE 4 - - +#define GCM_BLOCK_RFC4_IV_OFFSET 4 +#define GCM_BLOCK_RFC4_IV_SIZE 8 /* IV size for rfc's */ +#define GCM_BLOCK_RFC4_NONCE_OFFSET 0 +#define GCM_BLOCK_RFC4_NONCE_SIZE 4 /* Offsets into AES CCM configuration buffer */ #define CCM_B0_OFFSET 0 @@ -57,48 +53,49 @@ enum aead_ccm_header_size { ccm_header_size_zero = 0, ccm_header_size_2 = 2, ccm_header_size_6 = 6, - ccm_header_size_max = INT32_MAX + ccm_header_size_max = S32_MAX }; struct aead_req_ctx { /* Allocate cache line although only 4 bytes are needed to - * assure next field falls @ cache line - * Used for both: digest HW compare and CCM/GCM MAC value */ - uint8_t mac_buf[MAX_MAC_SIZE] ____cacheline_aligned; - uint8_t ctr_iv[AES_BLOCK_SIZE] ____cacheline_aligned; - - //used in gcm - uint8_t gcm_iv_inc1[AES_BLOCK_SIZE] ____cacheline_aligned; - uint8_t gcm_iv_inc2[AES_BLOCK_SIZE] ____cacheline_aligned; - uint8_t hkey[AES_BLOCK_SIZE] ____cacheline_aligned; + * assure next field falls @ cache line + * Used for both: digest HW compare and CCM/GCM MAC value + */ + u8 mac_buf[MAX_MAC_SIZE] ____cacheline_aligned; + u8 ctr_iv[AES_BLOCK_SIZE] ____cacheline_aligned; + + //used in gcm + u8 gcm_iv_inc1[AES_BLOCK_SIZE] ____cacheline_aligned; + u8 gcm_iv_inc2[AES_BLOCK_SIZE] ____cacheline_aligned; + u8 hkey[AES_BLOCK_SIZE] ____cacheline_aligned; struct { - uint8_t lenA[GCM_BLOCK_LEN_SIZE] ____cacheline_aligned; - uint8_t lenC[GCM_BLOCK_LEN_SIZE] ; + u8 lenA[GCM_BLOCK_LEN_SIZE] ____cacheline_aligned; + u8 lenC[GCM_BLOCK_LEN_SIZE]; } gcm_len_block; - uint8_t ccm_config[CCM_CONFIG_BUF_SIZE] ____cacheline_aligned; + u8 ccm_config[CCM_CONFIG_BUF_SIZE] ____cacheline_aligned; unsigned int hw_iv_size ____cacheline_aligned; /*HW actual size input*/ - uint8_t backup_mac[MAX_MAC_SIZE]; /*used to prevent cache coherence problem*/ - uint8_t *backup_iv; /*store iv for generated IV flow*/ - uint8_t *backup_giv; /*store iv for rfc3686(ctr) flow*/ + u8 backup_mac[MAX_MAC_SIZE]; /*used to prevent cache coherence problem*/ + u8 *backup_iv; /*store iv for generated IV flow*/ + u8 *backup_giv; /*store iv for rfc3686(ctr) flow*/ dma_addr_t mac_buf_dma_addr; /* internal ICV DMA buffer */ dma_addr_t ccm_iv0_dma_addr; /* buffer for internal ccm configurations */ dma_addr_t icv_dma_addr; /* Phys. address of ICV */ - //used in gcm + //used in gcm dma_addr_t gcm_iv_inc1_dma_addr; /* buffer for internal gcm configurations */ dma_addr_t gcm_iv_inc2_dma_addr; /* buffer for internal gcm configurations */ dma_addr_t hkey_dma_addr; /* Phys. address of hkey */ dma_addr_t gcm_block_len_dma_addr; /* Phys. address of gcm block len */ bool is_gcm4543; - uint8_t *icv_virt_addr; /* Virt. address of ICV */ + u8 *icv_virt_addr; /* Virt. address of ICV */ struct async_gen_req_ctx gen_ctx; struct ssi_mlli assoc; struct ssi_mlli src; struct ssi_mlli dst; - struct scatterlist* srcSgl; - struct scatterlist* dstSgl; + struct scatterlist *srcSgl; + struct scatterlist *dstSgl; unsigned int srcOffset; unsigned int dstOffset; enum ssi_req_dma_buf_type assoc_buff_type; diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c b/drivers/staging/ccree/ssi_buffer_mgr.c index 6471d3d2d375..b35871eeabd1 100644 --- a/drivers/staging/ccree/ssi_buffer_mgr.c +++ b/drivers/staging/ccree/ssi_buffer_mgr.c @@ -1,15 +1,15 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ @@ -33,42 +33,15 @@ #include "ssi_hash.h" #include "ssi_aead.h" -#define LLI_MAX_NUM_OF_DATA_ENTRIES 128 -#define LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES 4 -#define MLLI_TABLE_MIN_ALIGNMENT 4 /*Force the MLLI table to be align to uint32 */ -#define MAX_NUM_OF_BUFFERS_IN_MLLI 4 -#define MAX_NUM_OF_TOTAL_MLLI_ENTRIES (2*LLI_MAX_NUM_OF_DATA_ENTRIES + \ - LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES ) - #ifdef CC_DEBUG -#define DUMP_SGL(sg) \ - while (sg) { \ - SSI_LOG_DEBUG("page=%lu offset=%u length=%u (dma_len=%u) " \ - "dma_addr=%08x\n", (sg)->page_link, (sg)->offset, \ - (sg)->length, sg_dma_len(sg), (sg)->dma_address); \ - (sg) = sg_next(sg); \ - } -#define DUMP_MLLI_TABLE(mlli_p, nents) \ - do { \ - SSI_LOG_DEBUG("mlli=%pK nents=%u\n", (mlli_p), (nents)); \ - while((nents)--) { \ - SSI_LOG_DEBUG("addr=0x%08X size=0x%08X\n", \ - (mlli_p)[LLI_WORD0_OFFSET], \ - (mlli_p)[LLI_WORD1_OFFSET]); \ - (mlli_p) += LLI_ENTRY_WORD_SIZE; \ - } \ - } while (0) #define GET_DMA_BUFFER_TYPE(buff_type) ( \ ((buff_type) == SSI_DMA_BUF_NULL) ? "BUF_NULL" : \ ((buff_type) == SSI_DMA_BUF_DLLI) ? "BUF_DLLI" : \ ((buff_type) == SSI_DMA_BUF_MLLI) ? "BUF_MLLI" : "BUF_INVALID") #else -#define DX_BUFFER_MGR_DUMP_SGL(sg) -#define DX_BUFFER_MGR_DUMP_MLLI_TABLE(mlli_p, nents) #define GET_DMA_BUFFER_TYPE(buff_type) #endif - enum dma_buffer_type { DMA_NULL_TYPE = -1, DMA_SGL_TYPE = 1, @@ -92,103 +65,55 @@ struct buffer_array { int total_data_len[MAX_NUM_OF_BUFFERS_IN_MLLI]; enum dma_buffer_type type[MAX_NUM_OF_BUFFERS_IN_MLLI]; bool is_last[MAX_NUM_OF_BUFFERS_IN_MLLI]; - uint32_t * mlli_nents[MAX_NUM_OF_BUFFERS_IN_MLLI]; + u32 *mlli_nents[MAX_NUM_OF_BUFFERS_IN_MLLI]; }; -#ifdef CC_DMA_48BIT_SIM -dma_addr_t ssi_buff_mgr_update_dma_addr(dma_addr_t orig_addr, uint32_t data_len) -{ - dma_addr_t tmp_dma_addr; -#ifdef CC_DMA_48BIT_SIM_FULL - /* With this code all addresses will be switched to 48 bits. */ - /* The if condition protects from double expention */ - if((((orig_addr >> 16) & 0xFFFF) != 0xFFFF) && - (data_len <= CC_MAX_MLLI_ENTRY_SIZE)) { -#else - if((!(((orig_addr >> 16) & 0xFF) % 2)) && - (data_len <= CC_MAX_MLLI_ENTRY_SIZE)) { -#endif - tmp_dma_addr = ((orig_addr<<16) | 0xFFFF0000 | - (orig_addr & UINT16_MAX)); - SSI_LOG_DEBUG("MAP DMA: orig address=0x%llX " - "dma_address=0x%llX\n", - orig_addr, tmp_dma_addr); - return tmp_dma_addr; - } - return orig_addr; -} - -dma_addr_t ssi_buff_mgr_restore_dma_addr(dma_addr_t orig_addr) -{ - dma_addr_t tmp_dma_addr; -#ifdef CC_DMA_48BIT_SIM_FULL - /* With this code all addresses will be restored from 48 bits. */ - /* The if condition protects from double restoring */ - if((orig_addr >> 32) & 0xFFFF ) { -#else - if(((orig_addr >> 32) & 0xFFFF) && - !(((orig_addr >> 32) & 0xFF) % 2) ) { -#endif - /*return high 16 bits*/ - tmp_dma_addr = ((orig_addr >> 16)); - /*clean the 0xFFFF in the lower bits (set in the add expansion)*/ - tmp_dma_addr &= 0xFFFF0000; - /* Set the original 16 bits */ - tmp_dma_addr |= (orig_addr & UINT16_MAX); - SSI_LOG_DEBUG("Release DMA: orig address=0x%llX " - "dma_address=0x%llX\n", - orig_addr, tmp_dma_addr); - return tmp_dma_addr; - } - return orig_addr; -} -#endif /** * ssi_buffer_mgr_get_sgl_nents() - Get scatterlist number of entries. - * + * * @sg_list: SG list * @nbytes: [IN] Total SGL data bytes. - * @lbytes: [OUT] Returns the amount of bytes at the last entry + * @lbytes: [OUT] Returns the amount of bytes at the last entry */ static unsigned int ssi_buffer_mgr_get_sgl_nents( - struct scatterlist *sg_list, unsigned int nbytes, uint32_t *lbytes, bool *is_chained) + struct scatterlist *sg_list, unsigned int nbytes, u32 *lbytes, bool *is_chained) { unsigned int nents = 0; + while (nbytes != 0) { if (sg_is_chain(sg_list)) { - SSI_LOG_ERR("Unexpected chanined entry " - "in sg (entry =0x%X) \n", nents); + SSI_LOG_ERR("Unexpected chained entry " + "in sg (entry =0x%X)\n", nents); BUG(); } if (sg_list->length != 0) { nents++; /* get the number of bytes in the last entry */ *lbytes = nbytes; - nbytes -= ( sg_list->length > nbytes ) ? nbytes : sg_list->length; + nbytes -= (sg_list->length > nbytes) ? nbytes : sg_list->length; sg_list = sg_next(sg_list); } else { sg_list = (struct scatterlist *)sg_page(sg_list); - if (is_chained != NULL) { + if (is_chained) *is_chained = true; - } } } - SSI_LOG_DEBUG("nents %d last bytes %d\n",nents, *lbytes); + SSI_LOG_DEBUG("nents %d last bytes %d\n", nents, *lbytes); return nents; } /** * ssi_buffer_mgr_zero_sgl() - Zero scatter scatter list data. - * + * * @sgl: */ -void ssi_buffer_mgr_zero_sgl(struct scatterlist *sgl, uint32_t data_len) +void ssi_buffer_mgr_zero_sgl(struct scatterlist *sgl, u32 data_len) { struct scatterlist *current_sg = sgl; int sg_index = 0; while (sg_index <= data_len) { - if (current_sg == NULL) { + if (!current_sg) { /* reached the end of the sgl --> just return back */ return; } @@ -201,7 +126,7 @@ void ssi_buffer_mgr_zero_sgl(struct scatterlist *sgl, uint32_t data_len) /** * ssi_buffer_mgr_copy_scatterlist_portion() - Copy scatter list data, * from to_skip to end, to dest and vice versa - * + * * @dest: * @sg: * @to_skip: @@ -210,10 +135,10 @@ void ssi_buffer_mgr_zero_sgl(struct scatterlist *sgl, uint32_t data_len) */ void ssi_buffer_mgr_copy_scatterlist_portion( u8 *dest, struct scatterlist *sg, - uint32_t to_skip, uint32_t end, + u32 to_skip, u32 end, enum ssi_sg_cpy_direct direct) { - uint32_t nents, lbytes; + u32 nents, lbytes; nents = ssi_buffer_mgr_get_sgl_nents(sg, end, &lbytes, NULL); sg_copy_buffer(sg, nents, (void *)dest, (end - to_skip + 1), to_skip, @@ -221,37 +146,33 @@ void ssi_buffer_mgr_copy_scatterlist_portion( } static inline int ssi_buffer_mgr_render_buff_to_mlli( - dma_addr_t buff_dma, uint32_t buff_size, uint32_t *curr_nents, - uint32_t **mlli_entry_pp) + dma_addr_t buff_dma, u32 buff_size, u32 *curr_nents, + u32 **mlli_entry_pp) { - uint32_t *mlli_entry_p = *mlli_entry_pp; - uint32_t new_nents;; + u32 *mlli_entry_p = *mlli_entry_pp; + u32 new_nents;; /* Verify there is no memory overflow*/ - new_nents = (*curr_nents + buff_size/CC_MAX_MLLI_ENTRY_SIZE + 1); - if (new_nents > MAX_NUM_OF_TOTAL_MLLI_ENTRIES ) { + new_nents = (*curr_nents + buff_size / CC_MAX_MLLI_ENTRY_SIZE + 1); + if (new_nents > MAX_NUM_OF_TOTAL_MLLI_ENTRIES) return -ENOMEM; - } /*handle buffer longer than 64 kbytes */ - while (buff_size > CC_MAX_MLLI_ENTRY_SIZE ) { - SSI_UPDATE_DMA_ADDR_TO_48BIT(buff_dma, CC_MAX_MLLI_ENTRY_SIZE); - LLI_SET_ADDR(mlli_entry_p,buff_dma); - LLI_SET_SIZE(mlli_entry_p, CC_MAX_MLLI_ENTRY_SIZE); - SSI_LOG_DEBUG("entry[%d]: single_buff=0x%08X size=%08X\n",*curr_nents, + while (buff_size > CC_MAX_MLLI_ENTRY_SIZE) { + cc_lli_set_addr(mlli_entry_p, buff_dma); + cc_lli_set_size(mlli_entry_p, CC_MAX_MLLI_ENTRY_SIZE); + SSI_LOG_DEBUG("entry[%d]: single_buff=0x%08X size=%08X\n", *curr_nents, mlli_entry_p[LLI_WORD0_OFFSET], mlli_entry_p[LLI_WORD1_OFFSET]); - SSI_RESTORE_DMA_ADDR_TO_48BIT(buff_dma); buff_dma += CC_MAX_MLLI_ENTRY_SIZE; buff_size -= CC_MAX_MLLI_ENTRY_SIZE; mlli_entry_p = mlli_entry_p + 2; (*curr_nents)++; } /*Last entry */ - SSI_UPDATE_DMA_ADDR_TO_48BIT(buff_dma, buff_size); - LLI_SET_ADDR(mlli_entry_p,buff_dma); - LLI_SET_SIZE(mlli_entry_p, buff_size); - SSI_LOG_DEBUG("entry[%d]: single_buff=0x%08X size=%08X\n",*curr_nents, + cc_lli_set_addr(mlli_entry_p, buff_dma); + cc_lli_set_size(mlli_entry_p, buff_size); + SSI_LOG_DEBUG("entry[%d]: single_buff=0x%08X size=%08X\n", *curr_nents, mlli_entry_p[LLI_WORD0_OFFSET], mlli_entry_p[LLI_WORD1_OFFSET]); mlli_entry_p = mlli_entry_p + 2; @@ -260,28 +181,27 @@ static inline int ssi_buffer_mgr_render_buff_to_mlli( return 0; } - static inline int ssi_buffer_mgr_render_scatterlist_to_mlli( - struct scatterlist *sgl, uint32_t sgl_data_len, uint32_t sglOffset, uint32_t *curr_nents, - uint32_t **mlli_entry_pp) + struct scatterlist *sgl, u32 sgl_data_len, u32 sglOffset, u32 *curr_nents, + u32 **mlli_entry_pp) { struct scatterlist *curr_sgl = sgl; - uint32_t *mlli_entry_p = *mlli_entry_pp; - int32_t rc = 0; + u32 *mlli_entry_p = *mlli_entry_pp; + s32 rc = 0; - for ( ; (curr_sgl != NULL) && (sgl_data_len != 0); + for ( ; (curr_sgl) && (sgl_data_len != 0); curr_sgl = sg_next(curr_sgl)) { - uint32_t entry_data_len = + u32 entry_data_len = (sgl_data_len > sg_dma_len(curr_sgl) - sglOffset) ? - sg_dma_len(curr_sgl) - sglOffset : sgl_data_len ; + sg_dma_len(curr_sgl) - sglOffset : sgl_data_len; sgl_data_len -= entry_data_len; rc = ssi_buffer_mgr_render_buff_to_mlli( sg_dma_address(curr_sgl) + sglOffset, entry_data_len, curr_nents, &mlli_entry_p); - if(rc != 0) { + if (rc != 0) return rc; - } - sglOffset=0; + + sglOffset = 0; } *mlli_entry_pp = mlli_entry_p; return 0; @@ -292,8 +212,8 @@ static int ssi_buffer_mgr_generate_mlli( struct buffer_array *sg_data, struct mlli_params *mlli_params) { - uint32_t *mlli_p; - uint32_t total_nents = 0,prev_total_nents = 0; + u32 *mlli_p; + u32 total_nents = 0, prev_total_nents = 0; int rc = 0, i; SSI_LOG_DEBUG("NUM of SG's = %d\n", sg_data->num_of_buffers); @@ -302,21 +222,18 @@ static int ssi_buffer_mgr_generate_mlli( mlli_params->mlli_virt_addr = dma_pool_alloc( mlli_params->curr_pool, GFP_KERNEL, &(mlli_params->mlli_dma_addr)); - if (unlikely(mlli_params->mlli_virt_addr == NULL)) { + if (unlikely(!mlli_params->mlli_virt_addr)) { SSI_LOG_ERR("dma_pool_alloc() failed\n"); - rc =-ENOMEM; + rc = -ENOMEM; goto build_mlli_exit; } - SSI_UPDATE_DMA_ADDR_TO_48BIT(mlli_params->mlli_dma_addr, - (MAX_NUM_OF_TOTAL_MLLI_ENTRIES* - LLI_ENTRY_BYTE_SIZE)); /* Point to start of MLLI */ - mlli_p = (uint32_t *)mlli_params->mlli_virt_addr; + mlli_p = (u32 *)mlli_params->mlli_virt_addr; /* go over all SG's and link it to one MLLI table */ for (i = 0; i < sg_data->num_of_buffers; i++) { if (sg_data->type[i] == DMA_SGL_TYPE) rc = ssi_buffer_mgr_render_scatterlist_to_mlli( - sg_data->entry[i].sgl, + sg_data->entry[i].sgl, sg_data->total_data_len[i], sg_data->offset[i], &total_nents, &mlli_p); else /*DMA_BUFF_TYPE*/ @@ -324,15 +241,15 @@ static int ssi_buffer_mgr_generate_mlli( sg_data->entry[i].buffer_dma, sg_data->total_data_len[i], &total_nents, &mlli_p); - if(rc != 0) { + if (rc != 0) return rc; - } /* set last bit in the current table */ - if (sg_data->mlli_nents[i] != NULL) { - /*Calculate the current MLLI table length for the - length field in the descriptor*/ - *(sg_data->mlli_nents[i]) += + if (sg_data->mlli_nents[i]) { + /*Calculate the current MLLI table length for the + *length field in the descriptor + */ + *(sg_data->mlli_nents[i]) += (total_nents - prev_total_nents); prev_total_nents = total_nents; } @@ -354,7 +271,7 @@ build_mlli_exit: static inline void ssi_buffer_mgr_add_buffer_entry( struct buffer_array *sgl_data, dma_addr_t buffer_dma, unsigned int buffer_len, - bool is_last_entry, uint32_t *mlli_nents) + bool is_last_entry, u32 *mlli_nents) { unsigned int index = sgl_data->num_of_buffers; @@ -368,7 +285,7 @@ static inline void ssi_buffer_mgr_add_buffer_entry( sgl_data->type[index] = DMA_BUFF_TYPE; sgl_data->is_last[index] = is_last_entry; sgl_data->mlli_nents[index] = mlli_nents; - if (sgl_data->mlli_nents[index] != NULL) + if (sgl_data->mlli_nents[index]) *sgl_data->mlli_nents[index] = 0; sgl_data->num_of_buffers++; } @@ -380,7 +297,7 @@ static inline void ssi_buffer_mgr_add_scatterlist_entry( unsigned int data_len, unsigned int data_offset, bool is_last_table, - uint32_t *mlli_nents) + u32 *mlli_nents) { unsigned int index = sgl_data->num_of_buffers; @@ -393,22 +310,22 @@ static inline void ssi_buffer_mgr_add_scatterlist_entry( sgl_data->type[index] = DMA_SGL_TYPE; sgl_data->is_last[index] = is_last_table; sgl_data->mlli_nents[index] = mlli_nents; - if (sgl_data->mlli_nents[index] != NULL) + if (sgl_data->mlli_nents[index]) *sgl_data->mlli_nents[index] = 0; sgl_data->num_of_buffers++; } static int -ssi_buffer_mgr_dma_map_sg(struct device *dev, struct scatterlist *sg, uint32_t nents, +ssi_buffer_mgr_dma_map_sg(struct device *dev, struct scatterlist *sg, u32 nents, enum dma_data_direction direction) { - uint32_t i , j; + u32 i, j; struct scatterlist *l_sg = sg; + for (i = 0; i < nents; i++) { - if (l_sg == NULL) { + if (!l_sg) break; - } - if (unlikely(dma_map_sg(dev, l_sg, 1, direction) != 1)){ + if (unlikely(dma_map_sg(dev, l_sg, 1, direction) != 1)) { SSI_LOG_ERR("dma_map_page() sg buffer failed\n"); goto err; } @@ -419,10 +336,9 @@ ssi_buffer_mgr_dma_map_sg(struct device *dev, struct scatterlist *sg, uint32_t n err: /* Restore mapped parts */ for (j = 0; j < i; j++) { - if (sg == NULL) { + if (!sg) break; - } - dma_unmap_sg(dev,sg,1,direction); + dma_unmap_sg(dev, sg, 1, direction); sg = sg_next(sg); } return 0; @@ -431,8 +347,8 @@ err: static int ssi_buffer_mgr_map_scatterlist( struct device *dev, struct scatterlist *sg, unsigned int nbytes, int direction, - uint32_t *nents, uint32_t max_sg_nents, - uint32_t *lbytes, uint32_t *mapped_nents) + u32 *nents, u32 max_sg_nents, + u32 *lbytes, u32 *mapped_nents) { bool is_chained = false; @@ -441,20 +357,19 @@ static int ssi_buffer_mgr_map_scatterlist( if (unlikely(dma_map_sg(dev, sg, 1, direction) != 1)) { SSI_LOG_ERR("dma_map_sg() single buffer failed\n"); return -ENOMEM; - } + } SSI_LOG_DEBUG("Mapped sg: dma_address=0x%llX " - "page_link=0x%08lX addr=%pK offset=%u " + "page=%p addr=%pK offset=%u " "length=%u\n", - (unsigned long long)sg_dma_address(sg), - sg->page_link, - sg_virt(sg), + (unsigned long long)sg_dma_address(sg), + sg_page(sg), + sg_virt(sg), sg->offset, sg->length); *lbytes = nbytes; *nents = 1; *mapped_nents = 1; - SSI_UPDATE_DMA_ADDR_TO_48BIT(sg_dma_address(sg), sg_dma_len(sg)); } else { /*sg_is_last*/ - *nents = ssi_buffer_mgr_get_sgl_nents(sg, nbytes, lbytes, + *nents = ssi_buffer_mgr_get_sgl_nents(sg, nbytes, lbytes, &is_chained); if (*nents > max_sg_nents) { *nents = 0; @@ -464,21 +379,23 @@ static int ssi_buffer_mgr_map_scatterlist( } if (!is_chained) { /* In case of mmu the number of mapped nents might - be changed from the original sgl nents */ + * be changed from the original sgl nents + */ *mapped_nents = dma_map_sg(dev, sg, *nents, direction); - if (unlikely(*mapped_nents == 0)){ + if (unlikely(*mapped_nents == 0)) { *nents = 0; SSI_LOG_ERR("dma_map_sg() sg buffer failed\n"); return -ENOMEM; } } else { /*In this case the driver maps entry by entry so it - must have the same nents before and after map */ + * must have the same nents before and after map + */ *mapped_nents = ssi_buffer_mgr_dma_map_sg(dev, sg, *nents, direction); - if (unlikely(*mapped_nents != *nents)){ + if (unlikely(*mapped_nents != *nents)) { *nents = *mapped_nents; SSI_LOG_ERR("dma_map_sg() sg buffer failed\n"); return -ENOMEM; @@ -492,48 +409,47 @@ static int ssi_buffer_mgr_map_scatterlist( static inline int ssi_aead_handle_config_buf(struct device *dev, struct aead_req_ctx *areq_ctx, - uint8_t* config_data, + u8 *config_data, struct buffer_array *sg_data, unsigned int assoclen) { - SSI_LOG_DEBUG(" handle additional data config set to DLLI \n"); + SSI_LOG_DEBUG(" handle additional data config set to DLLI\n"); /* create sg for the current buffer */ sg_init_one(&areq_ctx->ccm_adata_sg, config_data, AES_BLOCK_SIZE + areq_ctx->ccm_hdr_size); - if (unlikely(dma_map_sg(dev, &areq_ctx->ccm_adata_sg, 1, + if (unlikely(dma_map_sg(dev, &areq_ctx->ccm_adata_sg, 1, DMA_TO_DEVICE) != 1)) { SSI_LOG_ERR("dma_map_sg() " "config buffer failed\n"); return -ENOMEM; } SSI_LOG_DEBUG("Mapped curr_buff: dma_address=0x%llX " - "page_link=0x%08lX addr=%pK " + "page=%p addr=%pK " "offset=%u length=%u\n", - (unsigned long long)sg_dma_address(&areq_ctx->ccm_adata_sg), - areq_ctx->ccm_adata_sg.page_link, + (unsigned long long)sg_dma_address(&areq_ctx->ccm_adata_sg), + sg_page(&areq_ctx->ccm_adata_sg), sg_virt(&areq_ctx->ccm_adata_sg), - areq_ctx->ccm_adata_sg.offset, + areq_ctx->ccm_adata_sg.offset, areq_ctx->ccm_adata_sg.length); /* prepare for case of MLLI */ if (assoclen > 0) { - ssi_buffer_mgr_add_scatterlist_entry(sg_data, 1, + ssi_buffer_mgr_add_scatterlist_entry(sg_data, 1, &areq_ctx->ccm_adata_sg, - (AES_BLOCK_SIZE + + (AES_BLOCK_SIZE + areq_ctx->ccm_hdr_size), 0, false, NULL); } return 0; } - static inline int ssi_ahash_handle_curr_buf(struct device *dev, struct ahash_req_ctx *areq_ctx, - uint8_t* curr_buff, - uint32_t curr_buff_cnt, + u8 *curr_buff, + u32 curr_buff_cnt, struct buffer_array *sg_data) { - SSI_LOG_DEBUG(" handle curr buff %x set to DLLI \n", curr_buff_cnt); + SSI_LOG_DEBUG(" handle curr buff %x set to DLLI\n", curr_buff_cnt); /* create sg for the current buffer */ - sg_init_one(areq_ctx->buff_sg,curr_buff, curr_buff_cnt); + sg_init_one(areq_ctx->buff_sg, curr_buff, curr_buff_cnt); if (unlikely(dma_map_sg(dev, areq_ctx->buff_sg, 1, DMA_TO_DEVICE) != 1)) { SSI_LOG_ERR("dma_map_sg() " @@ -541,12 +457,12 @@ static inline int ssi_ahash_handle_curr_buf(struct device *dev, return -ENOMEM; } SSI_LOG_DEBUG("Mapped curr_buff: dma_address=0x%llX " - "page_link=0x%08lX addr=%pK " + "page=%p addr=%pK " "offset=%u length=%u\n", - (unsigned long long)sg_dma_address(areq_ctx->buff_sg), - areq_ctx->buff_sg->page_link, + (unsigned long long)sg_dma_address(areq_ctx->buff_sg), + sg_page(areq_ctx->buff_sg), sg_virt(areq_ctx->buff_sg), - areq_ctx->buff_sg->offset, + areq_ctx->buff_sg->offset, areq_ctx->buff_sg->length); areq_ctx->data_dma_buf_type = SSI_DMA_BUF_DLLI; areq_ctx->curr_sg = areq_ctx->buff_sg; @@ -567,32 +483,28 @@ void ssi_buffer_mgr_unmap_blkcipher_request( struct blkcipher_req_ctx *req_ctx = (struct blkcipher_req_ctx *)ctx; if (likely(req_ctx->gen_ctx.iv_dma_addr != 0)) { - SSI_LOG_DEBUG("Unmapped iv: iv_dma_addr=0x%llX iv_size=%u\n", + SSI_LOG_DEBUG("Unmapped iv: iv_dma_addr=0x%llX iv_size=%u\n", (unsigned long long)req_ctx->gen_ctx.iv_dma_addr, ivsize); - SSI_RESTORE_DMA_ADDR_TO_48BIT(req_ctx->gen_ctx.iv_dma_addr); - dma_unmap_single(dev, req_ctx->gen_ctx.iv_dma_addr, - ivsize, + dma_unmap_single(dev, req_ctx->gen_ctx.iv_dma_addr, + ivsize, req_ctx->is_giv ? DMA_BIDIRECTIONAL : DMA_TO_DEVICE); } /* Release pool */ if (req_ctx->dma_buf_type == SSI_DMA_BUF_MLLI) { - SSI_RESTORE_DMA_ADDR_TO_48BIT(req_ctx->mlli_params.mlli_dma_addr); dma_pool_free(req_ctx->mlli_params.curr_pool, req_ctx->mlli_params.mlli_virt_addr, req_ctx->mlli_params.mlli_dma_addr); } - SSI_RESTORE_DMA_ADDR_TO_48BIT(sg_dma_address(src)); dma_unmap_sg(dev, src, req_ctx->in_nents, DMA_BIDIRECTIONAL); - SSI_LOG_DEBUG("Unmapped req->src=%pK\n", + SSI_LOG_DEBUG("Unmapped req->src=%pK\n", sg_virt(src)); if (src != dst) { - SSI_RESTORE_DMA_ADDR_TO_48BIT(sg_dma_address(dst)); - dma_unmap_sg(dev, dst, req_ctx->out_nents, + dma_unmap_sg(dev, dst, req_ctx->out_nents, DMA_BIDIRECTIONAL); SSI_LOG_DEBUG("Unmapped req->dst=%pK\n", sg_virt(dst)); @@ -609,40 +521,39 @@ int ssi_buffer_mgr_map_blkcipher_request( struct scatterlist *dst) { struct blkcipher_req_ctx *req_ctx = (struct blkcipher_req_ctx *)ctx; - struct mlli_params *mlli_params = &req_ctx->mlli_params; + struct mlli_params *mlli_params = &req_ctx->mlli_params; struct buff_mgr_handle *buff_mgr = drvdata->buff_mgr_handle; struct device *dev = &drvdata->plat_dev->dev; struct buffer_array sg_data; - uint32_t dummy = 0; + u32 dummy = 0; int rc = 0; - uint32_t mapped_nents = 0; + u32 mapped_nents = 0; req_ctx->dma_buf_type = SSI_DMA_BUF_DLLI; mlli_params->curr_pool = NULL; sg_data.num_of_buffers = 0; /* Map IV buffer */ - if (likely(ivsize != 0) ) { - dump_byte_array("iv", (uint8_t *)info, ivsize); - req_ctx->gen_ctx.iv_dma_addr = - dma_map_single(dev, (void *)info, - ivsize, - req_ctx->is_giv ? DMA_BIDIRECTIONAL: + if (likely(ivsize != 0)) { + dump_byte_array("iv", (u8 *)info, ivsize); + req_ctx->gen_ctx.iv_dma_addr = + dma_map_single(dev, (void *)info, + ivsize, + req_ctx->is_giv ? DMA_BIDIRECTIONAL : DMA_TO_DEVICE); - if (unlikely(dma_mapping_error(dev, + if (unlikely(dma_mapping_error(dev, req_ctx->gen_ctx.iv_dma_addr))) { SSI_LOG_ERR("Mapping iv %u B at va=%pK " "for DMA failed\n", ivsize, info); return -ENOMEM; } - SSI_UPDATE_DMA_ADDR_TO_48BIT(req_ctx->gen_ctx.iv_dma_addr, - ivsize); SSI_LOG_DEBUG("Mapped iv %u B at va=%pK to dma=0x%llX\n", ivsize, info, (unsigned long long)req_ctx->gen_ctx.iv_dma_addr); - } else + } else { req_ctx->gen_ctx.iv_dma_addr = 0; - + } + /* Map the src SGL */ rc = ssi_buffer_mgr_map_scatterlist(dev, src, nbytes, DMA_BIDIRECTIONAL, &req_ctx->in_nents, @@ -665,7 +576,7 @@ int ssi_buffer_mgr_map_blkcipher_request( } else { /* Map the dst sg */ if (unlikely(ssi_buffer_mgr_map_scatterlist( - dev,dst, nbytes, + dev, dst, nbytes, DMA_BIDIRECTIONAL, &req_ctx->out_nents, LLI_MAX_NUM_OF_DATA_ENTRIES, &dummy, &mapped_nents))){ @@ -682,17 +593,16 @@ int ssi_buffer_mgr_map_blkcipher_request( &req_ctx->in_mlli_nents); ssi_buffer_mgr_add_scatterlist_entry(&sg_data, req_ctx->out_nents, dst, - nbytes, 0, true, + nbytes, 0, true, &req_ctx->out_mlli_nents); } } - + if (unlikely(req_ctx->dma_buf_type == SSI_DMA_BUF_MLLI)) { mlli_params->curr_pool = buff_mgr->mlli_buffs_pool; rc = ssi_buffer_mgr_generate_mlli(dev, &sg_data, mlli_params); - if (unlikely(rc!= 0)) + if (unlikely(rc != 0)) goto ablkcipher_exit; - } SSI_LOG_DEBUG("areq_ctx->dma_buf_type = %s\n", @@ -711,39 +621,35 @@ void ssi_buffer_mgr_unmap_aead_request( struct aead_req_ctx *areq_ctx = aead_request_ctx(req); unsigned int hw_iv_size = areq_ctx->hw_iv_size; struct crypto_aead *tfm = crypto_aead_reqtfm(req); - uint32_t dummy; + struct ssi_drvdata *drvdata = dev_get_drvdata(dev); + u32 dummy; bool chained; - uint32_t size_to_unmap = 0; + u32 size_to_unmap = 0; if (areq_ctx->mac_buf_dma_addr != 0) { - SSI_RESTORE_DMA_ADDR_TO_48BIT(areq_ctx->mac_buf_dma_addr); - dma_unmap_single(dev, areq_ctx->mac_buf_dma_addr, + dma_unmap_single(dev, areq_ctx->mac_buf_dma_addr, MAX_MAC_SIZE, DMA_BIDIRECTIONAL); } #if SSI_CC_HAS_AES_GCM if (areq_ctx->cipher_mode == DRV_CIPHER_GCTR) { if (areq_ctx->hkey_dma_addr != 0) { - SSI_RESTORE_DMA_ADDR_TO_48BIT(areq_ctx->hkey_dma_addr); dma_unmap_single(dev, areq_ctx->hkey_dma_addr, AES_BLOCK_SIZE, DMA_BIDIRECTIONAL); } - + if (areq_ctx->gcm_block_len_dma_addr != 0) { - SSI_RESTORE_DMA_ADDR_TO_48BIT(areq_ctx->gcm_block_len_dma_addr); dma_unmap_single(dev, areq_ctx->gcm_block_len_dma_addr, AES_BLOCK_SIZE, DMA_TO_DEVICE); } - + if (areq_ctx->gcm_iv_inc1_dma_addr != 0) { - SSI_RESTORE_DMA_ADDR_TO_48BIT(areq_ctx->gcm_iv_inc1_dma_addr); - dma_unmap_single(dev, areq_ctx->gcm_iv_inc1_dma_addr, + dma_unmap_single(dev, areq_ctx->gcm_iv_inc1_dma_addr, AES_BLOCK_SIZE, DMA_TO_DEVICE); } - + if (areq_ctx->gcm_iv_inc2_dma_addr != 0) { - SSI_RESTORE_DMA_ADDR_TO_48BIT(areq_ctx->gcm_iv_inc2_dma_addr); - dma_unmap_single(dev, areq_ctx->gcm_iv_inc2_dma_addr, + dma_unmap_single(dev, areq_ctx->gcm_iv_inc2_dma_addr, AES_BLOCK_SIZE, DMA_TO_DEVICE); } } @@ -751,93 +657,87 @@ void ssi_buffer_mgr_unmap_aead_request( if (areq_ctx->ccm_hdr_size != ccm_header_size_null) { if (areq_ctx->ccm_iv0_dma_addr != 0) { - SSI_RESTORE_DMA_ADDR_TO_48BIT(areq_ctx->ccm_iv0_dma_addr); - dma_unmap_single(dev, areq_ctx->ccm_iv0_dma_addr, + dma_unmap_single(dev, areq_ctx->ccm_iv0_dma_addr, AES_BLOCK_SIZE, DMA_TO_DEVICE); } dma_unmap_sg(dev, &areq_ctx->ccm_adata_sg, 1, DMA_TO_DEVICE); } if (areq_ctx->gen_ctx.iv_dma_addr != 0) { - SSI_RESTORE_DMA_ADDR_TO_48BIT(areq_ctx->gen_ctx.iv_dma_addr); dma_unmap_single(dev, areq_ctx->gen_ctx.iv_dma_addr, hw_iv_size, DMA_BIDIRECTIONAL); } - /*In case a pool was set, a table was - allocated and should be released */ - if (areq_ctx->mlli_params.curr_pool != NULL) { - SSI_LOG_DEBUG("free MLLI buffer: dma=0x%08llX virt=%pK\n", + /*In case a pool was set, a table was + *allocated and should be released + */ + if (areq_ctx->mlli_params.curr_pool) { + SSI_LOG_DEBUG("free MLLI buffer: dma=0x%08llX virt=%pK\n", (unsigned long long)areq_ctx->mlli_params.mlli_dma_addr, areq_ctx->mlli_params.mlli_virt_addr); - SSI_RESTORE_DMA_ADDR_TO_48BIT(areq_ctx->mlli_params.mlli_dma_addr); dma_pool_free(areq_ctx->mlli_params.curr_pool, areq_ctx->mlli_params.mlli_virt_addr, areq_ctx->mlli_params.mlli_dma_addr); } - SSI_LOG_DEBUG("Unmapping src sgl: req->src=%pK areq_ctx->src.nents=%u areq_ctx->assoc.nents=%u assoclen:%u cryptlen=%u\n", sg_virt(req->src),areq_ctx->src.nents,areq_ctx->assoc.nents,req->assoclen,req->cryptlen); - SSI_RESTORE_DMA_ADDR_TO_48BIT(sg_dma_address(req->src)); - size_to_unmap = req->assoclen+req->cryptlen; - if(areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_ENCRYPT){ + SSI_LOG_DEBUG("Unmapping src sgl: req->src=%pK areq_ctx->src.nents=%u areq_ctx->assoc.nents=%u assoclen:%u cryptlen=%u\n", sg_virt(req->src), areq_ctx->src.nents, areq_ctx->assoc.nents, req->assoclen, req->cryptlen); + size_to_unmap = req->assoclen + req->cryptlen; + if (areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_ENCRYPT) size_to_unmap += areq_ctx->req_authsize; - } if (areq_ctx->is_gcm4543) size_to_unmap += crypto_aead_ivsize(tfm); - dma_unmap_sg(dev, req->src, ssi_buffer_mgr_get_sgl_nents(req->src,size_to_unmap,&dummy,&chained) , DMA_BIDIRECTIONAL); + dma_unmap_sg(dev, req->src, ssi_buffer_mgr_get_sgl_nents(req->src, size_to_unmap, &dummy, &chained), DMA_BIDIRECTIONAL); if (unlikely(req->src != req->dst)) { - SSI_LOG_DEBUG("Unmapping dst sgl: req->dst=%pK\n", + SSI_LOG_DEBUG("Unmapping dst sgl: req->dst=%pK\n", sg_virt(req->dst)); - SSI_RESTORE_DMA_ADDR_TO_48BIT(sg_dma_address(req->dst)); - dma_unmap_sg(dev, req->dst, ssi_buffer_mgr_get_sgl_nents(req->dst,size_to_unmap,&dummy,&chained), + dma_unmap_sg(dev, req->dst, ssi_buffer_mgr_get_sgl_nents(req->dst, size_to_unmap, &dummy, &chained), DMA_BIDIRECTIONAL); } -#if DX_HAS_ACP - if ((areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) && + if (drvdata->coherent && + (areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) && likely(req->src == req->dst)) { - uint32_t size_to_skip = req->assoclen; - if (areq_ctx->is_gcm4543) { + u32 size_to_skip = req->assoclen; + + if (areq_ctx->is_gcm4543) size_to_skip += crypto_aead_ivsize(tfm); - } + /* copy mac to a temporary location to deal with possible - data memory overriding that caused by cache coherence problem. */ + * data memory overriding that caused by cache coherence problem. + */ ssi_buffer_mgr_copy_scatterlist_portion( areq_ctx->backup_mac, req->src, - size_to_skip+ req->cryptlen - areq_ctx->req_authsize, - size_to_skip+ req->cryptlen, SSI_SG_FROM_BUF); + size_to_skip + req->cryptlen - areq_ctx->req_authsize, + size_to_skip + req->cryptlen, SSI_SG_FROM_BUF); } -#endif } static inline int ssi_buffer_mgr_get_aead_icv_nents( struct scatterlist *sgl, unsigned int sgl_nents, unsigned int authsize, - uint32_t last_entry_data_size, + u32 last_entry_data_size, bool *is_icv_fragmented) { unsigned int icv_max_size = 0; unsigned int icv_required_size = authsize > last_entry_data_size ? (authsize - last_entry_data_size) : authsize; unsigned int nents; unsigned int i; - + if (sgl_nents < MAX_ICV_NENTS_SUPPORTED) { *is_icv_fragmented = false; return 0; } - - for( i = 0 ; i < (sgl_nents - MAX_ICV_NENTS_SUPPORTED) ; i++) { - if (sgl == NULL) { + + for (i = 0 ; i < (sgl_nents - MAX_ICV_NENTS_SUPPORTED) ; i++) { + if (!sgl) break; - } sgl = sg_next(sgl); } - if (sgl != NULL) { + if (sgl) icv_max_size = sgl->length; - } if (last_entry_data_size > authsize) { nents = 0; /* ICV attached to data in last entry (not fragmented!) */ @@ -873,7 +773,7 @@ static inline int ssi_buffer_mgr_aead_chain_iv( struct device *dev = &drvdata->plat_dev->dev; int rc = 0; - if (unlikely(req->iv == NULL)) { + if (unlikely(!req->iv)) { areq_ctx->gen_ctx.iv_dma_addr = 0; goto chain_iv_exit; } @@ -884,14 +784,13 @@ static inline int ssi_buffer_mgr_aead_chain_iv( SSI_LOG_ERR("Mapping iv %u B at va=%pK for DMA failed\n", hw_iv_size, req->iv); rc = -ENOMEM; - goto chain_iv_exit; + goto chain_iv_exit; } - SSI_UPDATE_DMA_ADDR_TO_48BIT(areq_ctx->gen_ctx.iv_dma_addr, hw_iv_size); SSI_LOG_DEBUG("Mapped iv %u B at va=%pK to dma=0x%llX\n", - hw_iv_size, req->iv, + hw_iv_size, req->iv, (unsigned long long)areq_ctx->gen_ctx.iv_dma_addr); - if (do_chain == true && areq_ctx->plaintext_authenticate_only == true){ // TODO: what about CTR?? ask Ron + if (do_chain && areq_ctx->plaintext_authenticate_only) { // TODO: what about CTR?? ask Ron struct crypto_aead *tfm = crypto_aead_reqtfm(req); unsigned int iv_size_to_authenc = crypto_aead_ivsize(tfm); unsigned int iv_ofs = GCM_BLOCK_RFC4_IV_OFFSET; @@ -915,17 +814,16 @@ static inline int ssi_buffer_mgr_aead_chain_assoc( { struct aead_req_ctx *areq_ctx = aead_request_ctx(req); int rc = 0; - uint32_t mapped_nents = 0; + u32 mapped_nents = 0; struct scatterlist *current_sg = req->src; struct crypto_aead *tfm = crypto_aead_reqtfm(req); unsigned int sg_index = 0; - uint32_t size_of_assoc = req->assoclen; + u32 size_of_assoc = req->assoclen; - if (areq_ctx->is_gcm4543) { + if (areq_ctx->is_gcm4543) size_of_assoc += crypto_aead_ivsize(tfm); - } - if (sg_data == NULL) { + if (!sg_data) { rc = -EINVAL; goto chain_assoc_exit; } @@ -944,14 +842,13 @@ static inline int ssi_buffer_mgr_aead_chain_assoc( //it is assumed that if we reach here , the sgl is already mapped sg_index = current_sg->length; if (sg_index > size_of_assoc) { //the first entry in the scatter list contains all the associated data - mapped_nents++; - } - else{ + mapped_nents++; + } else { while (sg_index <= size_of_assoc) { current_sg = sg_next(current_sg); //if have reached the end of the sgl, then this is unexpected - if (current_sg == NULL) { - SSI_LOG_ERR("reached end of sg list. unexpected \n"); + if (!current_sg) { + SSI_LOG_ERR("reached end of sg list. unexpected\n"); BUG(); } sg_index += current_sg->length; @@ -966,11 +863,11 @@ static inline int ssi_buffer_mgr_aead_chain_assoc( areq_ctx->assoc.nents = mapped_nents; /* in CCM case we have additional entry for - * ccm header configurations */ + * ccm header configurations + */ if (areq_ctx->ccm_hdr_size != ccm_header_size_null) { if (unlikely((mapped_nents + 1) > LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES)) { - SSI_LOG_ERR("CCM case.Too many fragments. " "Current %d max %d\n", (areq_ctx->assoc.nents + 1), @@ -986,9 +883,8 @@ static inline int ssi_buffer_mgr_aead_chain_assoc( else areq_ctx->assoc_buff_type = SSI_DMA_BUF_MLLI; - if (unlikely((do_chain == true) || + if (unlikely((do_chain) || (areq_ctx->assoc_buff_type == SSI_DMA_BUF_MLLI))) { - SSI_LOG_DEBUG("Chain assoc: buff_type=%s nents=%u\n", GET_DMA_BUFFER_TYPE(areq_ctx->assoc_buff_type), areq_ctx->assoc.nents); @@ -1005,7 +901,7 @@ chain_assoc_exit: static inline void ssi_buffer_mgr_prepare_aead_data_dlli( struct aead_request *req, - uint32_t *src_last_bytes, uint32_t *dst_last_bytes) + u32 *src_last_bytes, u32 *dst_last_bytes) { struct aead_req_ctx *areq_ctx = aead_request_ctx(req); enum drv_crypto_direction direct = areq_ctx->gen_ctx.op_type; @@ -1015,7 +911,7 @@ static inline void ssi_buffer_mgr_prepare_aead_data_dlli( if (likely(req->src == req->dst)) { /*INPLACE*/ areq_ctx->icv_dma_addr = sg_dma_address( - areq_ctx->srcSgl)+ + areq_ctx->srcSgl) + (*src_last_bytes - authsize); areq_ctx->icv_virt_addr = sg_virt( areq_ctx->srcSgl) + @@ -1034,7 +930,7 @@ static inline void ssi_buffer_mgr_prepare_aead_data_dlli( areq_ctx->dstSgl) + (*dst_last_bytes - authsize); areq_ctx->icv_virt_addr = sg_virt( - areq_ctx->dstSgl)+ + areq_ctx->dstSgl) + (*dst_last_bytes - authsize); } } @@ -1043,7 +939,7 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli( struct ssi_drvdata *drvdata, struct aead_request *req, struct buffer_array *sg_data, - uint32_t *src_last_bytes, uint32_t *dst_last_bytes, + u32 *src_last_bytes, u32 *dst_last_bytes, bool is_last_table) { struct aead_req_ctx *areq_ctx = aead_request_ctx(req); @@ -1056,7 +952,7 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli( /*INPLACE*/ ssi_buffer_mgr_add_scatterlist_entry(sg_data, areq_ctx->src.nents, areq_ctx->srcSgl, - areq_ctx->cryptlen,areq_ctx->srcOffset, is_last_table, + areq_ctx->cryptlen, areq_ctx->srcOffset, is_last_table, &areq_ctx->src.mlli_nents); icv_nents = ssi_buffer_mgr_get_aead_icv_nents(areq_ctx->srcSgl, @@ -1067,24 +963,30 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli( goto prepare_data_mlli_exit; } - if (unlikely(areq_ctx->is_icv_fragmented == true)) { + if (unlikely(areq_ctx->is_icv_fragmented)) { /* Backup happens only when ICV is fragmented, ICV - verification is made by CPU compare in order to simplify - MAC verification upon request completion */ + * verification is made by CPU compare in order to simplify + * MAC verification upon request completion + */ if (direct == DRV_CRYPTO_DIRECTION_DECRYPT) { -#if !DX_HAS_ACP - /* In ACP platform we already copying ICV - for any INPLACE-DECRYPT operation, hence - we must neglect this code. */ - uint32_t size_to_skip = req->assoclen; - if (areq_ctx->is_gcm4543) { - size_to_skip += crypto_aead_ivsize(tfm); + if (!drvdata->coherent) { + /* In coherent platforms (e.g. ACP) + * already copying ICV for any + * INPLACE-DECRYPT operation, hence + * we must neglect this code. + */ + u32 skip = req->assoclen; + + if (areq_ctx->is_gcm4543) + skip += crypto_aead_ivsize(tfm); + + ssi_buffer_mgr_copy_scatterlist_portion( + areq_ctx->backup_mac, req->src, + (skip + req->cryptlen - + areq_ctx->req_authsize), + skip + req->cryptlen, + SSI_SG_TO_BUF); } - ssi_buffer_mgr_copy_scatterlist_portion( - areq_ctx->backup_mac, req->src, - size_to_skip+ req->cryptlen - areq_ctx->req_authsize, - size_to_skip+ req->cryptlen, SSI_SG_TO_BUF); -#endif areq_ctx->icv_virt_addr = areq_ctx->backup_mac; } else { areq_ctx->icv_virt_addr = areq_ctx->mac_buf; @@ -1096,7 +998,7 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli( &areq_ctx->srcSgl[areq_ctx->src.nents - 1]) + (*src_last_bytes - authsize); areq_ctx->icv_virt_addr = sg_virt( - &areq_ctx->srcSgl[areq_ctx->src.nents - 1]) + + &areq_ctx->srcSgl[areq_ctx->src.nents - 1]) + (*src_last_bytes - authsize); } @@ -1104,11 +1006,11 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli( /*NON-INPLACE and DECRYPT*/ ssi_buffer_mgr_add_scatterlist_entry(sg_data, areq_ctx->src.nents, areq_ctx->srcSgl, - areq_ctx->cryptlen, areq_ctx->srcOffset,is_last_table, + areq_ctx->cryptlen, areq_ctx->srcOffset, is_last_table, &areq_ctx->src.mlli_nents); ssi_buffer_mgr_add_scatterlist_entry(sg_data, areq_ctx->dst.nents, areq_ctx->dstSgl, - areq_ctx->cryptlen,areq_ctx->dstOffset, is_last_table, + areq_ctx->cryptlen, areq_ctx->dstOffset, is_last_table, &areq_ctx->dst.mlli_nents); icv_nents = ssi_buffer_mgr_get_aead_icv_nents(areq_ctx->srcSgl, @@ -1119,18 +1021,20 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli( goto prepare_data_mlli_exit; } - if (unlikely(areq_ctx->is_icv_fragmented == true)) { + if (unlikely(areq_ctx->is_icv_fragmented)) { /* Backup happens only when ICV is fragmented, ICV - verification is made by CPU compare in order to simplify - MAC verification upon request completion */ - uint32_t size_to_skip = req->assoclen; - if (areq_ctx->is_gcm4543) { + * verification is made by CPU compare in order to simplify + * MAC verification upon request completion + */ + u32 size_to_skip = req->assoclen; + + if (areq_ctx->is_gcm4543) size_to_skip += crypto_aead_ivsize(tfm); - } + ssi_buffer_mgr_copy_scatterlist_portion( areq_ctx->backup_mac, req->src, - size_to_skip+ req->cryptlen - areq_ctx->req_authsize, - size_to_skip+ req->cryptlen, SSI_SG_TO_BUF); + size_to_skip + req->cryptlen - areq_ctx->req_authsize, + size_to_skip + req->cryptlen, SSI_SG_TO_BUF); areq_ctx->icv_virt_addr = areq_ctx->backup_mac; } else { /* Contig. ICV */ /*Should hanlde if the sg is not contig.*/ @@ -1146,11 +1050,11 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli( /*NON-INPLACE and ENCRYPT*/ ssi_buffer_mgr_add_scatterlist_entry(sg_data, areq_ctx->dst.nents, areq_ctx->dstSgl, - areq_ctx->cryptlen,areq_ctx->dstOffset, is_last_table, + areq_ctx->cryptlen, areq_ctx->dstOffset, is_last_table, &areq_ctx->dst.mlli_nents); ssi_buffer_mgr_add_scatterlist_entry(sg_data, areq_ctx->src.nents, areq_ctx->srcSgl, - areq_ctx->cryptlen, areq_ctx->srcOffset,is_last_table, + areq_ctx->cryptlen, areq_ctx->srcOffset, is_last_table, &areq_ctx->src.mlli_nents); icv_nents = ssi_buffer_mgr_get_aead_icv_nents(areq_ctx->dstSgl, @@ -1161,7 +1065,7 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli( goto prepare_data_mlli_exit; } - if (likely(areq_ctx->is_icv_fragmented == false)) { + if (likely(!areq_ctx->is_icv_fragmented)) { /* Contig. ICV */ areq_ctx->icv_dma_addr = sg_dma_address( &areq_ctx->dstSgl[areq_ctx->dst.nents - 1]) + @@ -1191,40 +1095,40 @@ static inline int ssi_buffer_mgr_aead_chain_data( unsigned int authsize = areq_ctx->req_authsize; int src_last_bytes = 0, dst_last_bytes = 0; int rc = 0; - uint32_t src_mapped_nents = 0, dst_mapped_nents = 0; - uint32_t offset = 0; - unsigned int size_for_map = req->assoclen +req->cryptlen; /*non-inplace mode*/ + u32 src_mapped_nents = 0, dst_mapped_nents = 0; + u32 offset = 0; + unsigned int size_for_map = req->assoclen + req->cryptlen; /*non-inplace mode*/ struct crypto_aead *tfm = crypto_aead_reqtfm(req); - uint32_t sg_index = 0; + u32 sg_index = 0; bool chained = false; bool is_gcm4543 = areq_ctx->is_gcm4543; - uint32_t size_to_skip = req->assoclen; - if (is_gcm4543) { + u32 size_to_skip = req->assoclen; + + if (is_gcm4543) size_to_skip += crypto_aead_ivsize(tfm); - } + offset = size_to_skip; - if (sg_data == NULL) { + if (!sg_data) { rc = -EINVAL; goto chain_data_exit; } areq_ctx->srcSgl = req->src; areq_ctx->dstSgl = req->dst; - if (is_gcm4543) { + if (is_gcm4543) size_for_map += crypto_aead_ivsize(tfm); - } - size_for_map += (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ? authsize:0; - src_mapped_nents = ssi_buffer_mgr_get_sgl_nents(req->src,size_for_map,&src_last_bytes, &chained); + size_for_map += (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ? authsize : 0; + src_mapped_nents = ssi_buffer_mgr_get_sgl_nents(req->src, size_for_map, &src_last_bytes, &chained); sg_index = areq_ctx->srcSgl->length; //check where the data starts while (sg_index <= size_to_skip) { offset -= areq_ctx->srcSgl->length; areq_ctx->srcSgl = sg_next(areq_ctx->srcSgl); //if have reached the end of the sgl, then this is unexpected - if (areq_ctx->srcSgl == NULL) { - SSI_LOG_ERR("reached end of sg list. unexpected \n"); + if (!areq_ctx->srcSgl) { + SSI_LOG_ERR("reached end of sg list. unexpected\n"); BUG(); } sg_index += areq_ctx->srcSgl->length; @@ -1239,14 +1143,13 @@ static inline int ssi_buffer_mgr_aead_chain_data( areq_ctx->src.nents = src_mapped_nents; - areq_ctx->srcOffset = offset; + areq_ctx->srcOffset = offset; if (req->src != req->dst) { - size_for_map = req->assoclen +req->cryptlen; + size_for_map = req->assoclen + req->cryptlen; size_for_map += (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ? authsize : 0; - if (is_gcm4543) { + if (is_gcm4543) size_for_map += crypto_aead_ivsize(tfm); - } rc = ssi_buffer_mgr_map_scatterlist(dev, req->dst, size_for_map, DMA_BIDIRECTIONAL, &(areq_ctx->dst.nents), @@ -1254,22 +1157,21 @@ static inline int ssi_buffer_mgr_aead_chain_data( &dst_mapped_nents); if (unlikely(rc != 0)) { rc = -ENOMEM; - goto chain_data_exit; + goto chain_data_exit; } } - dst_mapped_nents = ssi_buffer_mgr_get_sgl_nents(req->dst,size_for_map,&dst_last_bytes, &chained); + dst_mapped_nents = ssi_buffer_mgr_get_sgl_nents(req->dst, size_for_map, &dst_last_bytes, &chained); sg_index = areq_ctx->dstSgl->length; offset = size_to_skip; //check where the data starts while (sg_index <= size_to_skip) { - offset -= areq_ctx->dstSgl->length; areq_ctx->dstSgl = sg_next(areq_ctx->dstSgl); //if have reached the end of the sgl, then this is unexpected - if (areq_ctx->dstSgl == NULL) { - SSI_LOG_ERR("reached end of sg list. unexpected \n"); + if (!areq_ctx->dstSgl) { + SSI_LOG_ERR("reached end of sg list. unexpected\n"); BUG(); } sg_index += areq_ctx->dstSgl->length; @@ -1285,7 +1187,7 @@ static inline int ssi_buffer_mgr_aead_chain_data( areq_ctx->dstOffset = offset; if ((src_mapped_nents > 1) || (dst_mapped_nents > 1) || - (do_chain == true)) { + do_chain) { areq_ctx->data_buff_type = SSI_DMA_BUF_MLLI; rc = ssi_buffer_mgr_prepare_aead_data_mlli(drvdata, req, sg_data, &src_last_bytes, &dst_last_bytes, is_last_table); @@ -1299,15 +1201,15 @@ chain_data_exit: return rc; } -static void ssi_buffer_mgr_update_aead_mlli_nents( struct ssi_drvdata *drvdata, +static void ssi_buffer_mgr_update_aead_mlli_nents(struct ssi_drvdata *drvdata, struct aead_request *req) { struct aead_req_ctx *areq_ctx = aead_request_ctx(req); - uint32_t curr_mlli_size = 0; - + u32 curr_mlli_size = 0; + if (areq_ctx->assoc_buff_type == SSI_DMA_BUF_MLLI) { areq_ctx->assoc.sram_addr = drvdata->mlli_sram_addr; - curr_mlli_size = areq_ctx->assoc.mlli_nents * + curr_mlli_size = areq_ctx->assoc.mlli_nents * LLI_ENTRY_BYTE_SIZE; } @@ -1318,32 +1220,32 @@ static void ssi_buffer_mgr_update_aead_mlli_nents( struct ssi_drvdata *drvdata, areq_ctx->src.sram_addr = drvdata->mlli_sram_addr + curr_mlli_size; areq_ctx->dst.sram_addr = areq_ctx->src.sram_addr; - if (areq_ctx->is_single_pass == false) - areq_ctx->assoc.mlli_nents += + if (!areq_ctx->is_single_pass) + areq_ctx->assoc.mlli_nents += areq_ctx->src.mlli_nents; } else { - if (areq_ctx->gen_ctx.op_type == + if (areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) { - areq_ctx->src.sram_addr = + areq_ctx->src.sram_addr = drvdata->mlli_sram_addr + curr_mlli_size; - areq_ctx->dst.sram_addr = - areq_ctx->src.sram_addr + - areq_ctx->src.mlli_nents * + areq_ctx->dst.sram_addr = + areq_ctx->src.sram_addr + + areq_ctx->src.mlli_nents * LLI_ENTRY_BYTE_SIZE; - if (areq_ctx->is_single_pass == false) - areq_ctx->assoc.mlli_nents += + if (!areq_ctx->is_single_pass) + areq_ctx->assoc.mlli_nents += areq_ctx->src.mlli_nents; } else { - areq_ctx->dst.sram_addr = + areq_ctx->dst.sram_addr = drvdata->mlli_sram_addr + curr_mlli_size; - areq_ctx->src.sram_addr = + areq_ctx->src.sram_addr = areq_ctx->dst.sram_addr + - areq_ctx->dst.mlli_nents * + areq_ctx->dst.mlli_nents * LLI_ENTRY_BYTE_SIZE; - if (areq_ctx->is_single_pass == false) - areq_ctx->assoc.mlli_nents += + if (!areq_ctx->is_single_pass) + areq_ctx->assoc.mlli_nents += areq_ctx->dst.mlli_nents; } } @@ -1363,33 +1265,34 @@ int ssi_buffer_mgr_map_aead_request( struct crypto_aead *tfm = crypto_aead_reqtfm(req); bool is_gcm4543 = areq_ctx->is_gcm4543; - uint32_t mapped_nents = 0; - uint32_t dummy = 0; /*used for the assoc data fragments */ - uint32_t size_to_map = 0; + u32 mapped_nents = 0; + u32 dummy = 0; /*used for the assoc data fragments */ + u32 size_to_map = 0; mlli_params->curr_pool = NULL; sg_data.num_of_buffers = 0; -#if DX_HAS_ACP - if ((areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) && + if (drvdata->coherent && + (areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) && likely(req->src == req->dst)) { - uint32_t size_to_skip = req->assoclen; - if (is_gcm4543) { + u32 size_to_skip = req->assoclen; + + if (is_gcm4543) size_to_skip += crypto_aead_ivsize(tfm); - } + /* copy mac to a temporary location to deal with possible - data memory overriding that caused by cache coherence problem. */ + * data memory overriding that caused by cache coherence problem. + */ ssi_buffer_mgr_copy_scatterlist_portion( areq_ctx->backup_mac, req->src, - size_to_skip+ req->cryptlen - areq_ctx->req_authsize, - size_to_skip+ req->cryptlen, SSI_SG_TO_BUF); + size_to_skip + req->cryptlen - areq_ctx->req_authsize, + size_to_skip + req->cryptlen, SSI_SG_TO_BUF); } -#endif /* cacluate the size for cipher remove ICV in decrypt*/ - areq_ctx->cryptlen = (areq_ctx->gen_ctx.op_type == - DRV_CRYPTO_DIRECTION_ENCRYPT) ? + areq_ctx->cryptlen = (areq_ctx->gen_ctx.op_type == + DRV_CRYPTO_DIRECTION_ENCRYPT) ? req->cryptlen : (req->cryptlen - authsize); @@ -1401,7 +1304,6 @@ int ssi_buffer_mgr_map_aead_request( rc = -ENOMEM; goto aead_map_failure; } - SSI_UPDATE_DMA_ADDR_TO_48BIT(areq_ctx->mac_buf_dma_addr, MAX_MAC_SIZE); if (areq_ctx->ccm_hdr_size != ccm_header_size_null) { areq_ctx->ccm_iv0_dma_addr = dma_map_single(dev, @@ -1416,8 +1318,6 @@ int ssi_buffer_mgr_map_aead_request( rc = -ENOMEM; goto aead_map_failure; } - SSI_UPDATE_DMA_ADDR_TO_48BIT(areq_ctx->ccm_iv0_dma_addr, - AES_BLOCK_SIZE); if (ssi_aead_handle_config_buf(dev, areq_ctx, areq_ctx->ccm_config, &sg_data, req->assoclen) != 0) { rc = -ENOMEM; @@ -1435,7 +1335,6 @@ int ssi_buffer_mgr_map_aead_request( rc = -ENOMEM; goto aead_map_failure; } - SSI_UPDATE_DMA_ADDR_TO_48BIT(areq_ctx->hkey_dma_addr, AES_BLOCK_SIZE); areq_ctx->gcm_block_len_dma_addr = dma_map_single(dev, &areq_ctx->gcm_len_block, AES_BLOCK_SIZE, DMA_TO_DEVICE); @@ -1445,7 +1344,6 @@ int ssi_buffer_mgr_map_aead_request( rc = -ENOMEM; goto aead_map_failure; } - SSI_UPDATE_DMA_ADDR_TO_48BIT(areq_ctx->gcm_block_len_dma_addr, AES_BLOCK_SIZE); areq_ctx->gcm_iv_inc1_dma_addr = dma_map_single(dev, areq_ctx->gcm_iv_inc1, @@ -1459,8 +1357,6 @@ int ssi_buffer_mgr_map_aead_request( rc = -ENOMEM; goto aead_map_failure; } - SSI_UPDATE_DMA_ADDR_TO_48BIT(areq_ctx->gcm_iv_inc1_dma_addr, - AES_BLOCK_SIZE); areq_ctx->gcm_iv_inc2_dma_addr = dma_map_single(dev, areq_ctx->gcm_iv_inc2, @@ -1474,32 +1370,30 @@ int ssi_buffer_mgr_map_aead_request( rc = -ENOMEM; goto aead_map_failure; } - SSI_UPDATE_DMA_ADDR_TO_48BIT(areq_ctx->gcm_iv_inc2_dma_addr, - AES_BLOCK_SIZE); } #endif /*SSI_CC_HAS_AES_GCM*/ size_to_map = req->cryptlen + req->assoclen; - if (areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_ENCRYPT) { + if (areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_ENCRYPT) size_to_map += authsize; - } + if (is_gcm4543) size_to_map += crypto_aead_ivsize(tfm); rc = ssi_buffer_mgr_map_scatterlist(dev, req->src, size_to_map, DMA_BIDIRECTIONAL, &(areq_ctx->src.nents), - LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES+LLI_MAX_NUM_OF_DATA_ENTRIES, &dummy, &mapped_nents); + LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES + LLI_MAX_NUM_OF_DATA_ENTRIES, &dummy, &mapped_nents); if (unlikely(rc != 0)) { rc = -ENOMEM; - goto aead_map_failure; + goto aead_map_failure; } - if (likely(areq_ctx->is_single_pass == true)) { + if (likely(areq_ctx->is_single_pass)) { /* - * Create MLLI table for: - * (1) Assoc. data - * (2) Src/Dst SGLs - * Note: IV is contg. buffer (not an SGL) - */ + * Create MLLI table for: + * (1) Assoc. data + * (2) Src/Dst SGLs + * Note: IV is contg. buffer (not an SGL) + */ rc = ssi_buffer_mgr_aead_chain_assoc(drvdata, req, &sg_data, true, false); if (unlikely(rc != 0)) goto aead_map_failure; @@ -1511,25 +1405,25 @@ int ssi_buffer_mgr_map_aead_request( goto aead_map_failure; } else { /* DOUBLE-PASS flow */ /* - * Prepare MLLI table(s) in this order: - * - * If ENCRYPT/DECRYPT (inplace): - * (1) MLLI table for assoc - * (2) IV entry (chained right after end of assoc) - * (3) MLLI for src/dst (inplace operation) - * - * If ENCRYPT (non-inplace) - * (1) MLLI table for assoc - * (2) IV entry (chained right after end of assoc) - * (3) MLLI for dst - * (4) MLLI for src - * - * If DECRYPT (non-inplace) - * (1) MLLI table for assoc - * (2) IV entry (chained right after end of assoc) - * (3) MLLI for src - * (4) MLLI for dst - */ + * Prepare MLLI table(s) in this order: + * + * If ENCRYPT/DECRYPT (inplace): + * (1) MLLI table for assoc + * (2) IV entry (chained right after end of assoc) + * (3) MLLI for src/dst (inplace operation) + * + * If ENCRYPT (non-inplace) + * (1) MLLI table for assoc + * (2) IV entry (chained right after end of assoc) + * (3) MLLI for dst + * (4) MLLI for src + * + * If DECRYPT (non-inplace) + * (1) MLLI table for assoc + * (2) IV entry (chained right after end of assoc) + * (3) MLLI for src + * (4) MLLI for dst + */ rc = ssi_buffer_mgr_aead_chain_assoc(drvdata, req, &sg_data, false, true); if (unlikely(rc != 0)) goto aead_map_failure; @@ -1545,17 +1439,15 @@ int ssi_buffer_mgr_map_aead_request( if (unlikely( (areq_ctx->assoc_buff_type == SSI_DMA_BUF_MLLI) || (areq_ctx->data_buff_type == SSI_DMA_BUF_MLLI))) { - mlli_params->curr_pool = buff_mgr->mlli_buffs_pool; rc = ssi_buffer_mgr_generate_mlli(dev, &sg_data, mlli_params); - if (unlikely(rc != 0)) { + if (unlikely(rc != 0)) goto aead_map_failure; - } ssi_buffer_mgr_update_aead_mlli_nents(drvdata, req); - SSI_LOG_DEBUG("assoc params mn %d\n",areq_ctx->assoc.mlli_nents); - SSI_LOG_DEBUG("src params mn %d\n",areq_ctx->src.mlli_nents); - SSI_LOG_DEBUG("dst params mn %d\n",areq_ctx->dst.mlli_nents); + SSI_LOG_DEBUG("assoc params mn %d\n", areq_ctx->assoc.mlli_nents); + SSI_LOG_DEBUG("src params mn %d\n", areq_ctx->src.mlli_nents); + SSI_LOG_DEBUG("dst params mn %d\n", areq_ctx->dst.mlli_nents); } return 0; @@ -1569,15 +1461,15 @@ int ssi_buffer_mgr_map_hash_request_final( { struct ahash_req_ctx *areq_ctx = (struct ahash_req_ctx *)ctx; struct device *dev = &drvdata->plat_dev->dev; - uint8_t* curr_buff = areq_ctx->buff_index ? areq_ctx->buff1 : + u8 *curr_buff = areq_ctx->buff_index ? areq_ctx->buff1 : areq_ctx->buff0; - uint32_t *curr_buff_cnt = areq_ctx->buff_index ? &areq_ctx->buff1_cnt : + u32 *curr_buff_cnt = areq_ctx->buff_index ? &areq_ctx->buff1_cnt : &areq_ctx->buff0_cnt; - struct mlli_params *mlli_params = &areq_ctx->mlli_params; + struct mlli_params *mlli_params = &areq_ctx->mlli_params; struct buffer_array sg_data; struct buff_mgr_handle *buff_mgr = drvdata->buff_mgr_handle; - uint32_t dummy = 0; - uint32_t mapped_nents = 0; + u32 dummy = 0; + u32 mapped_nents = 0; SSI_LOG_DEBUG(" final params : curr_buff=%pK " "curr_buff_cnt=0x%X nbytes = 0x%X " @@ -1594,10 +1486,10 @@ int ssi_buffer_mgr_map_hash_request_final( /* nothing to do */ return 0; } - + /*TODO: copy data in case that buffer is enough for operation */ /* map the previous buffer */ - if (*curr_buff_cnt != 0 ) { + if (*curr_buff_cnt != 0) { if (ssi_ahash_handle_curr_buf(dev, areq_ctx, curr_buff, *curr_buff_cnt, &sg_data) != 0) { return -ENOMEM; @@ -1605,7 +1497,7 @@ int ssi_buffer_mgr_map_hash_request_final( } if (src && (nbytes > 0) && do_update) { - if ( unlikely( ssi_buffer_mgr_map_scatterlist( dev,src, + if (unlikely(ssi_buffer_mgr_map_scatterlist(dev, src, nbytes, DMA_TO_DEVICE, &areq_ctx->in_nents, @@ -1613,9 +1505,9 @@ int ssi_buffer_mgr_map_hash_request_final( &dummy, &mapped_nents))){ goto unmap_curr_buff; } - if ( src && (mapped_nents == 1) - && (areq_ctx->data_dma_buf_type == SSI_DMA_BUF_NULL) ) { - memcpy(areq_ctx->buff_sg,src, + if (src && (mapped_nents == 1) + && (areq_ctx->data_dma_buf_type == SSI_DMA_BUF_NULL)) { + memcpy(areq_ctx->buff_sg, src, sizeof(struct scatterlist)); areq_ctx->buff_sg->length = nbytes; areq_ctx->curr_sg = areq_ctx->buff_sg; @@ -1623,7 +1515,6 @@ int ssi_buffer_mgr_map_hash_request_final( } else { areq_ctx->data_dma_buf_type = SSI_DMA_BUF_MLLI; } - } /*build mlli */ @@ -1641,7 +1532,7 @@ int ssi_buffer_mgr_map_hash_request_final( } } /* change the buffer index for the unmap function */ - areq_ctx->buff_index = (areq_ctx->buff_index^1); + areq_ctx->buff_index = (areq_ctx->buff_index ^ 1); SSI_LOG_DEBUG("areq_ctx->data_dma_buf_type = %s\n", GET_DMA_BUFFER_TYPE(areq_ctx->data_dma_buf_type)); return 0; @@ -1650,9 +1541,9 @@ fail_unmap_din: dma_unmap_sg(dev, src, areq_ctx->in_nents, DMA_TO_DEVICE); unmap_curr_buff: - if (*curr_buff_cnt != 0 ) { + if (*curr_buff_cnt != 0) dma_unmap_sg(dev, areq_ctx->buff_sg, 1, DMA_TO_DEVICE); - } + return -ENOMEM; } @@ -1661,26 +1552,26 @@ int ssi_buffer_mgr_map_hash_request_update( { struct ahash_req_ctx *areq_ctx = (struct ahash_req_ctx *)ctx; struct device *dev = &drvdata->plat_dev->dev; - uint8_t* curr_buff = areq_ctx->buff_index ? areq_ctx->buff1 : + u8 *curr_buff = areq_ctx->buff_index ? areq_ctx->buff1 : areq_ctx->buff0; - uint32_t *curr_buff_cnt = areq_ctx->buff_index ? &areq_ctx->buff1_cnt : + u32 *curr_buff_cnt = areq_ctx->buff_index ? &areq_ctx->buff1_cnt : &areq_ctx->buff0_cnt; - uint8_t* next_buff = areq_ctx->buff_index ? areq_ctx->buff0 : + u8 *next_buff = areq_ctx->buff_index ? areq_ctx->buff0 : areq_ctx->buff1; - uint32_t *next_buff_cnt = areq_ctx->buff_index ? &areq_ctx->buff0_cnt : + u32 *next_buff_cnt = areq_ctx->buff_index ? &areq_ctx->buff0_cnt : &areq_ctx->buff1_cnt; - struct mlli_params *mlli_params = &areq_ctx->mlli_params; + struct mlli_params *mlli_params = &areq_ctx->mlli_params; unsigned int update_data_len; - uint32_t total_in_len = nbytes + *curr_buff_cnt; + u32 total_in_len = nbytes + *curr_buff_cnt; struct buffer_array sg_data; struct buff_mgr_handle *buff_mgr = drvdata->buff_mgr_handle; unsigned int swap_index = 0; - uint32_t dummy = 0; - uint32_t mapped_nents = 0; - + u32 dummy = 0; + u32 mapped_nents = 0; + SSI_LOG_DEBUG(" update params : curr_buff=%pK " "curr_buff_cnt=0x%X nbytes=0x%X " - "src=%pK curr_index=%u \n", + "src=%pK curr_index=%u\n", curr_buff, *curr_buff_cnt, nbytes, src, areq_ctx->buff_index); /* Init the type of the dma buffer */ @@ -1695,12 +1586,12 @@ int ssi_buffer_mgr_map_hash_request_update( "*curr_buff_cnt=0x%X copy_to=%pK\n", curr_buff, *curr_buff_cnt, &curr_buff[*curr_buff_cnt]); - areq_ctx->in_nents = + areq_ctx->in_nents = ssi_buffer_mgr_get_sgl_nents(src, nbytes, &dummy, NULL); sg_copy_to_buffer(src, areq_ctx->in_nents, - &curr_buff[*curr_buff_cnt], nbytes); + &curr_buff[*curr_buff_cnt], nbytes); *curr_buff_cnt += nbytes; return 1; } @@ -1717,12 +1608,12 @@ int ssi_buffer_mgr_map_hash_request_update( /* Copy the new residue to next buffer */ if (*next_buff_cnt != 0) { SSI_LOG_DEBUG(" handle residue: next buff %pK skip data %u" - " residue %u \n", next_buff, + " residue %u\n", next_buff, (update_data_len - *curr_buff_cnt), *next_buff_cnt); ssi_buffer_mgr_copy_scatterlist_portion(next_buff, src, - (update_data_len -*curr_buff_cnt), - nbytes,SSI_SG_TO_BUF); + (update_data_len - *curr_buff_cnt), + nbytes, SSI_SG_TO_BUF); /* change the buffer index for next operation */ swap_index = 1; } @@ -1735,20 +1626,20 @@ int ssi_buffer_mgr_map_hash_request_update( /* change the buffer index for next operation */ swap_index = 1; } - - if ( update_data_len > *curr_buff_cnt ) { - if ( unlikely( ssi_buffer_mgr_map_scatterlist( dev,src, - (update_data_len -*curr_buff_cnt), + + if (update_data_len > *curr_buff_cnt) { + if (unlikely(ssi_buffer_mgr_map_scatterlist(dev, src, + (update_data_len - *curr_buff_cnt), DMA_TO_DEVICE, &areq_ctx->in_nents, LLI_MAX_NUM_OF_DATA_ENTRIES, &dummy, &mapped_nents))){ goto unmap_curr_buff; } - if ( (mapped_nents == 1) - && (areq_ctx->data_dma_buf_type == SSI_DMA_BUF_NULL) ) { + if ((mapped_nents == 1) + && (areq_ctx->data_dma_buf_type == SSI_DMA_BUF_NULL)) { /* only one entry in the SG and no previous data */ - memcpy(areq_ctx->buff_sg,src, + memcpy(areq_ctx->buff_sg, src, sizeof(struct scatterlist)); areq_ctx->buff_sg->length = update_data_len; areq_ctx->data_dma_buf_type = SSI_DMA_BUF_DLLI; @@ -1770,9 +1661,8 @@ int ssi_buffer_mgr_map_hash_request_update( mlli_params) != 0)) { goto fail_unmap_din; } - } - areq_ctx->buff_index = (areq_ctx->buff_index^swap_index); + areq_ctx->buff_index = (areq_ctx->buff_index ^ swap_index); return 0; @@ -1780,9 +1670,9 @@ fail_unmap_din: dma_unmap_sg(dev, src, areq_ctx->in_nents, DMA_TO_DEVICE); unmap_curr_buff: - if (*curr_buff_cnt != 0 ) { + if (*curr_buff_cnt != 0) dma_unmap_sg(dev, areq_ctx->buff_sg, 1, DMA_TO_DEVICE); - } + return -ENOMEM; } @@ -1790,36 +1680,35 @@ void ssi_buffer_mgr_unmap_hash_request( struct device *dev, void *ctx, struct scatterlist *src, bool do_revert) { struct ahash_req_ctx *areq_ctx = (struct ahash_req_ctx *)ctx; - uint32_t *prev_len = areq_ctx->buff_index ? &areq_ctx->buff0_cnt : + u32 *prev_len = areq_ctx->buff_index ? &areq_ctx->buff0_cnt : &areq_ctx->buff1_cnt; - /*In case a pool was set, a table was - allocated and should be released */ - if (areq_ctx->mlli_params.curr_pool != NULL) { - SSI_LOG_DEBUG("free MLLI buffer: dma=0x%llX virt=%pK\n", + /*In case a pool was set, a table was + *allocated and should be released + */ + if (areq_ctx->mlli_params.curr_pool) { + SSI_LOG_DEBUG("free MLLI buffer: dma=0x%llX virt=%pK\n", (unsigned long long)areq_ctx->mlli_params.mlli_dma_addr, areq_ctx->mlli_params.mlli_virt_addr); - SSI_RESTORE_DMA_ADDR_TO_48BIT(areq_ctx->mlli_params.mlli_dma_addr); dma_pool_free(areq_ctx->mlli_params.curr_pool, areq_ctx->mlli_params.mlli_virt_addr, areq_ctx->mlli_params.mlli_dma_addr); } - + if ((src) && likely(areq_ctx->in_nents != 0)) { SSI_LOG_DEBUG("Unmapped sg src: virt=%pK dma=0x%llX len=0x%X\n", sg_virt(src), - (unsigned long long)sg_dma_address(src), + (unsigned long long)sg_dma_address(src), sg_dma_len(src)); - SSI_RESTORE_DMA_ADDR_TO_48BIT(sg_dma_address(src)); - dma_unmap_sg(dev, src, + dma_unmap_sg(dev, src, areq_ctx->in_nents, DMA_TO_DEVICE); } if (*prev_len != 0) { SSI_LOG_DEBUG("Unmapped buffer: areq_ctx->buff_sg=%pK" - "dma=0x%llX len 0x%X\n", + " dma=0x%llX len 0x%X\n", sg_virt(areq_ctx->buff_sg), - (unsigned long long)sg_dma_address(areq_ctx->buff_sg), + (unsigned long long)sg_dma_address(areq_ctx->buff_sg), sg_dma_len(areq_ctx->buff_sg)); dma_unmap_sg(dev, areq_ctx->buff_sg, 1, DMA_TO_DEVICE); if (!do_revert) { @@ -1838,18 +1727,18 @@ int ssi_buffer_mgr_init(struct ssi_drvdata *drvdata) buff_mgr_handle = (struct buff_mgr_handle *) kmalloc(sizeof(struct buff_mgr_handle), GFP_KERNEL); - if (buff_mgr_handle == NULL) + if (!buff_mgr_handle) return -ENOMEM; drvdata->buff_mgr_handle = buff_mgr_handle; buff_mgr_handle->mlli_buffs_pool = dma_pool_create( "dx_single_mlli_tables", dev, - MAX_NUM_OF_TOTAL_MLLI_ENTRIES * + MAX_NUM_OF_TOTAL_MLLI_ENTRIES * LLI_ENTRY_BYTE_SIZE, MLLI_TABLE_MIN_ALIGNMENT, 0); - if (unlikely(buff_mgr_handle->mlli_buffs_pool == NULL)) + if (unlikely(!buff_mgr_handle->mlli_buffs_pool)) goto error; return 0; @@ -1863,12 +1752,10 @@ int ssi_buffer_mgr_fini(struct ssi_drvdata *drvdata) { struct buff_mgr_handle *buff_mgr_handle = drvdata->buff_mgr_handle; - if (buff_mgr_handle != NULL) { + if (buff_mgr_handle) { dma_pool_destroy(buff_mgr_handle->mlli_buffs_pool); kfree(drvdata->buff_mgr_handle); drvdata->buff_mgr_handle = NULL; - } return 0; } - diff --git a/drivers/staging/ccree/ssi_buffer_mgr.h b/drivers/staging/ccree/ssi_buffer_mgr.h index 5f4b032389f1..41f5223730f8 100644 --- a/drivers/staging/ccree/ssi_buffer_mgr.h +++ b/drivers/staging/ccree/ssi_buffer_mgr.h @@ -1,21 +1,21 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ /* \file buffer_mgr.h - Buffer Manager + * Buffer Manager */ #ifndef __SSI_BUFFER_MGR_H__ @@ -26,7 +26,6 @@ #include "ssi_config.h" #include "ssi_driver.h" - enum ssi_req_dma_buf_type { SSI_DMA_BUF_NULL = 0, SSI_DMA_BUF_DLLI, @@ -46,9 +45,9 @@ struct ssi_mlli { struct mlli_params { struct dma_pool *curr_pool; - uint8_t *mlli_virt_addr; + u8 *mlli_virt_addr; dma_addr_t mlli_dma_addr; - uint32_t mlli_len; + u32 mlli_len; }; int ssi_buffer_mgr_init(struct ssi_drvdata *drvdata); @@ -65,7 +64,7 @@ int ssi_buffer_mgr_map_blkcipher_request( struct scatterlist *dst); void ssi_buffer_mgr_unmap_blkcipher_request( - struct device *dev, + struct device *dev, void *ctx, unsigned int ivsize, struct scatterlist *src, @@ -81,25 +80,9 @@ int ssi_buffer_mgr_map_hash_request_update(struct ssi_drvdata *drvdata, void *ct void ssi_buffer_mgr_unmap_hash_request(struct device *dev, void *ctx, struct scatterlist *src, bool do_revert); -void ssi_buffer_mgr_copy_scatterlist_portion(u8 *dest, struct scatterlist *sg, uint32_t to_skip, uint32_t end, enum ssi_sg_cpy_direct direct); - -void ssi_buffer_mgr_zero_sgl(struct scatterlist *sgl, uint32_t data_len); - - -#ifdef CC_DMA_48BIT_SIM -dma_addr_t ssi_buff_mgr_update_dma_addr(dma_addr_t orig_addr, uint32_t data_len); -dma_addr_t ssi_buff_mgr_restore_dma_addr(dma_addr_t orig_addr); - -#define SSI_UPDATE_DMA_ADDR_TO_48BIT(addr,size) addr = \ - ssi_buff_mgr_update_dma_addr(addr,size) -#define SSI_RESTORE_DMA_ADDR_TO_48BIT(addr) addr = \ - ssi_buff_mgr_restore_dma_addr(addr) -#else - -#define SSI_UPDATE_DMA_ADDR_TO_48BIT(addr,size) addr = addr -#define SSI_RESTORE_DMA_ADDR_TO_48BIT(addr) addr = addr +void ssi_buffer_mgr_copy_scatterlist_portion(u8 *dest, struct scatterlist *sg, u32 to_skip, u32 end, enum ssi_sg_cpy_direct direct); -#endif +void ssi_buffer_mgr_zero_sgl(struct scatterlist *sgl, u32 data_len); #endif /*__BUFFER_MGR_H__*/ diff --git a/drivers/staging/ccree/ssi_cipher.c b/drivers/staging/ccree/ssi_cipher.c index 664ed7e52cf2..cd2eafc04232 100644 --- a/drivers/staging/ccree/ssi_cipher.c +++ b/drivers/staging/ccree/ssi_cipher.c @@ -1,15 +1,15 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ @@ -36,7 +36,6 @@ #define MAX_ABLKCIPHER_SEQ_LEN 6 #define template_ablkcipher template_u.ablkcipher -#define template_sblkcipher template_u.blkcipher #define SSI_MIN_AES_XTS_SIZE 0x10 #define SSI_MAX_AES_XTS_SIZE 0x2000 @@ -45,12 +44,13 @@ struct ssi_blkcipher_handle { }; struct cc_user_key_info { - uint8_t *key; + u8 *key; dma_addr_t key_dma_addr; }; + struct cc_hw_key_info { - enum HwCryptoKey key1_slot; - enum HwCryptoKey key2_slot; + enum cc_hw_crypto_key key1_slot; + enum cc_hw_crypto_key key2_slot; }; struct ssi_ablkcipher_ctx { @@ -68,11 +68,10 @@ struct ssi_ablkcipher_ctx { static void ssi_ablkcipher_complete(struct device *dev, void *ssi_req, void __iomem *cc_base); - -static int validate_keys_sizes(struct ssi_ablkcipher_ctx *ctx_p, uint32_t size) { - switch (ctx_p->flow_mode){ +static int validate_keys_sizes(struct ssi_ablkcipher_ctx *ctx_p, u32 size) { + switch (ctx_p->flow_mode) { case S_DIN_to_AES: - switch (size){ + switch (size) { case CC_AES_128_BIT_KEY_SIZE: case CC_AES_192_BIT_KEY_SIZE: if (likely((ctx_p->cipher_mode != DRV_CIPHER_XTS) && @@ -82,8 +81,8 @@ static int validate_keys_sizes(struct ssi_ablkcipher_ctx *ctx_p, uint32_t size) break; case CC_AES_256_BIT_KEY_SIZE: return 0; - case (CC_AES_192_BIT_KEY_SIZE*2): - case (CC_AES_256_BIT_KEY_SIZE*2): + case (CC_AES_192_BIT_KEY_SIZE * 2): + case (CC_AES_256_BIT_KEY_SIZE * 2): if (likely((ctx_p->cipher_mode == DRV_CIPHER_XTS) || (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) || (ctx_p->cipher_mode == DRV_CIPHER_BITLOCKER))) @@ -105,19 +104,17 @@ static int validate_keys_sizes(struct ssi_ablkcipher_ctx *ctx_p, uint32_t size) #endif default: break; - } return -EINVAL; } - static int validate_data_size(struct ssi_ablkcipher_ctx *ctx_p, unsigned int size) { - switch (ctx_p->flow_mode){ + switch (ctx_p->flow_mode) { case S_DIN_to_AES: - switch (ctx_p->cipher_mode){ + switch (ctx_p->cipher_mode) { case DRV_CIPHER_XTS: if ((size >= SSI_MIN_AES_XTS_SIZE) && - (size <= SSI_MAX_AES_XTS_SIZE) && + (size <= SSI_MAX_AES_XTS_SIZE) && IS_ALIGNED(size, AES_BLOCK_SIZE)) return 0; break; @@ -159,7 +156,6 @@ static int validate_data_size(struct ssi_ablkcipher_ctx *ctx_p, unsigned int siz #endif /*SSI_CC_HAS_MULTI2*/ default: break; - } return -EINVAL; } @@ -168,13 +164,11 @@ static unsigned int get_max_keysize(struct crypto_tfm *tfm) { struct ssi_crypto_alg *ssi_alg = container_of(tfm->__crt_alg, struct ssi_crypto_alg, crypto_alg); - if ((ssi_alg->crypto_alg.cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_ABLKCIPHER) { + if ((ssi_alg->crypto_alg.cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_ABLKCIPHER) return ssi_alg->crypto_alg.cra_ablkcipher.max_keysize; - } - if ((ssi_alg->crypto_alg.cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_BLKCIPHER) { + if ((ssi_alg->crypto_alg.cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_BLKCIPHER) return ssi_alg->crypto_alg.cra_blkcipher.max_keysize; - } return 0; } @@ -189,7 +183,7 @@ static int ssi_blkcipher_init(struct crypto_tfm *tfm) int rc = 0; unsigned int max_key_buf_size = get_max_keysize(tfm); - SSI_LOG_DEBUG("Initializing context @%p for %s\n", ctx_p, + SSI_LOG_DEBUG("Initializing context @%p for %s\n", ctx_p, crypto_tfm_alg_name(tfm)); CHECK_AND_RETURN_UPON_FIPS_ERROR(); @@ -199,7 +193,7 @@ static int ssi_blkcipher_init(struct crypto_tfm *tfm) dev = &ctx_p->drvdata->plat_dev->dev; /* Allocate key buffer, cache line aligned */ - ctx_p->user.key = kmalloc(max_key_buf_size, GFP_KERNEL|GFP_DMA); + ctx_p->user.key = kmalloc(max_key_buf_size, GFP_KERNEL | GFP_DMA); if (!ctx_p->user.key) { SSI_LOG_ERR("Allocating key buffer in context failed\n"); rc = -ENOMEM; @@ -215,7 +209,6 @@ static int ssi_blkcipher_init(struct crypto_tfm *tfm) max_key_buf_size, ctx_p->user.key); return -ENOMEM; } - SSI_UPDATE_DMA_ADDR_TO_48BIT(ctx_p->user.key_dma_addr, max_key_buf_size); SSI_LOG_DEBUG("Mapped key %u B at va=%pK to dma=0x%llX\n", max_key_buf_size, ctx_p->user.key, (unsigned long long)ctx_p->user.key_dma_addr); @@ -248,10 +241,9 @@ static void ssi_blkcipher_exit(struct crypto_tfm *tfm) } /* Unmap key buffer */ - SSI_RESTORE_DMA_ADDR_TO_48BIT(ctx_p->user.key_dma_addr); dma_unmap_single(dev, ctx_p->user.key_dma_addr, max_key_buf_size, DMA_TO_DEVICE); - SSI_LOG_DEBUG("Unmapped key buffer key_dma_addr=0x%llX\n", + SSI_LOG_DEBUG("Unmapped key buffer key_dma_addr=0x%llX\n", (unsigned long long)ctx_p->user.key_dma_addr); /* Free key buffer in context */ @@ -259,50 +251,48 @@ static void ssi_blkcipher_exit(struct crypto_tfm *tfm) SSI_LOG_DEBUG("Free key buffer in context. key=@%p\n", ctx_p->user.key); } +struct tdes_keys { + u8 key1[DES_KEY_SIZE]; + u8 key2[DES_KEY_SIZE]; + u8 key3[DES_KEY_SIZE]; +}; -typedef struct tdes_keys{ - u8 key1[DES_KEY_SIZE]; - u8 key2[DES_KEY_SIZE]; - u8 key3[DES_KEY_SIZE]; -}tdes_keys_t; - -static const u8 zero_buff[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; +static const u8 zero_buff[] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; /* The function verifies that tdes keys are not weak.*/ static int ssi_fips_verify_3des_keys(const u8 *key, unsigned int keylen) { #ifdef CCREE_FIPS_SUPPORT - tdes_keys_t *tdes_key = (tdes_keys_t*)key; + struct tdes_keys *tdes_key = (struct tdes_keys *)key; /* verify key1 != key2 and key3 != key2*/ - if (unlikely( (memcmp((u8*)tdes_key->key1, (u8*)tdes_key->key2, sizeof(tdes_key->key1)) == 0) || - (memcmp((u8*)tdes_key->key3, (u8*)tdes_key->key2, sizeof(tdes_key->key3)) == 0) )) { - return -ENOEXEC; - } + if (unlikely((memcmp((u8 *)tdes_key->key1, (u8 *)tdes_key->key2, sizeof(tdes_key->key1)) == 0) || + (memcmp((u8 *)tdes_key->key3, (u8 *)tdes_key->key2, sizeof(tdes_key->key3)) == 0))) { + return -ENOEXEC; + } #endif /* CCREE_FIPS_SUPPORT */ - return 0; + return 0; } /* The function verifies that xts keys are not weak.*/ static int ssi_fips_verify_xts_keys(const u8 *key, unsigned int keylen) { #ifdef CCREE_FIPS_SUPPORT - /* Weak key is define as key that its first half (128/256 lsb) equals its second half (128/256 msb) */ - int singleKeySize = keylen >> 1; + /* Weak key is define as key that its first half (128/256 lsb) equals its second half (128/256 msb) */ + int singleKeySize = keylen >> 1; - if (unlikely(memcmp(key, &key[singleKeySize], singleKeySize) == 0)) { + if (unlikely(memcmp(key, &key[singleKeySize], singleKeySize) == 0)) return -ENOEXEC; - } #endif /* CCREE_FIPS_SUPPORT */ - return 0; + return 0; } -static enum HwCryptoKey hw_key_to_cc_hw_key(int slot_num) +static enum cc_hw_crypto_key hw_key_to_cc_hw_key(int slot_num) { switch (slot_num) { case 0: @@ -317,35 +307,32 @@ static enum HwCryptoKey hw_key_to_cc_hw_key(int slot_num) return END_OF_KEYS; } -static int ssi_blkcipher_setkey(struct crypto_tfm *tfm, - const u8 *key, +static int ssi_blkcipher_setkey(struct crypto_tfm *tfm, + const u8 *key, unsigned int keylen) { struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); struct device *dev = &ctx_p->drvdata->plat_dev->dev; u32 tmp[DES_EXPKEY_WORDS]; unsigned int max_key_buf_size = get_max_keysize(tfm); - DECL_CYCLE_COUNT_RESOURCES; SSI_LOG_DEBUG("Setting key in context @%p for %s. keylen=%u\n", ctx_p, crypto_tfm_alg_name(tfm), keylen); - dump_byte_array("key", (uint8_t *)key, keylen); + dump_byte_array("key", (u8 *)key, keylen); CHECK_AND_RETURN_UPON_FIPS_ERROR(); SSI_LOG_DEBUG("ssi_blkcipher_setkey: after FIPS check"); - + /* STAT_PHASE_0: Init and sanity checks */ - START_CYCLE_COUNT(); #if SSI_CC_HAS_MULTI2 /*last byte of key buffer is round number and should not be a part of key size*/ - if (ctx_p->flow_mode == S_DIN_to_MULTI2) { - keylen -=1; - } + if (ctx_p->flow_mode == S_DIN_to_MULTI2) + keylen -= 1; #endif /*SSI_CC_HAS_MULTI2*/ - if (unlikely(validate_keys_sizes(ctx_p,keylen) != 0)) { + if (unlikely(validate_keys_sizes(ctx_p, keylen) != 0)) { SSI_LOG_ERR("Unsupported key size %d.\n", keylen); crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); return -EINVAL; @@ -353,7 +340,7 @@ static int ssi_blkcipher_setkey(struct crypto_tfm *tfm, if (ssi_is_hw_key(tfm)) { /* setting HW key slots */ - struct arm_hw_key_info *hki = (struct arm_hw_key_info*)key; + struct arm_hw_key_info *hki = (struct arm_hw_key_info *)key; if (unlikely(ctx_p->flow_mode != S_DIN_to_AES)) { SSI_LOG_ERR("HW key not supported for non-AES flows\n"); @@ -381,7 +368,6 @@ static int ssi_blkcipher_setkey(struct crypto_tfm *tfm, } ctx_p->keylen = keylen; - END_CYCLE_COUNT(STAT_OP_TYPE_SETKEY, STAT_PHASE_0); SSI_LOG_DEBUG("ssi_blkcipher_setkey: ssi_is_hw_key ret 0"); return 0; @@ -396,28 +382,24 @@ static int ssi_blkcipher_setkey(struct crypto_tfm *tfm, return -EINVAL; } } - if ((ctx_p->cipher_mode == DRV_CIPHER_XTS) && + if ((ctx_p->cipher_mode == DRV_CIPHER_XTS) && ssi_fips_verify_xts_keys(key, keylen) != 0) { SSI_LOG_DEBUG("ssi_blkcipher_setkey: weak XTS key"); return -EINVAL; } - if ((ctx_p->flow_mode == S_DIN_to_DES) && - (keylen == DES3_EDE_KEY_SIZE) && + if ((ctx_p->flow_mode == S_DIN_to_DES) && + (keylen == DES3_EDE_KEY_SIZE) && ssi_fips_verify_3des_keys(key, keylen) != 0) { SSI_LOG_DEBUG("ssi_blkcipher_setkey: weak 3DES key"); return -EINVAL; } - - END_CYCLE_COUNT(STAT_OP_TYPE_SETKEY, STAT_PHASE_0); - /* STAT_PHASE_1: Copy key to ctx */ - START_CYCLE_COUNT(); - SSI_RESTORE_DMA_ADDR_TO_48BIT(ctx_p->user.key_dma_addr); - dma_sync_single_for_cpu(dev, ctx_p->user.key_dma_addr, + dma_sync_single_for_cpu(dev, ctx_p->user.key_dma_addr, max_key_buf_size, DMA_TO_DEVICE); -#if SSI_CC_HAS_MULTI2 + if (ctx_p->flow_mode == S_DIN_to_MULTI2) { +#if SSI_CC_HAS_MULTI2 memcpy(ctx_p->user.key, key, CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE); ctx_p->key_round_number = key[CC_MULTI2_SYSTEM_N_DATA_KEY_SIZE]; if (ctx_p->key_round_number < CC_MULTI2_MIN_NUM_ROUNDS || @@ -425,10 +407,8 @@ static int ssi_blkcipher_setkey(struct crypto_tfm *tfm, crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN); SSI_LOG_DEBUG("ssi_blkcipher_setkey: SSI_CC_HAS_MULTI2 einval"); return -EINVAL; - } - } else #endif /*SSI_CC_HAS_MULTI2*/ - { + } else { memcpy(ctx_p->user.key, key, keylen); if (keylen == 24) memset(ctx_p->user.key + 24, 0, CC_AES_KEY_SIZE_MAX - 24); @@ -438,6 +418,7 @@ static int ssi_blkcipher_setkey(struct crypto_tfm *tfm, int key_len = keylen >> 1; int err; SHASH_DESC_ON_STACK(desc, ctx_p->shash_tfm); + desc->tfm = ctx_p->shash_tfm; err = crypto_shash_digest(desc, ctx_p->user.key, key_len, ctx_p->user.key + key_len); @@ -447,12 +428,9 @@ static int ssi_blkcipher_setkey(struct crypto_tfm *tfm, } } } - dma_sync_single_for_device(dev, ctx_p->user.key_dma_addr, + dma_sync_single_for_device(dev, ctx_p->user.key_dma_addr, max_key_buf_size, DMA_TO_DEVICE); - SSI_UPDATE_DMA_ADDR_TO_48BIT(ctx_p->user.key_dma_addr ,max_key_buf_size); ctx_p->keylen = keylen; - - END_CYCLE_COUNT(STAT_OP_TYPE_SETKEY, STAT_PHASE_1); SSI_LOG_DEBUG("ssi_blkcipher_setkey: return safely"); return 0; @@ -464,7 +442,7 @@ ssi_blkcipher_create_setup_desc( struct blkcipher_req_ctx *req_ctx, unsigned int ivsize, unsigned int nbytes, - HwDesc_s desc[], + struct cc_hw_desc desc[], unsigned int *seq_size) { struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); @@ -489,96 +467,92 @@ ssi_blkcipher_create_setup_desc( case DRV_CIPHER_CTR: case DRV_CIPHER_OFB: /* Load cipher state */ - HW_DESC_INIT(&desc[*seq_size]); - HW_DESC_SET_DIN_TYPE(&desc[*seq_size], DMA_DLLI, - iv_dma_addr, ivsize, - NS_BIT); - HW_DESC_SET_CIPHER_CONFIG0(&desc[*seq_size], direction); - HW_DESC_SET_FLOW_MODE(&desc[*seq_size], flow_mode); - HW_DESC_SET_CIPHER_MODE(&desc[*seq_size], cipher_mode); - if ((cipher_mode == DRV_CIPHER_CTR) || - (cipher_mode == DRV_CIPHER_OFB) ) { - HW_DESC_SET_SETUP_MODE(&desc[*seq_size], - SETUP_LOAD_STATE1); + hw_desc_init(&desc[*seq_size]); + set_din_type(&desc[*seq_size], DMA_DLLI, iv_dma_addr, ivsize, + NS_BIT); + set_cipher_config0(&desc[*seq_size], direction); + set_flow_mode(&desc[*seq_size], flow_mode); + set_cipher_mode(&desc[*seq_size], cipher_mode); + if ((cipher_mode == DRV_CIPHER_CTR) || + (cipher_mode == DRV_CIPHER_OFB)) { + set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE1); } else { - HW_DESC_SET_SETUP_MODE(&desc[*seq_size], - SETUP_LOAD_STATE0); + set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE0); } (*seq_size)++; /*FALLTHROUGH*/ case DRV_CIPHER_ECB: /* Load key */ - HW_DESC_INIT(&desc[*seq_size]); - HW_DESC_SET_CIPHER_MODE(&desc[*seq_size], cipher_mode); - HW_DESC_SET_CIPHER_CONFIG0(&desc[*seq_size], direction); + hw_desc_init(&desc[*seq_size]); + set_cipher_mode(&desc[*seq_size], cipher_mode); + set_cipher_config0(&desc[*seq_size], direction); if (flow_mode == S_DIN_to_AES) { - if (ssi_is_hw_key(tfm)) { - HW_DESC_SET_HW_CRYPTO_KEY(&desc[*seq_size], ctx_p->hw.key1_slot); + set_hw_crypto_key(&desc[*seq_size], + ctx_p->hw.key1_slot); } else { - HW_DESC_SET_DIN_TYPE(&desc[*seq_size], DMA_DLLI, - key_dma_addr, - ((key_len == 24) ? AES_MAX_KEY_SIZE : key_len), - NS_BIT); + set_din_type(&desc[*seq_size], DMA_DLLI, + key_dma_addr, ((key_len == 24) ? + AES_MAX_KEY_SIZE : + key_len), NS_BIT); } - HW_DESC_SET_KEY_SIZE_AES(&desc[*seq_size], key_len); + set_key_size_aes(&desc[*seq_size], key_len); } else { /*des*/ - HW_DESC_SET_DIN_TYPE(&desc[*seq_size], DMA_DLLI, - key_dma_addr, key_len, - NS_BIT); - HW_DESC_SET_KEY_SIZE_DES(&desc[*seq_size], key_len); + set_din_type(&desc[*seq_size], DMA_DLLI, key_dma_addr, + key_len, NS_BIT); + set_key_size_des(&desc[*seq_size], key_len); } - HW_DESC_SET_FLOW_MODE(&desc[*seq_size], flow_mode); - HW_DESC_SET_SETUP_MODE(&desc[*seq_size], SETUP_LOAD_KEY0); + set_flow_mode(&desc[*seq_size], flow_mode); + set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0); (*seq_size)++; break; case DRV_CIPHER_XTS: case DRV_CIPHER_ESSIV: case DRV_CIPHER_BITLOCKER: /* Load AES key */ - HW_DESC_INIT(&desc[*seq_size]); - HW_DESC_SET_CIPHER_MODE(&desc[*seq_size], cipher_mode); - HW_DESC_SET_CIPHER_CONFIG0(&desc[*seq_size], direction); + hw_desc_init(&desc[*seq_size]); + set_cipher_mode(&desc[*seq_size], cipher_mode); + set_cipher_config0(&desc[*seq_size], direction); if (ssi_is_hw_key(tfm)) { - HW_DESC_SET_HW_CRYPTO_KEY(&desc[*seq_size], ctx_p->hw.key1_slot); + set_hw_crypto_key(&desc[*seq_size], + ctx_p->hw.key1_slot); } else { - HW_DESC_SET_DIN_TYPE(&desc[*seq_size], DMA_DLLI, - key_dma_addr, key_len/2, - NS_BIT); + set_din_type(&desc[*seq_size], DMA_DLLI, key_dma_addr, + (key_len / 2), NS_BIT); } - HW_DESC_SET_KEY_SIZE_AES(&desc[*seq_size], key_len/2); - HW_DESC_SET_FLOW_MODE(&desc[*seq_size], flow_mode); - HW_DESC_SET_SETUP_MODE(&desc[*seq_size], SETUP_LOAD_KEY0); + set_key_size_aes(&desc[*seq_size], (key_len / 2)); + set_flow_mode(&desc[*seq_size], flow_mode); + set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0); (*seq_size)++; /* load XEX key */ - HW_DESC_INIT(&desc[*seq_size]); - HW_DESC_SET_CIPHER_MODE(&desc[*seq_size], cipher_mode); - HW_DESC_SET_CIPHER_CONFIG0(&desc[*seq_size], direction); + hw_desc_init(&desc[*seq_size]); + set_cipher_mode(&desc[*seq_size], cipher_mode); + set_cipher_config0(&desc[*seq_size], direction); if (ssi_is_hw_key(tfm)) { - HW_DESC_SET_HW_CRYPTO_KEY(&desc[*seq_size], ctx_p->hw.key2_slot); + set_hw_crypto_key(&desc[*seq_size], + ctx_p->hw.key2_slot); } else { - HW_DESC_SET_DIN_TYPE(&desc[*seq_size], DMA_DLLI, - (key_dma_addr+key_len/2), key_len/2, - NS_BIT); + set_din_type(&desc[*seq_size], DMA_DLLI, + (key_dma_addr + (key_len / 2)), + (key_len / 2), NS_BIT); } - HW_DESC_SET_XEX_DATA_UNIT_SIZE(&desc[*seq_size], du_size); - HW_DESC_SET_FLOW_MODE(&desc[*seq_size], S_DIN_to_AES2); - HW_DESC_SET_KEY_SIZE_AES(&desc[*seq_size], key_len/2); - HW_DESC_SET_SETUP_MODE(&desc[*seq_size], SETUP_LOAD_XEX_KEY); + set_xex_data_unit_size(&desc[*seq_size], du_size); + set_flow_mode(&desc[*seq_size], S_DIN_to_AES2); + set_key_size_aes(&desc[*seq_size], (key_len / 2)); + set_setup_mode(&desc[*seq_size], SETUP_LOAD_XEX_KEY); (*seq_size)++; - + /* Set state */ - HW_DESC_INIT(&desc[*seq_size]); - HW_DESC_SET_SETUP_MODE(&desc[*seq_size], SETUP_LOAD_STATE1); - HW_DESC_SET_CIPHER_MODE(&desc[*seq_size], cipher_mode); - HW_DESC_SET_CIPHER_CONFIG0(&desc[*seq_size], direction); - HW_DESC_SET_KEY_SIZE_AES(&desc[*seq_size], key_len/2); - HW_DESC_SET_FLOW_MODE(&desc[*seq_size], flow_mode); - HW_DESC_SET_DIN_TYPE(&desc[*seq_size], DMA_DLLI, - iv_dma_addr, CC_AES_BLOCK_SIZE, - NS_BIT); + hw_desc_init(&desc[*seq_size]); + set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE1); + set_cipher_mode(&desc[*seq_size], cipher_mode); + set_cipher_config0(&desc[*seq_size], direction); + set_key_size_aes(&desc[*seq_size], (key_len / 2)); + set_flow_mode(&desc[*seq_size], flow_mode); + set_din_type(&desc[*seq_size], DMA_DLLI, iv_dma_addr, + CC_AES_BLOCK_SIZE, NS_BIT); (*seq_size)++; break; default: @@ -592,49 +566,43 @@ static inline void ssi_blkcipher_create_multi2_setup_desc( struct crypto_tfm *tfm, struct blkcipher_req_ctx *req_ctx, unsigned int ivsize, - HwDesc_s desc[], + struct cc_hw_desc desc[], unsigned int *seq_size) { struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); - + int direction = req_ctx->gen_ctx.op_type; /* Load system key */ - HW_DESC_INIT(&desc[*seq_size]); - HW_DESC_SET_CIPHER_MODE(&desc[*seq_size], ctx_p->cipher_mode); - HW_DESC_SET_CIPHER_CONFIG0(&desc[*seq_size], direction); - HW_DESC_SET_DIN_TYPE(&desc[*seq_size], DMA_DLLI, ctx_p->user.key_dma_addr, - CC_MULTI2_SYSTEM_KEY_SIZE, - NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[*seq_size], ctx_p->flow_mode); - HW_DESC_SET_SETUP_MODE(&desc[*seq_size], SETUP_LOAD_KEY0); + hw_desc_init(&desc[*seq_size]); + set_cipher_mode(&desc[*seq_size], ctx_p->cipher_mode); + set_cipher_config0(&desc[*seq_size], direction); + set_din_type(&desc[*seq_size], DMA_DLLI, ctx_p->user.key_dma_addr, + CC_MULTI2_SYSTEM_KEY_SIZE, NS_BIT); + set_flow_mode(&desc[*seq_size], ctx_p->flow_mode); + set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0); (*seq_size)++; /* load data key */ - HW_DESC_INIT(&desc[*seq_size]); - HW_DESC_SET_DIN_TYPE(&desc[*seq_size], DMA_DLLI, - (ctx_p->user.key_dma_addr + - CC_MULTI2_SYSTEM_KEY_SIZE), - CC_MULTI2_DATA_KEY_SIZE, NS_BIT); - HW_DESC_SET_MULTI2_NUM_ROUNDS(&desc[*seq_size], - ctx_p->key_round_number); - HW_DESC_SET_FLOW_MODE(&desc[*seq_size], ctx_p->flow_mode); - HW_DESC_SET_CIPHER_MODE(&desc[*seq_size], ctx_p->cipher_mode); - HW_DESC_SET_CIPHER_CONFIG0(&desc[*seq_size], direction); - HW_DESC_SET_SETUP_MODE(&desc[*seq_size], SETUP_LOAD_STATE0 ); + hw_desc_init(&desc[*seq_size]); + set_din_type(&desc[*seq_size], DMA_DLLI, + (ctx_p->user.key_dma_addr + CC_MULTI2_SYSTEM_KEY_SIZE), + CC_MULTI2_DATA_KEY_SIZE, NS_BIT); + set_multi2_num_rounds(&desc[*seq_size], ctx_p->key_round_number); + set_flow_mode(&desc[*seq_size], ctx_p->flow_mode); + set_cipher_mode(&desc[*seq_size], ctx_p->cipher_mode); + set_cipher_config0(&desc[*seq_size], direction); + set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE0); (*seq_size)++; - - + /* Set state */ - HW_DESC_INIT(&desc[*seq_size]); - HW_DESC_SET_DIN_TYPE(&desc[*seq_size], DMA_DLLI, - req_ctx->gen_ctx.iv_dma_addr, - ivsize, NS_BIT); - HW_DESC_SET_CIPHER_CONFIG0(&desc[*seq_size], direction); - HW_DESC_SET_FLOW_MODE(&desc[*seq_size], ctx_p->flow_mode); - HW_DESC_SET_CIPHER_MODE(&desc[*seq_size], ctx_p->cipher_mode); - HW_DESC_SET_SETUP_MODE(&desc[*seq_size], SETUP_LOAD_STATE1); + hw_desc_init(&desc[*seq_size]); + set_din_type(&desc[*seq_size], DMA_DLLI, req_ctx->gen_ctx.iv_dma_addr, + ivsize, NS_BIT); + set_cipher_config0(&desc[*seq_size], direction); + set_flow_mode(&desc[*seq_size], ctx_p->flow_mode); + set_cipher_mode(&desc[*seq_size], ctx_p->cipher_mode); + set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE1); (*seq_size)++; - } #endif /*SSI_CC_HAS_MULTI2*/ @@ -645,7 +613,7 @@ ssi_blkcipher_create_data_desc( struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes, void *areq, - HwDesc_s desc[], + struct cc_hw_desc desc[], unsigned int *seq_size) { struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); @@ -668,25 +636,22 @@ ssi_blkcipher_create_data_desc( return; } /* Process */ - if (likely(req_ctx->dma_buf_type == SSI_DMA_BUF_DLLI)){ + if (likely(req_ctx->dma_buf_type == SSI_DMA_BUF_DLLI)) { SSI_LOG_DEBUG(" data params addr 0x%llX length 0x%X \n", (unsigned long long)sg_dma_address(src), nbytes); SSI_LOG_DEBUG(" data params addr 0x%llX length 0x%X \n", (unsigned long long)sg_dma_address(dst), nbytes); - HW_DESC_INIT(&desc[*seq_size]); - HW_DESC_SET_DIN_TYPE(&desc[*seq_size], DMA_DLLI, - sg_dma_address(src), - nbytes, NS_BIT); - HW_DESC_SET_DOUT_DLLI(&desc[*seq_size], - sg_dma_address(dst), - nbytes, - NS_BIT, (areq == NULL)? 0:1); - if (areq != NULL) { - HW_DESC_SET_QUEUE_LAST_IND(&desc[*seq_size]); - } - HW_DESC_SET_FLOW_MODE(&desc[*seq_size], flow_mode); + hw_desc_init(&desc[*seq_size]); + set_din_type(&desc[*seq_size], DMA_DLLI, sg_dma_address(src), + nbytes, NS_BIT); + set_dout_dlli(&desc[*seq_size], sg_dma_address(dst), + nbytes, NS_BIT, (!areq ? 0 : 1)); + if (areq) + set_queue_last_ind(&desc[*seq_size]); + + set_flow_mode(&desc[*seq_size], flow_mode); (*seq_size)++; } else { /* bypass */ @@ -695,77 +660,72 @@ ssi_blkcipher_create_data_desc( (unsigned long long)req_ctx->mlli_params.mlli_dma_addr, req_ctx->mlli_params.mlli_len, (unsigned int)ctx_p->drvdata->mlli_sram_addr); - HW_DESC_INIT(&desc[*seq_size]); - HW_DESC_SET_DIN_TYPE(&desc[*seq_size], DMA_DLLI, - req_ctx->mlli_params.mlli_dma_addr, - req_ctx->mlli_params.mlli_len, - NS_BIT); - HW_DESC_SET_DOUT_SRAM(&desc[*seq_size], - ctx_p->drvdata->mlli_sram_addr, - req_ctx->mlli_params.mlli_len); - HW_DESC_SET_FLOW_MODE(&desc[*seq_size], BYPASS); + hw_desc_init(&desc[*seq_size]); + set_din_type(&desc[*seq_size], DMA_DLLI, + req_ctx->mlli_params.mlli_dma_addr, + req_ctx->mlli_params.mlli_len, NS_BIT); + set_dout_sram(&desc[*seq_size], + ctx_p->drvdata->mlli_sram_addr, + req_ctx->mlli_params.mlli_len); + set_flow_mode(&desc[*seq_size], BYPASS); (*seq_size)++; - HW_DESC_INIT(&desc[*seq_size]); - HW_DESC_SET_DIN_TYPE(&desc[*seq_size], DMA_MLLI, - ctx_p->drvdata->mlli_sram_addr, - req_ctx->in_mlli_nents, NS_BIT); + hw_desc_init(&desc[*seq_size]); + set_din_type(&desc[*seq_size], DMA_MLLI, + ctx_p->drvdata->mlli_sram_addr, + req_ctx->in_mlli_nents, NS_BIT); if (req_ctx->out_nents == 0) { SSI_LOG_DEBUG(" din/dout params addr 0x%08X " "addr 0x%08X\n", (unsigned int)ctx_p->drvdata->mlli_sram_addr, (unsigned int)ctx_p->drvdata->mlli_sram_addr); - HW_DESC_SET_DOUT_MLLI(&desc[*seq_size], - ctx_p->drvdata->mlli_sram_addr, - req_ctx->in_mlli_nents, - NS_BIT,(areq == NULL)? 0:1); + set_dout_mlli(&desc[*seq_size], + ctx_p->drvdata->mlli_sram_addr, + req_ctx->in_mlli_nents, NS_BIT, + (!areq ? 0 : 1)); } else { SSI_LOG_DEBUG(" din/dout params " "addr 0x%08X addr 0x%08X\n", (unsigned int)ctx_p->drvdata->mlli_sram_addr, - (unsigned int)ctx_p->drvdata->mlli_sram_addr + - (uint32_t)LLI_ENTRY_BYTE_SIZE * + (unsigned int)ctx_p->drvdata->mlli_sram_addr + + (u32)LLI_ENTRY_BYTE_SIZE * req_ctx->in_nents); - HW_DESC_SET_DOUT_MLLI(&desc[*seq_size], - (ctx_p->drvdata->mlli_sram_addr + - LLI_ENTRY_BYTE_SIZE * - req_ctx->in_mlli_nents), - req_ctx->out_mlli_nents, NS_BIT,(areq == NULL)? 0:1); + set_dout_mlli(&desc[*seq_size], + (ctx_p->drvdata->mlli_sram_addr + + (LLI_ENTRY_BYTE_SIZE * + req_ctx->in_mlli_nents)), + req_ctx->out_mlli_nents, NS_BIT, + (!areq ? 0 : 1)); } - if (areq != NULL) { - HW_DESC_SET_QUEUE_LAST_IND(&desc[*seq_size]); - } - HW_DESC_SET_FLOW_MODE(&desc[*seq_size], flow_mode); + if (areq) + set_queue_last_ind(&desc[*seq_size]); + + set_flow_mode(&desc[*seq_size], flow_mode); (*seq_size)++; } } static int ssi_blkcipher_complete(struct device *dev, - struct ssi_ablkcipher_ctx *ctx_p, - struct blkcipher_req_ctx *req_ctx, - struct scatterlist *dst, struct scatterlist *src, - void *info, //req info - unsigned int ivsize, - void *areq, - void __iomem *cc_base) + struct ssi_ablkcipher_ctx *ctx_p, + struct blkcipher_req_ctx *req_ctx, + struct scatterlist *dst, + struct scatterlist *src, + unsigned int ivsize, + void *areq, + void __iomem *cc_base) { int completion_error = 0; - uint32_t inflight_counter; - DECL_CYCLE_COUNT_RESOURCES; + u32 inflight_counter; - START_CYCLE_COUNT(); ssi_buffer_mgr_unmap_blkcipher_request(dev, req_ctx, ivsize, src, dst); - info = req_ctx->backup_info; - END_CYCLE_COUNT(STAT_OP_TYPE_GENERIC, STAT_PHASE_4); - /*Set the inflight couter value to local variable*/ inflight_counter = ctx_p->drvdata->inflight_counter; /*Decrease the inflight counter*/ - if(ctx_p->flow_mode == BYPASS && ctx_p->drvdata->inflight_counter > 0) + if (ctx_p->flow_mode == BYPASS && ctx_p->drvdata->inflight_counter > 0) ctx_p->drvdata->inflight_counter--; - if(areq){ + if (areq) { ablkcipher_request_complete(areq, completion_error); return 0; } @@ -779,24 +739,22 @@ static int ssi_blkcipher_process( unsigned int nbytes, void *info, //req info unsigned int ivsize, - void *areq, + void *areq, enum drv_crypto_direction direction) { struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); struct device *dev = &ctx_p->drvdata->plat_dev->dev; - HwDesc_s desc[MAX_ABLKCIPHER_SEQ_LEN]; + struct cc_hw_desc desc[MAX_ABLKCIPHER_SEQ_LEN]; struct ssi_crypto_req ssi_req = {}; - int rc, seq_len = 0,cts_restore_flag = 0; - DECL_CYCLE_COUNT_RESOURCES; + int rc, seq_len = 0, cts_restore_flag = 0; SSI_LOG_DEBUG("%s areq=%p info=%p nbytes=%d\n", - ((direction==DRV_CRYPTO_DIRECTION_ENCRYPT)?"Encrypt":"Decrypt"), + ((direction == DRV_CRYPTO_DIRECTION_ENCRYPT) ? "Encrypt" : "Decrypt"), areq, info, nbytes); CHECK_AND_RETURN_UPON_FIPS_ERROR(); /* STAT_PHASE_0: Init and sanity checks */ - START_CYCLE_COUNT(); - + /* TODO: check data length according to mode */ if (unlikely(validate_data_size(ctx_p, nbytes))) { SSI_LOG_ERR("Unsupported data size %d.\n", nbytes); @@ -807,9 +765,8 @@ static int ssi_blkcipher_process( /* No data to process is valid */ return 0; } - /*For CTS in case of data size aligned to 16 use CBC mode*/ - if (((nbytes % AES_BLOCK_SIZE) == 0) && (ctx_p->cipher_mode == DRV_CIPHER_CBC_CTS)){ - + /*For CTS in case of data size aligned to 16 use CBC mode*/ + if (((nbytes % AES_BLOCK_SIZE) == 0) && (ctx_p->cipher_mode == DRV_CIPHER_CBC_CTS)) { ctx_p->cipher_mode = DRV_CIPHER_CBC; cts_restore_flag = 1; } @@ -826,83 +783,65 @@ static int ssi_blkcipher_process( /* Setup request context */ req_ctx->gen_ctx.op_type = direction; - - END_CYCLE_COUNT(ssi_req.op_type, STAT_PHASE_0); /* STAT_PHASE_1: Map buffers */ - START_CYCLE_COUNT(); - + rc = ssi_buffer_mgr_map_blkcipher_request(ctx_p->drvdata, req_ctx, ivsize, nbytes, info, src, dst); if (unlikely(rc != 0)) { SSI_LOG_ERR("map_request() failed\n"); goto exit_process; } - END_CYCLE_COUNT(ssi_req.op_type, STAT_PHASE_1); - /* STAT_PHASE_2: Create sequence */ - START_CYCLE_COUNT(); /* Setup processing */ #if SSI_CC_HAS_MULTI2 - if (ctx_p->flow_mode == S_DIN_to_MULTI2) { - ssi_blkcipher_create_multi2_setup_desc(tfm, - req_ctx, - ivsize, - desc, - &seq_len); - } else + if (ctx_p->flow_mode == S_DIN_to_MULTI2) + ssi_blkcipher_create_multi2_setup_desc(tfm, req_ctx, ivsize, + desc, &seq_len); + else #endif /*SSI_CC_HAS_MULTI2*/ - { - ssi_blkcipher_create_setup_desc(tfm, - req_ctx, - ivsize, - nbytes, - desc, - &seq_len); - } + ssi_blkcipher_create_setup_desc(tfm, req_ctx, ivsize, nbytes, + desc, &seq_len); /* Data processing */ ssi_blkcipher_create_data_desc(tfm, - req_ctx, + req_ctx, dst, src, nbytes, areq, desc, &seq_len); /* do we need to generate IV? */ - if (req_ctx->is_giv == true) { + if (req_ctx->is_giv) { ssi_req.ivgen_dma_addr[0] = req_ctx->gen_ctx.iv_dma_addr; ssi_req.ivgen_dma_addr_len = 1; /* set the IV size (8/16 B long)*/ ssi_req.ivgen_size = ivsize; } - END_CYCLE_COUNT(ssi_req.op_type, STAT_PHASE_2); /* STAT_PHASE_3: Lock HW and push sequence */ - START_CYCLE_COUNT(); - - rc = send_request(ctx_p->drvdata, &ssi_req, desc, seq_len, (areq == NULL)? 0:1); - if(areq != NULL) { + + rc = send_request(ctx_p->drvdata, &ssi_req, desc, seq_len, (!areq) ? 0 : 1); + if (areq) { if (unlikely(rc != -EINPROGRESS)) { /* Failed to send the request or request completed synchronously */ ssi_buffer_mgr_unmap_blkcipher_request(dev, req_ctx, ivsize, src, dst); } - END_CYCLE_COUNT(ssi_req.op_type, STAT_PHASE_3); } else { if (rc != 0) { ssi_buffer_mgr_unmap_blkcipher_request(dev, req_ctx, ivsize, src, dst); - END_CYCLE_COUNT(ssi_req.op_type, STAT_PHASE_3); } else { - END_CYCLE_COUNT(ssi_req.op_type, STAT_PHASE_3); - rc = ssi_blkcipher_complete(dev, ctx_p, req_ctx, dst, src, info, ivsize, NULL, ctx_p->drvdata->cc_base); - } + rc = ssi_blkcipher_complete(dev, ctx_p, req_ctx, dst, + src, ivsize, NULL, + ctx_p->drvdata->cc_base); + } } exit_process: if (cts_restore_flag != 0) ctx_p->cipher_mode = DRV_CIPHER_CBC_CTS; - + return rc; } @@ -916,86 +855,23 @@ static void ssi_ablkcipher_complete(struct device *dev, void *ssi_req, void __io CHECK_AND_RETURN_VOID_UPON_FIPS_ERROR(); - ssi_blkcipher_complete(dev, ctx_p, req_ctx, areq->dst, areq->src, areq->info, ivsize, areq, cc_base); -} - - - -static int ssi_sblkcipher_init(struct crypto_tfm *tfm) -{ - struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); - - /* Allocate sync ctx buffer */ - ctx_p->sync_ctx = kmalloc(sizeof(struct blkcipher_req_ctx), GFP_KERNEL|GFP_DMA); - if (!ctx_p->sync_ctx) { - SSI_LOG_ERR("Allocating sync ctx buffer in context failed\n"); - return -ENOMEM; - } - SSI_LOG_DEBUG("Allocated sync ctx buffer in context ctx_p->sync_ctx=@%p\n", - ctx_p->sync_ctx); - - return ssi_blkcipher_init(tfm); -} - - -static void ssi_sblkcipher_exit(struct crypto_tfm *tfm) -{ - struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); - - kfree(ctx_p->sync_ctx); - SSI_LOG_DEBUG("Free sync ctx buffer in context ctx_p->sync_ctx=@%p\n", ctx_p->sync_ctx); - - ssi_blkcipher_exit(tfm); -} - -#ifdef SYNC_ALGS -static int ssi_sblkcipher_encrypt(struct blkcipher_desc *desc, - struct scatterlist *dst, struct scatterlist *src, - unsigned int nbytes) -{ - struct crypto_blkcipher *blk_tfm = desc->tfm; - struct crypto_tfm *tfm = crypto_blkcipher_tfm(blk_tfm); - struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); - struct blkcipher_req_ctx *req_ctx = ctx_p->sync_ctx; - unsigned int ivsize = crypto_blkcipher_ivsize(blk_tfm); - - req_ctx->backup_info = desc->info; - req_ctx->is_giv = false; - - return ssi_blkcipher_process(tfm, req_ctx, dst, src, nbytes, desc->info, ivsize, NULL, DRV_CRYPTO_DIRECTION_ENCRYPT); -} - -static int ssi_sblkcipher_decrypt(struct blkcipher_desc *desc, - struct scatterlist *dst, struct scatterlist *src, - unsigned int nbytes) -{ - struct crypto_blkcipher *blk_tfm = desc->tfm; - struct crypto_tfm *tfm = crypto_blkcipher_tfm(blk_tfm); - struct ssi_ablkcipher_ctx *ctx_p = crypto_tfm_ctx(tfm); - struct blkcipher_req_ctx *req_ctx = ctx_p->sync_ctx; - unsigned int ivsize = crypto_blkcipher_ivsize(blk_tfm); - - req_ctx->backup_info = desc->info; - req_ctx->is_giv = false; - - return ssi_blkcipher_process(tfm, req_ctx, dst, src, nbytes, desc->info, ivsize, NULL, DRV_CRYPTO_DIRECTION_DECRYPT); + ssi_blkcipher_complete(dev, ctx_p, req_ctx, areq->dst, areq->src, + ivsize, areq, cc_base); } -#endif /* Async wrap functions */ static int ssi_ablkcipher_init(struct crypto_tfm *tfm) { struct ablkcipher_tfm *ablktfm = &tfm->crt_ablkcipher; - + ablktfm->reqsize = sizeof(struct blkcipher_req_ctx); return ssi_blkcipher_init(tfm); } - -static int ssi_ablkcipher_setkey(struct crypto_ablkcipher *tfm, - const u8 *key, +static int ssi_ablkcipher_setkey(struct crypto_ablkcipher *tfm, + const u8 *key, unsigned int keylen) { return ssi_blkcipher_setkey(crypto_ablkcipher_tfm(tfm), key, keylen); @@ -1026,7 +902,6 @@ static int ssi_ablkcipher_decrypt(struct ablkcipher_request *req) return ssi_blkcipher_process(tfm, req_ctx, req->dst, req->src, req->nbytes, req->info, ivsize, (void *)req, DRV_CRYPTO_DIRECTION_DECRYPT); } - /* DX Block cipher alg */ static struct ssi_alg_template blkcipher_algs[] = { /* Async template */ @@ -1047,7 +922,6 @@ static struct ssi_alg_template blkcipher_algs[] = { }, .cipher_mode = DRV_CIPHER_XTS, .flow_mode = S_DIN_to_AES, - .synchronous = false, }, { .name = "xts(aes)", @@ -1064,7 +938,6 @@ static struct ssi_alg_template blkcipher_algs[] = { }, .cipher_mode = DRV_CIPHER_XTS, .flow_mode = S_DIN_to_AES, - .synchronous = false, }, { .name = "xts(aes)", @@ -1081,7 +954,6 @@ static struct ssi_alg_template blkcipher_algs[] = { }, .cipher_mode = DRV_CIPHER_XTS, .flow_mode = S_DIN_to_AES, - .synchronous = false, }, #endif /*SSI_CC_HAS_AES_XTS*/ #if SSI_CC_HAS_AES_ESSIV @@ -1100,7 +972,6 @@ static struct ssi_alg_template blkcipher_algs[] = { }, .cipher_mode = DRV_CIPHER_ESSIV, .flow_mode = S_DIN_to_AES, - .synchronous = false, }, { .name = "essiv(aes)", @@ -1117,7 +988,6 @@ static struct ssi_alg_template blkcipher_algs[] = { }, .cipher_mode = DRV_CIPHER_ESSIV, .flow_mode = S_DIN_to_AES, - .synchronous = false, }, { .name = "essiv(aes)", @@ -1134,7 +1004,6 @@ static struct ssi_alg_template blkcipher_algs[] = { }, .cipher_mode = DRV_CIPHER_ESSIV, .flow_mode = S_DIN_to_AES, - .synchronous = false, }, #endif /*SSI_CC_HAS_AES_ESSIV*/ #if SSI_CC_HAS_AES_BITLOCKER @@ -1153,7 +1022,6 @@ static struct ssi_alg_template blkcipher_algs[] = { }, .cipher_mode = DRV_CIPHER_BITLOCKER, .flow_mode = S_DIN_to_AES, - .synchronous = false, }, { .name = "bitlocker(aes)", @@ -1170,7 +1038,6 @@ static struct ssi_alg_template blkcipher_algs[] = { }, .cipher_mode = DRV_CIPHER_BITLOCKER, .flow_mode = S_DIN_to_AES, - .synchronous = false, }, { .name = "bitlocker(aes)", @@ -1187,7 +1054,6 @@ static struct ssi_alg_template blkcipher_algs[] = { }, .cipher_mode = DRV_CIPHER_BITLOCKER, .flow_mode = S_DIN_to_AES, - .synchronous = false, }, #endif /*SSI_CC_HAS_AES_BITLOCKER*/ { @@ -1205,7 +1071,6 @@ static struct ssi_alg_template blkcipher_algs[] = { }, .cipher_mode = DRV_CIPHER_ECB, .flow_mode = S_DIN_to_AES, - .synchronous = false, }, { .name = "cbc(aes)", @@ -1219,10 +1084,9 @@ static struct ssi_alg_template blkcipher_algs[] = { .min_keysize = AES_MIN_KEY_SIZE, .max_keysize = AES_MAX_KEY_SIZE, .ivsize = AES_BLOCK_SIZE, - }, + }, .cipher_mode = DRV_CIPHER_CBC, .flow_mode = S_DIN_to_AES, - .synchronous = false, }, { .name = "ofb(aes)", @@ -1239,7 +1103,6 @@ static struct ssi_alg_template blkcipher_algs[] = { }, .cipher_mode = DRV_CIPHER_OFB, .flow_mode = S_DIN_to_AES, - .synchronous = false, }, #if SSI_CC_HAS_AES_CTS { @@ -1257,7 +1120,6 @@ static struct ssi_alg_template blkcipher_algs[] = { }, .cipher_mode = DRV_CIPHER_CBC_CTS, .flow_mode = S_DIN_to_AES, - .synchronous = false, }, #endif { @@ -1275,7 +1137,6 @@ static struct ssi_alg_template blkcipher_algs[] = { }, .cipher_mode = DRV_CIPHER_CTR, .flow_mode = S_DIN_to_AES, - .synchronous = false, }, { .name = "cbc(des3_ede)", @@ -1292,7 +1153,6 @@ static struct ssi_alg_template blkcipher_algs[] = { }, .cipher_mode = DRV_CIPHER_CBC, .flow_mode = S_DIN_to_DES, - .synchronous = false, }, { .name = "ecb(des3_ede)", @@ -1309,7 +1169,6 @@ static struct ssi_alg_template blkcipher_algs[] = { }, .cipher_mode = DRV_CIPHER_ECB, .flow_mode = S_DIN_to_DES, - .synchronous = false, }, { .name = "cbc(des)", @@ -1326,7 +1185,6 @@ static struct ssi_alg_template blkcipher_algs[] = { }, .cipher_mode = DRV_CIPHER_CBC, .flow_mode = S_DIN_to_DES, - .synchronous = false, }, { .name = "ecb(des)", @@ -1343,7 +1201,6 @@ static struct ssi_alg_template blkcipher_algs[] = { }, .cipher_mode = DRV_CIPHER_ECB, .flow_mode = S_DIN_to_DES, - .synchronous = false, }, #if SSI_CC_HAS_MULTI2 { @@ -1361,7 +1218,6 @@ static struct ssi_alg_template blkcipher_algs[] = { }, .cipher_mode = DRV_MULTI2_CBC, .flow_mode = S_DIN_to_MULTI2, - .synchronous = false, }, { .name = "ofb(multi2)", @@ -1378,12 +1234,11 @@ static struct ssi_alg_template blkcipher_algs[] = { }, .cipher_mode = DRV_MULTI2_OFB, .flow_mode = S_DIN_to_MULTI2, - .synchronous = false, }, #endif /*SSI_CC_HAS_MULTI2*/ }; -static +static struct ssi_crypto_alg *ssi_ablkcipher_create_alg(struct ssi_alg_template *template) { struct ssi_crypto_alg *t_alg; @@ -1405,19 +1260,13 @@ struct ssi_crypto_alg *ssi_ablkcipher_create_alg(struct ssi_alg_template *templa alg->cra_blocksize = template->blocksize; alg->cra_alignmask = 0; alg->cra_ctxsize = sizeof(struct ssi_ablkcipher_ctx); - - alg->cra_init = template->synchronous? ssi_sblkcipher_init:ssi_ablkcipher_init; - alg->cra_exit = template->synchronous? ssi_sblkcipher_exit:ssi_blkcipher_exit; - alg->cra_type = template->synchronous? &crypto_blkcipher_type:&crypto_ablkcipher_type; - if(template->synchronous) { - alg->cra_blkcipher = template->template_sblkcipher; - alg->cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | - template->type; - } else { - alg->cra_ablkcipher = template->template_ablkcipher; - alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY | + + alg->cra_init = ssi_ablkcipher_init; + alg->cra_exit = ssi_blkcipher_exit; + alg->cra_type = &crypto_ablkcipher_type; + alg->cra_ablkcipher = template->template_ablkcipher; + alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY | template->type; - } t_alg->cipher_mode = template->cipher_mode; t_alg->flow_mode = template->flow_mode; @@ -1428,12 +1277,13 @@ struct ssi_crypto_alg *ssi_ablkcipher_create_alg(struct ssi_alg_template *templa int ssi_ablkcipher_free(struct ssi_drvdata *drvdata) { struct ssi_crypto_alg *t_alg, *n; - struct ssi_blkcipher_handle *blkcipher_handle = + struct ssi_blkcipher_handle *blkcipher_handle = drvdata->blkcipher_handle; struct device *dev; + dev = &drvdata->plat_dev->dev; - if (blkcipher_handle != NULL) { + if (blkcipher_handle) { /* Remove registered algs */ list_for_each_entry_safe(t_alg, n, &blkcipher_handle->blkcipher_alg_list, @@ -1448,8 +1298,6 @@ int ssi_ablkcipher_free(struct ssi_drvdata *drvdata) return 0; } - - int ssi_ablkcipher_alloc(struct ssi_drvdata *drvdata) { struct ssi_blkcipher_handle *ablkcipher_handle; @@ -1459,7 +1307,7 @@ int ssi_ablkcipher_alloc(struct ssi_drvdata *drvdata) ablkcipher_handle = kmalloc(sizeof(struct ssi_blkcipher_handle), GFP_KERNEL); - if (ablkcipher_handle == NULL) + if (!ablkcipher_handle) return -ENOMEM; drvdata->blkcipher_handle = ablkcipher_handle; @@ -1489,9 +1337,9 @@ int ssi_ablkcipher_alloc(struct ssi_drvdata *drvdata) kfree(t_alg); goto fail0; } else { - list_add_tail(&t_alg->entry, + list_add_tail(&t_alg->entry, &ablkcipher_handle->blkcipher_alg_list); - SSI_LOG_DEBUG("Registered %s\n", + SSI_LOG_DEBUG("Registered %s\n", t_alg->crypto_alg.cra_driver_name); } } diff --git a/drivers/staging/ccree/ssi_cipher.h b/drivers/staging/ccree/ssi_cipher.h index ba4eb7c4893f..296b375d5d89 100644 --- a/drivers/staging/ccree/ssi_cipher.h +++ b/drivers/staging/ccree/ssi_cipher.h @@ -1,21 +1,21 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ /* \file ssi_cipher.h - ARM CryptoCell Cipher Crypto API + * ARM CryptoCell Cipher Crypto API */ #ifndef __SSI_CIPHER_H__ @@ -26,7 +26,6 @@ #include "ssi_driver.h" #include "ssi_buffer_mgr.h" - /* Crypto cipher flags */ #define CC_CRYPTO_CIPHER_KEY_KFDE0 (1 << 0) #define CC_CRYPTO_CIPHER_KEY_KFDE1 (1 << 1) @@ -36,21 +35,18 @@ #define CC_CRYPTO_CIPHER_KEY_KFDE_MASK (CC_CRYPTO_CIPHER_KEY_KFDE0 | CC_CRYPTO_CIPHER_KEY_KFDE1 | CC_CRYPTO_CIPHER_KEY_KFDE2 | CC_CRYPTO_CIPHER_KEY_KFDE3) - struct blkcipher_req_ctx { struct async_gen_req_ctx gen_ctx; enum ssi_req_dma_buf_type dma_buf_type; - uint32_t in_nents; - uint32_t in_mlli_nents; - uint32_t out_nents; - uint32_t out_mlli_nents; - uint8_t *backup_info; /*store iv for generated IV flow*/ + u32 in_nents; + u32 in_mlli_nents; + u32 out_nents; + u32 out_mlli_nents; + u8 *backup_info; /*store iv for generated IV flow*/ bool is_giv; struct mlli_params mlli_params; }; - - int ssi_ablkcipher_alloc(struct ssi_drvdata *drvdata); int ssi_ablkcipher_free(struct ssi_drvdata *drvdata); @@ -63,7 +59,6 @@ int ssi_ablkcipher_free(struct ssi_drvdata *drvdata); CRYPTO_ALG_BULK_DU_4096) #endif /* CRYPTO_ALG_BULK_MASK */ - #ifdef CRYPTO_TFM_REQ_HW_KEY static inline bool ssi_is_hw_key(struct crypto_tfm *tfm) @@ -71,7 +66,7 @@ static inline bool ssi_is_hw_key(struct crypto_tfm *tfm) return (crypto_tfm_get_flags(tfm) & CRYPTO_TFM_REQ_HW_KEY); } -#else +#else struct arm_hw_key_info { int hw_key1; @@ -85,5 +80,4 @@ static inline bool ssi_is_hw_key(struct crypto_tfm *tfm) #endif /* CRYPTO_TFM_REQ_HW_KEY */ - #endif /*__SSI_CIPHER_H__*/ diff --git a/drivers/staging/ccree/ssi_config.h b/drivers/staging/ccree/ssi_config.h index d96a5436f6d7..ff7597c2d77e 100644 --- a/drivers/staging/ccree/ssi_config.h +++ b/drivers/staging/ccree/ssi_config.h @@ -1,21 +1,21 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ /* \file ssi_config.h - Definitions for ARM CryptoCell Linux Crypto Driver + * Definitions for ARM CryptoCell Linux Crypto Driver */ #ifndef __SSI_CONFIG_H__ @@ -23,39 +23,14 @@ #include <linux/version.h> -#define DISABLE_COHERENT_DMA_OPS //#define FLUSH_CACHE_ALL //#define COMPLETION_DELAY //#define DX_DUMP_DESCS // #define DX_DUMP_BYTES // #define CC_DEBUG #define ENABLE_CC_SYSFS /* Enable sysfs interface for debugging REE driver */ -//#define ENABLE_CC_CYCLE_COUNT //#define DX_IRQ_DELAY 100000 #define DMA_BIT_MASK_LEN 48 /* was 32 bit, but for juno's sake it was enlarged to 48 bit */ -#if defined ENABLE_CC_CYCLE_COUNT && defined ENABLE_CC_SYSFS -#define CC_CYCLE_COUNT -#endif - - -#if defined (CONFIG_ARM64) // TODO currently only this mode was test on Juno (which is ARM64), need to enable coherent also. -#define DISABLE_COHERENT_DMA_OPS -#endif - -/* Define the CryptoCell DMA cache coherency signals configuration */ -#if defined (DISABLE_COHERENT_DMA_OPS) - /* Software Controlled Cache Coherency (SCCC) */ - #define SSI_CACHE_PARAMS (0x000) - /* CC attached to NONE-ACP such as HPP/ACE/AMBA4. - * The customer is responsible to enable/disable this feature - * according to his platform type. */ - #define DX_HAS_ACP 0 -#else - #define SSI_CACHE_PARAMS (0xEEE) - /* CC attached to ACP */ - #define DX_HAS_ACP 1 -#endif - #endif /*__DX_CONFIG_H__*/ diff --git a/drivers/staging/ccree/ssi_driver.c b/drivers/staging/ccree/ssi_driver.c index bc19adce6dee..78709b92736d 100644 --- a/drivers/staging/ccree/ssi_driver.c +++ b/drivers/staging/ccree/ssi_driver.c @@ -1,15 +1,15 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ @@ -57,6 +57,8 @@ #include <linux/sched.h> #include <linux/random.h> #include <linux/of.h> +#include <linux/clk.h> +#include <linux/of_address.h> #include "ssi_config.h" #include "ssi_driver.h" @@ -71,15 +73,14 @@ #include "ssi_pm.h" #include "ssi_fips_local.h" - #ifdef DX_DUMP_BYTES -void dump_byte_array(const char *name, const uint8_t *the_array, unsigned long size) +void dump_byte_array(const char *name, const u8 *the_array, unsigned long size) { - int i , line_offset = 0, ret = 0; - const uint8_t *cur_byte; + int i, line_offset = 0, ret = 0; + const u8 *cur_byte; char line_buf[80]; - if (the_array == NULL) { + if (!the_array) { SSI_LOG_ERR("cannot dump_byte_array - NULL pointer\n"); return; } @@ -87,17 +88,17 @@ void dump_byte_array(const char *name, const uint8_t *the_array, unsigned long s ret = snprintf(line_buf, sizeof(line_buf), "%s[%lu]: ", name, size); if (ret < 0) { - SSI_LOG_ERR("snprintf returned %d . aborting buffer array dump\n",ret); + SSI_LOG_ERR("snprintf returned %d . aborting buffer array dump\n", ret); return; } line_offset = ret; - for (i = 0 , cur_byte = the_array; + for (i = 0, cur_byte = the_array; (i < size) && (line_offset < sizeof(line_buf)); i++, cur_byte++) { ret = snprintf(line_buf + line_offset, sizeof(line_buf) - line_offset, "0x%02X ", *cur_byte); if (ret < 0) { - SSI_LOG_ERR("snprintf returned %d . aborting buffer array dump\n",ret); + SSI_LOG_ERR("snprintf returned %d . aborting buffer array dump\n", ret); return; } line_offset += ret; @@ -116,12 +117,10 @@ static irqreturn_t cc_isr(int irq, void *dev_id) { struct ssi_drvdata *drvdata = (struct ssi_drvdata *)dev_id; void __iomem *cc_base = drvdata->cc_base; - uint32_t irr; - uint32_t imr; - DECL_CYCLE_COUNT_RESOURCES; + u32 irr; + u32 imr; /* STAT_OP_TYPE_GENERIC STAT_PHASE_0: Interrupt */ - START_CYCLE_COUNT(); /* read the interrupt status */ irr = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IRR)); @@ -154,12 +153,12 @@ static irqreturn_t cc_isr(int irq, void *dev_id) #endif /* AXI error interrupt */ if (unlikely((irr & SSI_AXI_ERR_IRQ_MASK) != 0)) { - uint32_t axi_err; - + u32 axi_err; + /* Read the AXI error ID */ axi_err = CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_ERR)); SSI_LOG_DEBUG("AXI completion error: axim_mon_err=0x%08X\n", axi_err); - + irr &= ~SSI_AXI_ERR_IRQ_MASK; } @@ -168,15 +167,12 @@ static irqreturn_t cc_isr(int irq, void *dev_id) /* Just warning */ } - END_CYCLE_COUNT(STAT_OP_TYPE_GENERIC, STAT_PHASE_0); - START_CYCLE_COUNT_AT(drvdata->isr_exit_cycles); - return IRQ_HANDLED; } int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe) { - unsigned int val; + unsigned int val, cache_params; void __iomem *cc_base = drvdata->cc_base; /* Unmask all AXI interrupt sources AXI_CFG1 register */ @@ -192,7 +188,7 @@ int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe) /* Unmask relevant interrupt cause */ val = (~(SSI_COMP_IRQ_MASK | SSI_AXI_ERR_IRQ_MASK | SSI_GPR0_IRQ_MASK)); CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR), val); - + #ifdef DX_HOST_IRQ_TIMER_INIT_VAL_REG_OFFSET #ifdef DX_IRQ_DELAY /* Set CC IRQ delay */ @@ -205,15 +201,20 @@ int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe) } #endif + cache_params = (drvdata->coherent ? CC_COHERENT_CACHE_PARAMS : 0x0); + val = CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CACHE_PARAMS)); - if (is_probe == true) { + + if (is_probe) SSI_LOG_INFO("Cache params previous: 0x%08X\n", val); - } - CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CACHE_PARAMS), SSI_CACHE_PARAMS); + + CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CACHE_PARAMS), + cache_params); val = CC_HAL_READ_REGISTER(CC_REG_OFFSET(CRY_KERNEL, AXIM_CACHE_PARAMS)); - if (is_probe == true) { - SSI_LOG_INFO("Cache params current: 0x%08X (expected: 0x%08X)\n", val, SSI_CACHE_PARAMS); - } + + if (is_probe) + SSI_LOG_INFO("Cache params current: 0x%08X (expect: 0x%08X)\n", + val, cache_params); return 0; } @@ -224,15 +225,20 @@ static int init_cc_resources(struct platform_device *plat_dev) void __iomem *cc_base = NULL; bool irq_registered = false; struct ssi_drvdata *new_drvdata = kzalloc(sizeof(struct ssi_drvdata), GFP_KERNEL); - uint32_t signature_val; + struct device *dev = &plat_dev->dev; + struct device_node *np = dev->of_node; + u32 signature_val; int rc = 0; - if (unlikely(new_drvdata == NULL)) { + if (unlikely(!new_drvdata)) { SSI_LOG_ERR("Failed to allocate drvdata"); rc = -ENOMEM; goto init_cc_res_err; } + new_drvdata->clk = of_clk_get(np, 0); + new_drvdata->coherent = of_dma_is_coherent(np); + /*Initialize inflight counter used in dx_ablkcipher_secure_complete used for count of BYSPASS blocks operations*/ new_drvdata->inflight_counter = 0; @@ -240,7 +246,7 @@ static int init_cc_resources(struct platform_device *plat_dev) /* Get device resources */ /* First CC registers space */ new_drvdata->res_mem = platform_get_resource(plat_dev, IORESOURCE_MEM, 0); - if (unlikely(new_drvdata->res_mem == NULL)) { + if (unlikely(!new_drvdata->res_mem)) { SSI_LOG_ERR("Failed getting IO memory resource\n"); rc = -ENODEV; goto init_cc_res_err; @@ -251,14 +257,14 @@ static int init_cc_resources(struct platform_device *plat_dev) (unsigned long long)new_drvdata->res_mem->end); /* Map registers space */ req_mem_cc_regs = request_mem_region(new_drvdata->res_mem->start, resource_size(new_drvdata->res_mem), "arm_cc7x_regs"); - if (unlikely(req_mem_cc_regs == NULL)) { + if (unlikely(!req_mem_cc_regs)) { SSI_LOG_ERR("Couldn't allocate registers memory region at " "0x%08X\n", (unsigned int)new_drvdata->res_mem->start); rc = -EBUSY; goto init_cc_res_err; } cc_base = ioremap(new_drvdata->res_mem->start, resource_size(new_drvdata->res_mem)); - if (unlikely(cc_base == NULL)) { + if (unlikely(!cc_base)) { SSI_LOG_ERR("ioremap[CC](0x%08X,0x%08X) failed\n", (unsigned int)new_drvdata->res_mem->start, (unsigned int)resource_size(new_drvdata->res_mem)); rc = -ENOMEM; @@ -266,11 +272,10 @@ static int init_cc_resources(struct platform_device *plat_dev) } SSI_LOG_DEBUG("CC registers mapped from %pa to 0x%p\n", &new_drvdata->res_mem->start, cc_base); new_drvdata->cc_base = cc_base; - /* Then IRQ */ new_drvdata->res_irq = platform_get_resource(plat_dev, IORESOURCE_IRQ, 0); - if (unlikely(new_drvdata->res_irq == NULL)) { + if (unlikely(!new_drvdata->res_irq)) { SSI_LOG_ERR("Failed getting IRQ resource\n"); rc = -ENODEV; goto init_cc_res_err; @@ -291,9 +296,13 @@ static int init_cc_resources(struct platform_device *plat_dev) new_drvdata->plat_dev = plat_dev; - if(new_drvdata->plat_dev->dev.dma_mask == NULL) + rc = cc_clk_on(new_drvdata); + if (rc) + goto init_cc_res_err; + + if (!new_drvdata->plat_dev->dev.dma_mask) { - new_drvdata->plat_dev->dev.dma_mask = & new_drvdata->plat_dev->dev.coherent_dma_mask; + new_drvdata->plat_dev->dev.dma_mask = &new_drvdata->plat_dev->dev.coherent_dma_mask; } if (!new_drvdata->plat_dev->dev.coherent_dma_mask) { @@ -304,7 +313,7 @@ static int init_cc_resources(struct platform_device *plat_dev) signature_val = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_SIGNATURE)); if (signature_val != DX_DEV_SIGNATURE) { SSI_LOG_ERR("Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n", - signature_val, (uint32_t)DX_DEV_SIGNATURE); + signature_val, (u32)DX_DEV_SIGNATURE); rc = -EINVAL; goto init_cc_res_err; } @@ -396,8 +405,8 @@ static int init_cc_resources(struct platform_device *plat_dev) init_cc_res_err: SSI_LOG_ERR("Freeing CC HW resources!\n"); - - if (new_drvdata != NULL) { + + if (new_drvdata) { ssi_aead_free(new_drvdata); ssi_hash_free(new_drvdata); ssi_ablkcipher_free(new_drvdata); @@ -410,8 +419,8 @@ init_cc_res_err: #ifdef ENABLE_CC_SYSFS ssi_sysfs_fini(); #endif - - if (req_mem_cc_regs != NULL) { + + if (req_mem_cc_regs) { if (irq_registered) { free_irq(new_drvdata->res_irq->start, new_drvdata); new_drvdata->res_irq = NULL; @@ -432,9 +441,8 @@ init_cc_res_err: void fini_cc_regs(struct ssi_drvdata *drvdata) { /* Mask all interrupts */ - WRITE_REGISTER(drvdata->cc_base + + WRITE_REGISTER(drvdata->cc_base + CC_REG_OFFSET(HOST_RGF, HOST_IMR), 0xFFFFFFFF); - } static void cleanup_cc_resources(struct platform_device *plat_dev) @@ -442,9 +450,9 @@ static void cleanup_cc_resources(struct platform_device *plat_dev) struct ssi_drvdata *drvdata = (struct ssi_drvdata *)dev_get_drvdata(&plat_dev->dev); - ssi_aead_free(drvdata); - ssi_hash_free(drvdata); - ssi_ablkcipher_free(drvdata); + ssi_aead_free(drvdata); + ssi_hash_free(drvdata); + ssi_ablkcipher_free(drvdata); ssi_ivgen_fini(drvdata); ssi_power_mgr_fini(drvdata); ssi_buffer_mgr_fini(drvdata); @@ -455,15 +463,12 @@ static void cleanup_cc_resources(struct platform_device *plat_dev) ssi_sysfs_fini(); #endif - /* Mask all interrupts */ - WRITE_REGISTER(drvdata->cc_base + CC_REG_OFFSET(HOST_RGF, HOST_IMR), - 0xFFFFFFFF); + fini_cc_regs(drvdata); + cc_clk_off(drvdata); free_irq(drvdata->res_irq->start, drvdata); drvdata->res_irq = NULL; - fini_cc_regs(drvdata); - - if (drvdata->cc_base != NULL) { + if (drvdata->cc_base) { iounmap(drvdata->cc_base); release_mem_region(drvdata->res_mem->start, resource_size(drvdata->res_mem)); @@ -475,11 +480,38 @@ static void cleanup_cc_resources(struct platform_device *plat_dev) dev_set_drvdata(&plat_dev->dev, NULL); } +int cc_clk_on(struct ssi_drvdata *drvdata) +{ + struct clk *clk = drvdata->clk; + int rc; + + if (IS_ERR(clk)) + /* Not all devices have a clock associated with CCREE */ + return 0; + + rc = clk_prepare_enable(clk); + if (rc) + return rc; + + return 0; +} + +void cc_clk_off(struct ssi_drvdata *drvdata) +{ + struct clk *clk = drvdata->clk; + + if (IS_ERR(clk)) + /* Not all devices have a clock associated with CCREE */ + return; + + clk_disable_unprepare(clk); +} + static int cc7x_probe(struct platform_device *plat_dev) { int rc; #if defined(CONFIG_ARM) && defined(CC_DEBUG) - uint32_t ctr, cacheline_size; + u32 ctr, cacheline_size; asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr)); cacheline_size = 4 << ((ctr >> 16) & 0xf); @@ -489,7 +521,7 @@ static int cc7x_probe(struct platform_device *plat_dev) asm volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (ctr)); SSI_LOG_DEBUG("Main ID register (MIDR): Implementer 0x%02X, Arch 0x%01X," " Part 0x%03X, Rev r%dp%d\n", - (ctr>>24), (ctr>>16)&0xF, (ctr>>4)&0xFFF, (ctr>>20)&0xF, ctr&0xF); + (ctr >> 24), (ctr >> 16) & 0xF, (ctr >> 4) & 0xFFF, (ctr >> 20) & 0xF, ctr & 0xF); #endif /* Map registers space */ @@ -505,29 +537,26 @@ static int cc7x_probe(struct platform_device *plat_dev) static int cc7x_remove(struct platform_device *plat_dev) { SSI_LOG_DEBUG("Releasing cc7x resources...\n"); - + cleanup_cc_resources(plat_dev); SSI_LOG(KERN_INFO, "ARM cc7x_ree device terminated\n"); -#ifdef ENABLE_CYCLE_COUNT - display_all_stat_db(); -#endif - + return 0; } -#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP) + +#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) static struct dev_pm_ops arm_cc7x_driver_pm = { SET_RUNTIME_PM_OPS(ssi_power_mgr_runtime_suspend, ssi_power_mgr_runtime_resume, NULL) }; #endif -#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP) +#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) #define DX_DRIVER_RUNTIME_PM (&arm_cc7x_driver_pm) #else #define DX_DRIVER_RUNTIME_PM NULL #endif - #ifdef CONFIG_OF static const struct of_device_id arm_cc7x_dev_of_match[] = { {.compatible = "arm,cryptocell-712-ree"}, diff --git a/drivers/staging/ccree/ssi_driver.h b/drivers/staging/ccree/ssi_driver.h index 891958b99634..c1ed61f1a202 100644 --- a/drivers/staging/ccree/ssi_driver.h +++ b/drivers/staging/ccree/ssi_driver.h @@ -1,21 +1,21 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ /* \file ssi_driver.h - ARM CryptoCell Linux Crypto Driver + * ARM CryptoCell Linux Crypto Driver */ #ifndef __SSI_DRIVER_H__ @@ -36,29 +36,27 @@ #include <crypto/authenc.h> #include <crypto/hash.h> #include <linux/version.h> - -#ifndef INT32_MAX /* Missing in Linux kernel */ -#define INT32_MAX 0x7FFFFFFFL -#endif +#include <linux/clk.h> /* Registers definitions from shared/hw/ree_include */ #include "dx_reg_base_host.h" #include "dx_host.h" -#define DX_CC_HOST_VIRT /* must be defined before including dx_cc_regs.h */ -#include "cc_hw_queue_defs.h" #include "cc_regs.h" #include "dx_reg_common.h" #include "cc_hal.h" -#include "ssi_sram_mgr.h" #define CC_SUPPORT_SHA DX_DEV_SHA_MAX #include "cc_crypto_ctx.h" #include "ssi_sysfs.h" #include "hash_defs.h" #include "ssi_fips_local.h" +#include "cc_hw_queue_defs.h" +#include "ssi_sram_mgr.h" #define DRV_MODULE_VERSION "3.0" #define SSI_DEV_NAME_STR "cc715ree" +#define CC_COHERENT_CACHE_PARAMS 0xEEE + #define SSI_CC_HAS_AES_CCM 1 #define SSI_CC_HAS_AES_GCM 1 #define SSI_CC_HAS_AES_XTS 1 @@ -89,12 +87,13 @@ /* Definitions for HW descriptors DIN/DOUT fields */ #define NS_BIT 1 #define AXI_ID 0 -/* AXI_ID is not actually the AXI ID of the transaction but the value of AXI_ID - field in the HW descriptor. The DMA engine +8 that value. */ +/* AXI_ID is not actually the AXI ID of the transaction but the value of AXI_ID + * field in the HW descriptor. The DMA engine +8 that value. + */ /* Logging macros */ #define SSI_LOG(level, format, ...) \ - printk(level "cc715ree::%s: " format , __func__, ##__VA_ARGS__) + printk(level "cc715ree::%s: " format, __func__, ##__VA_ARGS__) #define SSI_LOG_ERR(format, ...) SSI_LOG(KERN_ERR, format, ##__VA_ARGS__) #define SSI_LOG_WARNING(format, ...) SSI_LOG(KERN_WARNING, format, ##__VA_ARGS__) #define SSI_LOG_NOTICE(format, ...) SSI_LOG(KERN_NOTICE, format, ##__VA_ARGS__) @@ -108,21 +107,18 @@ #define MIN(a, b) (((a) < (b)) ? (a) : (b)) #define MAX(a, b) (((a) > (b)) ? (a) : (b)) -#define SSI_MAX_IVGEN_DMA_ADDRESSES 3 +#define SSI_MAX_IVGEN_DMA_ADDRESSES 3 struct ssi_crypto_req { void (*user_cb)(struct device *dev, void *req, void __iomem *cc_base); void *user_arg; - dma_addr_t ivgen_dma_addr[SSI_MAX_IVGEN_DMA_ADDRESSES]; /* For the first 'ivgen_dma_addr_len' addresses of this array, - generated IV would be placed in it by send_request(). - Same generated IV for all addresses! */ + dma_addr_t ivgen_dma_addr[SSI_MAX_IVGEN_DMA_ADDRESSES]; + /* For the first 'ivgen_dma_addr_len' addresses of this array, + * generated IV would be placed in it by send_request(). + * Same generated IV for all addresses! + */ unsigned int ivgen_dma_addr_len; /* Amount of 'ivgen_dma_addr' elements to be filled. */ unsigned int ivgen_size; /* The generated IV size required, 8/16 B allowed. */ struct completion seq_compl; /* request completion */ -#ifdef ENABLE_CYCLE_COUNT - enum stat_op op_type; - cycles_t submit_cycle; - bool is_monitored_p; -#endif }; /** @@ -136,15 +132,13 @@ struct ssi_drvdata { struct resource *res_mem; struct resource *res_irq; void __iomem *cc_base; -#ifdef DX_BASE_ENV_REGS - void __iomem *env_base; /* ARM CryptoCell development FPGAs only */ -#endif unsigned int irq; - uint32_t irq_mask; - uint32_t fw_ver; + u32 irq_mask; + u32 fw_ver; /* Calibration time of start/stop - * monitor descriptors */ - uint32_t monitor_null_cycles; + * monitor descriptors + */ + u32 monitor_null_cycles; struct platform_device *plat_dev; ssi_sram_addr_t mlli_sram_addr; struct completion icache_setup_completion; @@ -156,12 +150,9 @@ struct ssi_drvdata { void *fips_handle; void *ivgen_handle; void *sram_mgr_handle; - -#ifdef ENABLE_CYCLE_COUNT - cycles_t isr_exit_cycles; /* Save for isr-to-tasklet latency */ -#endif - uint32_t inflight_counter; - + u32 inflight_counter; + struct clk *clk; + bool coherent; }; struct ssi_crypto_alg { @@ -189,7 +180,6 @@ struct ssi_alg_template { int cipher_mode; int flow_mode; /* Note: currently, refers to the cipher mode only. */ int auth_mode; - bool synchronous; struct ssi_drvdata *drvdata; }; @@ -199,30 +189,16 @@ struct async_gen_req_ctx { }; #ifdef DX_DUMP_BYTES -void dump_byte_array(const char *name, const uint8_t *the_array, unsigned long size); +void dump_byte_array(const char *name, const u8 *the_array, unsigned long size); #else #define dump_byte_array(name, array, size) do { \ } while (0); #endif -#ifdef ENABLE_CYCLE_COUNT -#define DECL_CYCLE_COUNT_RESOURCES cycles_t _last_cycles_read -#define START_CYCLE_COUNT() do { _last_cycles_read = get_cycles(); } while (0) -#define END_CYCLE_COUNT(_stat_op_type, _stat_phase) update_host_stat(_stat_op_type, _stat_phase, get_cycles() - _last_cycles_read) -#define GET_START_CYCLE_COUNT() _last_cycles_read -#define START_CYCLE_COUNT_AT(_var) do { _var = get_cycles(); } while(0) -#define END_CYCLE_COUNT_AT(_var, _stat_op_type, _stat_phase) update_host_stat(_stat_op_type, _stat_phase, get_cycles() - _var) -#else -#define DECL_CYCLE_COUNT_RESOURCES -#define START_CYCLE_COUNT() do { } while (0) -#define END_CYCLE_COUNT(_stat_op_type, _stat_phase) do { } while (0) -#define GET_START_CYCLE_COUNT() 0 -#define START_CYCLE_COUNT_AT(_var) do { } while (0) -#define END_CYCLE_COUNT_AT(_var, _stat_op_type, _stat_phase) do { } while (0) -#endif /*ENABLE_CYCLE_COUNT*/ - int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe); void fini_cc_regs(struct ssi_drvdata *drvdata); +int cc_clk_on(struct ssi_drvdata *drvdata); +void cc_clk_off(struct ssi_drvdata *drvdata); #endif /*__SSI_DRIVER_H__*/ diff --git a/drivers/staging/ccree/ssi_fips.c b/drivers/staging/ccree/ssi_fips.c index 50f748511979..fdc40f38332a 100644 --- a/drivers/staging/ccree/ssi_fips.c +++ b/drivers/staging/ccree/ssi_fips.c @@ -1,42 +1,39 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ - /************************************************************** -This file defines the driver FIPS APIs * -***************************************************************/ + * This file defines the driver FIPS APIs * + **************************************************************/ #include <linux/module.h> #include "ssi_fips.h" - -extern int ssi_fips_ext_get_state(ssi_fips_state_t *p_state); -extern int ssi_fips_ext_get_error(ssi_fips_error_t *p_err); +extern int ssi_fips_ext_get_state(enum cc_fips_state_t *p_state); +extern int ssi_fips_ext_get_error(enum cc_fips_error *p_err); /* -This function returns the REE FIPS state. -It should be called by kernel module. -*/ -int ssi_fips_get_state(ssi_fips_state_t *p_state) + * This function returns the REE FIPS state. + * It should be called by kernel module. + */ +int ssi_fips_get_state(enum cc_fips_state_t *p_state) { - int rc = 0; + int rc = 0; - if (p_state == NULL) { + if (!p_state) return -EINVAL; - } rc = ssi_fips_ext_get_state(p_state); @@ -46,16 +43,15 @@ int ssi_fips_get_state(ssi_fips_state_t *p_state) EXPORT_SYMBOL(ssi_fips_get_state); /* -This function returns the REE FIPS error. -It should be called by kernel module. -*/ -int ssi_fips_get_error(ssi_fips_error_t *p_err) + * This function returns the REE FIPS error. + * It should be called by kernel module. + */ +int ssi_fips_get_error(enum cc_fips_error *p_err) { - int rc = 0; + int rc = 0; - if (p_err == NULL) { + if (!p_err) return -EINVAL; - } rc = ssi_fips_ext_get_error(p_err); diff --git a/drivers/staging/ccree/ssi_fips.h b/drivers/staging/ccree/ssi_fips.h index 19bcdeb34308..4f5c6a9a8363 100644 --- a/drivers/staging/ccree/ssi_fips.h +++ b/drivers/staging/ccree/ssi_fips.h @@ -1,15 +1,15 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ @@ -17,26 +17,19 @@ #ifndef __SSI_FIPS_H__ #define __SSI_FIPS_H__ +/*! + * @file + * @brief This file contains FIPS related defintions and APIs. + */ -#ifndef INT32_MAX /* Missing in Linux kernel */ -#define INT32_MAX 0x7FFFFFFFL -#endif - - -/*! -@file -@brief This file contains FIPS related defintions and APIs. -*/ - -typedef enum ssi_fips_state { - CC_FIPS_STATE_NOT_SUPPORTED = 0, - CC_FIPS_STATE_SUPPORTED, - CC_FIPS_STATE_ERROR, - CC_FIPS_STATE_RESERVE32B = INT32_MAX -} ssi_fips_state_t; - +enum cc_fips_state { + CC_FIPS_STATE_NOT_SUPPORTED = 0, + CC_FIPS_STATE_SUPPORTED, + CC_FIPS_STATE_ERROR, + CC_FIPS_STATE_RESERVE32B = S32_MAX +}; -typedef enum ssi_fips_error { +enum cc_fips_error { CC_REE_FIPS_ERROR_OK = 0, CC_REE_FIPS_ERROR_GENERAL, CC_REE_FIPS_ERROR_FROM_TEE, @@ -58,13 +51,11 @@ typedef enum ssi_fips_error { CC_REE_FIPS_ERROR_HMAC_SHA256_PUT, CC_REE_FIPS_ERROR_HMAC_SHA512_PUT, CC_REE_FIPS_ERROR_ROM_CHECKSUM, - CC_REE_FIPS_ERROR_RESERVE32B = INT32_MAX -} ssi_fips_error_t; - - + CC_REE_FIPS_ERROR_RESERVE32B = S32_MAX +}; -int ssi_fips_get_state(ssi_fips_state_t *p_state); -int ssi_fips_get_error(ssi_fips_error_t *p_err); +int ssi_fips_get_state(enum cc_fips_state *p_state); +int ssi_fips_get_error(enum cc_fips_error *p_err); #endif /*__SSI_FIPS_H__*/ diff --git a/drivers/staging/ccree/ssi_fips_data.h b/drivers/staging/ccree/ssi_fips_data.h index 3fddd8f74e07..c41671dbee40 100644 --- a/drivers/staging/ccree/ssi_fips_data.h +++ b/drivers/staging/ccree/ssi_fips_data.h @@ -1,67 +1,66 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ /* -The test vectors were taken from: - -* AES -NIST Special Publication 800-38A 2001 Edition -Recommendation for Block Cipher Modes of Operation -http://csrc.nist.gov/publications/nistpubs/800-38a/sp800-38a.pdf -Appendix F: Example Vectors for Modes of Operation of the AES - -* AES CTS -Advanced Encryption Standard (AES) Encryption for Kerberos 5 -February 2005 -https://tools.ietf.org/html/rfc3962#appendix-B -B. Sample Test Vectors - -* AES XTS -http://csrc.nist.gov/groups/STM/cavp/#08 -http://csrc.nist.gov/groups/STM/cavp/documents/aes/XTSTestVectors.zip - -* AES CMAC -http://csrc.nist.gov/groups/STM/cavp/index.html#07 -http://csrc.nist.gov/groups/STM/cavp/documents/mac/cmactestvectors.zip - -* AES-CCM -http://csrc.nist.gov/groups/STM/cavp/#07 -http://csrc.nist.gov/groups/STM/cavp/documents/mac/ccmtestvectors.zip - -* AES-GCM -http://csrc.nist.gov/groups/STM/cavp/documents/mac/gcmtestvectors.zip - -* Triple-DES -NIST Special Publication 800-67 January 2012 -Recommendation for the Triple Data Encryption Algorithm (TDEA) Block Cipher -http://csrc.nist.gov/publications/nistpubs/800-67-Rev1/SP-800-67-Rev1.pdf -APPENDIX B: EXAMPLE OF TDEA FORWARD AND INVERSE CIPHER OPERATIONS -and -http://csrc.nist.gov/groups/STM/cavp/#01 -http://csrc.nist.gov/groups/STM/cavp/documents/des/tdesmct_intermediate.zip - -* HASH -http://csrc.nist.gov/groups/STM/cavp/#03 -http://csrc.nist.gov/groups/STM/cavp/documents/shs/shabytetestvectors.zip - -* HMAC -http://csrc.nist.gov/groups/STM/cavp/#07 -http://csrc.nist.gov/groups/STM/cavp/documents/mac/hmactestvectors.zip - -*/ + * The test vectors were taken from: + * + * * AES + * NIST Special Publication 800-38A 2001 Edition + * Recommendation for Block Cipher Modes of Operation + * http://csrc.nist.gov/publications/nistpubs/800-38a/sp800-38a.pdf + * Appendix F: Example Vectors for Modes of Operation of the AES + * + * * AES CTS + * Advanced Encryption Standard (AES) Encryption for Kerberos 5 + * February 2005 + * https://tools.ietf.org/html/rfc3962#appendix-B + * B. Sample Test Vectors + * + * * AES XTS + * http://csrc.nist.gov/groups/STM/cavp/#08 + * http://csrc.nist.gov/groups/STM/cavp/documents/aes/XTSTestVectors.zip + * + * * AES CMAC + * http://csrc.nist.gov/groups/STM/cavp/index.html#07 + * http://csrc.nist.gov/groups/STM/cavp/documents/mac/cmactestvectors.zip + * + * * AES-CCM + * http://csrc.nist.gov/groups/STM/cavp/#07 + * http://csrc.nist.gov/groups/STM/cavp/documents/mac/ccmtestvectors.zip + * + * * AES-GCM + * http://csrc.nist.gov/groups/STM/cavp/documents/mac/gcmtestvectors.zip + * + * * Triple-DES + * NIST Special Publication 800-67 January 2012 + * Recommendation for the Triple Data Encryption Algorithm (TDEA) Block Cipher + * http://csrc.nist.gov/publications/nistpubs/800-67-Rev1/SP-800-67-Rev1.pdf + * APPENDIX B: EXAMPLE OF TDEA FORWARD AND INVERSE CIPHER OPERATIONS + * and + * http://csrc.nist.gov/groups/STM/cavp/#01 + * http://csrc.nist.gov/groups/STM/cavp/documents/des/tdesmct_intermediate.zip + * + * * HASH + * http://csrc.nist.gov/groups/STM/cavp/#03 + * http://csrc.nist.gov/groups/STM/cavp/documents/shs/shabytetestvectors.zip + * + * * HMAC + * http://csrc.nist.gov/groups/STM/cavp/#07 + * http://csrc.nist.gov/groups/STM/cavp/documents/mac/hmactestvectors.zip + */ /* NIST AES */ #define AES_128_BIT_KEY_SIZE 16 @@ -86,19 +85,18 @@ http://csrc.nist.gov/groups/STM/cavp/documents/mac/hmactestvectors.zip #define NIST_AES_CBC_IV { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f } #define NIST_AES_128_CBC_CIPHER { 0x76, 0x49, 0xab, 0xac, 0x81, 0x19, 0xb2, 0x46, 0xce, 0xe9, 0x8e, 0x9b, 0x12, 0xe9, 0x19, 0x7d } -#define NIST_AES_192_CBC_CIPHER { 0x4f, 0x02, 0x1d, 0xb2, 0x43, 0xbc, 0x63, 0x3d, 0x71, 0x78, 0x18, 0x3a, 0x9f, 0xa0, 0x71, 0xe8 } -#define NIST_AES_256_CBC_CIPHER { 0xf5, 0x8c, 0x4c, 0x04, 0xd6, 0xe5, 0xf1, 0xba, 0x77, 0x9e, 0xab, 0xfb, 0x5f, 0x7b, 0xfb, 0xd6 } +#define NIST_AES_192_CBC_CIPHER { 0x4f, 0x02, 0x1d, 0xb2, 0x43, 0xbc, 0x63, 0x3d, 0x71, 0x78, 0x18, 0x3a, 0x9f, 0xa0, 0x71, 0xe8 } +#define NIST_AES_256_CBC_CIPHER { 0xf5, 0x8c, 0x4c, 0x04, 0xd6, 0xe5, 0xf1, 0xba, 0x77, 0x9e, 0xab, 0xfb, 0x5f, 0x7b, 0xfb, 0xd6 } #define NIST_AES_OFB_IV { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f } #define NIST_AES_128_OFB_CIPHER { 0x3b, 0x3f, 0xd9, 0x2e, 0xb7, 0x2d, 0xad, 0x20, 0x33, 0x34, 0x49, 0xf8, 0xe8, 0x3c, 0xfb, 0x4a } -#define NIST_AES_192_OFB_CIPHER { 0xcd, 0xc8, 0x0d, 0x6f, 0xdd, 0xf1, 0x8c, 0xab, 0x34, 0xc2, 0x59, 0x09, 0xc9, 0x9a, 0x41, 0x74 } +#define NIST_AES_192_OFB_CIPHER { 0xcd, 0xc8, 0x0d, 0x6f, 0xdd, 0xf1, 0x8c, 0xab, 0x34, 0xc2, 0x59, 0x09, 0xc9, 0x9a, 0x41, 0x74 } #define NIST_AES_256_OFB_CIPHER { 0xdc, 0x7e, 0x84, 0xbf, 0xda, 0x79, 0x16, 0x4b, 0x7e, 0xcd, 0x84, 0x86, 0x98, 0x5d, 0x38, 0x60 } #define NIST_AES_CTR_IV { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff } #define NIST_AES_128_CTR_CIPHER { 0x87, 0x4d, 0x61, 0x91, 0xb6, 0x20, 0xe3, 0x26, 0x1b, 0xef, 0x68, 0x64, 0x99, 0x0d, 0xb6, 0xce } -#define NIST_AES_192_CTR_CIPHER { 0x1a, 0xbc, 0x93, 0x24, 0x17, 0x52, 0x1c, 0xa2, 0x4f, 0x2b, 0x04, 0x59, 0xfe, 0x7e, 0x6e, 0x0b } -#define NIST_AES_256_CTR_CIPHER { 0x60, 0x1e, 0xc3, 0x13, 0x77, 0x57, 0x89, 0xa5, 0xb7, 0xa7, 0xf5, 0x04, 0xbb, 0xf3, 0xd2, 0x28 } - +#define NIST_AES_192_CTR_CIPHER { 0x1a, 0xbc, 0x93, 0x24, 0x17, 0x52, 0x1c, 0xa2, 0x4f, 0x2b, 0x04, 0x59, 0xfe, 0x7e, 0x6e, 0x0b } +#define NIST_AES_256_CTR_CIPHER { 0x60, 0x1e, 0xc3, 0x13, 0x77, 0x57, 0x89, 0xa5, 0xb7, 0xa7, 0xf5, 0x04, 0xbb, 0xf3, 0xd2, 0x28 } #define RFC3962_AES_128_KEY { 0x63, 0x68, 0x69, 0x63, 0x6b, 0x65, 0x6e, 0x20, 0x74, 0x65, 0x72, 0x69, 0x79, 0x61, 0x6b, 0x69 } #define RFC3962_AES_VECTOR_SIZE 17 @@ -106,13 +104,12 @@ http://csrc.nist.gov/groups/STM/cavp/documents/mac/hmactestvectors.zip #define RFC3962_AES_CBC_CTS_IV { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } #define RFC3962_AES_128_CBC_CTS_CIPHER { 0xc6, 0x35, 0x35, 0x68, 0xf2, 0xbf, 0x8c, 0xb4, 0xd8, 0xa5, 0x80, 0x36, 0x2d, 0xa7, 0xff, 0x7f, 0x97 } - #define NIST_AES_256_XTS_KEY { 0xa1, 0xb9, 0x0c, 0xba, 0x3f, 0x06, 0xac, 0x35, 0x3b, 0x2c, 0x34, 0x38, 0x76, 0x08, 0x17, 0x62, \ 0x09, 0x09, 0x23, 0x02, 0x6e, 0x91, 0x77, 0x18, 0x15, 0xf2, 0x9d, 0xab, 0x01, 0x93, 0x2f, 0x2f } #define NIST_AES_256_XTS_IV { 0x4f, 0xae, 0xf7, 0x11, 0x7c, 0xda, 0x59, 0xc6, 0x6e, 0x4b, 0x92, 0x01, 0x3e, 0x76, 0x8a, 0xd5 } #define NIST_AES_256_XTS_VECTOR_SIZE 16 -#define NIST_AES_256_XTS_PLAIN { 0xeb, 0xab, 0xce, 0x95, 0xb1, 0x4d, 0x3c, 0x8d, 0x6f, 0xb3, 0x50, 0x39, 0x07, 0x90, 0x31, 0x1c } -#define NIST_AES_256_XTS_CIPHER { 0x77, 0x8a, 0xe8, 0xb4, 0x3c, 0xb9, 0x8d, 0x5a, 0x82, 0x50, 0x81, 0xd5, 0xbe, 0x47, 0x1c, 0x63 } +#define NIST_AES_256_XTS_PLAIN { 0xeb, 0xab, 0xce, 0x95, 0xb1, 0x4d, 0x3c, 0x8d, 0x6f, 0xb3, 0x50, 0x39, 0x07, 0x90, 0x31, 0x1c } +#define NIST_AES_256_XTS_CIPHER { 0x77, 0x8a, 0xe8, 0xb4, 0x3c, 0xb9, 0x8d, 0x5a, 0x82, 0x50, 0x81, 0xd5, 0xbe, 0x47, 0x1c, 0x63 } #define NIST_AES_512_XTS_KEY { 0x1e, 0xa6, 0x61, 0xc5, 0x8d, 0x94, 0x3a, 0x0e, 0x48, 0x01, 0xe4, 0x2f, 0x4b, 0x09, 0x47, 0x14, \ 0x9e, 0x7f, 0x9f, 0x8e, 0x3e, 0x68, 0xd0, 0xc7, 0x50, 0x52, 0x10, 0xbd, 0x31, 0x1a, 0x0e, 0x7c, \ @@ -121,10 +118,9 @@ http://csrc.nist.gov/groups/STM/cavp/documents/mac/hmactestvectors.zip #define NIST_AES_512_XTS_IV { 0xad, 0xf8, 0xd9, 0x26, 0x27, 0x46, 0x4a, 0xd2, 0xf0, 0x42, 0x8e, 0x84, 0xa9, 0xf8, 0x75, 0x64, } #define NIST_AES_512_XTS_VECTOR_SIZE 32 #define NIST_AES_512_XTS_PLAIN { 0x2e, 0xed, 0xea, 0x52, 0xcd, 0x82, 0x15, 0xe1, 0xac, 0xc6, 0x47, 0xe8, 0x10, 0xbb, 0xc3, 0x64, \ - 0x2e, 0x87, 0x28, 0x7f, 0x8d, 0x2e, 0x57, 0xe3, 0x6c, 0x0a, 0x24, 0xfb, 0xc1, 0x2a, 0x20, 0x2e } + 0x2e, 0x87, 0x28, 0x7f, 0x8d, 0x2e, 0x57, 0xe3, 0x6c, 0x0a, 0x24, 0xfb, 0xc1, 0x2a, 0x20, 0x2e } #define NIST_AES_512_XTS_CIPHER { 0xcb, 0xaa, 0xd0, 0xe2, 0xf6, 0xce, 0xa3, 0xf5, 0x0b, 0x37, 0xf9, 0x34, 0xd4, 0x6a, 0x9b, 0x13, \ - 0x0b, 0x9d, 0x54, 0xf0, 0x7e, 0x34, 0xf3, 0x6a, 0xf7, 0x93, 0xe8, 0x6f, 0x73, 0xc6, 0xd7, 0xdb } - + 0x0b, 0x9d, 0x54, 0xf0, 0x7e, 0x34, 0xf3, 0x6a, 0xf7, 0x93, 0xe8, 0x6f, 0x73, 0xc6, 0xd7, 0xdb } /* NIST AES-CMAC */ #define NIST_AES_128_CMAC_KEY { 0x67, 0x08, 0xc9, 0x88, 0x7b, 0x84, 0x70, 0x84, 0xf1, 0x23, 0xd3, 0xdd, 0x9c, 0x3a, 0x81, 0x36 } @@ -148,27 +144,25 @@ http://csrc.nist.gov/groups/STM/cavp/documents/mac/hmactestvectors.zip #define NIST_AES_256_CMAC_VECTOR_SIZE 16 #define NIST_AES_256_CMAC_OUTPUT_SIZE 10 - /* NIST TDES */ #define TDES_NUM_OF_KEYS 3 #define NIST_TDES_VECTOR_SIZE 8 #define NIST_TDES_IV_SIZE 8 -#define NIST_TDES_ECB_IV { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define NIST_TDES_ECB_IV { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } #define NIST_TDES_ECB3_KEY { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, \ 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, 0x01, \ 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, 0x01, 0x23 } -#define NIST_TDES_ECB3_PLAIN_DATA { 0x54, 0x68, 0x65, 0x20, 0x71, 0x75, 0x66, 0x63 } -#define NIST_TDES_ECB3_CIPHER { 0xa8, 0x26, 0xfd, 0x8c, 0xe5, 0x3b, 0x85, 0x5f } +#define NIST_TDES_ECB3_PLAIN_DATA { 0x54, 0x68, 0x65, 0x20, 0x71, 0x75, 0x66, 0x63 } +#define NIST_TDES_ECB3_CIPHER { 0xa8, 0x26, 0xfd, 0x8c, 0xe5, 0x3b, 0x85, 0x5f } -#define NIST_TDES_CBC3_IV { 0xf8, 0xee, 0xe1, 0x35, 0x9c, 0x6e, 0x54, 0x40 } +#define NIST_TDES_CBC3_IV { 0xf8, 0xee, 0xe1, 0x35, 0x9c, 0x6e, 0x54, 0x40 } #define NIST_TDES_CBC3_KEY { 0xe9, 0xda, 0x37, 0xf8, 0xdc, 0x97, 0x6d, 0x5b, \ 0xb6, 0x8c, 0x04, 0xe3, 0xec, 0x98, 0x20, 0x15, \ 0xf4, 0x0e, 0x08, 0xb5, 0x97, 0x29, 0xf2, 0x8f } -#define NIST_TDES_CBC3_PLAIN_DATA { 0x3b, 0xb7, 0xa7, 0xdb, 0xa3, 0xd5, 0x92, 0x91 } -#define NIST_TDES_CBC3_CIPHER { 0x5b, 0x84, 0x24, 0xd2, 0x39, 0x3e, 0x55, 0xa2 } - +#define NIST_TDES_CBC3_PLAIN_DATA { 0x3b, 0xb7, 0xa7, 0xdb, 0xa3, 0xd5, 0x92, 0x91 } +#define NIST_TDES_CBC3_CIPHER { 0x5b, 0x84, 0x24, 0xd2, 0x39, 0x3e, 0x55, 0xa2 } /* NIST AES-CCM */ #define NIST_AESCCM_128_BIT_KEY_SIZE 16 @@ -208,7 +202,6 @@ http://csrc.nist.gov/groups/STM/cavp/documents/mac/hmactestvectors.zip #define NIST_AESCCM_256_CIPHER { 0xcc, 0x17, 0xbf, 0x87, 0x94, 0xc8, 0x43, 0x45, 0x7d, 0x89, 0x93, 0x91, 0x89, 0x8e, 0xd2, 0x2a } #define NIST_AESCCM_256_MAC { 0x6f, 0x9d, 0x28, 0xfc, 0xb6, 0x42, 0x34, 0xe1, 0xcd, 0x79, 0x3c, 0x41, 0x44, 0xf1, 0xda, 0x50 } - /* NIST AES-GCM */ #define NIST_AESGCM_128_BIT_KEY_SIZE 16 #define NIST_AESGCM_192_BIT_KEY_SIZE 24 @@ -242,7 +235,6 @@ http://csrc.nist.gov/groups/STM/cavp/documents/mac/hmactestvectors.zip #define NIST_AESGCM_256_CIPHER { 0x42, 0x6e, 0x0e, 0xfc, 0x69, 0x3b, 0x7b, 0xe1, 0xf3, 0x01, 0x8d, 0xb7, 0xdd, 0xbb, 0x7e, 0x4d } #define NIST_AESGCM_256_MAC { 0xee, 0x82, 0x57, 0x79, 0x5b, 0xe6, 0xa1, 0x16, 0x4d, 0x7e, 0x1d, 0x2d, 0x6c, 0xac, 0x77, 0xa7 } - /* NIST HASH */ #define NIST_SHA_MSG_SIZE 16 @@ -260,7 +252,6 @@ http://csrc.nist.gov/groups/STM/cavp/documents/mac/hmactestvectors.zip 0x8f, 0x2b, 0xa9, 0x1c, 0x3a, 0x9f, 0x0c, 0x16, 0x53, 0xc4, 0xbf, 0x0a, 0xda, 0x35, 0x64, 0x55, \ 0xea, 0x36, 0xfd, 0x31, 0xf8, 0xe7, 0x3e, 0x39, 0x51, 0xca, 0xd4, 0xeb, 0xba, 0x8c, 0x6e, 0x04 } - /* NIST HMAC */ #define NIST_HMAC_MSG_SIZE 128 diff --git a/drivers/staging/ccree/ssi_fips_ext.c b/drivers/staging/ccree/ssi_fips_ext.c index 2ac432fe1233..e7bf1843f60c 100644 --- a/drivers/staging/ccree/ssi_fips_ext.c +++ b/drivers/staging/ccree/ssi_fips_ext.c @@ -1,49 +1,47 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ /************************************************************** -This file defines the driver FIPS functions that should be -implemented by the driver user. Current implementation is sample code only. -***************************************************************/ + * This file defines the driver FIPS functions that should be + * implemented by the driver user. Current implementation is sample code only. + ***************************************************************/ #include <linux/module.h> #include "ssi_fips_local.h" #include "ssi_driver.h" - static bool tee_error; module_param(tee_error, bool, 0644); MODULE_PARM_DESC(tee_error, "Simulate TEE library failure flag: 0 - no error (default), 1 - TEE error occured "); -static ssi_fips_state_t fips_state = CC_FIPS_STATE_NOT_SUPPORTED; -static ssi_fips_error_t fips_error = CC_REE_FIPS_ERROR_OK; +static enum cc_fips_state_t fips_state = CC_FIPS_STATE_NOT_SUPPORTED; +static enum cc_fips_error fips_error = CC_REE_FIPS_ERROR_OK; /* -This function returns the FIPS REE state. -The function should be implemented by the driver user, depends on where . -the state value is stored. -The reference code uses global variable. -*/ -int ssi_fips_ext_get_state(ssi_fips_state_t *p_state) + * This function returns the FIPS REE state. + * The function should be implemented by the driver user, depends on where + * the state value is stored. + * The reference code uses global variable. + */ +int ssi_fips_ext_get_state(enum cc_fips_state_t *p_state) { - int rc = 0; + int rc = 0; - if (p_state == NULL) { + if (!p_state) return -EINVAL; - } *p_state = fips_state; @@ -51,18 +49,17 @@ int ssi_fips_ext_get_state(ssi_fips_state_t *p_state) } /* -This function returns the FIPS REE error. -The function should be implemented by the driver user, depends on where . -the error value is stored. -The reference code uses global variable. -*/ -int ssi_fips_ext_get_error(ssi_fips_error_t *p_err) + * This function returns the FIPS REE error. + * The function should be implemented by the driver user, depends on where + * the error value is stored. + * The reference code uses global variable. + */ +int ssi_fips_ext_get_error(enum cc_fips_error *p_err) { - int rc = 0; + int rc = 0; - if (p_err == NULL) { + if (!p_err) return -EINVAL; - } *p_err = fips_error; @@ -70,27 +67,26 @@ int ssi_fips_ext_get_error(ssi_fips_error_t *p_err) } /* -This function sets the FIPS REE state. -The function should be implemented by the driver user, depends on where . -the state value is stored. -The reference code uses global variable. -*/ -int ssi_fips_ext_set_state(ssi_fips_state_t state) + * This function sets the FIPS REE state. + * The function should be implemented by the driver user, depends on where + * the state value is stored. + * The reference code uses global variable. + */ +int ssi_fips_ext_set_state(enum cc_fips_state_t state) { fips_state = state; return 0; } /* -This function sets the FIPS REE error. -The function should be implemented by the driver user, depends on where . -the error value is stored. -The reference code uses global variable. -*/ -int ssi_fips_ext_set_error(ssi_fips_error_t err) + * This function sets the FIPS REE error. + * The function should be implemented by the driver user, depends on where + * the error value is stored. + * The reference code uses global variable. + */ +int ssi_fips_ext_set_error(enum cc_fips_error err) { fips_error = err; return 0; } - diff --git a/drivers/staging/ccree/ssi_fips_ll.c b/drivers/staging/ccree/ssi_fips_ll.c index d573574bbb98..3557e20c9e36 100644 --- a/drivers/staging/ccree/ssi_fips_ll.c +++ b/drivers/staging/ccree/ssi_fips_ll.c @@ -1,23 +1,23 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ /************************************************************** -This file defines the driver FIPS Low Level implmentaion functions, -that executes the KAT. -***************************************************************/ + * This file defines the driver FIPS Low Level implmentaion functions, + * that executes the KAT. + ***************************************************************/ #include <linux/kernel.h> #include "ssi_driver.h" @@ -27,151 +27,143 @@ that executes the KAT. #include "ssi_hash.h" #include "ssi_request_mgr.h" - -static const uint32_t digest_len_init[] = { +static const u32 digest_len_init[] = { 0x00000040, 0x00000000, 0x00000000, 0x00000000 }; -static const uint32_t sha1_init[] = { +static const u32 sha1_init[] = { SHA1_H4, SHA1_H3, SHA1_H2, SHA1_H1, SHA1_H0 }; -static const uint32_t sha256_init[] = { +static const u32 sha256_init[] = { SHA256_H7, SHA256_H6, SHA256_H5, SHA256_H4, SHA256_H3, SHA256_H2, SHA256_H1, SHA256_H0 }; #if (CC_SUPPORT_SHA > 256) -static const uint32_t digest_len_sha512_init[] = { +static const u32 digest_len_sha512_init[] = { 0x00000080, 0x00000000, 0x00000000, 0x00000000 }; -static const uint64_t sha512_init[] = { +static const u64 sha512_init[] = { SHA512_H7, SHA512_H6, SHA512_H5, SHA512_H4, SHA512_H3, SHA512_H2, SHA512_H1, SHA512_H0 }; #endif - #define NIST_CIPHER_AES_MAX_VECTOR_SIZE 32 struct fips_cipher_ctx { - uint8_t iv[CC_AES_IV_SIZE]; - uint8_t key[AES_512_BIT_KEY_SIZE]; - uint8_t din[NIST_CIPHER_AES_MAX_VECTOR_SIZE]; - uint8_t dout[NIST_CIPHER_AES_MAX_VECTOR_SIZE]; + u8 iv[CC_AES_IV_SIZE]; + u8 key[AES_512_BIT_KEY_SIZE]; + u8 din[NIST_CIPHER_AES_MAX_VECTOR_SIZE]; + u8 dout[NIST_CIPHER_AES_MAX_VECTOR_SIZE]; }; typedef struct _FipsCipherData { - uint8_t isAes; - uint8_t key[AES_512_BIT_KEY_SIZE]; + u8 isAes; + u8 key[AES_512_BIT_KEY_SIZE]; size_t keySize; - uint8_t iv[CC_AES_IV_SIZE]; + u8 iv[CC_AES_IV_SIZE]; enum drv_crypto_direction direction; enum drv_cipher_mode oprMode; - uint8_t dataIn[NIST_CIPHER_AES_MAX_VECTOR_SIZE]; - uint8_t dataOut[NIST_CIPHER_AES_MAX_VECTOR_SIZE]; + u8 dataIn[NIST_CIPHER_AES_MAX_VECTOR_SIZE]; + u8 dataOut[NIST_CIPHER_AES_MAX_VECTOR_SIZE]; size_t dataInSize; } FipsCipherData; - struct fips_cmac_ctx { - uint8_t key[AES_256_BIT_KEY_SIZE]; - uint8_t din[NIST_CIPHER_AES_MAX_VECTOR_SIZE]; - uint8_t mac_res[CC_DIGEST_SIZE_MAX]; + u8 key[AES_256_BIT_KEY_SIZE]; + u8 din[NIST_CIPHER_AES_MAX_VECTOR_SIZE]; + u8 mac_res[CC_DIGEST_SIZE_MAX]; }; typedef struct _FipsCmacData { enum drv_crypto_direction direction; - uint8_t key[AES_256_BIT_KEY_SIZE]; + u8 key[AES_256_BIT_KEY_SIZE]; size_t key_size; - uint8_t data_in[NIST_CIPHER_AES_MAX_VECTOR_SIZE]; + u8 data_in[NIST_CIPHER_AES_MAX_VECTOR_SIZE]; size_t data_in_size; - uint8_t mac_res[CC_DIGEST_SIZE_MAX]; + u8 mac_res[CC_DIGEST_SIZE_MAX]; size_t mac_res_size; } FipsCmacData; - struct fips_hash_ctx { - uint8_t initial_digest[CC_DIGEST_SIZE_MAX]; - uint8_t din[NIST_SHA_MSG_SIZE]; - uint8_t mac_res[CC_DIGEST_SIZE_MAX]; + u8 initial_digest[CC_DIGEST_SIZE_MAX]; + u8 din[NIST_SHA_MSG_SIZE]; + u8 mac_res[CC_DIGEST_SIZE_MAX]; }; typedef struct _FipsHashData { enum drv_hash_mode hash_mode; - uint8_t data_in[NIST_SHA_MSG_SIZE]; + u8 data_in[NIST_SHA_MSG_SIZE]; size_t data_in_size; - uint8_t mac_res[CC_DIGEST_SIZE_MAX]; + u8 mac_res[CC_DIGEST_SIZE_MAX]; } FipsHashData; - /* note that the hmac key length must be equal or less than block size (block size is 64 up to sha256 and 128 for sha384/512) */ struct fips_hmac_ctx { - uint8_t initial_digest[CC_DIGEST_SIZE_MAX]; - uint8_t key[CC_HMAC_BLOCK_SIZE_MAX]; - uint8_t k0[CC_HMAC_BLOCK_SIZE_MAX]; - uint8_t digest_bytes_len[HASH_LEN_SIZE]; - uint8_t tmp_digest[CC_DIGEST_SIZE_MAX]; - uint8_t din[NIST_HMAC_MSG_SIZE]; - uint8_t mac_res[CC_DIGEST_SIZE_MAX]; + u8 initial_digest[CC_DIGEST_SIZE_MAX]; + u8 key[CC_HMAC_BLOCK_SIZE_MAX]; + u8 k0[CC_HMAC_BLOCK_SIZE_MAX]; + u8 digest_bytes_len[HASH_LEN_SIZE]; + u8 tmp_digest[CC_DIGEST_SIZE_MAX]; + u8 din[NIST_HMAC_MSG_SIZE]; + u8 mac_res[CC_DIGEST_SIZE_MAX]; }; typedef struct _FipsHmacData { enum drv_hash_mode hash_mode; - uint8_t key[CC_HMAC_BLOCK_SIZE_MAX]; + u8 key[CC_HMAC_BLOCK_SIZE_MAX]; size_t key_size; - uint8_t data_in[NIST_HMAC_MSG_SIZE]; + u8 data_in[NIST_HMAC_MSG_SIZE]; size_t data_in_size; - uint8_t mac_res[CC_DIGEST_SIZE_MAX]; + u8 mac_res[CC_DIGEST_SIZE_MAX]; } FipsHmacData; - #define FIPS_CCM_B0_A0_ADATA_SIZE (NIST_AESCCM_IV_SIZE + NIST_AESCCM_IV_SIZE + NIST_AESCCM_ADATA_SIZE) struct fips_ccm_ctx { - uint8_t b0_a0_adata[FIPS_CCM_B0_A0_ADATA_SIZE]; - uint8_t iv[NIST_AESCCM_IV_SIZE]; - uint8_t ctr_cnt_0[NIST_AESCCM_IV_SIZE]; - uint8_t key[CC_AES_KEY_SIZE_MAX]; - uint8_t din[NIST_AESCCM_TEXT_SIZE]; - uint8_t dout[NIST_AESCCM_TEXT_SIZE]; - uint8_t mac_res[NIST_AESCCM_TAG_SIZE]; + u8 b0_a0_adata[FIPS_CCM_B0_A0_ADATA_SIZE]; + u8 iv[NIST_AESCCM_IV_SIZE]; + u8 ctr_cnt_0[NIST_AESCCM_IV_SIZE]; + u8 key[CC_AES_KEY_SIZE_MAX]; + u8 din[NIST_AESCCM_TEXT_SIZE]; + u8 dout[NIST_AESCCM_TEXT_SIZE]; + u8 mac_res[NIST_AESCCM_TAG_SIZE]; }; typedef struct _FipsCcmData { enum drv_crypto_direction direction; - uint8_t key[CC_AES_KEY_SIZE_MAX]; + u8 key[CC_AES_KEY_SIZE_MAX]; size_t keySize; - uint8_t nonce[NIST_AESCCM_NONCE_SIZE]; - uint8_t adata[NIST_AESCCM_ADATA_SIZE]; + u8 nonce[NIST_AESCCM_NONCE_SIZE]; + u8 adata[NIST_AESCCM_ADATA_SIZE]; size_t adataSize; - uint8_t dataIn[NIST_AESCCM_TEXT_SIZE]; + u8 dataIn[NIST_AESCCM_TEXT_SIZE]; size_t dataInSize; - uint8_t dataOut[NIST_AESCCM_TEXT_SIZE]; - uint8_t tagSize; - uint8_t macResOut[NIST_AESCCM_TAG_SIZE]; + u8 dataOut[NIST_AESCCM_TEXT_SIZE]; + u8 tagSize; + u8 macResOut[NIST_AESCCM_TAG_SIZE]; } FipsCcmData; - struct fips_gcm_ctx { - uint8_t adata[NIST_AESGCM_ADATA_SIZE]; - uint8_t key[CC_AES_KEY_SIZE_MAX]; - uint8_t hkey[CC_AES_KEY_SIZE_MAX]; - uint8_t din[NIST_AESGCM_TEXT_SIZE]; - uint8_t dout[NIST_AESGCM_TEXT_SIZE]; - uint8_t mac_res[NIST_AESGCM_TAG_SIZE]; - uint8_t len_block[AES_BLOCK_SIZE]; - uint8_t iv_inc1[AES_BLOCK_SIZE]; - uint8_t iv_inc2[AES_BLOCK_SIZE]; + u8 adata[NIST_AESGCM_ADATA_SIZE]; + u8 key[CC_AES_KEY_SIZE_MAX]; + u8 hkey[CC_AES_KEY_SIZE_MAX]; + u8 din[NIST_AESGCM_TEXT_SIZE]; + u8 dout[NIST_AESGCM_TEXT_SIZE]; + u8 mac_res[NIST_AESGCM_TAG_SIZE]; + u8 len_block[AES_BLOCK_SIZE]; + u8 iv_inc1[AES_BLOCK_SIZE]; + u8 iv_inc2[AES_BLOCK_SIZE]; }; typedef struct _FipsGcmData { enum drv_crypto_direction direction; - uint8_t key[CC_AES_KEY_SIZE_MAX]; + u8 key[CC_AES_KEY_SIZE_MAX]; size_t keySize; - uint8_t iv[NIST_AESGCM_IV_SIZE]; - uint8_t adata[NIST_AESGCM_ADATA_SIZE]; + u8 iv[NIST_AESGCM_IV_SIZE]; + u8 adata[NIST_AESGCM_ADATA_SIZE]; size_t adataSize; - uint8_t dataIn[NIST_AESGCM_TEXT_SIZE]; + u8 dataIn[NIST_AESGCM_TEXT_SIZE]; size_t dataInSize; - uint8_t dataOut[NIST_AESGCM_TEXT_SIZE]; - uint8_t tagSize; - uint8_t macResOut[NIST_AESGCM_TAG_SIZE]; + u8 dataOut[NIST_AESGCM_TEXT_SIZE]; + u8 tagSize; + u8 macResOut[NIST_AESGCM_TAG_SIZE]; } FipsGcmData; - typedef union _fips_ctx { struct fips_cipher_ctx cipher; struct fips_cmac_ctx cmac; @@ -181,7 +173,6 @@ typedef union _fips_ctx { struct fips_gcm_ctx gcm; } fips_ctx; - /* test data tables */ static const FipsCipherData FipsCipherDataTable[] = { /* AES */ @@ -214,8 +205,8 @@ static const FipsCipherData FipsCipherDataTable[] = { { 1, NIST_AES_256_XTS_KEY, CC_AES_256_BIT_KEY_SIZE, NIST_AES_256_XTS_IV, DRV_CRYPTO_DIRECTION_ENCRYPT, DRV_CIPHER_XTS, NIST_AES_256_XTS_PLAIN, NIST_AES_256_XTS_CIPHER, NIST_AES_256_XTS_VECTOR_SIZE }, { 1, NIST_AES_256_XTS_KEY, CC_AES_256_BIT_KEY_SIZE, NIST_AES_256_XTS_IV, DRV_CRYPTO_DIRECTION_DECRYPT, DRV_CIPHER_XTS, NIST_AES_256_XTS_CIPHER, NIST_AES_256_XTS_PLAIN, NIST_AES_256_XTS_VECTOR_SIZE }, #if (CC_SUPPORT_SHA > 256) - { 1, NIST_AES_512_XTS_KEY, 2*CC_AES_256_BIT_KEY_SIZE, NIST_AES_512_XTS_IV, DRV_CRYPTO_DIRECTION_ENCRYPT, DRV_CIPHER_XTS, NIST_AES_512_XTS_PLAIN, NIST_AES_512_XTS_CIPHER, NIST_AES_512_XTS_VECTOR_SIZE }, - { 1, NIST_AES_512_XTS_KEY, 2*CC_AES_256_BIT_KEY_SIZE, NIST_AES_512_XTS_IV, DRV_CRYPTO_DIRECTION_DECRYPT, DRV_CIPHER_XTS, NIST_AES_512_XTS_CIPHER, NIST_AES_512_XTS_PLAIN, NIST_AES_512_XTS_VECTOR_SIZE }, + { 1, NIST_AES_512_XTS_KEY, 2 * CC_AES_256_BIT_KEY_SIZE, NIST_AES_512_XTS_IV, DRV_CRYPTO_DIRECTION_ENCRYPT, DRV_CIPHER_XTS, NIST_AES_512_XTS_PLAIN, NIST_AES_512_XTS_CIPHER, NIST_AES_512_XTS_VECTOR_SIZE }, + { 1, NIST_AES_512_XTS_KEY, 2 * CC_AES_256_BIT_KEY_SIZE, NIST_AES_512_XTS_IV, DRV_CRYPTO_DIRECTION_DECRYPT, DRV_CIPHER_XTS, NIST_AES_512_XTS_CIPHER, NIST_AES_512_XTS_PLAIN, NIST_AES_512_XTS_VECTOR_SIZE }, #endif /* DES */ { 0, NIST_TDES_ECB3_KEY, CC_DRV_DES_TRIPLE_KEY_SIZE, NIST_TDES_ECB_IV, DRV_CRYPTO_DIRECTION_ENCRYPT, DRV_CIPHER_ECB, NIST_TDES_ECB3_PLAIN_DATA, NIST_TDES_ECB3_CIPHER, NIST_TDES_VECTOR_SIZE }, @@ -223,6 +214,7 @@ static const FipsCipherData FipsCipherDataTable[] = { { 0, NIST_TDES_CBC3_KEY, CC_DRV_DES_TRIPLE_KEY_SIZE, NIST_TDES_CBC3_IV, DRV_CRYPTO_DIRECTION_ENCRYPT, DRV_CIPHER_CBC, NIST_TDES_CBC3_PLAIN_DATA, NIST_TDES_CBC3_CIPHER, NIST_TDES_VECTOR_SIZE }, { 0, NIST_TDES_CBC3_KEY, CC_DRV_DES_TRIPLE_KEY_SIZE, NIST_TDES_CBC3_IV, DRV_CRYPTO_DIRECTION_DECRYPT, DRV_CIPHER_CBC, NIST_TDES_CBC3_CIPHER, NIST_TDES_CBC3_PLAIN_DATA, NIST_TDES_VECTOR_SIZE }, }; + #define FIPS_CIPHER_NUM_OF_TESTS (sizeof(FipsCipherDataTable) / sizeof(FipsCipherData)) static const FipsCmacData FipsCmacDataTable[] = { @@ -230,56 +222,60 @@ static const FipsCmacData FipsCmacDataTable[] = { { DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AES_192_CMAC_KEY, AES_192_BIT_KEY_SIZE, NIST_AES_192_CMAC_PLAIN_DATA, NIST_AES_192_CMAC_VECTOR_SIZE, NIST_AES_192_CMAC_MAC, NIST_AES_192_CMAC_OUTPUT_SIZE }, { DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AES_256_CMAC_KEY, AES_256_BIT_KEY_SIZE, NIST_AES_256_CMAC_PLAIN_DATA, NIST_AES_256_CMAC_VECTOR_SIZE, NIST_AES_256_CMAC_MAC, NIST_AES_256_CMAC_OUTPUT_SIZE }, }; + #define FIPS_CMAC_NUM_OF_TESTS (sizeof(FipsCmacDataTable) / sizeof(FipsCmacData)) static const FipsHashData FipsHashDataTable[] = { - { DRV_HASH_SHA1, NIST_SHA_1_MSG, NIST_SHA_MSG_SIZE, NIST_SHA_1_MD }, - { DRV_HASH_SHA256, NIST_SHA_256_MSG, NIST_SHA_MSG_SIZE, NIST_SHA_256_MD }, + { DRV_HASH_SHA1, NIST_SHA_1_MSG, NIST_SHA_MSG_SIZE, NIST_SHA_1_MD }, + { DRV_HASH_SHA256, NIST_SHA_256_MSG, NIST_SHA_MSG_SIZE, NIST_SHA_256_MD }, #if (CC_SUPPORT_SHA > 256) // { DRV_HASH_SHA512, NIST_SHA_512_MSG, NIST_SHA_MSG_SIZE, NIST_SHA_512_MD }, #endif }; + #define FIPS_HASH_NUM_OF_TESTS (sizeof(FipsHashDataTable) / sizeof(FipsHashData)) static const FipsHmacData FipsHmacDataTable[] = { - { DRV_HASH_SHA1, NIST_HMAC_SHA1_KEY, NIST_HMAC_SHA1_KEY_SIZE, NIST_HMAC_SHA1_MSG, NIST_HMAC_MSG_SIZE, NIST_HMAC_SHA1_MD }, - { DRV_HASH_SHA256, NIST_HMAC_SHA256_KEY, NIST_HMAC_SHA256_KEY_SIZE, NIST_HMAC_SHA256_MSG, NIST_HMAC_MSG_SIZE, NIST_HMAC_SHA256_MD }, + { DRV_HASH_SHA1, NIST_HMAC_SHA1_KEY, NIST_HMAC_SHA1_KEY_SIZE, NIST_HMAC_SHA1_MSG, NIST_HMAC_MSG_SIZE, NIST_HMAC_SHA1_MD }, + { DRV_HASH_SHA256, NIST_HMAC_SHA256_KEY, NIST_HMAC_SHA256_KEY_SIZE, NIST_HMAC_SHA256_MSG, NIST_HMAC_MSG_SIZE, NIST_HMAC_SHA256_MD }, #if (CC_SUPPORT_SHA > 256) // { DRV_HASH_SHA512, NIST_HMAC_SHA512_KEY, NIST_HMAC_SHA512_KEY_SIZE, NIST_HMAC_SHA512_MSG, NIST_HMAC_MSG_SIZE, NIST_HMAC_SHA512_MD }, #endif }; + #define FIPS_HMAC_NUM_OF_TESTS (sizeof(FipsHmacDataTable) / sizeof(FipsHmacData)) static const FipsCcmData FipsCcmDataTable[] = { - { DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESCCM_128_KEY, NIST_AESCCM_128_BIT_KEY_SIZE, NIST_AESCCM_128_NONCE, NIST_AESCCM_128_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_128_PLAIN_TEXT, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_128_CIPHER, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_128_MAC }, - { DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESCCM_128_KEY, NIST_AESCCM_128_BIT_KEY_SIZE, NIST_AESCCM_128_NONCE, NIST_AESCCM_128_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_128_CIPHER, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_128_PLAIN_TEXT, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_128_MAC }, - { DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESCCM_192_KEY, NIST_AESCCM_192_BIT_KEY_SIZE, NIST_AESCCM_192_NONCE, NIST_AESCCM_192_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_192_PLAIN_TEXT, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_192_CIPHER, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_192_MAC }, - { DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESCCM_192_KEY, NIST_AESCCM_192_BIT_KEY_SIZE, NIST_AESCCM_192_NONCE, NIST_AESCCM_192_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_192_CIPHER, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_192_PLAIN_TEXT, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_192_MAC }, - { DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESCCM_256_KEY, NIST_AESCCM_256_BIT_KEY_SIZE, NIST_AESCCM_256_NONCE, NIST_AESCCM_256_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_256_PLAIN_TEXT, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_256_CIPHER, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_256_MAC }, - { DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESCCM_256_KEY, NIST_AESCCM_256_BIT_KEY_SIZE, NIST_AESCCM_256_NONCE, NIST_AESCCM_256_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_256_CIPHER, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_256_PLAIN_TEXT, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_256_MAC }, + { DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESCCM_128_KEY, NIST_AESCCM_128_BIT_KEY_SIZE, NIST_AESCCM_128_NONCE, NIST_AESCCM_128_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_128_PLAIN_TEXT, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_128_CIPHER, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_128_MAC }, + { DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESCCM_128_KEY, NIST_AESCCM_128_BIT_KEY_SIZE, NIST_AESCCM_128_NONCE, NIST_AESCCM_128_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_128_CIPHER, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_128_PLAIN_TEXT, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_128_MAC }, + { DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESCCM_192_KEY, NIST_AESCCM_192_BIT_KEY_SIZE, NIST_AESCCM_192_NONCE, NIST_AESCCM_192_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_192_PLAIN_TEXT, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_192_CIPHER, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_192_MAC }, + { DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESCCM_192_KEY, NIST_AESCCM_192_BIT_KEY_SIZE, NIST_AESCCM_192_NONCE, NIST_AESCCM_192_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_192_CIPHER, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_192_PLAIN_TEXT, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_192_MAC }, + { DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESCCM_256_KEY, NIST_AESCCM_256_BIT_KEY_SIZE, NIST_AESCCM_256_NONCE, NIST_AESCCM_256_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_256_PLAIN_TEXT, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_256_CIPHER, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_256_MAC }, + { DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESCCM_256_KEY, NIST_AESCCM_256_BIT_KEY_SIZE, NIST_AESCCM_256_NONCE, NIST_AESCCM_256_ADATA, NIST_AESCCM_ADATA_SIZE, NIST_AESCCM_256_CIPHER, NIST_AESCCM_TEXT_SIZE, NIST_AESCCM_256_PLAIN_TEXT, NIST_AESCCM_TAG_SIZE, NIST_AESCCM_256_MAC }, }; + #define FIPS_CCM_NUM_OF_TESTS (sizeof(FipsCcmDataTable) / sizeof(FipsCcmData)) static const FipsGcmData FipsGcmDataTable[] = { - { DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESGCM_128_KEY, NIST_AESGCM_128_BIT_KEY_SIZE, NIST_AESGCM_128_IV, NIST_AESGCM_128_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_128_PLAIN_TEXT, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_128_CIPHER, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_128_MAC }, - { DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESGCM_128_KEY, NIST_AESGCM_128_BIT_KEY_SIZE, NIST_AESGCM_128_IV, NIST_AESGCM_128_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_128_CIPHER, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_128_PLAIN_TEXT, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_128_MAC }, - { DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESGCM_192_KEY, NIST_AESGCM_192_BIT_KEY_SIZE, NIST_AESGCM_192_IV, NIST_AESGCM_192_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_192_PLAIN_TEXT, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_192_CIPHER, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_192_MAC }, - { DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESGCM_192_KEY, NIST_AESGCM_192_BIT_KEY_SIZE, NIST_AESGCM_192_IV, NIST_AESGCM_192_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_192_CIPHER, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_192_PLAIN_TEXT, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_192_MAC }, - { DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESGCM_256_KEY, NIST_AESGCM_256_BIT_KEY_SIZE, NIST_AESGCM_256_IV, NIST_AESGCM_256_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_256_PLAIN_TEXT, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_256_CIPHER, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_256_MAC }, - { DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESGCM_256_KEY, NIST_AESGCM_256_BIT_KEY_SIZE, NIST_AESGCM_256_IV, NIST_AESGCM_256_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_256_CIPHER, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_256_PLAIN_TEXT, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_256_MAC }, + { DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESGCM_128_KEY, NIST_AESGCM_128_BIT_KEY_SIZE, NIST_AESGCM_128_IV, NIST_AESGCM_128_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_128_PLAIN_TEXT, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_128_CIPHER, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_128_MAC }, + { DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESGCM_128_KEY, NIST_AESGCM_128_BIT_KEY_SIZE, NIST_AESGCM_128_IV, NIST_AESGCM_128_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_128_CIPHER, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_128_PLAIN_TEXT, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_128_MAC }, + { DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESGCM_192_KEY, NIST_AESGCM_192_BIT_KEY_SIZE, NIST_AESGCM_192_IV, NIST_AESGCM_192_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_192_PLAIN_TEXT, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_192_CIPHER, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_192_MAC }, + { DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESGCM_192_KEY, NIST_AESGCM_192_BIT_KEY_SIZE, NIST_AESGCM_192_IV, NIST_AESGCM_192_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_192_CIPHER, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_192_PLAIN_TEXT, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_192_MAC }, + { DRV_CRYPTO_DIRECTION_ENCRYPT, NIST_AESGCM_256_KEY, NIST_AESGCM_256_BIT_KEY_SIZE, NIST_AESGCM_256_IV, NIST_AESGCM_256_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_256_PLAIN_TEXT, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_256_CIPHER, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_256_MAC }, + { DRV_CRYPTO_DIRECTION_DECRYPT, NIST_AESGCM_256_KEY, NIST_AESGCM_256_BIT_KEY_SIZE, NIST_AESGCM_256_IV, NIST_AESGCM_256_ADATA, NIST_AESGCM_ADATA_SIZE, NIST_AESGCM_256_CIPHER, NIST_AESGCM_TEXT_SIZE, NIST_AESGCM_256_PLAIN_TEXT, NIST_AESGCM_TAG_SIZE, NIST_AESGCM_256_MAC }, }; -#define FIPS_GCM_NUM_OF_TESTS (sizeof(FipsGcmDataTable) / sizeof(FipsGcmData)) +#define FIPS_GCM_NUM_OF_TESTS (sizeof(FipsGcmDataTable) / sizeof(FipsGcmData)) -static inline ssi_fips_error_t +static inline enum cc_fips_error FIPS_CipherToFipsError(enum drv_cipher_mode mode, bool is_aes) { switch (mode) { case DRV_CIPHER_ECB: - return is_aes ? CC_REE_FIPS_ERROR_AES_ECB_PUT : CC_REE_FIPS_ERROR_DES_ECB_PUT ; + return is_aes ? CC_REE_FIPS_ERROR_AES_ECB_PUT : CC_REE_FIPS_ERROR_DES_ECB_PUT; case DRV_CIPHER_CBC: - return is_aes ? CC_REE_FIPS_ERROR_AES_CBC_PUT : CC_REE_FIPS_ERROR_DES_CBC_PUT ; + return is_aes ? CC_REE_FIPS_ERROR_AES_CBC_PUT : CC_REE_FIPS_ERROR_DES_CBC_PUT; case DRV_CIPHER_OFB: return CC_REE_FIPS_ERROR_AES_OFB_PUT; case DRV_CIPHER_CTR: @@ -295,8 +291,7 @@ FIPS_CipherToFipsError(enum drv_cipher_mode mode, bool is_aes) return CC_REE_FIPS_ERROR_GENERAL; } - -static inline int +static inline int ssi_cipher_fips_run_test(struct ssi_drvdata *drvdata, bool is_aes, int cipher_mode, @@ -314,7 +309,7 @@ ssi_cipher_fips_run_test(struct ssi_drvdata *drvdata, int rc; struct ssi_crypto_req ssi_req = {0}; - HwDesc_s desc[FIPS_CIPHER_MAX_SEQ_LEN]; + struct cc_hw_desc desc[FIPS_CIPHER_MAX_SEQ_LEN]; int idx = 0; int s_flow_mode = is_aes ? S_DIN_to_AES : S_DIN_to_DES; @@ -325,74 +320,73 @@ ssi_cipher_fips_run_test(struct ssi_drvdata *drvdata, case DRV_CIPHER_CTR: case DRV_CIPHER_OFB: /* Load cipher state */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - iv_dma_addr, iv_len, NS_BIT); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], direction); - HW_DESC_SET_FLOW_MODE(&desc[idx], s_flow_mode); - HW_DESC_SET_CIPHER_MODE(&desc[idx], cipher_mode); - if ((cipher_mode == DRV_CIPHER_CTR) || - (cipher_mode == DRV_CIPHER_OFB) ) { - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE1); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, + iv_dma_addr, iv_len, NS_BIT); + set_cipher_config0(&desc[idx], direction); + set_flow_mode(&desc[idx], s_flow_mode); + set_cipher_mode(&desc[idx], cipher_mode); + if ((cipher_mode == DRV_CIPHER_CTR) || + (cipher_mode == DRV_CIPHER_OFB)) { + set_setup_mode(&desc[idx], SETUP_LOAD_STATE1); } else { - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); } idx++; /*FALLTHROUGH*/ case DRV_CIPHER_ECB: /* Load key */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], cipher_mode); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], direction); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], cipher_mode); + set_cipher_config0(&desc[idx], direction); if (is_aes) { - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - key_dma_addr, - ((key_len == 24) ? AES_MAX_KEY_SIZE : key_len), - NS_BIT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], key_len); + set_din_type(&desc[idx], DMA_DLLI, key_dma_addr, + ((key_len == 24) ? AES_MAX_KEY_SIZE : + key_len), NS_BIT); + set_key_size_aes(&desc[idx], key_len); } else {/*des*/ - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - key_dma_addr, key_len, - NS_BIT); - HW_DESC_SET_KEY_SIZE_DES(&desc[idx], key_len); + set_din_type(&desc[idx], DMA_DLLI, key_dma_addr, + key_len, NS_BIT); + set_key_size_des(&desc[idx], key_len); } - HW_DESC_SET_FLOW_MODE(&desc[idx], s_flow_mode); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + set_flow_mode(&desc[idx], s_flow_mode); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; break; case DRV_CIPHER_XTS: /* Load AES key */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], cipher_mode); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], direction); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - key_dma_addr, key_len/2, NS_BIT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], key_len/2); - HW_DESC_SET_FLOW_MODE(&desc[idx], s_flow_mode); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], cipher_mode); + set_cipher_config0(&desc[idx], direction); + set_din_type(&desc[idx], DMA_DLLI, key_dma_addr, (key_len / 2), + NS_BIT); + set_key_size_aes(&desc[idx], (key_len / 2)); + set_flow_mode(&desc[idx], s_flow_mode); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; /* load XEX key */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], cipher_mode); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], direction); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - (key_dma_addr+key_len/2), key_len/2, NS_BIT); - HW_DESC_SET_XEX_DATA_UNIT_SIZE(&desc[idx], data_size); - HW_DESC_SET_FLOW_MODE(&desc[idx], s_flow_mode); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], key_len/2); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_XEX_KEY); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], cipher_mode); + set_cipher_config0(&desc[idx], direction); + set_din_type(&desc[idx], DMA_DLLI, + (key_dma_addr + (key_len / 2)), + (key_len / 2), NS_BIT); + set_xex_data_unit_size(&desc[idx], data_size); + set_flow_mode(&desc[idx], s_flow_mode); + set_key_size_aes(&desc[idx], (key_len / 2)); + set_setup_mode(&desc[idx], SETUP_LOAD_XEX_KEY); idx++; /* Set state */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE1); - HW_DESC_SET_CIPHER_MODE(&desc[idx], cipher_mode); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], direction); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], key_len/2); - HW_DESC_SET_FLOW_MODE(&desc[idx], s_flow_mode); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - iv_dma_addr, CC_AES_BLOCK_SIZE, NS_BIT); + hw_desc_init(&desc[idx]); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE1); + set_cipher_mode(&desc[idx], cipher_mode); + set_cipher_config0(&desc[idx], direction); + set_key_size_aes(&desc[idx], (key_len / 2)); + set_flow_mode(&desc[idx], s_flow_mode); + set_din_type(&desc[idx], DMA_DLLI, iv_dma_addr, + CC_AES_BLOCK_SIZE, NS_BIT); idx++; break; default: @@ -401,10 +395,10 @@ ssi_cipher_fips_run_test(struct ssi_drvdata *drvdata, } /* create data descriptor */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, din_dma_addr, data_size, NS_BIT); - HW_DESC_SET_DOUT_DLLI(&desc[idx], dout_dma_addr, data_size, NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&desc[idx], is_aes ? DIN_AES_DOUT : DIN_DES_DOUT); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, din_dma_addr, data_size, NS_BIT); + set_dout_dlli(&desc[idx], dout_dma_addr, data_size, NS_BIT, 0); + set_flow_mode(&desc[idx], is_aes ? DIN_AES_DOUT : DIN_DES_DOUT); idx++; /* perform the operation - Lock HW and push sequence */ @@ -415,11 +409,10 @@ ssi_cipher_fips_run_test(struct ssi_drvdata *drvdata, return rc; } - -ssi_fips_error_t +enum cc_fips_error ssi_cipher_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer) { - ssi_fips_error_t error = CC_REE_FIPS_ERROR_OK; + enum cc_fips_error error = CC_REE_FIPS_ERROR_OK; size_t i; struct fips_cipher_ctx *virt_ctx = (struct fips_cipher_ctx *)cpu_addr_buffer; @@ -431,9 +424,9 @@ ssi_cipher_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffe for (i = 0; i < FIPS_CIPHER_NUM_OF_TESTS; ++i) { - FipsCipherData *cipherData = (FipsCipherData*)&FipsCipherDataTable[i]; + FipsCipherData *cipherData = (FipsCipherData *)&FipsCipherDataTable[i]; int rc = 0; - size_t iv_size = cipherData->isAes ? NIST_AES_IV_SIZE : NIST_TDES_IV_SIZE ; + size_t iv_size = cipherData->isAes ? NIST_AES_IV_SIZE : NIST_TDES_IV_SIZE; memset(cpu_addr_buffer, 0, sizeof(struct fips_cipher_ctx)); @@ -480,8 +473,7 @@ ssi_cipher_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffe return error; } - -static inline int +static inline int ssi_cmac_fips_run_test(struct ssi_drvdata *drvdata, dma_addr_t key_dma_addr, size_t key_len, @@ -495,46 +487,45 @@ ssi_cmac_fips_run_test(struct ssi_drvdata *drvdata, int rc; struct ssi_crypto_req ssi_req = {0}; - HwDesc_s desc[FIPS_CMAC_MAX_SEQ_LEN]; + struct cc_hw_desc desc[FIPS_CMAC_MAX_SEQ_LEN]; int idx = 0; /* Setup CMAC Key */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, key_dma_addr, - ((key_len == 24) ? AES_MAX_KEY_SIZE : key_len), NS_BIT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_CMAC); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], key_len); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, key_dma_addr, + ((key_len == 24) ? AES_MAX_KEY_SIZE : key_len), NS_BIT); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); + set_cipher_mode(&desc[idx], DRV_CIPHER_CMAC); + set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_key_size_aes(&desc[idx], key_len); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; /* Load MAC state */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, digest_dma_addr, CC_AES_BLOCK_SIZE, NS_BIT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_CMAC); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], key_len); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, digest_dma_addr, CC_AES_BLOCK_SIZE, + NS_BIT); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); + set_cipher_mode(&desc[idx], DRV_CIPHER_CMAC); + set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_key_size_aes(&desc[idx], key_len); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; - //ssi_hash_create_data_desc(state, ctx, DIN_AES_DOUT, desc, false, &idx); - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - din_dma_addr, - din_len, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_AES_DOUT); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, din_dma_addr, din_len, NS_BIT); + set_flow_mode(&desc[idx], DIN_AES_DOUT); idx++; - + /* Get final MAC result */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DOUT_DLLI(&desc[idx], digest_dma_addr, CC_AES_BLOCK_SIZE, NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_AES_to_DOUT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_CMAC); + hw_desc_init(&desc[idx]); + set_dout_dlli(&desc[idx], digest_dma_addr, CC_AES_BLOCK_SIZE, NS_BIT, + 0); + set_flow_mode(&desc[idx], S_AES_to_DOUT); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); + set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_cipher_mode(&desc[idx], DRV_CIPHER_CMAC); idx++; /* perform the operation - Lock HW and push sequence */ @@ -545,10 +536,10 @@ ssi_cmac_fips_run_test(struct ssi_drvdata *drvdata, return rc; } -ssi_fips_error_t +enum cc_fips_error ssi_cmac_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer) { - ssi_fips_error_t error = CC_REE_FIPS_ERROR_OK; + enum cc_fips_error error = CC_REE_FIPS_ERROR_OK; size_t i; struct fips_cmac_ctx *virt_ctx = (struct fips_cmac_ctx *)cpu_addr_buffer; @@ -559,7 +550,7 @@ ssi_cmac_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, for (i = 0; i < FIPS_CMAC_NUM_OF_TESTS; ++i) { - FipsCmacData *cmac_data = (FipsCmacData*)&FipsCmacDataTable[i]; + FipsCmacData *cmac_data = (FipsCmacData *)&FipsCmacDataTable[i]; int rc = 0; memset(cpu_addr_buffer, 0, sizeof(struct fips_cmac_ctx)); @@ -604,8 +595,7 @@ ssi_cmac_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, return error; } - -static inline ssi_fips_error_t +static inline enum cc_fips_error FIPS_HashToFipsError(enum drv_hash_mode hash_mode) { switch (hash_mode) { @@ -624,7 +614,7 @@ FIPS_HashToFipsError(enum drv_hash_mode hash_mode) return CC_REE_FIPS_ERROR_GENERAL; } -static inline int +static inline int ssi_hash_fips_run_test(struct ssi_drvdata *drvdata, dma_addr_t initial_digest_dma_addr, dma_addr_t din_dma_addr, @@ -640,45 +630,47 @@ ssi_hash_fips_run_test(struct ssi_drvdata *drvdata, int rc; struct ssi_crypto_req ssi_req = {0}; - HwDesc_s desc[FIPS_HASH_MAX_SEQ_LEN]; + struct cc_hw_desc desc[FIPS_HASH_MAX_SEQ_LEN]; int idx = 0; /* Load initial digest */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hw_mode); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, initial_digest_dma_addr, inter_digestsize, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], hw_mode); + set_din_type(&desc[idx], DMA_DLLI, initial_digest_dma_addr, + inter_digestsize, NS_BIT); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); idx++; /* Load the hash current length */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hw_mode); - HW_DESC_SET_DIN_CONST(&desc[idx], 0, HASH_LEN_SIZE); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_ENABLED); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], hw_mode); + set_din_const(&desc[idx], 0, HASH_LEN_SIZE); + set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; /* data descriptor */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, din_dma_addr, data_in_size, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_HASH); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, din_dma_addr, data_in_size, NS_BIT); + set_flow_mode(&desc[idx], DIN_HASH); idx++; /* Get final MAC result */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hw_mode); - HW_DESC_SET_DOUT_DLLI(&desc[idx], mac_res_dma_addr, digest_size, NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_DISABLED); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], hw_mode); + set_dout_dlli(&desc[idx], mac_res_dma_addr, digest_size, NS_BIT, 0); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); + set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); if (unlikely((hash_mode == DRV_HASH_MD5) || (hash_mode == DRV_HASH_SHA384) || (hash_mode == DRV_HASH_SHA512))) { - HW_DESC_SET_BYTES_SWAP(&desc[idx], 1); + set_bytes_swap(&desc[idx], 1); } else { - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], HASH_DIGEST_RESULT_LITTLE_ENDIAN); + set_cipher_config0(&desc[idx], + HASH_DIGEST_RESULT_LITTLE_ENDIAN); } idx++; @@ -689,10 +681,10 @@ ssi_hash_fips_run_test(struct ssi_drvdata *drvdata, return rc; } -ssi_fips_error_t +enum cc_fips_error ssi_hash_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer) { - ssi_fips_error_t error = CC_REE_FIPS_ERROR_OK; + enum cc_fips_error error = CC_REE_FIPS_ERROR_OK; size_t i; struct fips_hash_ctx *virt_ctx = (struct fips_hash_ctx *)cpu_addr_buffer; @@ -703,7 +695,7 @@ ssi_hash_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, for (i = 0; i < FIPS_HASH_NUM_OF_TESTS; ++i) { - FipsHashData *hash_data = (FipsHashData*)&FipsHashDataTable[i]; + FipsHashData *hash_data = (FipsHashData *)&FipsHashDataTable[i]; int rc = 0; enum drv_hash_hw_mode hw_mode = 0; int digest_size = 0; @@ -717,20 +709,20 @@ ssi_hash_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, digest_size = CC_SHA1_DIGEST_SIZE; inter_digestsize = CC_SHA1_DIGEST_SIZE; /* copy the initial digest into the allocated cache coherent buffer */ - memcpy(virt_ctx->initial_digest, (void*)sha1_init, CC_SHA1_DIGEST_SIZE); + memcpy(virt_ctx->initial_digest, (void *)sha1_init, CC_SHA1_DIGEST_SIZE); break; case DRV_HASH_SHA256: hw_mode = DRV_HASH_HW_SHA256; digest_size = CC_SHA256_DIGEST_SIZE; inter_digestsize = CC_SHA256_DIGEST_SIZE; - memcpy(virt_ctx->initial_digest, (void*)sha256_init, CC_SHA256_DIGEST_SIZE); + memcpy(virt_ctx->initial_digest, (void *)sha256_init, CC_SHA256_DIGEST_SIZE); break; #if (CC_SUPPORT_SHA > 256) case DRV_HASH_SHA512: hw_mode = DRV_HASH_HW_SHA512; digest_size = CC_SHA512_DIGEST_SIZE; inter_digestsize = CC_SHA512_DIGEST_SIZE; - memcpy(virt_ctx->initial_digest, (void*)sha512_init, CC_SHA512_DIGEST_SIZE); + memcpy(virt_ctx->initial_digest, (void *)sha512_init, CC_SHA512_DIGEST_SIZE); break; #endif default: @@ -757,7 +749,7 @@ ssi_hash_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, FIPS_LOG("ssi_hash_fips_run_test %d returned error - rc = %d \n", i, rc); error = FIPS_HashToFipsError(hash_data->hash_mode); break; - } + } /* compare actual mac result to expected */ if (memcmp(virt_ctx->mac_res, hash_data->mac_res, digest_size) != 0) @@ -772,14 +764,13 @@ ssi_hash_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, error = FIPS_HashToFipsError(hash_data->hash_mode); break; - } + } } return error; } - -static inline ssi_fips_error_t +static inline enum cc_fips_error FIPS_HmacToFipsError(enum drv_hash_mode hash_mode) { switch (hash_mode) { @@ -798,7 +789,7 @@ FIPS_HmacToFipsError(enum drv_hash_mode hash_mode) return CC_REE_FIPS_ERROR_GENERAL; } -static inline int +static inline int ssi_hmac_fips_run_test(struct ssi_drvdata *drvdata, dma_addr_t initial_digest_dma_addr, dma_addr_t key_dma_addr, @@ -816,34 +807,34 @@ ssi_hmac_fips_run_test(struct ssi_drvdata *drvdata, dma_addr_t digest_bytes_len_dma_addr) { /* The implemented flow is not the same as the one implemented in ssi_hash.c (setkey + digest flows). - In this flow, there is no need to store and reload some of the intermidiate results. */ + * In this flow, there is no need to store and reload some of the intermidiate results. + */ /* max number of descriptors used for the flow */ #define FIPS_HMAC_MAX_SEQ_LEN 12 int rc; struct ssi_crypto_req ssi_req = {0}; - HwDesc_s desc[FIPS_HMAC_MAX_SEQ_LEN]; + struct cc_hw_desc desc[FIPS_HMAC_MAX_SEQ_LEN]; int idx = 0; int i; /* calc the hash opad first and ipad only afterwards (unlike the flow in ssi_hash.c) */ unsigned int hmacPadConst[2] = { HMAC_OPAD_CONST, HMAC_IPAD_CONST }; // assume (key_size <= block_size) - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, key_dma_addr, key_size, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], BYPASS); - HW_DESC_SET_DOUT_DLLI(&desc[idx], k0_dma_addr, key_size, NS_BIT, 0); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, key_dma_addr, key_size, NS_BIT); + set_flow_mode(&desc[idx], BYPASS); + set_dout_dlli(&desc[idx], k0_dma_addr, key_size, NS_BIT, 0); idx++; // if needed, append Key with zeros to create K0 if ((block_size - key_size) != 0) { - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_CONST(&desc[idx], 0, (block_size - key_size)); - HW_DESC_SET_FLOW_MODE(&desc[idx], BYPASS); - HW_DESC_SET_DOUT_DLLI(&desc[idx], - (k0_dma_addr + key_size), (block_size - key_size), - NS_BIT, 0); + hw_desc_init(&desc[idx]); + set_din_const(&desc[idx], 0, (block_size - key_size)); + set_flow_mode(&desc[idx], BYPASS); + set_dout_dlli(&desc[idx], (k0_dma_addr + key_size), + (block_size - key_size), NS_BIT, 0); idx++; } @@ -858,50 +849,47 @@ ssi_hmac_fips_run_test(struct ssi_drvdata *drvdata, /* calc derived HMAC key */ for (i = 0; i < 2; i++) { /* Load hash initial state */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hw_mode); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, initial_digest_dma_addr, inter_digestsize, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], hw_mode); + set_din_type(&desc[idx], DMA_DLLI, initial_digest_dma_addr, + inter_digestsize, NS_BIT); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); idx++; - /* Load the hash current length*/ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hw_mode); - HW_DESC_SET_DIN_CONST(&desc[idx], 0, HASH_LEN_SIZE); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], hw_mode); + set_din_const(&desc[idx], 0, HASH_LEN_SIZE); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; /* Prepare opad/ipad key */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_XOR_VAL(&desc[idx], hmacPadConst[i]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hw_mode); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE1); + hw_desc_init(&desc[idx]); + set_xor_val(&desc[idx], hmacPadConst[i]); + set_cipher_mode(&desc[idx], hw_mode); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE1); idx++; /* Perform HASH update */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - k0_dma_addr, - block_size, NS_BIT); - HW_DESC_SET_CIPHER_MODE(&desc[idx],hw_mode); - HW_DESC_SET_XOR_ACTIVE(&desc[idx]); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_HASH); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, k0_dma_addr, block_size, + NS_BIT); + set_cipher_mode(&desc[idx], hw_mode); + set_xor_active(&desc[idx]); + set_flow_mode(&desc[idx], DIN_HASH); idx++; if (i == 0) { /* First iteration - calc H(K0^opad) into tmp_digest_dma_addr */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hw_mode); - HW_DESC_SET_DOUT_DLLI(&desc[idx], - tmp_digest_dma_addr, - inter_digestsize, - NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], hw_mode); + set_dout_dlli(&desc[idx], tmp_digest_dma_addr, + inter_digestsize, NS_BIT, 0); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); idx++; // is this needed?? or continue with current descriptors?? @@ -916,85 +904,86 @@ ssi_hmac_fips_run_test(struct ssi_drvdata *drvdata, } /* data descriptor */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - din_dma_addr, data_in_size, - NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_HASH); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, din_dma_addr, data_in_size, NS_BIT); + set_flow_mode(&desc[idx], DIN_HASH); idx++; /* HW last hash block padding (aka. "DO_PAD") */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hw_mode); - HW_DESC_SET_DOUT_DLLI(&desc[idx], k0_dma_addr, HASH_LEN_SIZE, NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE1); - HW_DESC_SET_CIPHER_DO(&desc[idx], DO_PAD); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], hw_mode); + set_dout_dlli(&desc[idx], k0_dma_addr, HASH_LEN_SIZE, NS_BIT, 0); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE1); + set_cipher_do(&desc[idx], DO_PAD); idx++; /* store the hash digest result in the context */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hw_mode); - HW_DESC_SET_DOUT_DLLI(&desc[idx], k0_dma_addr, digest_size, NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], hw_mode); + set_dout_dlli(&desc[idx], k0_dma_addr, digest_size, NS_BIT, 0); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); if (unlikely((hash_mode == DRV_HASH_MD5) || (hash_mode == DRV_HASH_SHA384) || (hash_mode == DRV_HASH_SHA512))) { - HW_DESC_SET_BYTES_SWAP(&desc[idx], 1); + set_bytes_swap(&desc[idx], 1); } else { - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], HASH_DIGEST_RESULT_LITTLE_ENDIAN); + set_cipher_config0(&desc[idx], + HASH_DIGEST_RESULT_LITTLE_ENDIAN); } - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); idx++; /* at this point: - tmp_digest = H(o_key_pad) - k0 = H(i_key_pad || m) - */ + * tmp_digest = H(o_key_pad) + * k0 = H(i_key_pad || m) + */ /* Loading hash opad xor key state */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hw_mode); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, tmp_digest_dma_addr, inter_digestsize, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], hw_mode); + set_din_type(&desc[idx], DMA_DLLI, tmp_digest_dma_addr, + inter_digestsize, NS_BIT); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); idx++; /* Load the hash current length */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hw_mode); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, digest_bytes_len_dma_addr, HASH_LEN_SIZE, NS_BIT); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_ENABLED); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], hw_mode); + set_din_type(&desc[idx], DMA_DLLI, digest_bytes_len_dma_addr, + HASH_LEN_SIZE, NS_BIT); + set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; /* Memory Barrier: wait for IPAD/OPAD axi write to complete */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_NO_DMA(&desc[idx], 0, 0xfffff0); - HW_DESC_SET_DOUT_NO_DMA(&desc[idx], 0, 0, 1); + hw_desc_init(&desc[idx]); + set_din_no_dma(&desc[idx], 0, 0xfffff0); + set_dout_no_dma(&desc[idx], 0, 0, 1); idx++; /* Perform HASH update */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, k0_dma_addr, digest_size, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_HASH); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, k0_dma_addr, digest_size, NS_BIT); + set_flow_mode(&desc[idx], DIN_HASH); idx++; - /* Get final MAC result */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], hw_mode); - HW_DESC_SET_DOUT_DLLI(&desc[idx], mac_res_dma_addr, digest_size, NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_DISABLED); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], hw_mode); + set_dout_dlli(&desc[idx], mac_res_dma_addr, digest_size, NS_BIT, 0); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); + set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); if (unlikely((hash_mode == DRV_HASH_MD5) || (hash_mode == DRV_HASH_SHA384) || (hash_mode == DRV_HASH_SHA512))) { - HW_DESC_SET_BYTES_SWAP(&desc[idx], 1); + set_bytes_swap(&desc[idx], 1); } else { - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], HASH_DIGEST_RESULT_LITTLE_ENDIAN); + set_cipher_config0(&desc[idx], + HASH_DIGEST_RESULT_LITTLE_ENDIAN); } idx++; @@ -1005,10 +994,10 @@ ssi_hmac_fips_run_test(struct ssi_drvdata *drvdata, return rc; } -ssi_fips_error_t +enum cc_fips_error ssi_hmac_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer) { - ssi_fips_error_t error = CC_REE_FIPS_ERROR_OK; + enum cc_fips_error error = CC_REE_FIPS_ERROR_OK; size_t i; struct fips_hmac_ctx *virt_ctx = (struct fips_hmac_ctx *)cpu_addr_buffer; @@ -1023,7 +1012,7 @@ ssi_hmac_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, for (i = 0; i < FIPS_HMAC_NUM_OF_TESTS; ++i) { - FipsHmacData *hmac_data = (FipsHmacData*)&FipsHmacDataTable[i]; + FipsHmacData *hmac_data = (FipsHmacData *)&FipsHmacDataTable[i]; int rc = 0; enum drv_hash_hw_mode hw_mode = 0; int digest_size = 0; @@ -1038,7 +1027,7 @@ ssi_hmac_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, digest_size = CC_SHA1_DIGEST_SIZE; block_size = CC_SHA1_BLOCK_SIZE; inter_digestsize = CC_SHA1_DIGEST_SIZE; - memcpy(virt_ctx->initial_digest, (void*)sha1_init, CC_SHA1_DIGEST_SIZE); + memcpy(virt_ctx->initial_digest, (void *)sha1_init, CC_SHA1_DIGEST_SIZE); memcpy(virt_ctx->digest_bytes_len, digest_len_init, HASH_LEN_SIZE); break; case DRV_HASH_SHA256: @@ -1046,7 +1035,7 @@ ssi_hmac_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, digest_size = CC_SHA256_DIGEST_SIZE; block_size = CC_SHA256_BLOCK_SIZE; inter_digestsize = CC_SHA256_DIGEST_SIZE; - memcpy(virt_ctx->initial_digest, (void*)sha256_init, CC_SHA256_DIGEST_SIZE); + memcpy(virt_ctx->initial_digest, (void *)sha256_init, CC_SHA256_DIGEST_SIZE); memcpy(virt_ctx->digest_bytes_len, digest_len_init, HASH_LEN_SIZE); break; #if (CC_SUPPORT_SHA > 256) @@ -1055,7 +1044,7 @@ ssi_hmac_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, digest_size = CC_SHA512_DIGEST_SIZE; block_size = CC_SHA512_BLOCK_SIZE; inter_digestsize = CC_SHA512_DIGEST_SIZE; - memcpy(virt_ctx->initial_digest, (void*)sha512_init, CC_SHA512_DIGEST_SIZE); + memcpy(virt_ctx->initial_digest, (void *)sha512_init, CC_SHA512_DIGEST_SIZE); memcpy(virt_ctx->digest_bytes_len, digest_len_sha512_init, HASH_LEN_SIZE); break; #endif @@ -1111,8 +1100,7 @@ ssi_hmac_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, return error; } - -static inline int +static inline int ssi_ccm_fips_run_test(struct ssi_drvdata *drvdata, enum drv_crypto_direction direction, dma_addr_t key_dma_addr, @@ -1131,7 +1119,7 @@ ssi_ccm_fips_run_test(struct ssi_drvdata *drvdata, int rc; struct ssi_crypto_req ssi_req = {0}; - HwDesc_s desc[FIPS_CCM_MAX_SEQ_LEN]; + struct cc_hw_desc desc[FIPS_CCM_MAX_SEQ_LEN]; unsigned int idx = 0; unsigned int cipher_flow_mode; @@ -1142,100 +1130,103 @@ ssi_ccm_fips_run_test(struct ssi_drvdata *drvdata, } /* load key */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_CTR); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, key_dma_addr, - ((key_size == NIST_AESCCM_192_BIT_KEY_SIZE) ? CC_AES_KEY_SIZE_MAX : key_size), - NS_BIT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], key_size); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_CTR); + set_din_type(&desc[idx], DMA_DLLI, key_dma_addr, + ((key_size == NIST_AESCCM_192_BIT_KEY_SIZE) ? + CC_AES_KEY_SIZE_MAX : key_size), NS_BIT) + set_key_size_aes(&desc[idx], key_size); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); + set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; /* load ctr state */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_CTR); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], key_size); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - iv_dma_addr, AES_BLOCK_SIZE, - NS_BIT); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE1); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_CTR); + set_key_size_aes(&desc[idx], key_size); + set_din_type(&desc[idx], DMA_DLLI, iv_dma_addr, AES_BLOCK_SIZE, + NS_BIT); + set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE1); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; /* load MAC key */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_CBC_MAC); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, key_dma_addr, - ((key_size == NIST_AESCCM_192_BIT_KEY_SIZE) ? CC_AES_KEY_SIZE_MAX : key_size), - NS_BIT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], key_size); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_AES_NOT_HASH_MODE(&desc[idx]); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_CBC_MAC); + set_din_type(&desc[idx], DMA_DLLI, key_dma_addr, + ((key_size == NIST_AESCCM_192_BIT_KEY_SIZE) ? + CC_AES_KEY_SIZE_MAX : key_size), NS_BIT); + set_key_size_aes(&desc[idx], key_size); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); + set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_aes_not_hash_mode(&desc[idx]); idx++; /* load MAC state */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_CBC_MAC); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], key_size); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, mac_res_dma_addr, NIST_AESCCM_TAG_SIZE, NS_BIT); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_AES_NOT_HASH_MODE(&desc[idx]); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_CBC_MAC); + set_key_size_aes(&desc[idx], key_size); + set_din_type(&desc[idx], DMA_DLLI, mac_res_dma_addr, + NIST_AESCCM_TAG_SIZE, NS_BIT); + set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_aes_not_hash_mode(&desc[idx]); idx++; /* prcess assoc data */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, b0_a0_adata_dma_addr, b0_a0_adata_size, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_HASH); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, b0_a0_adata_dma_addr, + b0_a0_adata_size, NS_BIT); + set_flow_mode(&desc[idx], DIN_HASH); idx++; /* process the cipher */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, din_dma_addr, din_size, NS_BIT); - HW_DESC_SET_DOUT_DLLI(&desc[idx], dout_dma_addr, din_size, NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&desc[idx], cipher_flow_mode); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, din_dma_addr, din_size, NS_BIT); + set_dout_dlli(&desc[idx], dout_dma_addr, din_size, NS_BIT, 0); + set_flow_mode(&desc[idx], cipher_flow_mode); idx++; /* Read temporal MAC */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_CBC_MAC); - HW_DESC_SET_DOUT_DLLI(&desc[idx], mac_res_dma_addr, NIST_AESCCM_TAG_SIZE, NS_BIT, 0); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], HASH_DIGEST_RESULT_LITTLE_ENDIAN); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_AES_NOT_HASH_MODE(&desc[idx]); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_CBC_MAC); + set_dout_dlli(&desc[idx], mac_res_dma_addr, NIST_AESCCM_TAG_SIZE, + NS_BIT, 0); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); + set_cipher_config0(&desc[idx], HASH_DIGEST_RESULT_LITTLE_ENDIAN); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_aes_not_hash_mode(&desc[idx]); idx++; /* load AES-CTR state (for last MAC calculation)*/ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_CTR); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - ctr_cnt_0_dma_addr, - AES_BLOCK_SIZE, NS_BIT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], key_size); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE1); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_CTR); + set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); + set_din_type(&desc[idx], DMA_DLLI, ctr_cnt_0_dma_addr, AES_BLOCK_SIZE, + NS_BIT); + set_key_size_aes(&desc[idx], key_size); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE1); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; /* Memory Barrier */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_NO_DMA(&desc[idx], 0, 0xfffff0); - HW_DESC_SET_DOUT_NO_DMA(&desc[idx], 0, 0, 1); + hw_desc_init(&desc[idx]); + set_din_no_dma(&desc[idx], 0, 0xfffff0); + set_dout_no_dma(&desc[idx], 0, 0, 1); idx++; /* encrypt the "T" value and store MAC inplace */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, mac_res_dma_addr, NIST_AESCCM_TAG_SIZE, NS_BIT); - HW_DESC_SET_DOUT_DLLI(&desc[idx], mac_res_dma_addr, NIST_AESCCM_TAG_SIZE, NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_AES_DOUT); - idx++; + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, mac_res_dma_addr, + NIST_AESCCM_TAG_SIZE, NS_BIT); + set_dout_dlli(&desc[idx], mac_res_dma_addr, NIST_AESCCM_TAG_SIZE, + NS_BIT, 0); + set_flow_mode(&desc[idx], DIN_AES_DOUT); + idx++; /* perform the operation - Lock HW and push sequence */ BUG_ON(idx > FIPS_CCM_MAX_SEQ_LEN); @@ -1244,10 +1235,10 @@ ssi_ccm_fips_run_test(struct ssi_drvdata *drvdata, return rc; } -ssi_fips_error_t +enum cc_fips_error ssi_ccm_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer) { - ssi_fips_error_t error = CC_REE_FIPS_ERROR_OK; + enum cc_fips_error error = CC_REE_FIPS_ERROR_OK; size_t i; struct fips_ccm_ctx *virt_ctx = (struct fips_ccm_ctx *)cpu_addr_buffer; @@ -1262,7 +1253,7 @@ ssi_ccm_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, for (i = 0; i < FIPS_CCM_NUM_OF_TESTS; ++i) { - FipsCcmData *ccmData = (FipsCcmData*)&FipsCcmDataTable[i]; + FipsCcmData *ccmData = (FipsCcmData *)&FipsCcmDataTable[i]; int rc = 0; memset(cpu_addr_buffer, 0, sizeof(struct fips_ccm_ctx)); @@ -1273,6 +1264,7 @@ ssi_ccm_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, { /* build B0 -- B0, nonce, l(m) */ __be16 data = cpu_to_be16(NIST_AESCCM_TEXT_SIZE); + virt_ctx->b0_a0_adata[0] = NIST_AESCCM_B0_VAL; memcpy(virt_ctx->b0_a0_adata + 1, ccmData->nonce, NIST_AESCCM_NONCE_SIZE); memcpy(virt_ctx->b0_a0_adata + 14, (u8 *)&data, sizeof(__be16)); @@ -1313,9 +1305,9 @@ ssi_ccm_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, if (memcmp(virt_ctx->dout, ccmData->dataOut, ccmData->dataInSize) != 0) { FIPS_LOG("dout comparison error %d - size=%d \n", i, ccmData->dataInSize); - error = CC_REE_FIPS_ERROR_AESCCM_PUT; + error = CC_REE_FIPS_ERROR_AESCCM_PUT; break; - } + } /* compare actual mac result to expected */ if (memcmp(virt_ctx->mac_res, ccmData->macResOut, ccmData->tagSize) != 0) @@ -1336,7 +1328,6 @@ ssi_ccm_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, return error; } - static inline int ssi_gcm_fips_run_test(struct ssi_drvdata *drvdata, enum drv_crypto_direction direction, @@ -1358,7 +1349,7 @@ ssi_gcm_fips_run_test(struct ssi_drvdata *drvdata, int rc; struct ssi_crypto_req ssi_req = {0}; - HwDesc_s desc[FIPS_GCM_MAX_SEQ_LEN]; + struct cc_hw_desc desc[FIPS_GCM_MAX_SEQ_LEN]; unsigned int idx = 0; unsigned int cipher_flow_mode; @@ -1372,186 +1363,162 @@ ssi_gcm_fips_run_test(struct ssi_drvdata *drvdata, // ssi_aead_gcm_setup_ghash_desc(req, desc, seq_size); ///////////////////////////////// 1 //////////////////////////////////// - /* load key to AES*/ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_ECB); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); - HW_DESC_SET_DIN_TYPE(&desc[idx], - DMA_DLLI, key_dma_addr, key_size, - NS_BIT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], key_size); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + /* load key to AES */ + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_ECB); + set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); + set_din_type(&desc[idx], DMA_DLLI, key_dma_addr, key_size, NS_BIT); + set_key_size_aes(&desc[idx], key_size); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; /* process one zero block to generate hkey */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_CONST(&desc[idx], 0x0, AES_BLOCK_SIZE); - HW_DESC_SET_DOUT_DLLI(&desc[idx], - hkey_dma_addr, AES_BLOCK_SIZE, - NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_AES_DOUT); + hw_desc_init(&desc[idx]); + set_din_const(&desc[idx], 0x0, AES_BLOCK_SIZE); + set_dout_dlli(&desc[idx], hkey_dma_addr, AES_BLOCK_SIZE, NS_BIT, 0); + set_flow_mode(&desc[idx], DIN_AES_DOUT); idx++; /* Memory Barrier */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_NO_DMA(&desc[idx], 0, 0xfffff0); - HW_DESC_SET_DOUT_NO_DMA(&desc[idx], 0, 0, 1); + hw_desc_init(&desc[idx]); + set_din_no_dma(&desc[idx], 0, 0xfffff0); + set_dout_no_dma(&desc[idx], 0, 0, 1); idx++; /* Load GHASH subkey */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - hkey_dma_addr, AES_BLOCK_SIZE, - NS_BIT); - HW_DESC_SET_DOUT_NO_DMA(&desc[idx], 0, 0, 1); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_AES_NOT_HASH_MODE(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_HASH_HW_GHASH); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_ENABLED); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, hkey_dma_addr, AES_BLOCK_SIZE, + NS_BIT); + set_dout_no_dma(&desc[idx], 0, 0, 1); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_aes_not_hash_mode(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_HASH_HW_GHASH); + set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; /* Configure Hash Engine to work with GHASH. - Since it was not possible to extend HASH submodes to add GHASH, - The following command is necessary in order to select GHASH (according to HW designers)*/ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_NO_DMA(&desc[idx], 0, 0xfffff0); - HW_DESC_SET_DOUT_NO_DMA(&desc[idx], 0, 0, 1); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_AES_NOT_HASH_MODE(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_HASH_HW_GHASH); - HW_DESC_SET_CIPHER_DO(&desc[idx], 1); //1=AES_SK RKEK - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_ENABLED); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + * Since it was not possible to extend HASH submodes to add GHASH, + * The following command is necessary in order to + * select GHASH (according to HW designers) + */ + hw_desc_init(&desc[idx]); + set_din_no_dma(&desc[idx], 0, 0xfffff0); + set_dout_no_dma(&desc[idx], 0, 0, 1); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_aes_not_hash_mode(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_HASH_HW_GHASH); + set_cipher_do(&desc[idx], 1); //1=AES_SK RKEK + set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); + set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; /* Load GHASH initial STATE (which is 0). (for any hash there is an initial state) */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_CONST(&desc[idx], 0x0, AES_BLOCK_SIZE); - HW_DESC_SET_DOUT_NO_DMA(&desc[idx], 0, 0, 1); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_AES_NOT_HASH_MODE(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_HASH_HW_GHASH); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_ENABLED); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); + hw_desc_init(&desc[idx]); + set_din_const(&desc[idx], 0x0, AES_BLOCK_SIZE); + set_dout_no_dma(&desc[idx], 0, 0, 1); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_aes_not_hash_mode(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_HASH_HW_GHASH); + set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); idx++; - - ///////////////////////////////// 2 //////////////////////////////////// /* prcess(ghash) assoc data */ // if (req->assoclen > 0) // ssi_aead_create_assoc_desc(req, DIN_HASH, desc, seq_size); ///////////////////////////////// 2 //////////////////////////////////// - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - adata_dma_addr, adata_size, - NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_HASH); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, adata_dma_addr, adata_size, NS_BIT); + set_flow_mode(&desc[idx], DIN_HASH); idx++; - ///////////////////////////////// 3 //////////////////////////////////// // ssi_aead_gcm_setup_gctr_desc(req, desc, seq_size); ///////////////////////////////// 3 //////////////////////////////////// /* load key to AES*/ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_GCTR); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - key_dma_addr, key_size, - NS_BIT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], key_size); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_GCTR); + set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); + set_din_type(&desc[idx], DMA_DLLI, key_dma_addr, key_size, NS_BIT); + set_key_size_aes(&desc[idx], key_size); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; /* load AES/CTR initial CTR value inc by 2*/ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_GCTR); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], key_size); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - iv_inc2_dma_addr, AES_BLOCK_SIZE, - NS_BIT); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE1); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_GCTR); + set_key_size_aes(&desc[idx], key_size); + set_din_type(&desc[idx], DMA_DLLI, iv_inc2_dma_addr, AES_BLOCK_SIZE, + NS_BIT); + set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE1); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; - ///////////////////////////////// 4 //////////////////////////////////// /* process(gctr+ghash) */ // if (req_ctx->cryptlen != 0) -// ssi_aead_process_cipher_data_desc(req, cipher_flow_mode, desc, seq_size); +// ssi_aead_process_cipher_data_desc(req, cipher_flow_mode, desc, seq_size); ///////////////////////////////// 4 //////////////////////////////////// - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - din_dma_addr, din_size, - NS_BIT); - HW_DESC_SET_DOUT_DLLI(&desc[idx], - dout_dma_addr, din_size, - NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&desc[idx], cipher_flow_mode); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, din_dma_addr, din_size, NS_BIT); + set_dout_dlli(&desc[idx], dout_dma_addr, din_size, NS_BIT, 0); + set_flow_mode(&desc[idx], cipher_flow_mode); idx++; - ///////////////////////////////// 5 //////////////////////////////////// // ssi_aead_process_gcm_result_desc(req, desc, seq_size); ///////////////////////////////// 5 //////////////////////////////////// /* prcess(ghash) gcm_block_len */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - block_len_dma_addr, AES_BLOCK_SIZE, - NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_HASH); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, block_len_dma_addr, AES_BLOCK_SIZE, + NS_BIT); + set_flow_mode(&desc[idx], DIN_HASH); idx++; /* Store GHASH state after GHASH(Associated Data + Cipher +LenBlock) */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_HASH_HW_GHASH); - HW_DESC_SET_DIN_NO_DMA(&desc[idx], 0, 0xfffff0); - HW_DESC_SET_DOUT_DLLI(&desc[idx], - mac_res_dma_addr, AES_BLOCK_SIZE, - NS_BIT, 0); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_AES_NOT_HASH_MODE(&desc[idx]); - idx++; + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_HASH_HW_GHASH); + set_din_no_dma(&desc[idx], 0, 0xfffff0); + set_dout_dlli(&desc[idx], mac_res_dma_addr, AES_BLOCK_SIZE, NS_BIT, 0); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_aes_not_hash_mode(&desc[idx]); + idx++; /* load AES/CTR initial CTR value inc by 1*/ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_GCTR); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], key_size); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - iv_inc1_dma_addr, AES_BLOCK_SIZE, - NS_BIT); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE1); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_GCTR); + set_key_size_aes(&desc[idx], key_size); + set_din_type(&desc[idx], DMA_DLLI, iv_inc1_dma_addr, AES_BLOCK_SIZE, + NS_BIT); + set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE1); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; /* Memory Barrier */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_NO_DMA(&desc[idx], 0, 0xfffff0); - HW_DESC_SET_DOUT_NO_DMA(&desc[idx], 0, 0, 1); + hw_desc_init(&desc[idx]); + set_din_no_dma(&desc[idx], 0, 0xfffff0); + set_dout_no_dma(&desc[idx], 0, 0, 1); idx++; /* process GCTR on stored GHASH and store MAC inplace */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_GCTR); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - mac_res_dma_addr, AES_BLOCK_SIZE, - NS_BIT); - HW_DESC_SET_DOUT_DLLI(&desc[idx], - mac_res_dma_addr, AES_BLOCK_SIZE, - NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_AES_DOUT); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_GCTR); + set_din_type(&desc[idx], DMA_DLLI, mac_res_dma_addr, AES_BLOCK_SIZE, + NS_BIT); + set_dout_dlli(&desc[idx], mac_res_dma_addr, AES_BLOCK_SIZE, NS_BIT, 0); + set_flow_mode(&desc[idx], DIN_AES_DOUT); idx++; /* perform the operation - Lock HW and push sequence */ @@ -1561,10 +1528,10 @@ ssi_gcm_fips_run_test(struct ssi_drvdata *drvdata, return rc; } -ssi_fips_error_t +enum cc_fips_error ssi_gcm_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer) { - ssi_fips_error_t error = CC_REE_FIPS_ERROR_OK; + enum cc_fips_error error = CC_REE_FIPS_ERROR_OK; size_t i; struct fips_gcm_ctx *virt_ctx = (struct fips_gcm_ctx *)cpu_addr_buffer; @@ -1581,7 +1548,7 @@ ssi_gcm_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, for (i = 0; i < FIPS_GCM_NUM_OF_TESTS; ++i) { - FipsGcmData *gcmData = (FipsGcmData*)&FipsGcmDataTable[i]; + FipsGcmData *gcmData = (FipsGcmData *)&FipsGcmDataTable[i]; int rc = 0; memset(cpu_addr_buffer, 0, sizeof(struct fips_gcm_ctx)); @@ -1594,6 +1561,7 @@ ssi_gcm_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, /* len_block */ { __be64 len_bits; + len_bits = cpu_to_be64(gcmData->adataSize * 8); memcpy(virt_ctx->len_block, &len_bits, sizeof(len_bits)); len_bits = cpu_to_be64(gcmData->dataInSize * 8); @@ -1602,6 +1570,7 @@ ssi_gcm_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, /* iv_inc1, iv_inc2 */ { __be32 counter = cpu_to_be32(1); + memcpy(virt_ctx->iv_inc1, gcmData->iv, NIST_AESGCM_IV_SIZE); memcpy(virt_ctx->iv_inc1 + NIST_AESGCM_IV_SIZE, &counter, sizeof(counter)); counter = cpu_to_be32(2); @@ -1666,7 +1635,6 @@ ssi_gcm_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, return error; } - size_t ssi_fips_max_mem_alloc_size(void) { FIPS_DBG("sizeof(struct fips_cipher_ctx) %d \n", sizeof(struct fips_cipher_ctx)); diff --git a/drivers/staging/ccree/ssi_fips_local.c b/drivers/staging/ccree/ssi_fips_local.c index 51b535a2a09a..aefb71dc9e9a 100644 --- a/drivers/staging/ccree/ssi_fips_local.c +++ b/drivers/staging/ccree/ssi_fips_local.c @@ -1,22 +1,22 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ /************************************************************** -This file defines the driver FIPS internal function, used by the driver itself. -***************************************************************/ + * This file defines the driver FIPS internal function, used by the driver itself. + ***************************************************************/ #include <linux/kernel.h> #include <linux/module.h> #include <linux/platform_device.h> @@ -26,7 +26,6 @@ This file defines the driver FIPS internal function, used by the driver itself. #include "ssi_driver.h" #include "cc_hal.h" - #define FIPS_POWER_UP_TEST_CIPHER 1 #define FIPS_POWER_UP_TEST_CMAC 1 #define FIPS_POWER_UP_TEST_HASH 1 @@ -49,62 +48,57 @@ struct ssi_fips_handle { #endif }; - -extern int ssi_fips_get_state(ssi_fips_state_t *p_state); -extern int ssi_fips_get_error(ssi_fips_error_t *p_err); -extern int ssi_fips_ext_set_state(ssi_fips_state_t state); -extern int ssi_fips_ext_set_error(ssi_fips_error_t err); +extern int ssi_fips_get_state(enum cc_fips_state_t *p_state); +extern int ssi_fips_get_error(enum cc_fips_error *p_err); +extern int ssi_fips_ext_set_state(enum cc_fips_state_t state); +extern int ssi_fips_ext_set_error(enum cc_fips_error err); /* FIPS power-up tests */ -extern ssi_fips_error_t ssi_cipher_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer); -extern ssi_fips_error_t ssi_cmac_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer); -extern ssi_fips_error_t ssi_hash_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer); -extern ssi_fips_error_t ssi_hmac_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer); -extern ssi_fips_error_t ssi_ccm_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer); -extern ssi_fips_error_t ssi_gcm_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer); +extern enum cc_fips_error ssi_cipher_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer); +extern enum cc_fips_error ssi_cmac_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer); +extern enum cc_fips_error ssi_hash_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer); +extern enum cc_fips_error ssi_hmac_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer); +extern enum cc_fips_error ssi_ccm_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer); +extern enum cc_fips_error ssi_gcm_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer); extern size_t ssi_fips_max_mem_alloc_size(void); - /* The function called once at driver entry point to check whether TEE FIPS error occured.*/ static enum ssi_fips_error ssi_fips_get_tee_error(struct ssi_drvdata *drvdata) { - uint32_t regVal; + u32 regVal; void __iomem *cc_base = drvdata->cc_base; regVal = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, GPR_HOST)); - if (regVal == (CC_FIPS_SYNC_TEE_STATUS | CC_FIPS_SYNC_MODULE_OK)) { + if (regVal == (CC_FIPS_SYNC_TEE_STATUS | CC_FIPS_SYNC_MODULE_OK)) return CC_REE_FIPS_ERROR_OK; - } + return CC_REE_FIPS_ERROR_FROM_TEE; } - -/* - This function should push the FIPS REE library status towards the TEE library. - By writing the error state to HOST_GPR0 register. The function is called from . - driver entry point so no need to protect by mutex. -*/ -static void ssi_fips_update_tee_upon_ree_status(struct ssi_drvdata *drvdata, ssi_fips_error_t err) +/* + * This function should push the FIPS REE library status towards the TEE library. + * By writing the error state to HOST_GPR0 register. The function is called from + * driver entry point so no need to protect by mutex. + */ +static void ssi_fips_update_tee_upon_ree_status(struct ssi_drvdata *drvdata, enum cc_fips_error err) { void __iomem *cc_base = drvdata->cc_base; - if (err == CC_REE_FIPS_ERROR_OK) { - CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_GPR0), (CC_FIPS_SYNC_REE_STATUS|CC_FIPS_SYNC_MODULE_OK)); - } else { - CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_GPR0), (CC_FIPS_SYNC_REE_STATUS|CC_FIPS_SYNC_MODULE_ERROR)); - } -} - + if (err == CC_REE_FIPS_ERROR_OK) + CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_GPR0), (CC_FIPS_SYNC_REE_STATUS | CC_FIPS_SYNC_MODULE_OK)); + else + CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_GPR0), (CC_FIPS_SYNC_REE_STATUS | CC_FIPS_SYNC_MODULE_ERROR)); +} void ssi_fips_fini(struct ssi_drvdata *drvdata) { struct ssi_fips_handle *fips_h = drvdata->fips_handle; - if (fips_h == NULL) + if (!fips_h) return; /* Not allocated */ #ifdef COMP_IN_WQ - if (fips_h->workq != NULL) { + if (fips_h->workq) { flush_workqueue(fips_h->workq); destroy_workqueue(fips_h->workq); } @@ -119,7 +113,7 @@ void ssi_fips_fini(struct ssi_drvdata *drvdata) void fips_handler(struct ssi_drvdata *drvdata) { - struct ssi_fips_handle *fips_handle_ptr = + struct ssi_fips_handle *fips_handle_ptr = drvdata->fips_handle; #ifdef COMP_IN_WQ queue_delayed_work(fips_handle_ptr->workq, &fips_handle_ptr->fipswork, 0); @@ -128,8 +122,6 @@ void fips_handler(struct ssi_drvdata *drvdata) #endif } - - #ifdef COMP_IN_WQ static void fips_wq_handler(struct work_struct *work) { @@ -145,29 +137,27 @@ static void fips_dsr(unsigned long devarg) { struct ssi_drvdata *drvdata = (struct ssi_drvdata *)devarg; void __iomem *cc_base = drvdata->cc_base; - uint32_t irq; - uint32_t teeFipsError = 0; + u32 irq; + u32 teeFipsError = 0; irq = (drvdata->irq & (SSI_GPR0_IRQ_MASK)); if (irq & SSI_GPR0_IRQ_MASK) { teeFipsError = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, GPR_HOST)); - if (teeFipsError != (CC_FIPS_SYNC_TEE_STATUS | CC_FIPS_SYNC_MODULE_OK)) { + if (teeFipsError != (CC_FIPS_SYNC_TEE_STATUS | CC_FIPS_SYNC_MODULE_OK)) ssi_fips_set_error(drvdata, CC_REE_FIPS_ERROR_FROM_TEE); - } } /* after verifing that there is nothing to do, Unmask AXI completion interrupt */ - CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR), + CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR), CC_HAL_READ_REGISTER( CC_REG_OFFSET(HOST_RGF, HOST_IMR)) & ~irq); } - -ssi_fips_error_t cc_fips_run_power_up_tests(struct ssi_drvdata *drvdata) +enum cc_fips_error cc_fips_run_power_up_tests(struct ssi_drvdata *drvdata) { - ssi_fips_error_t fips_error = CC_REE_FIPS_ERROR_OK; - void * cpu_addr_buffer = NULL; + enum cc_fips_error fips_error = CC_REE_FIPS_ERROR_OK; + void *cpu_addr_buffer = NULL; dma_addr_t dma_handle; size_t alloc_buff_size = ssi_fips_max_mem_alloc_size(); struct device *dev = &drvdata->plat_dev->dev; @@ -177,9 +167,9 @@ ssi_fips_error_t cc_fips_run_power_up_tests(struct ssi_drvdata *drvdata) // the dma_handle is the returned phy address - use it in the HW descriptor FIPS_DBG("dma_alloc_coherent \n"); cpu_addr_buffer = dma_alloc_coherent(dev, alloc_buff_size, &dma_handle, GFP_KERNEL); - if (cpu_addr_buffer == NULL) { + if (!cpu_addr_buffer) return CC_REE_FIPS_ERROR_GENERAL; - } + FIPS_DBG("allocated coherent buffer - addr 0x%08X , size = %d \n", (size_t)cpu_addr_buffer, alloc_buff_size); #if FIPS_POWER_UP_TEST_CIPHER @@ -229,13 +219,12 @@ ssi_fips_error_t cc_fips_run_power_up_tests(struct ssi_drvdata *drvdata) return fips_error; } - - -/* The function checks if FIPS supported and FIPS error exists.* -* It should be used in every driver API.*/ +/* The function checks if FIPS supported and FIPS error exists.* + * It should be used in every driver API. + */ int ssi_fips_check_fips_error(void) { - ssi_fips_state_t fips_state; + enum cc_fips_state_t fips_state; if (ssi_fips_get_state(&fips_state) != 0) { FIPS_LOG("ssi_fips_get_state FAILED, returning.. \n"); @@ -248,62 +237,61 @@ int ssi_fips_check_fips_error(void) return 0; } - -/* The function sets the REE FIPS state.* -* It should be used while driver is being loaded .*/ -int ssi_fips_set_state(ssi_fips_state_t state) +/* The function sets the REE FIPS state.* + * It should be used while driver is being loaded. + */ +int ssi_fips_set_state(enum cc_fips_state_t state) { return ssi_fips_ext_set_state(state); } -/* The function sets the REE FIPS error, and pushes the error to TEE library. * -* It should be used when any of the KAT tests fails .*/ -int ssi_fips_set_error(struct ssi_drvdata *p_drvdata, ssi_fips_error_t err) +/* The function sets the REE FIPS error, and pushes the error to TEE library. * + * It should be used when any of the KAT tests fails. + */ +int ssi_fips_set_error(struct ssi_drvdata *p_drvdata, enum cc_fips_error err) { int rc = 0; - ssi_fips_error_t current_err; + enum cc_fips_error current_err; - FIPS_LOG("ssi_fips_set_error - fips_error = %d \n", err); + FIPS_LOG("ssi_fips_set_error - fips_error = %d \n", err); // setting no error is not allowed - if (err == CC_REE_FIPS_ERROR_OK) { - return -ENOEXEC; - } - // If error exists, do not set new error - if (ssi_fips_get_error(¤t_err) != 0) { - return -ENOEXEC; - } - if (current_err != CC_REE_FIPS_ERROR_OK) { - return -ENOEXEC; - } - // set REE internal error and state + if (err == CC_REE_FIPS_ERROR_OK) + return -ENOEXEC; + + // If error exists, do not set new error + if (ssi_fips_get_error(¤t_err) != 0) + return -ENOEXEC; + + if (current_err != CC_REE_FIPS_ERROR_OK) + return -ENOEXEC; + + // set REE internal error and state rc = ssi_fips_ext_set_error(err); - if (rc != 0) { - return -ENOEXEC; - } + if (rc != 0) + return -ENOEXEC; + rc = ssi_fips_ext_set_state(CC_FIPS_STATE_ERROR); - if (rc != 0) { - return -ENOEXEC; - } + if (rc != 0) + return -ENOEXEC; - // push error towards TEE libraray, if it's not TEE error - if (err != CC_REE_FIPS_ERROR_FROM_TEE) { + // push error towards TEE libraray, if it's not TEE error + if (err != CC_REE_FIPS_ERROR_FROM_TEE) ssi_fips_update_tee_upon_ree_status(p_drvdata, err); - } + return rc; } - /* The function called once at driver entry point .*/ int ssi_fips_init(struct ssi_drvdata *p_drvdata) { - ssi_fips_error_t rc = CC_REE_FIPS_ERROR_OK; + enum cc_fips_error rc = CC_REE_FIPS_ERROR_OK; struct ssi_fips_handle *fips_h; FIPS_DBG("CC FIPS code .. (fips=%d) \n", ssi_fips_support); - fips_h = kzalloc(sizeof(struct ssi_fips_handle),GFP_KERNEL); - if (fips_h == NULL) { + fips_h = kzalloc(sizeof(struct ssi_fips_handle), GFP_KERNEL); + if (!fips_h) { ssi_fips_set_error(p_drvdata, CC_REE_FIPS_ERROR_GENERAL); return -ENOMEM; } @@ -313,7 +301,7 @@ int ssi_fips_init(struct ssi_drvdata *p_drvdata) #ifdef COMP_IN_WQ SSI_LOG_DEBUG("Initializing fips workqueue\n"); fips_h->workq = create_singlethread_workqueue("arm_cc7x_fips_wq"); - if (unlikely(fips_h->workq == NULL)) { + if (unlikely(!fips_h->workq)) { SSI_LOG_ERR("Failed creating fips work queue\n"); ssi_fips_set_error(p_drvdata, CC_REE_FIPS_ERROR_GENERAL); rc = -ENOMEM; @@ -326,7 +314,7 @@ int ssi_fips_init(struct ssi_drvdata *p_drvdata) #endif /* init fips driver data */ - rc = ssi_fips_set_state((ssi_fips_support == 0)? CC_FIPS_STATE_NOT_SUPPORTED : CC_FIPS_STATE_SUPPORTED); + rc = ssi_fips_set_state((ssi_fips_support == 0) ? CC_FIPS_STATE_NOT_SUPPORTED : CC_FIPS_STATE_SUPPORTED); if (unlikely(rc != 0)) { ssi_fips_set_error(p_drvdata, CC_REE_FIPS_ERROR_GENERAL); rc = -EAGAIN; diff --git a/drivers/staging/ccree/ssi_fips_local.h b/drivers/staging/ccree/ssi_fips_local.h index 65997c15a20e..8c7994fe9fae 100644 --- a/drivers/staging/ccree/ssi_fips_local.h +++ b/drivers/staging/ccree/ssi_fips_local.h @@ -1,15 +1,15 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ @@ -17,32 +17,23 @@ #ifndef __SSI_FIPS_LOCAL_H__ #define __SSI_FIPS_LOCAL_H__ - #ifdef CONFIG_CCX7REE_FIPS_SUPPORT #include "ssi_fips.h" struct ssi_drvdata; -// IG - how to make 1 file for TEE and REE -typedef enum CC_FipsSyncStatus{ - CC_FIPS_SYNC_MODULE_OK = 0x0, - CC_FIPS_SYNC_MODULE_ERROR = 0x1, - CC_FIPS_SYNC_REE_STATUS = 0x4, - CC_FIPS_SYNC_TEE_STATUS = 0x8, - CC_FIPS_SYNC_STATUS_RESERVE32B = INT32_MAX -}CCFipsSyncStatus_t; - - #define CHECK_AND_RETURN_UPON_FIPS_ERROR() {\ - if (ssi_fips_check_fips_error() != 0) {\ - return -ENOEXEC;\ - }\ + if (ssi_fips_check_fips_error() != 0) {\ + return -ENOEXEC;\ + } \ } + #define CHECK_AND_RETURN_VOID_UPON_FIPS_ERROR() {\ - if (ssi_fips_check_fips_error() != 0) {\ - return;\ - }\ + if (ssi_fips_check_fips_error() != 0) {\ + return;\ + } \ } + #define SSI_FIPS_INIT(p_drvData) (ssi_fips_init(p_drvData)) #define SSI_FIPS_FINI(p_drvData) (ssi_fips_fini(p_drvData)) @@ -53,7 +44,7 @@ typedef enum CC_FipsSyncStatus{ int ssi_fips_init(struct ssi_drvdata *p_drvdata); void ssi_fips_fini(struct ssi_drvdata *drvdata); int ssi_fips_check_fips_error(void); -int ssi_fips_set_error(struct ssi_drvdata *p_drvdata, ssi_fips_error_t err); +int ssi_fips_set_error(struct ssi_drvdata *p_drvdata, enum cc_fips_error err); void fips_handler(struct ssi_drvdata *drvdata); #else /* CONFIG_CC7XXREE_FIPS_SUPPORT */ @@ -72,6 +63,5 @@ void fips_handler(struct ssi_drvdata *drvdata); #endif /* CONFIG_CC7XXREE_FIPS_SUPPORT */ - #endif /*__SSI_FIPS_LOCAL_H__*/ diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c index f99d4219b01e..ae8f36af3837 100644 --- a/drivers/staging/ccree/ssi_hash.c +++ b/drivers/staging/ccree/ssi_hash.c @@ -1,15 +1,15 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ @@ -42,64 +42,61 @@ struct ssi_hash_handle { struct completion init_comp; }; -static const uint32_t digest_len_init[] = { +static const u32 digest_len_init[] = { 0x00000040, 0x00000000, 0x00000000, 0x00000000 }; -static const uint32_t md5_init[] = { +static const u32 md5_init[] = { SHA1_H3, SHA1_H2, SHA1_H1, SHA1_H0 }; -static const uint32_t sha1_init[] = { +static const u32 sha1_init[] = { SHA1_H4, SHA1_H3, SHA1_H2, SHA1_H1, SHA1_H0 }; -static const uint32_t sha224_init[] = { +static const u32 sha224_init[] = { SHA224_H7, SHA224_H6, SHA224_H5, SHA224_H4, SHA224_H3, SHA224_H2, SHA224_H1, SHA224_H0 }; -static const uint32_t sha256_init[] = { +static const u32 sha256_init[] = { SHA256_H7, SHA256_H6, SHA256_H5, SHA256_H4, SHA256_H3, SHA256_H2, SHA256_H1, SHA256_H0 }; #if (DX_DEV_SHA_MAX > 256) -static const uint32_t digest_len_sha512_init[] = { +static const u32 digest_len_sha512_init[] = { 0x00000080, 0x00000000, 0x00000000, 0x00000000 }; -static const uint64_t sha384_init[] = { +static const u64 sha384_init[] = { SHA384_H7, SHA384_H6, SHA384_H5, SHA384_H4, SHA384_H3, SHA384_H2, SHA384_H1, SHA384_H0 }; -static const uint64_t sha512_init[] = { +static const u64 sha512_init[] = { SHA512_H7, SHA512_H6, SHA512_H5, SHA512_H4, SHA512_H3, SHA512_H2, SHA512_H1, SHA512_H0 }; #endif static void ssi_hash_create_xcbc_setup( - struct ahash_request *areq, - HwDesc_s desc[], + struct ahash_request *areq, + struct cc_hw_desc desc[], unsigned int *seq_size); -static void ssi_hash_create_cmac_setup(struct ahash_request *areq, - HwDesc_s desc[], +static void ssi_hash_create_cmac_setup(struct ahash_request *areq, + struct cc_hw_desc desc[], unsigned int *seq_size); struct ssi_hash_alg { struct list_head entry; - bool synchronize; int hash_mode; int hw_mode; int inter_digestsize; struct ssi_drvdata *drvdata; - union { - struct ahash_alg ahash_alg; - struct shash_alg shash_alg; - }; + struct ahash_alg ahash_alg; }; - struct hash_key_req_ctx { - uint32_t keylen; + u32 keylen; dma_addr_t key_dma_addr; }; /* hash per-session context */ struct ssi_hash_ctx { struct ssi_drvdata *drvdata; - /* holds the origin digest; the digest after "setkey" if HMAC,* - the initial digest if HASH. */ - uint8_t digest_buff[SSI_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned; - uint8_t opad_tmp_keys_buff[SSI_MAX_HASH_OPAD_TMP_KEYS_SIZE] ____cacheline_aligned; + /* holds the origin digest; the digest after "setkey" if HMAC,* + * the initial digest if HASH. + */ + u8 digest_buff[SSI_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned; + u8 opad_tmp_keys_buff[SSI_MAX_HASH_OPAD_TMP_KEYS_SIZE] ____cacheline_aligned; + dma_addr_t opad_tmp_keys_dma_addr ____cacheline_aligned; dma_addr_t digest_buff_dma_addr; /* use for hmac with key large then mode block size */ @@ -111,31 +108,29 @@ struct ssi_hash_ctx { bool is_hmac; }; -static const struct crypto_type crypto_shash_type; - static void ssi_hash_create_data_desc( struct ahash_req_ctx *areq_ctx, - struct ssi_hash_ctx *ctx, - unsigned int flow_mode,HwDesc_s desc[], + struct ssi_hash_ctx *ctx, + unsigned int flow_mode, struct cc_hw_desc desc[], bool is_not_last_data, unsigned int *seq_size); -static inline void ssi_set_hash_endianity(uint32_t mode, HwDesc_s *desc) +static inline void ssi_set_hash_endianity(u32 mode, struct cc_hw_desc *desc) { if (unlikely((mode == DRV_HASH_MD5) || (mode == DRV_HASH_SHA384) || (mode == DRV_HASH_SHA512))) { - HW_DESC_SET_BYTES_SWAP(desc, 1); + set_bytes_swap(desc, 1); } else { - HW_DESC_SET_CIPHER_CONFIG0(desc, HASH_DIGEST_RESULT_LITTLE_ENDIAN); + set_cipher_config0(desc, HASH_DIGEST_RESULT_LITTLE_ENDIAN); } } -static int ssi_hash_map_result(struct device *dev, - struct ahash_req_ctx *state, +static int ssi_hash_map_result(struct device *dev, + struct ahash_req_ctx *state, unsigned int digestsize) { - state->digest_result_dma_addr = + state->digest_result_dma_addr = dma_map_single(dev, (void *)state->digest_result_buff, digestsize, DMA_BIDIRECTIONAL); @@ -144,8 +139,6 @@ static int ssi_hash_map_result(struct device *dev, digestsize); return -ENOMEM; } - SSI_UPDATE_DMA_ADDR_TO_48BIT(state->digest_result_dma_addr, - digestsize); SSI_LOG_DEBUG("Mapped digest result buffer %u B " "at va=%pK to dma=0x%llX\n", digestsize, state->digest_result_buff, @@ -154,33 +147,33 @@ static int ssi_hash_map_result(struct device *dev, return 0; } -static int ssi_hash_map_request(struct device *dev, - struct ahash_req_ctx *state, +static int ssi_hash_map_request(struct device *dev, + struct ahash_req_ctx *state, struct ssi_hash_ctx *ctx) { bool is_hmac = ctx->is_hmac; ssi_sram_addr_t larval_digest_addr = ssi_ahash_get_larval_digest_sram_addr( ctx->drvdata, ctx->hash_mode); struct ssi_crypto_req ssi_req = {}; - HwDesc_s desc; + struct cc_hw_desc desc; int rc = -ENOMEM; - state->buff0 = kzalloc(SSI_MAX_HASH_BLCK_SIZE ,GFP_KERNEL|GFP_DMA); + state->buff0 = kzalloc(SSI_MAX_HASH_BLCK_SIZE, GFP_KERNEL | GFP_DMA); if (!state->buff0) { SSI_LOG_ERR("Allocating buff0 in context failed\n"); goto fail0; } - state->buff1 = kzalloc(SSI_MAX_HASH_BLCK_SIZE ,GFP_KERNEL|GFP_DMA); + state->buff1 = kzalloc(SSI_MAX_HASH_BLCK_SIZE, GFP_KERNEL | GFP_DMA); if (!state->buff1) { SSI_LOG_ERR("Allocating buff1 in context failed\n"); goto fail_buff0; } - state->digest_result_buff = kzalloc(SSI_MAX_HASH_DIGEST_SIZE ,GFP_KERNEL|GFP_DMA); + state->digest_result_buff = kzalloc(SSI_MAX_HASH_DIGEST_SIZE, GFP_KERNEL | GFP_DMA); if (!state->digest_result_buff) { SSI_LOG_ERR("Allocating digest_result_buff in context failed\n"); goto fail_buff1; } - state->digest_buff = kzalloc(ctx->inter_digestsize, GFP_KERNEL|GFP_DMA); + state->digest_buff = kzalloc(ctx->inter_digestsize, GFP_KERNEL | GFP_DMA); if (!state->digest_buff) { SSI_LOG_ERR("Allocating digest-buffer in context failed\n"); goto fail_digest_result_buff; @@ -188,7 +181,7 @@ static int ssi_hash_map_request(struct device *dev, SSI_LOG_DEBUG("Allocated digest-buffer in context ctx->digest_buff=@%p\n", state->digest_buff); if (ctx->hw_mode != DRV_CIPHER_XCBC_MAC) { - state->digest_bytes_len = kzalloc(HASH_LEN_SIZE, GFP_KERNEL|GFP_DMA); + state->digest_bytes_len = kzalloc(HASH_LEN_SIZE, GFP_KERNEL | GFP_DMA); if (!state->digest_bytes_len) { SSI_LOG_ERR("Allocating digest-bytes-len in context failed\n"); goto fail1; @@ -198,7 +191,7 @@ static int ssi_hash_map_request(struct device *dev, state->digest_bytes_len = NULL; } - state->opad_digest_buff = kzalloc(ctx->inter_digestsize, GFP_KERNEL|GFP_DMA); + state->opad_digest_buff = kzalloc(ctx->inter_digestsize, GFP_KERNEL | GFP_DMA); if (!state->opad_digest_buff) { SSI_LOG_ERR("Allocating opad-digest-buffer in context failed\n"); goto fail2; @@ -211,50 +204,40 @@ static int ssi_hash_map_request(struct device *dev, ctx->inter_digestsize, state->digest_buff); goto fail3; } - SSI_UPDATE_DMA_ADDR_TO_48BIT(state->digest_buff_dma_addr, - ctx->inter_digestsize); SSI_LOG_DEBUG("Mapped digest %d B at va=%pK to dma=0x%llX\n", ctx->inter_digestsize, state->digest_buff, (unsigned long long)state->digest_buff_dma_addr); if (is_hmac) { - SSI_RESTORE_DMA_ADDR_TO_48BIT(ctx->digest_buff_dma_addr); dma_sync_single_for_cpu(dev, ctx->digest_buff_dma_addr, ctx->inter_digestsize, DMA_BIDIRECTIONAL); - SSI_UPDATE_DMA_ADDR_TO_48BIT(ctx->digest_buff_dma_addr, - ctx->inter_digestsize); if ((ctx->hw_mode == DRV_CIPHER_XCBC_MAC) || (ctx->hw_mode == DRV_CIPHER_CMAC)) { memset(state->digest_buff, 0, ctx->inter_digestsize); } else { /*sha*/ memcpy(state->digest_buff, ctx->digest_buff, ctx->inter_digestsize); #if (DX_DEV_SHA_MAX > 256) - if (unlikely((ctx->hash_mode == DRV_HASH_SHA512) || (ctx->hash_mode == DRV_HASH_SHA384))) { + if (unlikely((ctx->hash_mode == DRV_HASH_SHA512) || (ctx->hash_mode == DRV_HASH_SHA384))) memcpy(state->digest_bytes_len, digest_len_sha512_init, HASH_LEN_SIZE); - } else { + else memcpy(state->digest_bytes_len, digest_len_init, HASH_LEN_SIZE); - } #else memcpy(state->digest_bytes_len, digest_len_init, HASH_LEN_SIZE); #endif } - SSI_RESTORE_DMA_ADDR_TO_48BIT(state->digest_buff_dma_addr); dma_sync_single_for_device(dev, state->digest_buff_dma_addr, ctx->inter_digestsize, DMA_BIDIRECTIONAL); - SSI_UPDATE_DMA_ADDR_TO_48BIT(state->digest_buff_dma_addr, - ctx->inter_digestsize); if (ctx->hash_mode != DRV_HASH_NULL) { - SSI_RESTORE_DMA_ADDR_TO_48BIT(ctx->opad_tmp_keys_dma_addr); dma_sync_single_for_cpu(dev, ctx->opad_tmp_keys_dma_addr, ctx->inter_digestsize, DMA_BIDIRECTIONAL); memcpy(state->opad_digest_buff, ctx->opad_tmp_keys_buff, ctx->inter_digestsize); - SSI_UPDATE_DMA_ADDR_TO_48BIT(ctx->opad_tmp_keys_dma_addr, - ctx->inter_digestsize); - } + } } else { /*hash*/ /* Copy the initial digests if hash flow. The SRAM contains the - initial digests in the expected order for all SHA* */ - HW_DESC_INIT(&desc); - HW_DESC_SET_DIN_SRAM(&desc, larval_digest_addr, ctx->inter_digestsize); - HW_DESC_SET_DOUT_DLLI(&desc, state->digest_buff_dma_addr, ctx->inter_digestsize, NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&desc, BYPASS); + * initial digests in the expected order for all SHA* + */ + hw_desc_init(&desc); + set_din_sram(&desc, larval_digest_addr, ctx->inter_digestsize); + set_dout_dlli(&desc, state->digest_buff_dma_addr, + ctx->inter_digestsize, NS_BIT, 0); + set_flow_mode(&desc, BYPASS); rc = send_request(ctx->drvdata, &ssi_req, &desc, 1, 0); if (unlikely(rc != 0)) { @@ -270,8 +253,6 @@ static int ssi_hash_map_request(struct device *dev, HASH_LEN_SIZE, state->digest_bytes_len); goto fail4; } - SSI_UPDATE_DMA_ADDR_TO_48BIT(state->digest_bytes_len_dma_addr, - HASH_LEN_SIZE); SSI_LOG_DEBUG("Mapped digest len %u B at va=%pK to dma=0x%llX\n", HASH_LEN_SIZE, state->digest_bytes_len, (unsigned long long)state->digest_bytes_len_dma_addr); @@ -286,8 +267,6 @@ static int ssi_hash_map_request(struct device *dev, ctx->inter_digestsize, state->opad_digest_buff); goto fail5; } - SSI_UPDATE_DMA_ADDR_TO_48BIT(state->opad_digest_dma_addr, - ctx->inter_digestsize); SSI_LOG_DEBUG("Mapped opad digest %d B at va=%pK to dma=0x%llX\n", ctx->inter_digestsize, state->opad_digest_buff, (unsigned long long)state->opad_digest_dma_addr); @@ -303,13 +282,11 @@ static int ssi_hash_map_request(struct device *dev, fail5: if (state->digest_bytes_len_dma_addr != 0) { - SSI_RESTORE_DMA_ADDR_TO_48BIT(state->digest_bytes_len_dma_addr); dma_unmap_single(dev, state->digest_bytes_len_dma_addr, HASH_LEN_SIZE, DMA_BIDIRECTIONAL); state->digest_bytes_len_dma_addr = 0; } fail4: if (state->digest_buff_dma_addr != 0) { - SSI_RESTORE_DMA_ADDR_TO_48BIT(state->digest_buff_dma_addr); dma_unmap_single(dev, state->digest_buff_dma_addr, ctx->inter_digestsize, DMA_BIDIRECTIONAL); state->digest_buff_dma_addr = 0; } @@ -320,17 +297,17 @@ fail2: fail1: kfree(state->digest_buff); fail_digest_result_buff: - if (state->digest_result_buff != NULL) { + if (state->digest_result_buff) { kfree(state->digest_result_buff); state->digest_result_buff = NULL; } fail_buff1: - if (state->buff1 != NULL) { + if (state->buff1) { kfree(state->buff1); state->buff1 = NULL; } fail_buff0: - if (state->buff0 != NULL) { + if (state->buff0) { kfree(state->buff0); state->buff0 = NULL; } @@ -338,12 +315,11 @@ fail0: return rc; } -static void ssi_hash_unmap_request(struct device *dev, - struct ahash_req_ctx *state, +static void ssi_hash_unmap_request(struct device *dev, + struct ahash_req_ctx *state, struct ssi_hash_ctx *ctx) { if (state->digest_buff_dma_addr != 0) { - SSI_RESTORE_DMA_ADDR_TO_48BIT(state->digest_buff_dma_addr); dma_unmap_single(dev, state->digest_buff_dma_addr, ctx->inter_digestsize, DMA_BIDIRECTIONAL); SSI_LOG_DEBUG("Unmapped digest-buffer: digest_buff_dma_addr=0x%llX\n", @@ -351,7 +327,6 @@ static void ssi_hash_unmap_request(struct device *dev, state->digest_buff_dma_addr = 0; } if (state->digest_bytes_len_dma_addr != 0) { - SSI_RESTORE_DMA_ADDR_TO_48BIT(state->digest_bytes_len_dma_addr); dma_unmap_single(dev, state->digest_bytes_len_dma_addr, HASH_LEN_SIZE, DMA_BIDIRECTIONAL); SSI_LOG_DEBUG("Unmapped digest-bytes-len buffer: digest_bytes_len_dma_addr=0x%llX\n", @@ -359,7 +334,6 @@ static void ssi_hash_unmap_request(struct device *dev, state->digest_bytes_len_dma_addr = 0; } if (state->opad_digest_dma_addr != 0) { - SSI_RESTORE_DMA_ADDR_TO_48BIT(state->opad_digest_dma_addr); dma_unmap_single(dev, state->opad_digest_dma_addr, ctx->inter_digestsize, DMA_BIDIRECTIONAL); SSI_LOG_DEBUG("Unmapped opad-digest: opad_digest_dma_addr=0x%llX\n", @@ -375,19 +349,18 @@ static void ssi_hash_unmap_request(struct device *dev, kfree(state->buff0); } -static void ssi_hash_unmap_result(struct device *dev, - struct ahash_req_ctx *state, +static void ssi_hash_unmap_result(struct device *dev, + struct ahash_req_ctx *state, unsigned int digestsize, u8 *result) { if (state->digest_result_dma_addr != 0) { - SSI_RESTORE_DMA_ADDR_TO_48BIT(state->digest_result_dma_addr); dma_unmap_single(dev, state->digest_result_dma_addr, digestsize, - DMA_BIDIRECTIONAL); + DMA_BIDIRECTIONAL); SSI_LOG_DEBUG("unmpa digest result buffer " "va (%pK) pa (%llx) len %u\n", - state->digest_result_buff, + state->digest_result_buff, (unsigned long long)state->digest_result_dma_addr, digestsize); memcpy(result, @@ -414,8 +387,8 @@ static void ssi_hash_digest_complete(struct device *dev, void *ssi_req, void __i struct ahash_req_ctx *state = ahash_request_ctx(req); struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); - uint32_t digestsize = crypto_ahash_digestsize(tfm); - + u32 digestsize = crypto_ahash_digestsize(tfm); + SSI_LOG_DEBUG("req=%pK\n", req); ssi_buffer_mgr_unmap_hash_request(dev, state, req->src, false); @@ -430,8 +403,8 @@ static void ssi_hash_complete(struct device *dev, void *ssi_req, void __iomem *c struct ahash_req_ctx *state = ahash_request_ctx(req); struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); - uint32_t digestsize = crypto_ahash_digestsize(tfm); - + u32 digestsize = crypto_ahash_digestsize(tfm); + SSI_LOG_DEBUG("req=%pK\n", req); ssi_buffer_mgr_unmap_hash_request(dev, state, req->src, false); @@ -440,24 +413,23 @@ static void ssi_hash_complete(struct device *dev, void *ssi_req, void __iomem *c req->base.complete(&req->base, 0); } -static int ssi_hash_digest(struct ahash_req_ctx *state, - struct ssi_hash_ctx *ctx, - unsigned int digestsize, - struct scatterlist *src, - unsigned int nbytes, u8 *result, +static int ssi_hash_digest(struct ahash_req_ctx *state, + struct ssi_hash_ctx *ctx, + unsigned int digestsize, + struct scatterlist *src, + unsigned int nbytes, u8 *result, void *async_req) { struct device *dev = &ctx->drvdata->plat_dev->dev; bool is_hmac = ctx->is_hmac; struct ssi_crypto_req ssi_req = {}; - HwDesc_s desc[SSI_MAX_AHASH_SEQ_LEN]; + struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; ssi_sram_addr_t larval_digest_addr = ssi_ahash_get_larval_digest_sram_addr( ctx->drvdata, ctx->hash_mode); int idx = 0; int rc = 0; - - SSI_LOG_DEBUG("===== %s-digest (%d) ====\n", is_hmac?"hmac":"hash", nbytes); + SSI_LOG_DEBUG("===== %s-digest (%d) ====\n", is_hmac ? "hmac" : "hash", nbytes); CHECK_AND_RETURN_UPON_FIPS_ERROR(); @@ -480,102 +452,109 @@ static int ssi_hash_digest(struct ahash_req_ctx *state, /* Setup DX request structure */ ssi_req.user_cb = (void *)ssi_hash_digest_complete; ssi_req.user_arg = (void *)async_req; -#ifdef ENABLE_CYCLE_COUNT - ssi_req.op_type = STAT_OP_TYPE_ENCODE; /* Use "Encode" stats */ -#endif } /* If HMAC then load hash IPAD xor key, if HASH then load initial digest */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); if (is_hmac) { - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, ctx->inter_digestsize, NS_BIT); + set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, + ctx->inter_digestsize, NS_BIT); } else { - HW_DESC_SET_DIN_SRAM(&desc[idx], larval_digest_addr, ctx->inter_digestsize); + set_din_sram(&desc[idx], larval_digest_addr, + ctx->inter_digestsize); } - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); idx++; /* Load the hash current length */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); if (is_hmac) { - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, state->digest_bytes_len_dma_addr, HASH_LEN_SIZE, NS_BIT); + set_din_type(&desc[idx], DMA_DLLI, + state->digest_bytes_len_dma_addr, HASH_LEN_SIZE, + NS_BIT); } else { - HW_DESC_SET_DIN_CONST(&desc[idx], 0, HASH_LEN_SIZE); - if (likely(nbytes != 0)) { - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_ENABLED); - } else { - HW_DESC_SET_CIPHER_DO(&desc[idx], DO_PAD); - } - } - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + set_din_const(&desc[idx], 0, HASH_LEN_SIZE); + if (likely(nbytes != 0)) + set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); + else + set_cipher_do(&desc[idx], DO_PAD); + } + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; ssi_hash_create_data_desc(state, ctx, DIN_HASH, desc, false, &idx); if (is_hmac) { /* HW last hash block padding (aka. "DO_PAD") */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DOUT_DLLI(&desc[idx], state->digest_buff_dma_addr, HASH_LEN_SIZE, NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE1); - HW_DESC_SET_CIPHER_DO(&desc[idx], DO_PAD); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_dout_dlli(&desc[idx], state->digest_buff_dma_addr, + HASH_LEN_SIZE, NS_BIT, 0); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE1); + set_cipher_do(&desc[idx], DO_PAD); idx++; /* store the hash digest result in the context */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DOUT_DLLI(&desc[idx], state->digest_buff_dma_addr, digestsize, NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_dout_dlli(&desc[idx], state->digest_buff_dma_addr, + digestsize, NS_BIT, 0); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); ssi_set_hash_endianity(ctx->hash_mode, &desc[idx]); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); idx++; /* Loading hash opad xor key state */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, state->opad_digest_dma_addr, ctx->inter_digestsize, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_din_type(&desc[idx], DMA_DLLI, state->opad_digest_dma_addr, + ctx->inter_digestsize, NS_BIT); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); idx++; /* Load the hash current length */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DIN_SRAM(&desc[idx], ssi_ahash_get_initial_digest_len_sram_addr(ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_ENABLED); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_din_sram(&desc[idx], + ssi_ahash_get_initial_digest_len_sram_addr( +ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); + set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; /* Memory Barrier: wait for IPAD/OPAD axi write to complete */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_NO_DMA(&desc[idx], 0, 0xfffff0); - HW_DESC_SET_DOUT_NO_DMA(&desc[idx], 0, 0, 1); + hw_desc_init(&desc[idx]); + set_din_no_dma(&desc[idx], 0, 0xfffff0); + set_dout_no_dma(&desc[idx], 0, 0, 1); idx++; /* Perform HASH update */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, digestsize, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_HASH); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, + digestsize, NS_BIT); + set_flow_mode(&desc[idx], DIN_HASH); idx++; } /* Get final MAC result */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DOUT_DLLI(&desc[idx], state->digest_result_dma_addr, digestsize, NS_BIT, async_req? 1:0); /*TODO*/ - if (async_req) { - HW_DESC_SET_QUEUE_LAST_IND(&desc[idx]); - } - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_DISABLED); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + /* TODO */ + set_dout_dlli(&desc[idx], state->digest_result_dma_addr, digestsize, + NS_BIT, (async_req ? 1 : 0)); + if (async_req) + set_queue_last_ind(&desc[idx]); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); + set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); ssi_set_hash_endianity(ctx->hash_mode, &desc[idx]); idx++; @@ -593,7 +572,7 @@ static int ssi_hash_digest(struct ahash_req_ctx *state, SSI_LOG_ERR("send_request() failed (rc=%d)\n", rc); ssi_buffer_mgr_unmap_hash_request(dev, state, src, true); } else { - ssi_buffer_mgr_unmap_hash_request(dev, state, src, false); + ssi_buffer_mgr_unmap_hash_request(dev, state, src, false); } ssi_hash_unmap_result(dev, state, digestsize, result); ssi_hash_unmap_request(dev, state, ctx); @@ -601,21 +580,21 @@ static int ssi_hash_digest(struct ahash_req_ctx *state, return rc; } -static int ssi_hash_update(struct ahash_req_ctx *state, - struct ssi_hash_ctx *ctx, - unsigned int block_size, - struct scatterlist *src, - unsigned int nbytes, +static int ssi_hash_update(struct ahash_req_ctx *state, + struct ssi_hash_ctx *ctx, + unsigned int block_size, + struct scatterlist *src, + unsigned int nbytes, void *async_req) { struct device *dev = &ctx->drvdata->plat_dev->dev; struct ssi_crypto_req ssi_req = {}; - HwDesc_s desc[SSI_MAX_AHASH_SEQ_LEN]; - uint32_t idx = 0; + struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; + u32 idx = 0; int rc; SSI_LOG_DEBUG("===== %s-update (%d) ====\n", ctx->is_hmac ? - "hmac":"hash", nbytes); + "hmac" : "hash", nbytes); CHECK_AND_RETURN_UPON_FIPS_ERROR(); if (nbytes == 0) { @@ -638,45 +617,45 @@ static int ssi_hash_update(struct ahash_req_ctx *state, /* Setup DX request structure */ ssi_req.user_cb = (void *)ssi_hash_update_complete; ssi_req.user_arg = async_req; -#ifdef ENABLE_CYCLE_COUNT - ssi_req.op_type = STAT_OP_TYPE_ENCODE; /* Use "Encode" stats */ -#endif } /* Restore hash digest */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, ctx->inter_digestsize, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, + ctx->inter_digestsize, NS_BIT); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); idx++; /* Restore hash current length */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, state->digest_bytes_len_dma_addr, HASH_LEN_SIZE, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_din_type(&desc[idx], DMA_DLLI, state->digest_bytes_len_dma_addr, + HASH_LEN_SIZE, NS_BIT); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; ssi_hash_create_data_desc(state, ctx, DIN_HASH, desc, false, &idx); /* store the hash digest result in context */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DOUT_DLLI(&desc[idx], state->digest_buff_dma_addr, ctx->inter_digestsize, NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_dout_dlli(&desc[idx], state->digest_buff_dma_addr, + ctx->inter_digestsize, NS_BIT, 0); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); idx++; /* store current hash length in context */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DOUT_DLLI(&desc[idx], state->digest_bytes_len_dma_addr, HASH_LEN_SIZE, NS_BIT, async_req? 1:0); - if (async_req) { - HW_DESC_SET_QUEUE_LAST_IND(&desc[idx]); - } - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE1); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_dout_dlli(&desc[idx], state->digest_bytes_len_dma_addr, + HASH_LEN_SIZE, NS_BIT, (async_req ? 1 : 0)); + if (async_req) + set_queue_last_ind(&desc[idx]); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE1); idx++; if (async_req) { @@ -697,26 +676,26 @@ static int ssi_hash_update(struct ahash_req_ctx *state, return rc; } -static int ssi_hash_finup(struct ahash_req_ctx *state, - struct ssi_hash_ctx *ctx, - unsigned int digestsize, - struct scatterlist *src, - unsigned int nbytes, - u8 *result, +static int ssi_hash_finup(struct ahash_req_ctx *state, + struct ssi_hash_ctx *ctx, + unsigned int digestsize, + struct scatterlist *src, + unsigned int nbytes, + u8 *result, void *async_req) { struct device *dev = &ctx->drvdata->plat_dev->dev; bool is_hmac = ctx->is_hmac; struct ssi_crypto_req ssi_req = {}; - HwDesc_s desc[SSI_MAX_AHASH_SEQ_LEN]; + struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; int idx = 0; int rc; - SSI_LOG_DEBUG("===== %s-finup (%d) ====\n", is_hmac?"hmac":"hash", nbytes); + SSI_LOG_DEBUG("===== %s-finup (%d) ====\n", is_hmac ? "hmac" : "hash", nbytes); CHECK_AND_RETURN_UPON_FIPS_ERROR(); - if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, src , nbytes, 1) != 0)) { + if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, src, nbytes, 1) != 0)) { SSI_LOG_ERR("map_ahash_request_final() failed\n"); return -ENOMEM; } @@ -729,81 +708,86 @@ static int ssi_hash_finup(struct ahash_req_ctx *state, /* Setup DX request structure */ ssi_req.user_cb = (void *)ssi_hash_complete; ssi_req.user_arg = async_req; -#ifdef ENABLE_CYCLE_COUNT - ssi_req.op_type = STAT_OP_TYPE_ENCODE; /* Use "Encode" stats */ -#endif } /* Restore hash digest */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, ctx->inter_digestsize, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, + ctx->inter_digestsize, NS_BIT); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); idx++; /* Restore hash current length */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_ENABLED); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, state->digest_bytes_len_dma_addr, HASH_LEN_SIZE, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); + set_din_type(&desc[idx], DMA_DLLI, state->digest_bytes_len_dma_addr, + HASH_LEN_SIZE, NS_BIT); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; ssi_hash_create_data_desc(state, ctx, DIN_HASH, desc, false, &idx); if (is_hmac) { /* Store the hash digest result in the context */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DOUT_DLLI(&desc[idx], state->digest_buff_dma_addr, digestsize, NS_BIT, 0); - ssi_set_hash_endianity(ctx->hash_mode,&desc[idx]); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_dout_dlli(&desc[idx], state->digest_buff_dma_addr, + digestsize, NS_BIT, 0); + ssi_set_hash_endianity(ctx->hash_mode, &desc[idx]); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); idx++; /* Loading hash OPAD xor key state */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, state->opad_digest_dma_addr, ctx->inter_digestsize, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_din_type(&desc[idx], DMA_DLLI, state->opad_digest_dma_addr, + ctx->inter_digestsize, NS_BIT); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); idx++; /* Load the hash current length */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DIN_SRAM(&desc[idx], ssi_ahash_get_initial_digest_len_sram_addr(ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_ENABLED); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_din_sram(&desc[idx], + ssi_ahash_get_initial_digest_len_sram_addr( +ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); + set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; /* Memory Barrier: wait for IPAD/OPAD axi write to complete */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_NO_DMA(&desc[idx], 0, 0xfffff0); - HW_DESC_SET_DOUT_NO_DMA(&desc[idx], 0, 0, 1); + hw_desc_init(&desc[idx]); + set_din_no_dma(&desc[idx], 0, 0xfffff0); + set_dout_no_dma(&desc[idx], 0, 0, 1); idx++; /* Perform HASH update on last digest */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, digestsize, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_HASH); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, + digestsize, NS_BIT); + set_flow_mode(&desc[idx], DIN_HASH); idx++; } /* Get final MAC result */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DOUT_DLLI(&desc[idx], state->digest_result_dma_addr, digestsize, NS_BIT, async_req? 1:0); /*TODO*/ - if (async_req) { - HW_DESC_SET_QUEUE_LAST_IND(&desc[idx]); - } - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_DISABLED); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); - ssi_set_hash_endianity(ctx->hash_mode,&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); + hw_desc_init(&desc[idx]); + /* TODO */ + set_dout_dlli(&desc[idx], state->digest_result_dma_addr, digestsize, + NS_BIT, (async_req ? 1 : 0)); + if (async_req) + set_queue_last_ind(&desc[idx]); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); + ssi_set_hash_endianity(ctx->hash_mode, &desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); idx++; if (async_req) { @@ -828,22 +812,22 @@ static int ssi_hash_finup(struct ahash_req_ctx *state, return rc; } -static int ssi_hash_final(struct ahash_req_ctx *state, - struct ssi_hash_ctx *ctx, - unsigned int digestsize, - struct scatterlist *src, - unsigned int nbytes, - u8 *result, +static int ssi_hash_final(struct ahash_req_ctx *state, + struct ssi_hash_ctx *ctx, + unsigned int digestsize, + struct scatterlist *src, + unsigned int nbytes, + u8 *result, void *async_req) { struct device *dev = &ctx->drvdata->plat_dev->dev; bool is_hmac = ctx->is_hmac; struct ssi_crypto_req ssi_req = {}; - HwDesc_s desc[SSI_MAX_AHASH_SEQ_LEN]; + struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; int idx = 0; int rc; - SSI_LOG_DEBUG("===== %s-final (%d) ====\n", is_hmac?"hmac":"hash", nbytes); + SSI_LOG_DEBUG("===== %s-final (%d) ====\n", is_hmac ? "hmac" : "hash", nbytes); CHECK_AND_RETURN_UPON_FIPS_ERROR(); @@ -861,90 +845,95 @@ static int ssi_hash_final(struct ahash_req_ctx *state, /* Setup DX request structure */ ssi_req.user_cb = (void *)ssi_hash_complete; ssi_req.user_arg = async_req; -#ifdef ENABLE_CYCLE_COUNT - ssi_req.op_type = STAT_OP_TYPE_ENCODE; /* Use "Encode" stats */ -#endif } /* Restore hash digest */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, ctx->inter_digestsize, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, + ctx->inter_digestsize, NS_BIT); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); idx++; /* Restore hash current length */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_DISABLED); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, state->digest_bytes_len_dma_addr, HASH_LEN_SIZE, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); + set_din_type(&desc[idx], DMA_DLLI, state->digest_bytes_len_dma_addr, + HASH_LEN_SIZE, NS_BIT); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; ssi_hash_create_data_desc(state, ctx, DIN_HASH, desc, false, &idx); /* "DO-PAD" must be enabled only when writing current length to HW */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_DO(&desc[idx], DO_PAD); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DOUT_DLLI(&desc[idx], state->digest_bytes_len_dma_addr, HASH_LEN_SIZE, NS_BIT, 0); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE1); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); + hw_desc_init(&desc[idx]); + set_cipher_do(&desc[idx], DO_PAD); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_dout_dlli(&desc[idx], state->digest_bytes_len_dma_addr, + HASH_LEN_SIZE, NS_BIT, 0); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE1); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); idx++; if (is_hmac) { /* Store the hash digest result in the context */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DOUT_DLLI(&desc[idx], state->digest_buff_dma_addr, digestsize, NS_BIT, 0); - ssi_set_hash_endianity(ctx->hash_mode,&desc[idx]); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_dout_dlli(&desc[idx], state->digest_buff_dma_addr, + digestsize, NS_BIT, 0); + ssi_set_hash_endianity(ctx->hash_mode, &desc[idx]); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); idx++; /* Loading hash OPAD xor key state */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, state->opad_digest_dma_addr, ctx->inter_digestsize, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_din_type(&desc[idx], DMA_DLLI, state->opad_digest_dma_addr, + ctx->inter_digestsize, NS_BIT); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); idx++; /* Load the hash current length */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DIN_SRAM(&desc[idx], ssi_ahash_get_initial_digest_len_sram_addr(ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_ENABLED); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_din_sram(&desc[idx], + ssi_ahash_get_initial_digest_len_sram_addr( +ctx->drvdata, ctx->hash_mode), HASH_LEN_SIZE); + set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; /* Memory Barrier: wait for IPAD/OPAD axi write to complete */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_NO_DMA(&desc[idx], 0, 0xfffff0); - HW_DESC_SET_DOUT_NO_DMA(&desc[idx], 0, 0, 1); + hw_desc_init(&desc[idx]); + set_din_no_dma(&desc[idx], 0, 0xfffff0); + set_dout_no_dma(&desc[idx], 0, 0, 1); idx++; /* Perform HASH update on last digest */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, digestsize, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_HASH); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, + digestsize, NS_BIT); + set_flow_mode(&desc[idx], DIN_HASH); idx++; } /* Get final MAC result */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DOUT_DLLI(&desc[idx], state->digest_result_dma_addr, digestsize, NS_BIT, async_req? 1:0); - if (async_req) { - HW_DESC_SET_QUEUE_LAST_IND(&desc[idx]); - } - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_DISABLED); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); - ssi_set_hash_endianity(ctx->hash_mode,&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); + hw_desc_init(&desc[idx]); + set_dout_dlli(&desc[idx], state->digest_result_dma_addr, digestsize, + NS_BIT, (async_req ? 1 : 0)); + if (async_req) + set_queue_last_ind(&desc[idx]); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); + ssi_set_hash_endianity(ctx->hash_mode, &desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); idx++; if (async_req) { @@ -972,33 +961,18 @@ static int ssi_hash_final(struct ahash_req_ctx *state, static int ssi_hash_init(struct ahash_req_ctx *state, struct ssi_hash_ctx *ctx) { struct device *dev = &ctx->drvdata->plat_dev->dev; - state->xcbc_count = 0; - CHECK_AND_RETURN_UPON_FIPS_ERROR(); - ssi_hash_map_request(dev, state, ctx); - - return 0; -} + state->xcbc_count = 0; -#ifdef EXPORT_FIXED -static int ssi_hash_export(struct ssi_hash_ctx *ctx, void *out) -{ CHECK_AND_RETURN_UPON_FIPS_ERROR(); - memcpy(out, ctx, sizeof(struct ssi_hash_ctx)); - return 0; -} + ssi_hash_map_request(dev, state, ctx); -static int ssi_hash_import(struct ssi_hash_ctx *ctx, const void *in) -{ - CHECK_AND_RETURN_UPON_FIPS_ERROR(); - memcpy(ctx, in, sizeof(struct ssi_hash_ctx)); return 0; } -#endif static int ssi_hash_setkey(void *hash, - const u8 *key, - unsigned int keylen, + const u8 *key, + unsigned int keylen, bool synchronize) { unsigned int hmacPadConst[2] = { HMAC_IPAD_CONST, HMAC_OPAD_CONST }; @@ -1007,27 +981,22 @@ static int ssi_hash_setkey(void *hash, int blocksize = 0; int digestsize = 0; int i, idx = 0, rc = 0; - HwDesc_s desc[SSI_MAX_AHASH_SEQ_LEN]; + struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; ssi_sram_addr_t larval_addr; SSI_LOG_DEBUG("ssi_hash_setkey: start keylen: %d", keylen); - + CHECK_AND_RETURN_UPON_FIPS_ERROR(); - if (synchronize) { - ctx = crypto_shash_ctx(((struct crypto_shash *)hash)); - blocksize = crypto_tfm_alg_blocksize(&((struct crypto_shash *)hash)->base); - digestsize = crypto_shash_digestsize(((struct crypto_shash *)hash)); - } else { - ctx = crypto_ahash_ctx(((struct crypto_ahash *)hash)); - blocksize = crypto_tfm_alg_blocksize(&((struct crypto_ahash *)hash)->base); - digestsize = crypto_ahash_digestsize(((struct crypto_ahash *)hash)); - } - + ctx = crypto_ahash_ctx(((struct crypto_ahash *)hash)); + blocksize = crypto_tfm_alg_blocksize(&((struct crypto_ahash *)hash)->base); + digestsize = crypto_ahash_digestsize(((struct crypto_ahash *)hash)); + larval_addr = ssi_ahash_get_larval_digest_sram_addr( ctx->drvdata, ctx->hash_mode); /* The keylen value distinguishes HASH in case keylen is ZERO bytes, - any NON-ZERO value utilizes HMAC flow */ + * any NON-ZERO value utilizes HMAC flow + */ ctx->key_params.keylen = keylen; ctx->key_params.key_dma_addr = 0; ctx->is_hmac = true; @@ -1043,7 +1012,6 @@ static int ssi_hash_setkey(void *hash, " DMA failed\n", key, keylen); return -ENOMEM; } - SSI_UPDATE_DMA_ADDR_TO_48BIT(ctx->key_params.key_dma_addr, keylen); SSI_LOG_DEBUG("mapping key-buffer: key_dma_addr=0x%llX " "keylen=%u\n", (unsigned long long)ctx->key_params.key_dma_addr, @@ -1051,79 +1019,76 @@ static int ssi_hash_setkey(void *hash, if (keylen > blocksize) { /* Load hash initial state */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DIN_SRAM(&desc[idx], larval_addr, - ctx->inter_digestsize); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_din_sram(&desc[idx], larval_addr, + ctx->inter_digestsize); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); idx++; - + /* Load the hash current length*/ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DIN_CONST(&desc[idx], 0, HASH_LEN_SIZE); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_ENABLED); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_din_const(&desc[idx], 0, HASH_LEN_SIZE); + set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; - - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - ctx->key_params.key_dma_addr, - keylen, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_HASH); + + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, + ctx->key_params.key_dma_addr, keylen, + NS_BIT); + set_flow_mode(&desc[idx], DIN_HASH); idx++; - + /* Get hashed key */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DOUT_DLLI(&desc[idx], ctx->opad_tmp_keys_dma_addr, - digestsize, NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); - HW_DESC_SET_CIPHER_CONFIG1(&desc[idx], HASH_PADDING_DISABLED); - ssi_set_hash_endianity(ctx->hash_mode,&desc[idx]); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_dout_dlli(&desc[idx], ctx->opad_tmp_keys_dma_addr, + digestsize, NS_BIT, 0); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); + set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED); + ssi_set_hash_endianity(ctx->hash_mode, &desc[idx]); idx++; - - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_CONST(&desc[idx], 0, (blocksize - digestsize)); - HW_DESC_SET_FLOW_MODE(&desc[idx], BYPASS); - HW_DESC_SET_DOUT_DLLI(&desc[idx], - (ctx->opad_tmp_keys_dma_addr + digestsize), - (blocksize - digestsize), - NS_BIT, 0); + + hw_desc_init(&desc[idx]); + set_din_const(&desc[idx], 0, (blocksize - digestsize)); + set_flow_mode(&desc[idx], BYPASS); + set_dout_dlli(&desc[idx], (ctx->opad_tmp_keys_dma_addr + + digestsize), + (blocksize - digestsize), NS_BIT, 0); idx++; } else { - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - ctx->key_params.key_dma_addr, - keylen, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], BYPASS); - HW_DESC_SET_DOUT_DLLI(&desc[idx], - (ctx->opad_tmp_keys_dma_addr), - keylen, NS_BIT, 0); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, + ctx->key_params.key_dma_addr, keylen, + NS_BIT); + set_flow_mode(&desc[idx], BYPASS); + set_dout_dlli(&desc[idx], ctx->opad_tmp_keys_dma_addr, + keylen, NS_BIT, 0); idx++; if ((blocksize - keylen) != 0) { - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_CONST(&desc[idx], 0, (blocksize - keylen)); - HW_DESC_SET_FLOW_MODE(&desc[idx], BYPASS); - HW_DESC_SET_DOUT_DLLI(&desc[idx], - (ctx->opad_tmp_keys_dma_addr + keylen), - (blocksize - keylen), - NS_BIT, 0); + hw_desc_init(&desc[idx]); + set_din_const(&desc[idx], 0, + (blocksize - keylen)); + set_flow_mode(&desc[idx], BYPASS); + set_dout_dlli(&desc[idx], + (ctx->opad_tmp_keys_dma_addr + + keylen), (blocksize - keylen), + NS_BIT, 0); idx++; } } } else { - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_CONST(&desc[idx], 0, blocksize); - HW_DESC_SET_FLOW_MODE(&desc[idx], BYPASS); - HW_DESC_SET_DOUT_DLLI(&desc[idx], - (ctx->opad_tmp_keys_dma_addr), - blocksize, - NS_BIT, 0); + hw_desc_init(&desc[idx]); + set_din_const(&desc[idx], 0, blocksize); + set_flow_mode(&desc[idx], BYPASS); + set_dout_dlli(&desc[idx], (ctx->opad_tmp_keys_dma_addr), + blocksize, NS_BIT, 0); idx++; } @@ -1136,71 +1101,59 @@ static int ssi_hash_setkey(void *hash, /* calc derived HMAC key */ for (idx = 0, i = 0; i < 2; i++) { /* Load hash initial state */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DIN_SRAM(&desc[idx], larval_addr, - ctx->inter_digestsize); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_din_sram(&desc[idx], larval_addr, ctx->inter_digestsize); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); idx++; /* Load the hash current length*/ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DIN_CONST(&desc[idx], 0, HASH_LEN_SIZE); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_din_const(&desc[idx], 0, HASH_LEN_SIZE); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; /* Prepare ipad key */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_XOR_VAL(&desc[idx], hmacPadConst[i]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_HASH); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE1); + hw_desc_init(&desc[idx]); + set_xor_val(&desc[idx], hmacPadConst[i]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_flow_mode(&desc[idx], S_DIN_to_HASH); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE1); idx++; /* Perform HASH update */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - ctx->opad_tmp_keys_dma_addr, - blocksize, NS_BIT); - HW_DESC_SET_CIPHER_MODE(&desc[idx],ctx->hw_mode); - HW_DESC_SET_XOR_ACTIVE(&desc[idx]); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_HASH); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, ctx->opad_tmp_keys_dma_addr, + blocksize, NS_BIT); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_xor_active(&desc[idx]); + set_flow_mode(&desc[idx], DIN_HASH); idx++; /* Get the IPAD/OPAD xor key (Note, IPAD is the initial digest of the first HASH "update" state) */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); if (i > 0) /* Not first iteration */ - HW_DESC_SET_DOUT_DLLI(&desc[idx], - ctx->opad_tmp_keys_dma_addr, - ctx->inter_digestsize, - NS_BIT, 0); + set_dout_dlli(&desc[idx], ctx->opad_tmp_keys_dma_addr, + ctx->inter_digestsize, NS_BIT, 0); else /* First iteration */ - HW_DESC_SET_DOUT_DLLI(&desc[idx], - ctx->digest_buff_dma_addr, - ctx->inter_digestsize, - NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_HASH_to_DOUT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); + set_dout_dlli(&desc[idx], ctx->digest_buff_dma_addr, + ctx->inter_digestsize, NS_BIT, 0); + set_flow_mode(&desc[idx], S_HASH_to_DOUT); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); idx++; } rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 0); out: - if (rc != 0) { - if (synchronize) { - crypto_shash_set_flags((struct crypto_shash *)hash, CRYPTO_TFM_RES_BAD_KEY_LEN); - } else { - crypto_ahash_set_flags((struct crypto_ahash *)hash, CRYPTO_TFM_RES_BAD_KEY_LEN); - } - } + if (rc) + crypto_ahash_set_flags((struct crypto_ahash *)hash, CRYPTO_TFM_RES_BAD_KEY_LEN); if (ctx->key_params.key_dma_addr) { - SSI_RESTORE_DMA_ADDR_TO_48BIT(ctx->key_params.key_dma_addr); dma_unmap_single(&ctx->drvdata->plat_dev->dev, ctx->key_params.key_dma_addr, ctx->key_params.keylen, DMA_TO_DEVICE); @@ -1211,14 +1164,13 @@ out: return rc; } - static int ssi_xcbc_setkey(struct crypto_ahash *ahash, const u8 *key, unsigned int keylen) { struct ssi_crypto_req ssi_req = {}; struct ssi_hash_ctx *ctx = crypto_ahash_ctx(ahash); int idx = 0, rc = 0; - HwDesc_s desc[SSI_MAX_AHASH_SEQ_LEN]; + struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; SSI_LOG_DEBUG("===== setkey (%d) ====\n", keylen); CHECK_AND_RETURN_UPON_FIPS_ERROR(); @@ -1244,43 +1196,43 @@ static int ssi_xcbc_setkey(struct crypto_ahash *ahash, " DMA failed\n", key, keylen); return -ENOMEM; } - SSI_UPDATE_DMA_ADDR_TO_48BIT(ctx->key_params.key_dma_addr, keylen); SSI_LOG_DEBUG("mapping key-buffer: key_dma_addr=0x%llX " "keylen=%u\n", (unsigned long long)ctx->key_params.key_dma_addr, ctx->key_params.keylen); - + ctx->is_hmac = true; /* 1. Load the AES key */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, ctx->key_params.key_dma_addr, keylen, NS_BIT); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_ECB); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], keylen); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, ctx->key_params.key_dma_addr, + keylen, NS_BIT); + set_cipher_mode(&desc[idx], DRV_CIPHER_ECB); + set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT); + set_key_size_aes(&desc[idx], keylen); + set_flow_mode(&desc[idx], S_DIN_to_AES); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_CONST(&desc[idx], 0x01010101, CC_AES_128_BIT_KEY_SIZE); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_AES_DOUT); - HW_DESC_SET_DOUT_DLLI(&desc[idx], (ctx->opad_tmp_keys_dma_addr + - XCBC_MAC_K1_OFFSET), + hw_desc_init(&desc[idx]); + set_din_const(&desc[idx], 0x01010101, CC_AES_128_BIT_KEY_SIZE); + set_flow_mode(&desc[idx], DIN_AES_DOUT); + set_dout_dlli(&desc[idx], (ctx->opad_tmp_keys_dma_addr + + XCBC_MAC_K1_OFFSET), CC_AES_128_BIT_KEY_SIZE, NS_BIT, 0); idx++; - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_CONST(&desc[idx], 0x02020202, CC_AES_128_BIT_KEY_SIZE); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_AES_DOUT); - HW_DESC_SET_DOUT_DLLI(&desc[idx], (ctx->opad_tmp_keys_dma_addr + - XCBC_MAC_K2_OFFSET), + hw_desc_init(&desc[idx]); + set_din_const(&desc[idx], 0x02020202, CC_AES_128_BIT_KEY_SIZE); + set_flow_mode(&desc[idx], DIN_AES_DOUT); + set_dout_dlli(&desc[idx], (ctx->opad_tmp_keys_dma_addr + + XCBC_MAC_K2_OFFSET), CC_AES_128_BIT_KEY_SIZE, NS_BIT, 0); idx++; - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_CONST(&desc[idx], 0x03030303, CC_AES_128_BIT_KEY_SIZE); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_AES_DOUT); - HW_DESC_SET_DOUT_DLLI(&desc[idx], (ctx->opad_tmp_keys_dma_addr + + hw_desc_init(&desc[idx]); + set_din_const(&desc[idx], 0x03030303, CC_AES_128_BIT_KEY_SIZE); + set_flow_mode(&desc[idx], DIN_AES_DOUT); + set_dout_dlli(&desc[idx], (ctx->opad_tmp_keys_dma_addr + XCBC_MAC_K3_OFFSET), CC_AES_128_BIT_KEY_SIZE, NS_BIT, 0); idx++; @@ -1290,7 +1242,6 @@ static int ssi_xcbc_setkey(struct crypto_ahash *ahash, if (rc != 0) crypto_ahash_set_flags(ahash, CRYPTO_TFM_RES_BAD_KEY_LEN); - SSI_RESTORE_DMA_ADDR_TO_48BIT(ctx->key_params.key_dma_addr); dma_unmap_single(&ctx->drvdata->plat_dev->dev, ctx->key_params.key_dma_addr, ctx->key_params.keylen, DMA_TO_DEVICE); @@ -1300,12 +1251,13 @@ static int ssi_xcbc_setkey(struct crypto_ahash *ahash, return rc; } + #if SSI_CC_HAS_CMAC static int ssi_cmac_setkey(struct crypto_ahash *ahash, const u8 *key, unsigned int keylen) { struct ssi_hash_ctx *ctx = crypto_ahash_ctx(ahash); - DECL_CYCLE_COUNT_RESOURCES; + SSI_LOG_DEBUG("===== setkey (%d) ====\n", keylen); CHECK_AND_RETURN_UPON_FIPS_ERROR(); @@ -1323,25 +1275,20 @@ static int ssi_cmac_setkey(struct crypto_ahash *ahash, ctx->key_params.keylen = keylen; /* STAT_PHASE_1: Copy key to ctx */ - START_CYCLE_COUNT(); - - SSI_RESTORE_DMA_ADDR_TO_48BIT(ctx->opad_tmp_keys_dma_addr); + dma_sync_single_for_cpu(&ctx->drvdata->plat_dev->dev, - ctx->opad_tmp_keys_dma_addr, + ctx->opad_tmp_keys_dma_addr, keylen, DMA_TO_DEVICE); memcpy(ctx->opad_tmp_keys_buff, key, keylen); if (keylen == 24) memset(ctx->opad_tmp_keys_buff + 24, 0, CC_AES_KEY_SIZE_MAX - 24); - + dma_sync_single_for_device(&ctx->drvdata->plat_dev->dev, - ctx->opad_tmp_keys_dma_addr, + ctx->opad_tmp_keys_dma_addr, keylen, DMA_TO_DEVICE); - SSI_UPDATE_DMA_ADDR_TO_48BIT(ctx->opad_tmp_keys_dma_addr, keylen); - + ctx->key_params.keylen = keylen; - - END_CYCLE_COUNT(STAT_OP_TYPE_SETKEY, STAT_PHASE_1); return 0; } @@ -1352,7 +1299,6 @@ static void ssi_hash_free_ctx(struct ssi_hash_ctx *ctx) struct device *dev = &ctx->drvdata->plat_dev->dev; if (ctx->digest_buff_dma_addr != 0) { - SSI_RESTORE_DMA_ADDR_TO_48BIT(ctx->digest_buff_dma_addr); dma_unmap_single(dev, ctx->digest_buff_dma_addr, sizeof(ctx->digest_buff), DMA_BIDIRECTIONAL); SSI_LOG_DEBUG("Unmapped digest-buffer: " @@ -1361,7 +1307,6 @@ static void ssi_hash_free_ctx(struct ssi_hash_ctx *ctx) ctx->digest_buff_dma_addr = 0; } if (ctx->opad_tmp_keys_dma_addr != 0) { - SSI_RESTORE_DMA_ADDR_TO_48BIT(ctx->opad_tmp_keys_dma_addr); dma_unmap_single(dev, ctx->opad_tmp_keys_dma_addr, sizeof(ctx->opad_tmp_keys_buff), DMA_BIDIRECTIONAL); @@ -1372,10 +1317,8 @@ static void ssi_hash_free_ctx(struct ssi_hash_ctx *ctx) } ctx->key_params.keylen = 0; - } - static int ssi_hash_alloc_ctx(struct ssi_hash_ctx *ctx) { struct device *dev = &ctx->drvdata->plat_dev->dev; @@ -1388,8 +1331,6 @@ static int ssi_hash_alloc_ctx(struct ssi_hash_ctx *ctx) sizeof(ctx->digest_buff), ctx->digest_buff); goto fail; } - SSI_UPDATE_DMA_ADDR_TO_48BIT(ctx->digest_buff_dma_addr, - sizeof(ctx->digest_buff)); SSI_LOG_DEBUG("Mapped digest %zu B at va=%pK to dma=0x%llX\n", sizeof(ctx->digest_buff), ctx->digest_buff, (unsigned long long)ctx->digest_buff_dma_addr); @@ -1401,8 +1342,6 @@ static int ssi_hash_alloc_ctx(struct ssi_hash_ctx *ctx) ctx->opad_tmp_keys_buff); goto fail; } - SSI_UPDATE_DMA_ADDR_TO_48BIT(ctx->opad_tmp_keys_dma_addr, - sizeof(ctx->opad_tmp_keys_buff)); SSI_LOG_DEBUG("Mapped opad_tmp_keys %zu B at va=%pK to dma=0x%llX\n", sizeof(ctx->opad_tmp_keys_buff), ctx->opad_tmp_keys_buff, (unsigned long long)ctx->opad_tmp_keys_dma_addr); @@ -1415,34 +1354,16 @@ fail: return -ENOMEM; } -static int ssi_shash_cra_init(struct crypto_tfm *tfm) -{ - struct ssi_hash_ctx *ctx = crypto_tfm_ctx(tfm); - struct shash_alg * shash_alg = - container_of(tfm->__crt_alg, struct shash_alg, base); - struct ssi_hash_alg *ssi_alg = - container_of(shash_alg, struct ssi_hash_alg, shash_alg); - - CHECK_AND_RETURN_UPON_FIPS_ERROR(); - ctx->hash_mode = ssi_alg->hash_mode; - ctx->hw_mode = ssi_alg->hw_mode; - ctx->inter_digestsize = ssi_alg->inter_digestsize; - ctx->drvdata = ssi_alg->drvdata; - - return ssi_hash_alloc_ctx(ctx); -} - static int ssi_ahash_cra_init(struct crypto_tfm *tfm) { struct ssi_hash_ctx *ctx = crypto_tfm_ctx(tfm); - struct hash_alg_common * hash_alg_common = + struct hash_alg_common *hash_alg_common = container_of(tfm->__crt_alg, struct hash_alg_common, base); - struct ahash_alg *ahash_alg = + struct ahash_alg *ahash_alg = container_of(hash_alg_common, struct ahash_alg, halg); struct ssi_hash_alg *ssi_alg = container_of(ahash_alg, struct ssi_hash_alg, ahash_alg); - CHECK_AND_RETURN_UPON_FIPS_ERROR(); crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), sizeof(struct ahash_req_ctx)); @@ -1471,9 +1392,9 @@ static int ssi_mac_update(struct ahash_request *req) struct device *dev = &ctx->drvdata->plat_dev->dev; unsigned int block_size = crypto_tfm_alg_blocksize(&tfm->base); struct ssi_crypto_req ssi_req = {}; - HwDesc_s desc[SSI_MAX_AHASH_SEQ_LEN]; + struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; int rc; - uint32_t idx = 0; + u32 idx = 0; CHECK_AND_RETURN_UPON_FIPS_ERROR(); if (req->nbytes == 0) { @@ -1494,29 +1415,26 @@ static int ssi_mac_update(struct ahash_request *req) return -ENOMEM; } - if (ctx->hw_mode == DRV_CIPHER_XCBC_MAC) { + if (ctx->hw_mode == DRV_CIPHER_XCBC_MAC) ssi_hash_create_xcbc_setup(req, desc, &idx); - } else { + else ssi_hash_create_cmac_setup(req, desc, &idx); - } - + ssi_hash_create_data_desc(state, ctx, DIN_AES_DOUT, desc, true, &idx); /* store the hash digest result in context */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_DOUT_DLLI(&desc[idx], state->digest_buff_dma_addr, ctx->inter_digestsize, NS_BIT, 1); - HW_DESC_SET_QUEUE_LAST_IND(&desc[idx]); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_AES_to_DOUT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_dout_dlli(&desc[idx], state->digest_buff_dma_addr, + ctx->inter_digestsize, NS_BIT, 1); + set_queue_last_ind(&desc[idx]); + set_flow_mode(&desc[idx], S_AES_to_DOUT); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); idx++; /* Setup DX request structure */ ssi_req.user_cb = (void *)ssi_hash_update_complete; ssi_req.user_arg = (void *)req; -#ifdef ENABLE_CYCLE_COUNT - ssi_req.op_type = STAT_OP_TYPE_ENCODE; /* Use "Encode" stats */ -#endif rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); if (unlikely(rc != -EINPROGRESS)) { @@ -1533,15 +1451,14 @@ static int ssi_mac_final(struct ahash_request *req) struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); struct device *dev = &ctx->drvdata->plat_dev->dev; struct ssi_crypto_req ssi_req = {}; - HwDesc_s desc[SSI_MAX_AHASH_SEQ_LEN]; + struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; int idx = 0; int rc = 0; - uint32_t keySize, keyLen; - uint32_t digestsize = crypto_ahash_digestsize(tfm); + u32 keySize, keyLen; + u32 digestsize = crypto_ahash_digestsize(tfm); - uint32_t rem_cnt = state->buff_index ? state->buff1_cnt : + u32 rem_cnt = state->buff_index ? state->buff1_cnt : state->buff0_cnt; - CHECK_AND_RETURN_UPON_FIPS_ERROR(); if (ctx->hw_mode == DRV_CIPHER_XCBC_MAC) { @@ -1567,68 +1484,66 @@ static int ssi_mac_final(struct ahash_request *req) /* Setup DX request structure */ ssi_req.user_cb = (void *)ssi_hash_complete; ssi_req.user_arg = (void *)req; -#ifdef ENABLE_CYCLE_COUNT - ssi_req.op_type = STAT_OP_TYPE_ENCODE; /* Use "Encode" stats */ -#endif if (state->xcbc_count && (rem_cnt == 0)) { /* Load key for ECB decryption */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_ECB); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DRV_CRYPTO_DIRECTION_DECRYPT); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - (ctx->opad_tmp_keys_dma_addr + - XCBC_MAC_K1_OFFSET), - keySize, NS_BIT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], keyLen); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], DRV_CIPHER_ECB); + set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_DECRYPT); + set_din_type(&desc[idx], DMA_DLLI, + (ctx->opad_tmp_keys_dma_addr + + XCBC_MAC_K1_OFFSET), keySize, NS_BIT); + set_key_size_aes(&desc[idx], keyLen); + set_flow_mode(&desc[idx], S_DIN_to_AES); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); idx++; - /* Initiate decryption of block state to previous block_state-XOR-M[n] */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, CC_AES_BLOCK_SIZE, NS_BIT); - HW_DESC_SET_DOUT_DLLI(&desc[idx], state->digest_buff_dma_addr, CC_AES_BLOCK_SIZE, NS_BIT,0); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_AES_DOUT); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, + CC_AES_BLOCK_SIZE, NS_BIT); + set_dout_dlli(&desc[idx], state->digest_buff_dma_addr, + CC_AES_BLOCK_SIZE, NS_BIT, 0); + set_flow_mode(&desc[idx], DIN_AES_DOUT); idx++; /* Memory Barrier: wait for axi write to complete */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_NO_DMA(&desc[idx], 0, 0xfffff0); - HW_DESC_SET_DOUT_NO_DMA(&desc[idx], 0, 0, 1); + hw_desc_init(&desc[idx]); + set_din_no_dma(&desc[idx], 0, 0xfffff0); + set_dout_no_dma(&desc[idx], 0, 0, 1); idx++; } - - if (ctx->hw_mode == DRV_CIPHER_XCBC_MAC) { + + if (ctx->hw_mode == DRV_CIPHER_XCBC_MAC) ssi_hash_create_xcbc_setup(req, desc, &idx); - } else { + else ssi_hash_create_cmac_setup(req, desc, &idx); - } if (state->xcbc_count == 0) { - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], keyLen); - HW_DESC_SET_CMAC_SIZE0_MODE(&desc[idx]); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_key_size_aes(&desc[idx], keyLen); + set_cmac_size0_mode(&desc[idx]); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; } else if (rem_cnt > 0) { ssi_hash_create_data_desc(state, ctx, DIN_AES_DOUT, desc, false, &idx); } else { - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_CONST(&desc[idx], 0x00, CC_AES_BLOCK_SIZE); - HW_DESC_SET_FLOW_MODE(&desc[idx], DIN_AES_DOUT); + hw_desc_init(&desc[idx]); + set_din_const(&desc[idx], 0x00, CC_AES_BLOCK_SIZE); + set_flow_mode(&desc[idx], DIN_AES_DOUT); idx++; } - + /* Get final MAC result */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DOUT_DLLI(&desc[idx], state->digest_result_dma_addr, digestsize, NS_BIT, 1); /*TODO*/ - HW_DESC_SET_QUEUE_LAST_IND(&desc[idx]); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_AES_to_DOUT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); + hw_desc_init(&desc[idx]); + /* TODO */ + set_dout_dlli(&desc[idx], state->digest_result_dma_addr, + digestsize, NS_BIT, 1); + set_queue_last_ind(&desc[idx]); + set_flow_mode(&desc[idx], S_AES_to_DOUT); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); + set_cipher_mode(&desc[idx], ctx->hw_mode); idx++; rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); @@ -1647,11 +1562,11 @@ static int ssi_mac_finup(struct ahash_request *req) struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); struct device *dev = &ctx->drvdata->plat_dev->dev; struct ssi_crypto_req ssi_req = {}; - HwDesc_s desc[SSI_MAX_AHASH_SEQ_LEN]; + struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; int idx = 0; int rc = 0; - uint32_t key_len = 0; - uint32_t digestsize = crypto_ahash_digestsize(tfm); + u32 key_len = 0; + u32 digestsize = crypto_ahash_digestsize(tfm); SSI_LOG_DEBUG("===== finup xcbc(%d) ====\n", req->nbytes); CHECK_AND_RETURN_UPON_FIPS_ERROR(); @@ -1659,7 +1574,7 @@ static int ssi_mac_finup(struct ahash_request *req) SSI_LOG_DEBUG("No data to update. Call to fdx_mac_final \n"); return ssi_mac_final(req); } - + if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, req->src, req->nbytes, 1) != 0)) { SSI_LOG_ERR("map_ahash_request_final() failed\n"); return -ENOMEM; @@ -1672,9 +1587,6 @@ static int ssi_mac_finup(struct ahash_request *req) /* Setup DX request structure */ ssi_req.user_cb = (void *)ssi_hash_complete; ssi_req.user_arg = (void *)req; -#ifdef ENABLE_CYCLE_COUNT - ssi_req.op_type = STAT_OP_TYPE_ENCODE; /* Use "Encode" stats */ -#endif if (ctx->hw_mode == DRV_CIPHER_XCBC_MAC) { key_len = CC_AES_128_BIT_KEY_SIZE; @@ -1685,23 +1597,25 @@ static int ssi_mac_finup(struct ahash_request *req) } if (req->nbytes == 0) { - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], key_len); - HW_DESC_SET_CMAC_SIZE0_MODE(&desc[idx]); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_key_size_aes(&desc[idx], key_len); + set_cmac_size0_mode(&desc[idx]); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; } else { ssi_hash_create_data_desc(state, ctx, DIN_AES_DOUT, desc, false, &idx); } - + /* Get final MAC result */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DOUT_DLLI(&desc[idx], state->digest_result_dma_addr, digestsize, NS_BIT, 1); /*TODO*/ - HW_DESC_SET_QUEUE_LAST_IND(&desc[idx]); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_AES_to_DOUT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); + hw_desc_init(&desc[idx]); + /* TODO */ + set_dout_dlli(&desc[idx], state->digest_result_dma_addr, + digestsize, NS_BIT, 1); + set_queue_last_ind(&desc[idx]); + set_flow_mode(&desc[idx], S_AES_to_DOUT); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); + set_cipher_mode(&desc[idx], ctx->hw_mode); idx++; rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); @@ -1719,16 +1633,16 @@ static int ssi_mac_digest(struct ahash_request *req) struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); struct device *dev = &ctx->drvdata->plat_dev->dev; - uint32_t digestsize = crypto_ahash_digestsize(tfm); + u32 digestsize = crypto_ahash_digestsize(tfm); struct ssi_crypto_req ssi_req = {}; - HwDesc_s desc[SSI_MAX_AHASH_SEQ_LEN]; - uint32_t keyLen; + struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN]; + u32 keyLen; int idx = 0; int rc; SSI_LOG_DEBUG("===== -digest mac (%d) ====\n", req->nbytes); CHECK_AND_RETURN_UPON_FIPS_ERROR(); - + if (unlikely(ssi_hash_map_request(dev, state, ctx) != 0)) { SSI_LOG_ERR("map_ahash_source() failed\n"); return -ENOMEM; @@ -1742,15 +1656,11 @@ static int ssi_mac_digest(struct ahash_request *req) SSI_LOG_ERR("map_ahash_request_final() failed\n"); return -ENOMEM; } - + /* Setup DX request structure */ ssi_req.user_cb = (void *)ssi_hash_digest_complete; ssi_req.user_arg = (void *)req; -#ifdef ENABLE_CYCLE_COUNT - ssi_req.op_type = STAT_OP_TYPE_ENCODE; /* Use "Encode" stats */ -#endif - if (ctx->hw_mode == DRV_CIPHER_XCBC_MAC) { keyLen = CC_AES_128_BIT_KEY_SIZE; ssi_hash_create_xcbc_setup(req, desc, &idx); @@ -1760,24 +1670,25 @@ static int ssi_mac_digest(struct ahash_request *req) } if (req->nbytes == 0) { - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], keyLen); - HW_DESC_SET_CMAC_SIZE0_MODE(&desc[idx]); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_cipher_mode(&desc[idx], ctx->hw_mode); + set_key_size_aes(&desc[idx], keyLen); + set_cmac_size0_mode(&desc[idx]); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; } else { ssi_hash_create_data_desc(state, ctx, DIN_AES_DOUT, desc, false, &idx); } - + /* Get final MAC result */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DOUT_DLLI(&desc[idx], state->digest_result_dma_addr, CC_AES_BLOCK_SIZE, NS_BIT,1); - HW_DESC_SET_QUEUE_LAST_IND(&desc[idx]); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_AES_to_DOUT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_WRITE_STATE0); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx],DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_CIPHER_MODE(&desc[idx], ctx->hw_mode); + hw_desc_init(&desc[idx]); + set_dout_dlli(&desc[idx], state->digest_result_dma_addr, + CC_AES_BLOCK_SIZE, NS_BIT, 1); + set_queue_last_ind(&desc[idx]); + set_flow_mode(&desc[idx], S_AES_to_DOUT); + set_setup_mode(&desc[idx], SETUP_WRITE_STATE0); + set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_cipher_mode(&desc[idx], ctx->hw_mode); idx++; rc = send_request(ctx->drvdata, &ssi_req, desc, idx, 1); @@ -1790,108 +1701,14 @@ static int ssi_mac_digest(struct ahash_request *req) return rc; } -//shash wrap functions -#ifdef SYNC_ALGS -static int ssi_shash_digest(struct shash_desc *desc, - const u8 *data, unsigned int len, u8 *out) -{ - struct ahash_req_ctx *state = shash_desc_ctx(desc); - struct crypto_shash *tfm = desc->tfm; - struct ssi_hash_ctx *ctx = crypto_shash_ctx(tfm); - uint32_t digestsize = crypto_shash_digestsize(tfm); - struct scatterlist src; - - if (len == 0) { - return ssi_hash_digest(state, ctx, digestsize, NULL, 0, out, NULL); - } - - /* sg_init_one may crash when len is 0 (depends on kernel configuration) */ - sg_init_one(&src, (const void *)data, len); - - return ssi_hash_digest(state, ctx, digestsize, &src, len, out, NULL); -} - -static int ssi_shash_update(struct shash_desc *desc, - const u8 *data, unsigned int len) -{ - struct ahash_req_ctx *state = shash_desc_ctx(desc); - struct crypto_shash *tfm = desc->tfm; - struct ssi_hash_ctx *ctx = crypto_shash_ctx(tfm); - uint32_t blocksize = crypto_tfm_alg_blocksize(&tfm->base); - struct scatterlist src; - - sg_init_one(&src, (const void *)data, len); - - return ssi_hash_update(state, ctx, blocksize, &src, len, NULL); -} - -static int ssi_shash_finup(struct shash_desc *desc, - const u8 *data, unsigned int len, u8 *out) -{ - struct ahash_req_ctx *state = shash_desc_ctx(desc); - struct crypto_shash *tfm = desc->tfm; - struct ssi_hash_ctx *ctx = crypto_shash_ctx(tfm); - uint32_t digestsize = crypto_shash_digestsize(tfm); - struct scatterlist src; - - sg_init_one(&src, (const void *)data, len); - - return ssi_hash_finup(state, ctx, digestsize, &src, len, out, NULL); -} - -static int ssi_shash_final(struct shash_desc *desc, u8 *out) -{ - struct ahash_req_ctx *state = shash_desc_ctx(desc); - struct crypto_shash *tfm = desc->tfm; - struct ssi_hash_ctx *ctx = crypto_shash_ctx(tfm); - uint32_t digestsize = crypto_shash_digestsize(tfm); - - return ssi_hash_final(state, ctx, digestsize, NULL, 0, out, NULL); -} - -static int ssi_shash_init(struct shash_desc *desc) -{ - struct ahash_req_ctx *state = shash_desc_ctx(desc); - struct crypto_shash *tfm = desc->tfm; - struct ssi_hash_ctx *ctx = crypto_shash_ctx(tfm); - - return ssi_hash_init(state, ctx); -} - -#ifdef EXPORT_FIXED -static int ssi_shash_export(struct shash_desc *desc, void *out) -{ - struct crypto_shash *tfm = desc->tfm; - struct ssi_hash_ctx *ctx = crypto_shash_ctx(tfm); - - return ssi_hash_export(ctx, out); -} - -static int ssi_shash_import(struct shash_desc *desc, const void *in) -{ - struct crypto_shash *tfm = desc->tfm; - struct ssi_hash_ctx *ctx = crypto_shash_ctx(tfm); - - return ssi_hash_import(ctx, in); -} -#endif - -static int ssi_shash_setkey(struct crypto_shash *tfm, - const u8 *key, unsigned int keylen) -{ - return ssi_hash_setkey((void *) tfm, key, keylen, true); -} - -#endif /* SYNC_ALGS */ - //ahash wrap functions static int ssi_ahash_digest(struct ahash_request *req) { struct ahash_req_ctx *state = ahash_request_ctx(req); struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); - uint32_t digestsize = crypto_ahash_digestsize(tfm); - + u32 digestsize = crypto_ahash_digestsize(tfm); + return ssi_hash_digest(state, ctx, digestsize, req->src, req->nbytes, req->result, (void *)req); } @@ -1901,7 +1718,7 @@ static int ssi_ahash_update(struct ahash_request *req) struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); unsigned int block_size = crypto_tfm_alg_blocksize(&tfm->base); - + return ssi_hash_update(state, ctx, block_size, req->src, req->nbytes, (void *)req); } @@ -1910,8 +1727,8 @@ static int ssi_ahash_finup(struct ahash_request *req) struct ahash_req_ctx *state = ahash_request_ctx(req); struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); - uint32_t digestsize = crypto_ahash_digestsize(tfm); - + u32 digestsize = crypto_ahash_digestsize(tfm); + return ssi_hash_finup(state, ctx, digestsize, req->src, req->nbytes, req->result, (void *)req); } @@ -1920,8 +1737,8 @@ static int ssi_ahash_final(struct ahash_request *req) struct ahash_req_ctx *state = ahash_request_ctx(req); struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); - uint32_t digestsize = crypto_ahash_digestsize(tfm); - + u32 digestsize = crypto_ahash_digestsize(tfm); + return ssi_hash_final(state, ctx, digestsize, req->src, req->nbytes, req->result, (void *)req); } @@ -1929,81 +1746,161 @@ static int ssi_ahash_init(struct ahash_request *req) { struct ahash_req_ctx *state = ahash_request_ctx(req); struct crypto_ahash *tfm = crypto_ahash_reqtfm(req); - struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); + struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); SSI_LOG_DEBUG("===== init (%d) ====\n", req->nbytes); return ssi_hash_init(state, ctx); } -#ifdef EXPORT_FIXED static int ssi_ahash_export(struct ahash_request *req, void *out) { struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); struct ssi_hash_ctx *ctx = crypto_ahash_ctx(ahash); - - return ssi_hash_export(ctx, out); + struct device *dev = &ctx->drvdata->plat_dev->dev; + struct ahash_req_ctx *state = ahash_request_ctx(req); + u8 *curr_buff = state->buff_index ? state->buff1 : state->buff0; + u32 curr_buff_cnt = state->buff_index ? state->buff1_cnt : + state->buff0_cnt; + const u32 tmp = CC_EXPORT_MAGIC; + + CHECK_AND_RETURN_UPON_FIPS_ERROR(); + + memcpy(out, &tmp, sizeof(u32)); + out += sizeof(u32); + + dma_sync_single_for_cpu(dev, state->digest_buff_dma_addr, + ctx->inter_digestsize, DMA_BIDIRECTIONAL); + memcpy(out, state->digest_buff, ctx->inter_digestsize); + out += ctx->inter_digestsize; + + if (state->digest_bytes_len_dma_addr) { + dma_sync_single_for_cpu(dev, state->digest_bytes_len_dma_addr, + HASH_LEN_SIZE, DMA_BIDIRECTIONAL); + memcpy(out, state->digest_bytes_len, HASH_LEN_SIZE); + } else { + /* Poison the unused exported digest len field. */ + memset(out, 0x5F, HASH_LEN_SIZE); + } + out += HASH_LEN_SIZE; + + memcpy(out, &curr_buff_cnt, sizeof(u32)); + out += sizeof(u32); + + memcpy(out, curr_buff, curr_buff_cnt); + + /* No sync for device ineeded since we did not change the data, + * we only copy it + */ + + return 0; } static int ssi_ahash_import(struct ahash_request *req, const void *in) { struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); struct ssi_hash_ctx *ctx = crypto_ahash_ctx(ahash); - - return ssi_hash_import(ctx, in); + struct device *dev = &ctx->drvdata->plat_dev->dev; + struct ahash_req_ctx *state = ahash_request_ctx(req); + u32 tmp; + int rc; + + CHECK_AND_RETURN_UPON_FIPS_ERROR(); + + memcpy(&tmp, in, sizeof(u32)); + if (tmp != CC_EXPORT_MAGIC) { + rc = -EINVAL; + goto out; + } + in += sizeof(u32); + + rc = ssi_hash_init(state, ctx); + if (rc) + goto out; + + dma_sync_single_for_cpu(dev, state->digest_buff_dma_addr, + ctx->inter_digestsize, DMA_BIDIRECTIONAL); + memcpy(state->digest_buff, in, ctx->inter_digestsize); + in += ctx->inter_digestsize; + + if (state->digest_bytes_len_dma_addr) { + dma_sync_single_for_cpu(dev, state->digest_bytes_len_dma_addr, + HASH_LEN_SIZE, DMA_BIDIRECTIONAL); + memcpy(state->digest_bytes_len, in, HASH_LEN_SIZE); + } + in += HASH_LEN_SIZE; + + dma_sync_single_for_device(dev, state->digest_buff_dma_addr, + ctx->inter_digestsize, DMA_BIDIRECTIONAL); + + if (state->digest_bytes_len_dma_addr) + dma_sync_single_for_device(dev, + state->digest_bytes_len_dma_addr, + HASH_LEN_SIZE, DMA_BIDIRECTIONAL); + + state->buff_index = 0; + + /* Sanity check the data as much as possible */ + memcpy(&tmp, in, sizeof(u32)); + if (tmp > SSI_MAX_HASH_BLCK_SIZE) { + rc = -EINVAL; + goto out; + } + in += sizeof(u32); + + state->buff0_cnt = tmp; + memcpy(state->buff0, in, state->buff0_cnt); + +out: + return rc; } -#endif static int ssi_ahash_setkey(struct crypto_ahash *ahash, const u8 *key, unsigned int keylen) -{ - return ssi_hash_setkey((void *) ahash, key, keylen, false); +{ + return ssi_hash_setkey((void *)ahash, key, keylen, false); } struct ssi_hash_template { char name[CRYPTO_MAX_ALG_NAME]; char driver_name[CRYPTO_MAX_ALG_NAME]; - char hmac_name[CRYPTO_MAX_ALG_NAME]; - char hmac_driver_name[CRYPTO_MAX_ALG_NAME]; + char mac_name[CRYPTO_MAX_ALG_NAME]; + char mac_driver_name[CRYPTO_MAX_ALG_NAME]; unsigned int blocksize; bool synchronize; - union { - struct ahash_alg template_ahash; - struct shash_alg template_shash; - }; + struct ahash_alg template_ahash; int hash_mode; int hw_mode; int inter_digestsize; struct ssi_drvdata *drvdata; }; +#define CC_STATE_SIZE(_x) \ + ((_x) + HASH_LEN_SIZE + SSI_MAX_HASH_BLCK_SIZE + (2 * sizeof(u32))) + /* hash descriptors */ static struct ssi_hash_template driver_hash[] = { //Asynchronize hash template { .name = "sha1", .driver_name = "sha1-dx", - .hmac_name = "hmac(sha1)", - .hmac_driver_name = "hmac-sha1-dx", + .mac_name = "hmac(sha1)", + .mac_driver_name = "hmac-sha1-dx", .blocksize = SHA1_BLOCK_SIZE, .synchronize = false, - { - .template_ahash = { - .init = ssi_ahash_init, - .update = ssi_ahash_update, - .final = ssi_ahash_final, - .finup = ssi_ahash_finup, - .digest = ssi_ahash_digest, -#ifdef EXPORT_FIXED - .export = ssi_ahash_export, - .import = ssi_ahash_import, -#endif - .setkey = ssi_ahash_setkey, - .halg = { - .digestsize = SHA1_DIGEST_SIZE, - .statesize = sizeof(struct sha1_state), - }, - }, + .template_ahash = { + .init = ssi_ahash_init, + .update = ssi_ahash_update, + .final = ssi_ahash_final, + .finup = ssi_ahash_finup, + .digest = ssi_ahash_digest, + .export = ssi_ahash_export, + .import = ssi_ahash_import, + .setkey = ssi_ahash_setkey, + .halg = { + .digestsize = SHA1_DIGEST_SIZE, + .statesize = CC_STATE_SIZE(SHA1_DIGEST_SIZE), + }, }, .hash_mode = DRV_HASH_SHA1, .hw_mode = DRV_HASH_HW_SHA1, @@ -2012,27 +1909,22 @@ static struct ssi_hash_template driver_hash[] = { { .name = "sha256", .driver_name = "sha256-dx", - .hmac_name = "hmac(sha256)", - .hmac_driver_name = "hmac-sha256-dx", + .mac_name = "hmac(sha256)", + .mac_driver_name = "hmac-sha256-dx", .blocksize = SHA256_BLOCK_SIZE, - .synchronize = false, - { - .template_ahash = { - .init = ssi_ahash_init, - .update = ssi_ahash_update, - .final = ssi_ahash_final, - .finup = ssi_ahash_finup, - .digest = ssi_ahash_digest, -#ifdef EXPORT_FIXED - .export = ssi_ahash_export, - .import = ssi_ahash_import, -#endif - .setkey = ssi_ahash_setkey, - .halg = { - .digestsize = SHA256_DIGEST_SIZE, - .statesize = sizeof(struct sha256_state), - }, - }, + .template_ahash = { + .init = ssi_ahash_init, + .update = ssi_ahash_update, + .final = ssi_ahash_final, + .finup = ssi_ahash_finup, + .digest = ssi_ahash_digest, + .export = ssi_ahash_export, + .import = ssi_ahash_import, + .setkey = ssi_ahash_setkey, + .halg = { + .digestsize = SHA256_DIGEST_SIZE, + .statesize = CC_STATE_SIZE(SHA256_DIGEST_SIZE) + }, }, .hash_mode = DRV_HASH_SHA256, .hw_mode = DRV_HASH_HW_SHA256, @@ -2041,27 +1933,22 @@ static struct ssi_hash_template driver_hash[] = { { .name = "sha224", .driver_name = "sha224-dx", - .hmac_name = "hmac(sha224)", - .hmac_driver_name = "hmac-sha224-dx", + .mac_name = "hmac(sha224)", + .mac_driver_name = "hmac-sha224-dx", .blocksize = SHA224_BLOCK_SIZE, - .synchronize = false, - { - .template_ahash = { - .init = ssi_ahash_init, - .update = ssi_ahash_update, - .final = ssi_ahash_final, - .finup = ssi_ahash_finup, - .digest = ssi_ahash_digest, -#ifdef EXPORT_FIXED - .export = ssi_ahash_export, - .import = ssi_ahash_import, -#endif - .setkey = ssi_ahash_setkey, - .halg = { - .digestsize = SHA224_DIGEST_SIZE, - .statesize = sizeof(struct sha256_state), - }, - }, + .template_ahash = { + .init = ssi_ahash_init, + .update = ssi_ahash_update, + .final = ssi_ahash_final, + .finup = ssi_ahash_finup, + .digest = ssi_ahash_digest, + .export = ssi_ahash_export, + .import = ssi_ahash_import, + .setkey = ssi_ahash_setkey, + .halg = { + .digestsize = SHA224_DIGEST_SIZE, + .statesize = CC_STATE_SIZE(SHA224_DIGEST_SIZE), + }, }, .hash_mode = DRV_HASH_SHA224, .hw_mode = DRV_HASH_HW_SHA256, @@ -2071,27 +1958,22 @@ static struct ssi_hash_template driver_hash[] = { { .name = "sha384", .driver_name = "sha384-dx", - .hmac_name = "hmac(sha384)", - .hmac_driver_name = "hmac-sha384-dx", + .mac_name = "hmac(sha384)", + .mac_driver_name = "hmac-sha384-dx", .blocksize = SHA384_BLOCK_SIZE, - .synchronize = false, - { - .template_ahash = { - .init = ssi_ahash_init, - .update = ssi_ahash_update, - .final = ssi_ahash_final, - .finup = ssi_ahash_finup, - .digest = ssi_ahash_digest, -#ifdef EXPORT_FIXED - .export = ssi_ahash_export, - .import = ssi_ahash_import, -#endif - .setkey = ssi_ahash_setkey, - .halg = { - .digestsize = SHA384_DIGEST_SIZE, - .statesize = sizeof(struct sha512_state), - }, - }, + .template_ahash = { + .init = ssi_ahash_init, + .update = ssi_ahash_update, + .final = ssi_ahash_final, + .finup = ssi_ahash_finup, + .digest = ssi_ahash_digest, + .export = ssi_ahash_export, + .import = ssi_ahash_import, + .setkey = ssi_ahash_setkey, + .halg = { + .digestsize = SHA384_DIGEST_SIZE, + .statesize = CC_STATE_SIZE(SHA384_DIGEST_SIZE), + }, }, .hash_mode = DRV_HASH_SHA384, .hw_mode = DRV_HASH_HW_SHA512, @@ -2100,27 +1982,22 @@ static struct ssi_hash_template driver_hash[] = { { .name = "sha512", .driver_name = "sha512-dx", - .hmac_name = "hmac(sha512)", - .hmac_driver_name = "hmac-sha512-dx", + .mac_name = "hmac(sha512)", + .mac_driver_name = "hmac-sha512-dx", .blocksize = SHA512_BLOCK_SIZE, - .synchronize = false, - { - .template_ahash = { - .init = ssi_ahash_init, - .update = ssi_ahash_update, - .final = ssi_ahash_final, - .finup = ssi_ahash_finup, - .digest = ssi_ahash_digest, -#ifdef EXPORT_FIXED - .export = ssi_ahash_export, - .import = ssi_ahash_import, -#endif - .setkey = ssi_ahash_setkey, - .halg = { - .digestsize = SHA512_DIGEST_SIZE, - .statesize = sizeof(struct sha512_state), - }, - }, + .template_ahash = { + .init = ssi_ahash_init, + .update = ssi_ahash_update, + .final = ssi_ahash_final, + .finup = ssi_ahash_finup, + .digest = ssi_ahash_digest, + .export = ssi_ahash_export, + .import = ssi_ahash_import, + .setkey = ssi_ahash_setkey, + .halg = { + .digestsize = SHA512_DIGEST_SIZE, + .statesize = CC_STATE_SIZE(SHA512_DIGEST_SIZE), + }, }, .hash_mode = DRV_HASH_SHA512, .hw_mode = DRV_HASH_HW_SHA512, @@ -2130,54 +2007,44 @@ static struct ssi_hash_template driver_hash[] = { { .name = "md5", .driver_name = "md5-dx", - .hmac_name = "hmac(md5)", - .hmac_driver_name = "hmac-md5-dx", + .mac_name = "hmac(md5)", + .mac_driver_name = "hmac-md5-dx", .blocksize = MD5_HMAC_BLOCK_SIZE, - .synchronize = false, - { - .template_ahash = { - .init = ssi_ahash_init, - .update = ssi_ahash_update, - .final = ssi_ahash_final, - .finup = ssi_ahash_finup, - .digest = ssi_ahash_digest, -#ifdef EXPORT_FIXED - .export = ssi_ahash_export, - .import = ssi_ahash_import, -#endif - .setkey = ssi_ahash_setkey, - .halg = { - .digestsize = MD5_DIGEST_SIZE, - .statesize = sizeof(struct md5_state), - }, - }, + .template_ahash = { + .init = ssi_ahash_init, + .update = ssi_ahash_update, + .final = ssi_ahash_final, + .finup = ssi_ahash_finup, + .digest = ssi_ahash_digest, + .export = ssi_ahash_export, + .import = ssi_ahash_import, + .setkey = ssi_ahash_setkey, + .halg = { + .digestsize = MD5_DIGEST_SIZE, + .statesize = CC_STATE_SIZE(MD5_DIGEST_SIZE), + }, }, .hash_mode = DRV_HASH_MD5, .hw_mode = DRV_HASH_HW_MD5, .inter_digestsize = MD5_DIGEST_SIZE, }, { - .name = "xcbc(aes)", - .driver_name = "xcbc-aes-dx", + .mac_name = "xcbc(aes)", + .mac_driver_name = "xcbc-aes-dx", .blocksize = AES_BLOCK_SIZE, - .synchronize = false, - { - .template_ahash = { - .init = ssi_ahash_init, - .update = ssi_mac_update, - .final = ssi_mac_final, - .finup = ssi_mac_finup, - .digest = ssi_mac_digest, - .setkey = ssi_xcbc_setkey, -#ifdef EXPORT_FIXED - .export = ssi_ahash_export, - .import = ssi_ahash_import, -#endif - .halg = { - .digestsize = AES_BLOCK_SIZE, - .statesize = sizeof(struct aeshash_state), - }, - }, + .template_ahash = { + .init = ssi_ahash_init, + .update = ssi_mac_update, + .final = ssi_mac_final, + .finup = ssi_mac_finup, + .digest = ssi_mac_digest, + .setkey = ssi_xcbc_setkey, + .export = ssi_ahash_export, + .import = ssi_ahash_import, + .halg = { + .digestsize = AES_BLOCK_SIZE, + .statesize = CC_STATE_SIZE(AES_BLOCK_SIZE), + }, }, .hash_mode = DRV_HASH_NULL, .hw_mode = DRV_CIPHER_XCBC_MAC, @@ -2185,34 +2052,29 @@ static struct ssi_hash_template driver_hash[] = { }, #if SSI_CC_HAS_CMAC { - .name = "cmac(aes)", - .driver_name = "cmac-aes-dx", + .mac_name = "cmac(aes)", + .mac_driver_name = "cmac-aes-dx", .blocksize = AES_BLOCK_SIZE, - .synchronize = false, - { - .template_ahash = { - .init = ssi_ahash_init, - .update = ssi_mac_update, - .final = ssi_mac_final, - .finup = ssi_mac_finup, - .digest = ssi_mac_digest, - .setkey = ssi_cmac_setkey, -#ifdef EXPORT_FIXED - .export = ssi_ahash_export, - .import = ssi_ahash_import, -#endif - .halg = { - .digestsize = AES_BLOCK_SIZE, - .statesize = sizeof(struct aeshash_state), - }, - }, + .template_ahash = { + .init = ssi_ahash_init, + .update = ssi_mac_update, + .final = ssi_mac_final, + .finup = ssi_mac_finup, + .digest = ssi_mac_digest, + .setkey = ssi_cmac_setkey, + .export = ssi_ahash_export, + .import = ssi_ahash_import, + .halg = { + .digestsize = AES_BLOCK_SIZE, + .statesize = CC_STATE_SIZE(AES_BLOCK_SIZE), + }, }, .hash_mode = DRV_HASH_NULL, .hw_mode = DRV_CIPHER_CMAC, .inter_digestsize = AES_BLOCK_SIZE, }, #endif - + }; static struct ssi_hash_alg * @@ -2220,6 +2082,7 @@ ssi_hash_create_alg(struct ssi_hash_template *template, bool keyed) { struct ssi_hash_alg *t_crypto_alg; struct crypto_alg *alg; + struct ahash_alg *halg; t_crypto_alg = kzalloc(sizeof(struct ssi_hash_alg), GFP_KERNEL); if (!t_crypto_alg) { @@ -2227,27 +2090,17 @@ ssi_hash_create_alg(struct ssi_hash_template *template, bool keyed) return ERR_PTR(-ENOMEM); } - t_crypto_alg->synchronize = template->synchronize; - if (template->synchronize) { - struct shash_alg *halg; - t_crypto_alg->shash_alg = template->template_shash; - halg = &t_crypto_alg->shash_alg; - alg = &halg->base; - if (!keyed) halg->setkey = NULL; - } else { - struct ahash_alg *halg; - t_crypto_alg->ahash_alg = template->template_ahash; - halg = &t_crypto_alg->ahash_alg; - alg = &halg->halg.base; - if (!keyed) halg->setkey = NULL; - } + t_crypto_alg->ahash_alg = template->template_ahash; + halg = &t_crypto_alg->ahash_alg; + alg = &halg->halg.base; if (keyed) { snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", - template->hmac_name); + template->mac_name); snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", - template->hmac_driver_name); + template->mac_driver_name); } else { + halg->setkey = NULL; snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", template->name); snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s", @@ -2259,18 +2112,11 @@ ssi_hash_create_alg(struct ssi_hash_template *template, bool keyed) alg->cra_blocksize = template->blocksize; alg->cra_alignmask = 0; alg->cra_exit = ssi_hash_cra_exit; - - if (template->synchronize) { - alg->cra_init = ssi_shash_cra_init; - alg->cra_flags = CRYPTO_ALG_TYPE_SHASH | - CRYPTO_ALG_KERN_DRIVER_ONLY; - alg->cra_type = &crypto_shash_type; - } else { - alg->cra_init = ssi_ahash_cra_init; - alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_TYPE_AHASH | + + alg->cra_init = ssi_ahash_cra_init; + alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_TYPE_AHASH | CRYPTO_ALG_KERN_DRIVER_ONLY; - alg->cra_type = &crypto_ahash_type; - } + alg->cra_type = &crypto_ahash_type; t_crypto_alg->hash_mode = template->hash_mode; t_crypto_alg->hw_mode = template->hw_mode; @@ -2284,7 +2130,7 @@ int ssi_hash_init_sram_digest_consts(struct ssi_drvdata *drvdata) struct ssi_hash_handle *hash_handle = drvdata->hash_handle; ssi_sram_addr_t sram_buff_ofs = hash_handle->digest_len_sram_addr; unsigned int larval_seq_len = 0; - HwDesc_s larval_seq[CC_DIGEST_SIZE_MAX/sizeof(uint32_t)]; + struct cc_hw_desc larval_seq[CC_DIGEST_SIZE_MAX / sizeof(u32)]; int rc = 0; #if (DX_DEV_SHA_MAX > 256) int i; @@ -2351,15 +2197,15 @@ int ssi_hash_init_sram_digest_consts(struct ssi_drvdata *drvdata) #if (DX_DEV_SHA_MAX > 256) /* We are forced to swap each double-word larval before copying to sram */ for (i = 0; i < ARRAY_SIZE(sha384_init); i++) { - const uint32_t const0 = ((uint32_t *)((uint64_t *)&sha384_init[i]))[1]; - const uint32_t const1 = ((uint32_t *)((uint64_t *)&sha384_init[i]))[0]; + const u32 const0 = ((u32 *)((u64 *)&sha384_init[i]))[1]; + const u32 const1 = ((u32 *)((u64 *)&sha384_init[i]))[0]; ssi_sram_mgr_const2sram_desc(&const0, sram_buff_ofs, 1, larval_seq, &larval_seq_len); - sram_buff_ofs += sizeof(uint32_t); + sram_buff_ofs += sizeof(u32); ssi_sram_mgr_const2sram_desc(&const1, sram_buff_ofs, 1, larval_seq, &larval_seq_len); - sram_buff_ofs += sizeof(uint32_t); + sram_buff_ofs += sizeof(u32); } rc = send_request_init(drvdata, larval_seq, larval_seq_len); if (unlikely(rc != 0)) { @@ -2369,15 +2215,15 @@ int ssi_hash_init_sram_digest_consts(struct ssi_drvdata *drvdata) larval_seq_len = 0; for (i = 0; i < ARRAY_SIZE(sha512_init); i++) { - const uint32_t const0 = ((uint32_t *)((uint64_t *)&sha512_init[i]))[1]; - const uint32_t const1 = ((uint32_t *)((uint64_t *)&sha512_init[i]))[0]; + const u32 const0 = ((u32 *)((u64 *)&sha512_init[i]))[1]; + const u32 const1 = ((u32 *)((u64 *)&sha512_init[i]))[0]; ssi_sram_mgr_const2sram_desc(&const0, sram_buff_ofs, 1, larval_seq, &larval_seq_len); - sram_buff_ofs += sizeof(uint32_t); + sram_buff_ofs += sizeof(u32); ssi_sram_mgr_const2sram_desc(&const1, sram_buff_ofs, 1, larval_seq, &larval_seq_len); - sram_buff_ofs += sizeof(uint32_t); + sram_buff_ofs += sizeof(u32); } rc = send_request_init(drvdata, larval_seq, larval_seq_len); if (unlikely(rc != 0)) { @@ -2394,12 +2240,12 @@ int ssi_hash_alloc(struct ssi_drvdata *drvdata) { struct ssi_hash_handle *hash_handle; ssi_sram_addr_t sram_buff; - uint32_t sram_size_to_alloc; + u32 sram_size_to_alloc; int rc = 0; int alg; hash_handle = kzalloc(sizeof(struct ssi_hash_handle), GFP_KERNEL); - if (hash_handle == NULL) { + if (!hash_handle) { SSI_LOG_ERR("kzalloc failed to allocate %zu B\n", sizeof(struct ssi_hash_handle)); rc = -ENOMEM; @@ -2418,7 +2264,7 @@ int ssi_hash_alloc(struct ssi_drvdata *drvdata) sizeof(sha1_init) + sizeof(sha224_init) + sizeof(sha256_init); - + sram_buff = ssi_sram_mgr_alloc(drvdata, sram_size_to_alloc); if (sram_buff == NULL_SRAM_ADDR) { SSI_LOG_ERR("SRAM pool exhausted\n"); @@ -2441,41 +2287,33 @@ int ssi_hash_alloc(struct ssi_drvdata *drvdata) /* ahash registration */ for (alg = 0; alg < ARRAY_SIZE(driver_hash); alg++) { struct ssi_hash_alg *t_alg; - + int hw_mode = driver_hash[alg].hw_mode; + /* register hmac version */ + t_alg = ssi_hash_create_alg(&driver_hash[alg], true); + if (IS_ERR(t_alg)) { + rc = PTR_ERR(t_alg); + SSI_LOG_ERR("%s alg allocation failed\n", + driver_hash[alg].driver_name); + goto fail; + } + t_alg->drvdata = drvdata; - if ((((struct ssi_hash_template)driver_hash[alg]).hw_mode != DRV_CIPHER_XCBC_MAC) && - (((struct ssi_hash_template)driver_hash[alg]).hw_mode != DRV_CIPHER_CMAC)) { - t_alg = ssi_hash_create_alg(&driver_hash[alg], true); - if (IS_ERR(t_alg)) { - rc = PTR_ERR(t_alg); - SSI_LOG_ERR("%s alg allocation failed\n", - driver_hash[alg].driver_name); - goto fail; - } - t_alg->drvdata = drvdata; - - if (t_alg->synchronize) { - rc = crypto_register_shash(&t_alg->shash_alg); - if (unlikely(rc != 0)) { - SSI_LOG_ERR("%s alg registration failed\n", - t_alg->shash_alg.base.cra_driver_name); - kfree(t_alg); - goto fail; - } else - list_add_tail(&t_alg->entry, &hash_handle->hash_list); - } else { - rc = crypto_register_ahash(&t_alg->ahash_alg); - if (unlikely(rc != 0)) { - SSI_LOG_ERR("%s alg registration failed\n", - t_alg->ahash_alg.halg.base.cra_driver_name); - kfree(t_alg); - goto fail; - } else - list_add_tail(&t_alg->entry, &hash_handle->hash_list); - } + rc = crypto_register_ahash(&t_alg->ahash_alg); + if (unlikely(rc)) { + SSI_LOG_ERR("%s alg registration failed\n", + driver_hash[alg].driver_name); + kfree(t_alg); + goto fail; + } else { + list_add_tail(&t_alg->entry, + &hash_handle->hash_list); } + if ((hw_mode == DRV_CIPHER_XCBC_MAC) || + (hw_mode == DRV_CIPHER_CMAC)) + continue; + /* register hash version */ t_alg = ssi_hash_create_alg(&driver_hash[alg], false); if (IS_ERR(t_alg)) { @@ -2485,26 +2323,15 @@ int ssi_hash_alloc(struct ssi_drvdata *drvdata) goto fail; } t_alg->drvdata = drvdata; - - if (t_alg->synchronize) { - rc = crypto_register_shash(&t_alg->shash_alg); - if (unlikely(rc != 0)) { - SSI_LOG_ERR("%s alg registration failed\n", - t_alg->shash_alg.base.cra_driver_name); - kfree(t_alg); - goto fail; - } else - list_add_tail(&t_alg->entry, &hash_handle->hash_list); - + + rc = crypto_register_ahash(&t_alg->ahash_alg); + if (unlikely(rc)) { + SSI_LOG_ERR("%s alg registration failed\n", + driver_hash[alg].driver_name); + kfree(t_alg); + goto fail; } else { - rc = crypto_register_ahash(&t_alg->ahash_alg); - if (unlikely(rc != 0)) { - SSI_LOG_ERR("%s alg registration failed\n", - t_alg->ahash_alg.halg.base.cra_driver_name); - kfree(t_alg); - goto fail; - } else - list_add_tail(&t_alg->entry, &hash_handle->hash_list); + list_add_tail(&t_alg->entry, &hash_handle->hash_list); } } @@ -2512,7 +2339,7 @@ int ssi_hash_alloc(struct ssi_drvdata *drvdata) fail: - if (drvdata->hash_handle != NULL) { + if (drvdata->hash_handle) { kfree(drvdata->hash_handle); drvdata->hash_handle = NULL; } @@ -2524,26 +2351,21 @@ int ssi_hash_free(struct ssi_drvdata *drvdata) struct ssi_hash_alg *t_hash_alg, *hash_n; struct ssi_hash_handle *hash_handle = drvdata->hash_handle; - if (hash_handle != NULL) { - + if (hash_handle) { list_for_each_entry_safe(t_hash_alg, hash_n, &hash_handle->hash_list, entry) { - if (t_hash_alg->synchronize) { - crypto_unregister_shash(&t_hash_alg->shash_alg); - } else { - crypto_unregister_ahash(&t_hash_alg->ahash_alg); - } + crypto_unregister_ahash(&t_hash_alg->ahash_alg); list_del(&t_hash_alg->entry); kfree(t_hash_alg); } - + kfree(hash_handle); drvdata->hash_handle = NULL; } return 0; } -static void ssi_hash_create_xcbc_setup(struct ahash_request *areq, - HwDesc_s desc[], +static void ssi_hash_create_xcbc_setup(struct ahash_request *areq, + struct cc_hw_desc desc[], unsigned int *seq_size) { unsigned int idx = *seq_size; struct ahash_req_ctx *state = ahash_request_ctx(areq); @@ -2551,55 +2373,56 @@ static void ssi_hash_create_xcbc_setup(struct ahash_request *areq, struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); /* Setup XCBC MAC K1 */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, (ctx->opad_tmp_keys_dma_addr - + XCBC_MAC_K1_OFFSET), - CC_AES_128_BIT_KEY_SIZE, NS_BIT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_XCBC_MAC); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], CC_AES_128_BIT_KEY_SIZE); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, (ctx->opad_tmp_keys_dma_addr + + XCBC_MAC_K1_OFFSET), + CC_AES_128_BIT_KEY_SIZE, NS_BIT); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); + set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC); + set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; /* Setup XCBC MAC K2 */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, (ctx->opad_tmp_keys_dma_addr - + XCBC_MAC_K2_OFFSET), - CC_AES_128_BIT_KEY_SIZE, NS_BIT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE1); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_XCBC_MAC); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], CC_AES_128_BIT_KEY_SIZE); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, (ctx->opad_tmp_keys_dma_addr + + XCBC_MAC_K2_OFFSET), + CC_AES_128_BIT_KEY_SIZE, NS_BIT); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE1); + set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC); + set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; /* Setup XCBC MAC K3 */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, (ctx->opad_tmp_keys_dma_addr - + XCBC_MAC_K3_OFFSET), - CC_AES_128_BIT_KEY_SIZE, NS_BIT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE2); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_XCBC_MAC); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], CC_AES_128_BIT_KEY_SIZE); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, (ctx->opad_tmp_keys_dma_addr + + XCBC_MAC_K3_OFFSET), + CC_AES_128_BIT_KEY_SIZE, NS_BIT); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE2); + set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC); + set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; /* Loading MAC state */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, CC_AES_BLOCK_SIZE, NS_BIT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_XCBC_MAC); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], CC_AES_128_BIT_KEY_SIZE); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, + CC_AES_BLOCK_SIZE, NS_BIT); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); + set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC); + set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; *seq_size = idx; } -static void ssi_hash_create_cmac_setup(struct ahash_request *areq, - HwDesc_s desc[], +static void ssi_hash_create_cmac_setup(struct ahash_request *areq, + struct cc_hw_desc desc[], unsigned int *seq_size) { unsigned int idx = *seq_size; @@ -2608,24 +2431,26 @@ static void ssi_hash_create_cmac_setup(struct ahash_request *areq, struct ssi_hash_ctx *ctx = crypto_ahash_ctx(tfm); /* Setup CMAC Key */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, ctx->opad_tmp_keys_dma_addr, - ((ctx->key_params.keylen == 24) ? AES_MAX_KEY_SIZE : ctx->key_params.keylen), NS_BIT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_KEY0); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_CMAC); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], ctx->key_params.keylen); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, ctx->opad_tmp_keys_dma_addr, + ((ctx->key_params.keylen == 24) ? AES_MAX_KEY_SIZE : + ctx->key_params.keylen), NS_BIT); + set_setup_mode(&desc[idx], SETUP_LOAD_KEY0); + set_cipher_mode(&desc[idx], DRV_CIPHER_CMAC); + set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_key_size_aes(&desc[idx], ctx->key_params.keylen); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; /* Load MAC state */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, CC_AES_BLOCK_SIZE, NS_BIT); - HW_DESC_SET_SETUP_MODE(&desc[idx], SETUP_LOAD_STATE0); - HW_DESC_SET_CIPHER_MODE(&desc[idx], DRV_CIPHER_CMAC); - HW_DESC_SET_CIPHER_CONFIG0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_KEY_SIZE_AES(&desc[idx], ctx->key_params.keylen); - HW_DESC_SET_FLOW_MODE(&desc[idx], S_DIN_to_AES); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, state->digest_buff_dma_addr, + CC_AES_BLOCK_SIZE, NS_BIT); + set_setup_mode(&desc[idx], SETUP_LOAD_STATE0); + set_cipher_mode(&desc[idx], DRV_CIPHER_CMAC); + set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_key_size_aes(&desc[idx], ctx->key_params.keylen); + set_flow_mode(&desc[idx], S_DIN_to_AES); idx++; *seq_size = idx; } @@ -2633,18 +2458,18 @@ static void ssi_hash_create_cmac_setup(struct ahash_request *areq, static void ssi_hash_create_data_desc(struct ahash_req_ctx *areq_ctx, struct ssi_hash_ctx *ctx, unsigned int flow_mode, - HwDesc_s desc[], - bool is_not_last_data, + struct cc_hw_desc desc[], + bool is_not_last_data, unsigned int *seq_size) { unsigned int idx = *seq_size; if (likely(areq_ctx->data_dma_buf_type == SSI_DMA_BUF_DLLI)) { - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - sg_dma_address(areq_ctx->curr_sg), - areq_ctx->curr_sg->length, NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], flow_mode); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, + sg_dma_address(areq_ctx->curr_sg), + areq_ctx->curr_sg->length, NS_BIT); + set_flow_mode(&desc[idx], flow_mode); idx++; } else { if (areq_ctx->data_dma_buf_type == SSI_DMA_BUF_NULL) { @@ -2653,42 +2478,38 @@ static void ssi_hash_create_data_desc(struct ahash_req_ctx *areq_ctx, return; } /* bypass */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_DLLI, - areq_ctx->mlli_params.mlli_dma_addr, - areq_ctx->mlli_params.mlli_len, - NS_BIT); - HW_DESC_SET_DOUT_SRAM(&desc[idx], - ctx->drvdata->mlli_sram_addr, - areq_ctx->mlli_params.mlli_len); - HW_DESC_SET_FLOW_MODE(&desc[idx], BYPASS); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_DLLI, + areq_ctx->mlli_params.mlli_dma_addr, + areq_ctx->mlli_params.mlli_len, NS_BIT); + set_dout_sram(&desc[idx], ctx->drvdata->mlli_sram_addr, + areq_ctx->mlli_params.mlli_len); + set_flow_mode(&desc[idx], BYPASS); idx++; /* process */ - HW_DESC_INIT(&desc[idx]); - HW_DESC_SET_DIN_TYPE(&desc[idx], DMA_MLLI, - ctx->drvdata->mlli_sram_addr, - areq_ctx->mlli_nents, - NS_BIT); - HW_DESC_SET_FLOW_MODE(&desc[idx], flow_mode); + hw_desc_init(&desc[idx]); + set_din_type(&desc[idx], DMA_MLLI, + ctx->drvdata->mlli_sram_addr, + areq_ctx->mlli_nents, NS_BIT); + set_flow_mode(&desc[idx], flow_mode); idx++; } - if (is_not_last_data) { - HW_DESC_SET_DIN_NOT_LAST_INDICATION(&desc[idx-1]); - } + if (is_not_last_data) + set_din_not_last_indication(&desc[(idx - 1)]); /* return updated desc sequence size */ *seq_size = idx; } /*! - * Gets the address of the initial digest in SRAM + * Gets the address of the initial digest in SRAM * according to the given hash mode - * + * * \param drvdata * \param mode The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256 - * - * \return uint32_t The address of the inital digest in SRAM + * + * \return u32 The address of the inital digest in SRAM */ -ssi_sram_addr_t ssi_ahash_get_larval_digest_sram_addr(void *drvdata, uint32_t mode) +ssi_sram_addr_t ssi_ahash_get_larval_digest_sram_addr(void *drvdata, u32 mode) { struct ssi_drvdata *_drvdata = (struct ssi_drvdata *)drvdata; struct ssi_hash_handle *hash_handle = _drvdata->hash_handle; @@ -2734,7 +2555,7 @@ ssi_sram_addr_t ssi_ahash_get_larval_digest_sram_addr(void *drvdata, uint32_t mo } ssi_sram_addr_t -ssi_ahash_get_initial_digest_len_sram_addr(void *drvdata, uint32_t mode) +ssi_ahash_get_initial_digest_len_sram_addr(void *drvdata, u32 mode) { struct ssi_drvdata *_drvdata = (struct ssi_drvdata *)drvdata; struct ssi_hash_handle *hash_handle = _drvdata->hash_handle; diff --git a/drivers/staging/ccree/ssi_hash.h b/drivers/staging/ccree/ssi_hash.h index a2b076d3af72..2400e389d65a 100644 --- a/drivers/staging/ccree/ssi_hash.h +++ b/drivers/staging/ccree/ssi_hash.h @@ -1,21 +1,21 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ /* \file ssi_hash.h - ARM CryptoCell Hash Crypto API + * ARM CryptoCell Hash Crypto API */ #ifndef __SSI_HASH_H__ @@ -39,6 +39,8 @@ #define XCBC_MAC_K2_OFFSET 16 #define XCBC_MAC_K3_OFFSET 32 +#define CC_EXPORT_MAGIC 0xC2EE1070U + // this struct was taken from drivers/crypto/nx/nx-aes-xcbc.c and it is used for xcbc/cmac statesize struct aeshash_state { u8 state[AES_BLOCK_SIZE]; @@ -48,27 +50,27 @@ struct aeshash_state { /* ahash state */ struct ahash_req_ctx { - uint8_t* buff0; - uint8_t* buff1; - uint8_t* digest_result_buff; + u8 *buff0; + u8 *buff1; + u8 *digest_result_buff; struct async_gen_req_ctx gen_ctx; enum ssi_req_dma_buf_type data_dma_buf_type; - uint8_t *digest_buff; - uint8_t *opad_digest_buff; - uint8_t *digest_bytes_len; + u8 *digest_buff; + u8 *opad_digest_buff; + u8 *digest_bytes_len; dma_addr_t opad_digest_dma_addr; dma_addr_t digest_buff_dma_addr; dma_addr_t digest_bytes_len_dma_addr; dma_addr_t digest_result_dma_addr; - uint32_t buff0_cnt; - uint32_t buff1_cnt; - uint32_t buff_index; - uint32_t xcbc_count; /* count xcbc update operatations */ + u32 buff0_cnt; + u32 buff1_cnt; + u32 buff_index; + u32 xcbc_count; /* count xcbc update operatations */ struct scatterlist buff_sg[2]; struct scatterlist *curr_sg; - uint32_t in_nents; - uint32_t mlli_nents; - struct mlli_params mlli_params; + u32 in_nents; + u32 mlli_nents; + struct mlli_params mlli_params; }; int ssi_hash_alloc(struct ssi_drvdata *drvdata); @@ -77,25 +79,25 @@ int ssi_hash_free(struct ssi_drvdata *drvdata); /*! * Gets the initial digest length - * - * \param drvdata + * + * \param drvdata * \param mode The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256/SHA384/SHA512 - * - * \return uint32_t returns the address of the initial digest length in SRAM + * + * \return u32 returns the address of the initial digest length in SRAM */ ssi_sram_addr_t -ssi_ahash_get_initial_digest_len_sram_addr(void *drvdata, uint32_t mode); +ssi_ahash_get_initial_digest_len_sram_addr(void *drvdata, u32 mode); /*! - * Gets the address of the initial digest in SRAM + * Gets the address of the initial digest in SRAM * according to the given hash mode - * - * \param drvdata + * + * \param drvdata * \param mode The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256/SHA384/SHA512 - * - * \return uint32_t The address of the inital digest in SRAM + * + * \return u32 The address of the inital digest in SRAM */ -ssi_sram_addr_t ssi_ahash_get_larval_digest_sram_addr(void *drvdata, uint32_t mode); +ssi_sram_addr_t ssi_ahash_get_larval_digest_sram_addr(void *drvdata, u32 mode); #endif /*__SSI_HASH_H__*/ diff --git a/drivers/staging/ccree/ssi_ivgen.c b/drivers/staging/ccree/ssi_ivgen.c index f16f4692f404..5ff3368c04d9 100644 --- a/drivers/staging/ccree/ssi_ivgen.c +++ b/drivers/staging/ccree/ssi_ivgen.c @@ -1,15 +1,15 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ @@ -26,13 +26,14 @@ /* The max. size of pool *MUST* be <= SRAM total size */ #define SSI_IVPOOL_SIZE 1024 /* The first 32B fraction of pool are dedicated to the - next encryption "key" & "IV" for pool regeneration */ + * next encryption "key" & "IV" for pool regeneration + */ #define SSI_IVPOOL_META_SIZE (CC_AES_IV_SIZE + AES_KEYSIZE_128) #define SSI_IVPOOL_GEN_SEQ_LEN 4 /** - * struct ssi_ivgen_ctx -IV pool generation context - * @pool: the start address of the iv-pool resides in internal RAM + * struct ssi_ivgen_ctx -IV pool generation context + * @pool: the start address of the iv-pool resides in internal RAM * @ctr_key_dma: address of pool's encryption key material in internal RAM * @ctr_iv_dma: address of pool's counter iv in internal RAM * @next_iv_ofs: the offset to the next available IV in pool @@ -43,62 +44,62 @@ struct ssi_ivgen_ctx { ssi_sram_addr_t pool; ssi_sram_addr_t ctr_key; ssi_sram_addr_t ctr_iv; - uint32_t next_iv_ofs; - uint8_t *pool_meta; + u32 next_iv_ofs; + u8 *pool_meta; dma_addr_t pool_meta_dma; }; /*! - * Generates SSI_IVPOOL_SIZE of random bytes by + * Generates SSI_IVPOOL_SIZE of random bytes by * encrypting 0's using AES128-CTR. - * + * * \param ivgen iv-pool context * \param iv_seq IN/OUT array to the descriptors sequence - * \param iv_seq_len IN/OUT pointer to the sequence length + * \param iv_seq_len IN/OUT pointer to the sequence length */ static int ssi_ivgen_generate_pool( struct ssi_ivgen_ctx *ivgen_ctx, - HwDesc_s iv_seq[], + struct cc_hw_desc iv_seq[], unsigned int *iv_seq_len) { unsigned int idx = *iv_seq_len; - if ( (*iv_seq_len + SSI_IVPOOL_GEN_SEQ_LEN) > SSI_IVPOOL_SEQ_LEN) { + if ((*iv_seq_len + SSI_IVPOOL_GEN_SEQ_LEN) > SSI_IVPOOL_SEQ_LEN) { /* The sequence will be longer than allowed */ return -EINVAL; } /* Setup key */ - HW_DESC_INIT(&iv_seq[idx]); - HW_DESC_SET_DIN_SRAM(&iv_seq[idx], ivgen_ctx->ctr_key, AES_KEYSIZE_128); - HW_DESC_SET_SETUP_MODE(&iv_seq[idx], SETUP_LOAD_KEY0); - HW_DESC_SET_CIPHER_CONFIG0(&iv_seq[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_FLOW_MODE(&iv_seq[idx], S_DIN_to_AES); - HW_DESC_SET_KEY_SIZE_AES(&iv_seq[idx], CC_AES_128_BIT_KEY_SIZE); - HW_DESC_SET_CIPHER_MODE(&iv_seq[idx], DRV_CIPHER_CTR); + hw_desc_init(&iv_seq[idx]); + set_din_sram(&iv_seq[idx], ivgen_ctx->ctr_key, AES_KEYSIZE_128); + set_setup_mode(&iv_seq[idx], SETUP_LOAD_KEY0); + set_cipher_config0(&iv_seq[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_flow_mode(&iv_seq[idx], S_DIN_to_AES); + set_key_size_aes(&iv_seq[idx], CC_AES_128_BIT_KEY_SIZE); + set_cipher_mode(&iv_seq[idx], DRV_CIPHER_CTR); idx++; /* Setup cipher state */ - HW_DESC_INIT(&iv_seq[idx]); - HW_DESC_SET_DIN_SRAM(&iv_seq[idx], ivgen_ctx->ctr_iv, CC_AES_IV_SIZE); - HW_DESC_SET_CIPHER_CONFIG0(&iv_seq[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); - HW_DESC_SET_FLOW_MODE(&iv_seq[idx], S_DIN_to_AES); - HW_DESC_SET_SETUP_MODE(&iv_seq[idx], SETUP_LOAD_STATE1); - HW_DESC_SET_KEY_SIZE_AES(&iv_seq[idx], CC_AES_128_BIT_KEY_SIZE); - HW_DESC_SET_CIPHER_MODE(&iv_seq[idx], DRV_CIPHER_CTR); + hw_desc_init(&iv_seq[idx]); + set_din_sram(&iv_seq[idx], ivgen_ctx->ctr_iv, CC_AES_IV_SIZE); + set_cipher_config0(&iv_seq[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT); + set_flow_mode(&iv_seq[idx], S_DIN_to_AES); + set_setup_mode(&iv_seq[idx], SETUP_LOAD_STATE1); + set_key_size_aes(&iv_seq[idx], CC_AES_128_BIT_KEY_SIZE); + set_cipher_mode(&iv_seq[idx], DRV_CIPHER_CTR); idx++; /* Perform dummy encrypt to skip first block */ - HW_DESC_INIT(&iv_seq[idx]); - HW_DESC_SET_DIN_CONST(&iv_seq[idx], 0, CC_AES_IV_SIZE); - HW_DESC_SET_DOUT_SRAM(&iv_seq[idx], ivgen_ctx->pool, CC_AES_IV_SIZE); - HW_DESC_SET_FLOW_MODE(&iv_seq[idx], DIN_AES_DOUT); + hw_desc_init(&iv_seq[idx]); + set_din_const(&iv_seq[idx], 0, CC_AES_IV_SIZE); + set_dout_sram(&iv_seq[idx], ivgen_ctx->pool, CC_AES_IV_SIZE); + set_flow_mode(&iv_seq[idx], DIN_AES_DOUT); idx++; /* Generate IV pool */ - HW_DESC_INIT(&iv_seq[idx]); - HW_DESC_SET_DIN_CONST(&iv_seq[idx], 0, SSI_IVPOOL_SIZE); - HW_DESC_SET_DOUT_SRAM(&iv_seq[idx], ivgen_ctx->pool, SSI_IVPOOL_SIZE); - HW_DESC_SET_FLOW_MODE(&iv_seq[idx], DIN_AES_DOUT); + hw_desc_init(&iv_seq[idx]); + set_din_const(&iv_seq[idx], 0, SSI_IVPOOL_SIZE); + set_dout_sram(&iv_seq[idx], ivgen_ctx->pool, SSI_IVPOOL_SIZE); + set_flow_mode(&iv_seq[idx], DIN_AES_DOUT); idx++; *iv_seq_len = idx; /* Update sequence length */ @@ -110,17 +111,17 @@ static int ssi_ivgen_generate_pool( } /*! - * Generates the initial pool in SRAM. - * This function should be invoked when resuming DX driver. - * - * \param drvdata - * + * Generates the initial pool in SRAM. + * This function should be invoked when resuming DX driver. + * + * \param drvdata + * * \return int Zero for success, negative value otherwise. */ int ssi_ivgen_init_sram_pool(struct ssi_drvdata *drvdata) { struct ssi_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle; - HwDesc_s iv_seq[SSI_IVPOOL_SEQ_LEN]; + struct cc_hw_desc iv_seq[SSI_IVPOOL_SEQ_LEN]; unsigned int iv_seq_len = 0; int rc; @@ -132,40 +133,38 @@ int ssi_ivgen_init_sram_pool(struct ssi_drvdata *drvdata) ivgen_ctx->ctr_iv = ivgen_ctx->pool + AES_KEYSIZE_128; /* Copy initial enc. key and IV to SRAM at a single descriptor */ - HW_DESC_INIT(&iv_seq[iv_seq_len]); - HW_DESC_SET_DIN_TYPE(&iv_seq[iv_seq_len], DMA_DLLI, - ivgen_ctx->pool_meta_dma, SSI_IVPOOL_META_SIZE, - NS_BIT); - HW_DESC_SET_DOUT_SRAM(&iv_seq[iv_seq_len], ivgen_ctx->pool, - SSI_IVPOOL_META_SIZE); - HW_DESC_SET_FLOW_MODE(&iv_seq[iv_seq_len], BYPASS); + hw_desc_init(&iv_seq[iv_seq_len]); + set_din_type(&iv_seq[iv_seq_len], DMA_DLLI, ivgen_ctx->pool_meta_dma, + SSI_IVPOOL_META_SIZE, NS_BIT); + set_dout_sram(&iv_seq[iv_seq_len], ivgen_ctx->pool, + SSI_IVPOOL_META_SIZE); + set_flow_mode(&iv_seq[iv_seq_len], BYPASS); iv_seq_len++; /* Generate initial pool */ rc = ssi_ivgen_generate_pool(ivgen_ctx, iv_seq, &iv_seq_len); - if (unlikely(rc != 0)) { + if (unlikely(rc != 0)) return rc; - } + /* Fire-and-forget */ return send_request_init(drvdata, iv_seq, iv_seq_len); } /*! * Free iv-pool and ivgen context. - * - * \param drvdata + * + * \param drvdata */ void ssi_ivgen_fini(struct ssi_drvdata *drvdata) { struct ssi_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle; struct device *device = &(drvdata->plat_dev->dev); - if (ivgen_ctx == NULL) + if (!ivgen_ctx) return; - if (ivgen_ctx->pool_meta != NULL) { + if (ivgen_ctx->pool_meta) { memset(ivgen_ctx->pool_meta, 0, SSI_IVPOOL_META_SIZE); - SSI_RESTORE_DMA_ADDR_TO_48BIT(ivgen_ctx->pool_meta_dma); dma_free_coherent(device, SSI_IVPOOL_META_SIZE, ivgen_ctx->pool_meta, ivgen_ctx->pool_meta_dma); } @@ -177,11 +176,11 @@ void ssi_ivgen_fini(struct ssi_drvdata *drvdata) } /*! - * Allocates iv-pool and maps resources. - * This function generates the first IV pool. - * + * Allocates iv-pool and maps resources. + * This function generates the first IV pool. + * * \param drvdata Driver's private context - * + * * \return int Zero for success, negative value otherwise. */ int ssi_ivgen_init(struct ssi_drvdata *drvdata) @@ -209,8 +208,6 @@ int ssi_ivgen_init(struct ssi_drvdata *drvdata) rc = -ENOMEM; goto out; } - SSI_UPDATE_DMA_ADDR_TO_48BIT(ivgen_ctx->pool_meta_dma, - SSI_IVPOOL_META_SIZE); /* Allocate IV pool in SRAM */ ivgen_ctx->pool = ssi_sram_mgr_alloc(drvdata, SSI_IVPOOL_SIZE); if (ivgen_ctx->pool == NULL_SRAM_ADDR) { @@ -228,22 +225,22 @@ out: /*! * Acquires 16 Bytes IV from the iv-pool - * + * * \param drvdata Driver private context * \param iv_out_dma Array of physical IV out addresses * \param iv_out_dma_len Length of iv_out_dma array (additional elements of iv_out_dma array are ignore) - * \param iv_out_size May be 8 or 16 bytes long + * \param iv_out_size May be 8 or 16 bytes long * \param iv_seq IN/OUT array to the descriptors sequence - * \param iv_seq_len IN/OUT pointer to the sequence length - * - * \return int Zero for success, negative value otherwise. + * \param iv_seq_len IN/OUT pointer to the sequence length + * + * \return int Zero for success, negative value otherwise. */ int ssi_ivgen_getiv( struct ssi_drvdata *drvdata, dma_addr_t iv_out_dma[], unsigned int iv_out_dma_len, unsigned int iv_out_size, - HwDesc_s iv_seq[], + struct cc_hw_desc iv_seq[], unsigned int *iv_seq_len) { struct ssi_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle; @@ -254,34 +251,35 @@ int ssi_ivgen_getiv( (iv_out_size != CTR_RFC3686_IV_SIZE)) { return -EINVAL; } - if ( (iv_out_dma_len + 1) > SSI_IVPOOL_SEQ_LEN) { + if ((iv_out_dma_len + 1) > SSI_IVPOOL_SEQ_LEN) { /* The sequence will be longer than allowed */ return -EINVAL; } //check that number of generated IV is limited to max dma address iv buffer size - if ( iv_out_dma_len > SSI_MAX_IVGEN_DMA_ADDRESSES) { + if (iv_out_dma_len > SSI_MAX_IVGEN_DMA_ADDRESSES) { /* The sequence will be longer than allowed */ return -EINVAL; } for (t = 0; t < iv_out_dma_len; t++) { /* Acquire IV from pool */ - HW_DESC_INIT(&iv_seq[idx]); - HW_DESC_SET_DIN_SRAM(&iv_seq[idx], - ivgen_ctx->pool + ivgen_ctx->next_iv_ofs, - iv_out_size); - HW_DESC_SET_DOUT_DLLI(&iv_seq[idx], iv_out_dma[t], - iv_out_size, NS_BIT, 0); - HW_DESC_SET_FLOW_MODE(&iv_seq[idx], BYPASS); + hw_desc_init(&iv_seq[idx]); + set_din_sram(&iv_seq[idx], (ivgen_ctx->pool + + ivgen_ctx->next_iv_ofs), + iv_out_size); + set_dout_dlli(&iv_seq[idx], iv_out_dma[t], iv_out_size, + NS_BIT, 0); + set_flow_mode(&iv_seq[idx], BYPASS); idx++; } /* Bypass operation is proceeded by crypto sequence, hence must - * assure bypass-write-transaction by a memory barrier */ - HW_DESC_INIT(&iv_seq[idx]); - HW_DESC_SET_DIN_NO_DMA(&iv_seq[idx], 0, 0xfffff0); - HW_DESC_SET_DOUT_NO_DMA(&iv_seq[idx], 0, 0, 1); + * assure bypass-write-transaction by a memory barrier + */ + hw_desc_init(&iv_seq[idx]); + set_din_no_dma(&iv_seq[idx], 0, 0xfffff0); + set_dout_no_dma(&iv_seq[idx], 0, 0, 1); idx++; *iv_seq_len = idx; /* update seq length */ @@ -298,4 +296,3 @@ int ssi_ivgen_getiv( return 0; } - diff --git a/drivers/staging/ccree/ssi_ivgen.h b/drivers/staging/ccree/ssi_ivgen.h index bc69cd8ca418..961aea411cb3 100644 --- a/drivers/staging/ccree/ssi_ivgen.h +++ b/drivers/staging/ccree/ssi_ivgen.h @@ -1,15 +1,15 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ @@ -19,54 +19,53 @@ #include "cc_hw_queue_defs.h" - #define SSI_IVPOOL_SEQ_LEN 8 /*! - * Allocates iv-pool and maps resources. - * This function generates the first IV pool. - * + * Allocates iv-pool and maps resources. + * This function generates the first IV pool. + * * \param drvdata Driver's private context - * + * * \return int Zero for success, negative value otherwise. */ int ssi_ivgen_init(struct ssi_drvdata *drvdata); /*! * Free iv-pool and ivgen context. - * - * \param drvdata + * + * \param drvdata */ void ssi_ivgen_fini(struct ssi_drvdata *drvdata); /*! - * Generates the initial pool in SRAM. - * This function should be invoked when resuming DX driver. - * - * \param drvdata - * + * Generates the initial pool in SRAM. + * This function should be invoked when resuming DX driver. + * + * \param drvdata + * * \return int Zero for success, negative value otherwise. */ int ssi_ivgen_init_sram_pool(struct ssi_drvdata *drvdata); /*! * Acquires 16 Bytes IV from the iv-pool - * + * * \param drvdata Driver private context * \param iv_out_dma Array of physical IV out addresses * \param iv_out_dma_len Length of iv_out_dma array (additional elements of iv_out_dma array are ignore) - * \param iv_out_size May be 8 or 16 bytes long + * \param iv_out_size May be 8 or 16 bytes long * \param iv_seq IN/OUT array to the descriptors sequence - * \param iv_seq_len IN/OUT pointer to the sequence length - * - * \return int Zero for success, negative value otherwise. + * \param iv_seq_len IN/OUT pointer to the sequence length + * + * \return int Zero for success, negative value otherwise. */ int ssi_ivgen_getiv( struct ssi_drvdata *drvdata, dma_addr_t iv_out_dma[], unsigned int iv_out_dma_len, unsigned int iv_out_size, - HwDesc_s iv_seq[], + struct cc_hw_desc iv_seq[], unsigned int *iv_seq_len); #endif /*__SSI_IVGEN_H__*/ diff --git a/drivers/staging/ccree/ssi_pm.c b/drivers/staging/ccree/ssi_pm.c index dd399f28a68c..52a8ed579177 100644 --- a/drivers/staging/ccree/ssi_pm.c +++ b/drivers/staging/ccree/ssi_pm.c @@ -1,20 +1,19 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ - #include "ssi_config.h" #include <linux/kernel.h> #include <linux/platform_device.h> @@ -29,15 +28,12 @@ #include "ssi_ivgen.h" #include "ssi_hash.h" #include "ssi_pm.h" -#include "ssi_pm_ext.h" - -#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP) +#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) #define POWER_DOWN_ENABLE 0x01 #define POWER_DOWN_DISABLE 0x00 - int ssi_power_mgr_runtime_suspend(struct device *dev) { struct ssi_drvdata *drvdata = @@ -52,9 +48,7 @@ int ssi_power_mgr_runtime_suspend(struct device *dev) return rc; } fini_cc_regs(drvdata); - - /* Specific HW suspend code */ - ssi_pm_ext_hw_suspend(dev); + cc_clk_off(drvdata); return 0; } @@ -66,24 +60,28 @@ int ssi_power_mgr_runtime_resume(struct device *dev) SSI_LOG_DEBUG("ssi_power_mgr_runtime_resume , unset HOST_POWER_DOWN_EN\n"); WRITE_REGISTER(drvdata->cc_base + CC_REG_OFFSET(HOST_RGF, HOST_POWER_DOWN_EN), POWER_DOWN_DISABLE); - /* Specific HW resume code */ - ssi_pm_ext_hw_resume(dev); + + rc = cc_clk_on(drvdata); + if (rc) { + SSI_LOG_ERR("failed getting clock back on. We're toast.\n"); + return rc; + } rc = init_cc_regs(drvdata, false); - if (rc !=0) { - SSI_LOG_ERR("init_cc_regs (%x)\n",rc); + if (rc != 0) { + SSI_LOG_ERR("init_cc_regs (%x)\n", rc); return rc; } rc = ssi_request_mgr_runtime_resume_queue(drvdata); - if (rc !=0) { - SSI_LOG_ERR("ssi_request_mgr_runtime_resume_queue (%x)\n",rc); + if (rc != 0) { + SSI_LOG_ERR("ssi_request_mgr_runtime_resume_queue (%x)\n", rc); return rc; } /* must be after the queue resuming as it uses the HW queue*/ ssi_hash_init_sram_digest_consts(drvdata); - + ssi_ivgen_init_sram_pool(drvdata); return 0; } @@ -109,26 +107,22 @@ int ssi_power_mgr_runtime_put_suspend(struct device *dev) (struct ssi_drvdata *)dev_get_drvdata(dev))) { pm_runtime_mark_last_busy(dev); rc = pm_runtime_put_autosuspend(dev); - } - else { + } else { /* Something wrong happens*/ BUG(); } return rc; - } #endif - - int ssi_power_mgr_init(struct ssi_drvdata *drvdata) { int rc = 0; -#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP) +#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) struct platform_device *plat_dev = drvdata->plat_dev; /* must be before the enabling to avoid resdundent suspending */ - pm_runtime_set_autosuspend_delay(&plat_dev->dev,SSI_SUSPEND_TIMEOUT); + pm_runtime_set_autosuspend_delay(&plat_dev->dev, SSI_SUSPEND_TIMEOUT); pm_runtime_use_autosuspend(&plat_dev->dev); /* activate the PM module */ rc = pm_runtime_set_active(&plat_dev->dev); @@ -142,7 +136,7 @@ int ssi_power_mgr_init(struct ssi_drvdata *drvdata) void ssi_power_mgr_fini(struct ssi_drvdata *drvdata) { -#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP) +#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) struct platform_device *plat_dev = drvdata->plat_dev; pm_runtime_disable(&plat_dev->dev); diff --git a/drivers/staging/ccree/ssi_pm.h b/drivers/staging/ccree/ssi_pm.h index 516fc3f445a8..63673f60d2d8 100644 --- a/drivers/staging/ccree/ssi_pm.h +++ b/drivers/staging/ccree/ssi_pm.h @@ -1,38 +1,35 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ /* \file ssi_pm.h - */ + */ #ifndef __SSI_POWER_MGR_H__ #define __SSI_POWER_MGR_H__ - #include "ssi_config.h" #include "ssi_driver.h" - #define SSI_SUSPEND_TIMEOUT 3000 - int ssi_power_mgr_init(struct ssi_drvdata *drvdata); void ssi_power_mgr_fini(struct ssi_drvdata *drvdata); -#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP) +#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) int ssi_power_mgr_runtime_suspend(struct device *dev); int ssi_power_mgr_runtime_resume(struct device *dev); diff --git a/drivers/staging/ccree/ssi_pm_ext.c b/drivers/staging/ccree/ssi_pm_ext.c deleted file mode 100644 index f86bbab22073..000000000000 --- a/drivers/staging/ccree/ssi_pm_ext.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see <http://www.gnu.org/licenses/>. - */ - - -#include "ssi_config.h" -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/interrupt.h> -#include <crypto/ctr.h> -#include <linux/pm_runtime.h> -#include "ssi_driver.h" -#include "ssi_sram_mgr.h" -#include "ssi_pm_ext.h" - -/* -This function should suspend the HW (if possiable), It should be implemented by -the driver user. -The reference code clears the internal SRAM to imitate lose of state. -*/ -void ssi_pm_ext_hw_suspend(struct device *dev) -{ - struct ssi_drvdata *drvdata = - (struct ssi_drvdata *)dev_get_drvdata(dev); - unsigned int val; - void __iomem *cc_base = drvdata->cc_base; - unsigned int sram_addr = 0; - - CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, SRAM_ADDR), sram_addr); - - for (;sram_addr < SSI_CC_SRAM_SIZE ; sram_addr+=4) { - CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, SRAM_DATA), 0x0); - - do { - val = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, SRAM_DATA_READY)); - } while (!(val &0x1)); - } -} - -/* -This function should resume the HW (if possiable).It should be implemented by -the driver user. -*/ -void ssi_pm_ext_hw_resume(struct device *dev) -{ - return; -} - diff --git a/drivers/staging/ccree/ssi_pm_ext.h b/drivers/staging/ccree/ssi_pm_ext.h deleted file mode 100644 index b4e2795de29e..000000000000 --- a/drivers/staging/ccree/ssi_pm_ext.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see <http://www.gnu.org/licenses/>. - */ - -/* \file ssi_pm_ext.h - */ - -#ifndef __PM_EXT_H__ -#define __PM_EXT_H__ - - -#include "ssi_config.h" -#include "ssi_driver.h" - -void ssi_pm_ext_hw_suspend(struct device *dev); - -void ssi_pm_ext_hw_resume(struct device *dev); - - -#endif /*__POWER_MGR_H__*/ - diff --git a/drivers/staging/ccree/ssi_request_mgr.c b/drivers/staging/ccree/ssi_request_mgr.c index 8611adf3bb2e..46d9396f9ff9 100644 --- a/drivers/staging/ccree/ssi_request_mgr.c +++ b/drivers/staging/ccree/ssi_request_mgr.c @@ -1,15 +1,15 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ @@ -35,91 +35,22 @@ #define SSI_MAX_POLL_ITER 10 -#define AXIM_MON_BASE_OFFSET CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_COMP) - -#ifdef CC_CYCLE_COUNT - -#define MONITOR_CNTR_BIT 0 - -/** - * Monitor descriptor. - * Used to measure CC performance. - */ -#define INIT_CC_MONITOR_DESC(desc_p) \ -do { \ - HW_DESC_INIT(desc_p); \ - HW_DESC_SET_DIN_MONITOR_CNTR(desc_p); \ -} while (0) - -/** - * Try adding monitor descriptor BEFORE enqueuing sequence. - */ -#define CC_CYCLE_DESC_HEAD(cc_base_addr, desc_p, lock_p, is_monitored_p) \ -do { \ - if (!test_and_set_bit(MONITOR_CNTR_BIT, (lock_p))) { \ - enqueue_seq((cc_base_addr), (desc_p), 1); \ - *(is_monitored_p) = true; \ - } else { \ - *(is_monitored_p) = false; \ - } \ -} while (0) - -/** - * If CC_CYCLE_DESC_HEAD was successfully added: - * 1. Add memory barrier descriptor to ensure last AXI transaction. - * 2. Add monitor descriptor to sequence tail AFTER enqueuing sequence. - */ -#define CC_CYCLE_DESC_TAIL(cc_base_addr, desc_p, is_monitored) \ -do { \ - if ((is_monitored) == true) { \ - HwDesc_s barrier_desc; \ - HW_DESC_INIT(&barrier_desc); \ - HW_DESC_SET_DIN_NO_DMA(&barrier_desc, 0, 0xfffff0); \ - HW_DESC_SET_DOUT_NO_DMA(&barrier_desc, 0, 0, 1); \ - enqueue_seq((cc_base_addr), &barrier_desc, 1); \ - enqueue_seq((cc_base_addr), (desc_p), 1); \ - } \ -} while (0) - -/** - * Try reading CC monitor counter value upon sequence complete. - * Can only succeed if the lock_p is taken by the owner of the given request. - */ -#define END_CC_MONITOR_COUNT(cc_base_addr, stat_op_type, stat_phase, monitor_null_cycles, lock_p, is_monitored) \ -do { \ - uint32_t elapsed_cycles; \ - if ((is_monitored) == true) { \ - elapsed_cycles = READ_REGISTER((cc_base_addr) + CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_MEASURE_CNTR)); \ - clear_bit(MONITOR_CNTR_BIT, (lock_p)); \ - if (elapsed_cycles > 0) \ - update_cc_stat(stat_op_type, stat_phase, (elapsed_cycles - monitor_null_cycles)); \ - } \ -} while (0) - -#else /*CC_CYCLE_COUNT*/ - -#define INIT_CC_MONITOR_DESC(desc_p) do { } while (0) -#define CC_CYCLE_DESC_HEAD(cc_base_addr, desc_p, lock_p, is_monitored_p) do { } while (0) -#define CC_CYCLE_DESC_TAIL(cc_base_addr, desc_p, is_monitored) do { } while (0) -#define END_CC_MONITOR_COUNT(cc_base_addr, stat_op_type, stat_phase, monitor_null_cycles, lock_p, is_monitored) do { } while (0) -#endif /*CC_CYCLE_COUNT*/ - - struct ssi_request_mgr_handle { /* Request manager resources */ unsigned int hw_queue_size; /* HW capability */ unsigned int min_free_hw_slots; unsigned int max_used_sw_slots; struct ssi_crypto_req req_queue[MAX_REQUEST_QUEUE_SIZE]; - uint32_t req_queue_head; - uint32_t req_queue_tail; - uint32_t axi_completed; - uint32_t q_free_slots; + u32 req_queue_head; + u32 req_queue_tail; + u32 axi_completed; + u32 q_free_slots; spinlock_t hw_lock; - HwDesc_s compl_desc; - uint8_t *dummy_comp_buff; + struct cc_hw_desc compl_desc; + u8 *dummy_comp_buff; dma_addr_t dummy_comp_buff_dma; - HwDesc_s monitor_desc; + struct cc_hw_desc monitor_desc; + volatile unsigned long monitor_lock; #ifdef COMP_IN_WQ struct workqueue_struct *workq; @@ -127,7 +58,7 @@ struct ssi_request_mgr_handle { #else struct tasklet_struct comptask; #endif -#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP) +#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) bool is_runtime_suspended; #endif }; @@ -141,18 +72,17 @@ void request_mgr_fini(struct ssi_drvdata *drvdata) { struct ssi_request_mgr_handle *req_mgr_h = drvdata->request_mgr_handle; - if (req_mgr_h == NULL) + if (!req_mgr_h) return; /* Not allocated */ if (req_mgr_h->dummy_comp_buff_dma != 0) { - SSI_RESTORE_DMA_ADDR_TO_48BIT(req_mgr_h->dummy_comp_buff_dma); dma_free_coherent(&drvdata->plat_dev->dev, - sizeof(uint32_t), req_mgr_h->dummy_comp_buff, + sizeof(u32), req_mgr_h->dummy_comp_buff, req_mgr_h->dummy_comp_buff_dma); } SSI_LOG_DEBUG("max_used_hw_slots=%d\n", (req_mgr_h->hw_queue_size - - req_mgr_h->min_free_hw_slots) ); + req_mgr_h->min_free_hw_slots)); SSI_LOG_DEBUG("max_used_sw_slots=%d\n", req_mgr_h->max_used_sw_slots); #ifdef COMP_IN_WQ @@ -169,15 +99,11 @@ void request_mgr_fini(struct ssi_drvdata *drvdata) int request_mgr_init(struct ssi_drvdata *drvdata) { -#ifdef CC_CYCLE_COUNT - HwDesc_s monitor_desc[2]; - struct ssi_crypto_req monitor_req = {0}; -#endif struct ssi_request_mgr_handle *req_mgr_h; int rc = 0; - req_mgr_h = kzalloc(sizeof(struct ssi_request_mgr_handle),GFP_KERNEL); - if (req_mgr_h == NULL) { + req_mgr_h = kzalloc(sizeof(struct ssi_request_mgr_handle), GFP_KERNEL); + if (!req_mgr_h) { rc = -ENOMEM; goto req_mgr_init_err; } @@ -188,7 +114,7 @@ int request_mgr_init(struct ssi_drvdata *drvdata) #ifdef COMP_IN_WQ SSI_LOG_DEBUG("Initializing completion workqueue\n"); req_mgr_h->workq = create_singlethread_workqueue("arm_cc7x_wq"); - if (unlikely(req_mgr_h->workq == NULL)) { + if (unlikely(!req_mgr_h->workq)) { SSI_LOG_ERR("Failed creating work queue\n"); rc = -ENOMEM; goto req_mgr_init_err; @@ -210,45 +136,23 @@ int request_mgr_init(struct ssi_drvdata *drvdata) req_mgr_h->min_free_hw_slots = req_mgr_h->hw_queue_size; req_mgr_h->max_used_sw_slots = 0; - /* Allocate DMA word for "dummy" completion descriptor use */ req_mgr_h->dummy_comp_buff = dma_alloc_coherent(&drvdata->plat_dev->dev, - sizeof(uint32_t), &req_mgr_h->dummy_comp_buff_dma, GFP_KERNEL); + sizeof(u32), &req_mgr_h->dummy_comp_buff_dma, GFP_KERNEL); if (!req_mgr_h->dummy_comp_buff) { SSI_LOG_ERR("Not enough memory to allocate DMA (%zu) dropped " - "buffer\n", sizeof(uint32_t)); + "buffer\n", sizeof(u32)); rc = -ENOMEM; goto req_mgr_init_err; } - SSI_UPDATE_DMA_ADDR_TO_48BIT(req_mgr_h->dummy_comp_buff_dma, - sizeof(uint32_t)); /* Init. "dummy" completion descriptor */ - HW_DESC_INIT(&req_mgr_h->compl_desc); - HW_DESC_SET_DIN_CONST(&req_mgr_h->compl_desc, 0, sizeof(uint32_t)); - HW_DESC_SET_DOUT_DLLI(&req_mgr_h->compl_desc, - req_mgr_h->dummy_comp_buff_dma, - sizeof(uint32_t), NS_BIT, 1); - HW_DESC_SET_FLOW_MODE(&req_mgr_h->compl_desc, BYPASS); - HW_DESC_SET_QUEUE_LAST_IND(&req_mgr_h->compl_desc); - -#ifdef CC_CYCLE_COUNT - /* For CC-HW cycle performance trace */ - INIT_CC_MONITOR_DESC(&req_mgr_h->monitor_desc); - set_bit(MONITOR_CNTR_BIT, &req_mgr_h->monitor_lock); - monitor_desc[0] = req_mgr_h->monitor_desc; - monitor_desc[1] = req_mgr_h->monitor_desc; - - rc = send_request(drvdata, &monitor_req, monitor_desc, 2, 0); - if (unlikely(rc != 0)) - goto req_mgr_init_err; - - drvdata->monitor_null_cycles = READ_REGISTER(drvdata->cc_base + - CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_MEASURE_CNTR)); - SSI_LOG_ERR("Calibration time=0x%08x\n", drvdata->monitor_null_cycles); - - clear_bit(MONITOR_CNTR_BIT, &req_mgr_h->monitor_lock); -#endif + hw_desc_init(&req_mgr_h->compl_desc); + set_din_const(&req_mgr_h->compl_desc, 0, sizeof(u32)); + set_dout_dlli(&req_mgr_h->compl_desc, req_mgr_h->dummy_comp_buff_dma, + sizeof(u32), NS_BIT, 1); + set_flow_mode(&req_mgr_h->compl_desc, BYPASS); + set_queue_last_ind(&req_mgr_h->compl_desc); return 0; @@ -259,18 +163,18 @@ req_mgr_init_err: static inline void enqueue_seq( void __iomem *cc_base, - HwDesc_s seq[], unsigned int seq_len) + struct cc_hw_desc seq[], unsigned int seq_len) { int i; for (i = 0; i < seq_len; i++) { - writel_relaxed(seq[i].word[0], (volatile void __iomem *)(cc_base+CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0))); - writel_relaxed(seq[i].word[1], (volatile void __iomem *)(cc_base+CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0))); - writel_relaxed(seq[i].word[2], (volatile void __iomem *)(cc_base+CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0))); - writel_relaxed(seq[i].word[3], (volatile void __iomem *)(cc_base+CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0))); - writel_relaxed(seq[i].word[4], (volatile void __iomem *)(cc_base+CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0))); + writel_relaxed(seq[i].word[0], (volatile void __iomem *)(cc_base + CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0))); + writel_relaxed(seq[i].word[1], (volatile void __iomem *)(cc_base + CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0))); + writel_relaxed(seq[i].word[2], (volatile void __iomem *)(cc_base + CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0))); + writel_relaxed(seq[i].word[3], (volatile void __iomem *)(cc_base + CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0))); + writel_relaxed(seq[i].word[4], (volatile void __iomem *)(cc_base + CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0))); wmb(); - writel_relaxed(seq[i].word[5], (volatile void __iomem *)(cc_base+CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0))); + writel_relaxed(seq[i].word[5], (volatile void __iomem *)(cc_base + CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_WORD0))); #ifdef DX_DUMP_DESCS SSI_LOG_DEBUG("desc[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n", i, seq[i].word[0], seq[i].word[1], seq[i].word[2], seq[i].word[3], seq[i].word[4], seq[i].word[5]); @@ -279,62 +183,63 @@ static inline void enqueue_seq( } /*! - * Completion will take place if and only if user requested completion - * by setting "is_dout = 0" in send_request(). - * - * \param dev + * Completion will take place if and only if user requested completion + * by setting "is_dout = 0" in send_request(). + * + * \param dev * \param dx_compl_h The completion event to signal */ static void request_mgr_complete(struct device *dev, void *dx_compl_h, void __iomem *cc_base) { struct completion *this_compl = dx_compl_h; + complete(this_compl); } - static inline int request_mgr_queues_status_check( struct ssi_request_mgr_handle *req_mgr_h, void __iomem *cc_base, unsigned int total_seq_len) { unsigned long poll_queue; - - /* SW queue is checked only once as it will not - be chaned during the poll becasue the spinlock_bh - is held by the thread */ + + /* SW queue is checked only once as it will not + * be chaned during the poll becasue the spinlock_bh + * is held by the thread + */ if (unlikely(((req_mgr_h->req_queue_head + 1) & - (MAX_REQUEST_QUEUE_SIZE - 1)) == + (MAX_REQUEST_QUEUE_SIZE - 1)) == req_mgr_h->req_queue_tail)) { - SSI_LOG_ERR("SW FIFO is full. req_queue_head=%d sw_fifo_len=%d\n", + SSI_LOG_ERR("SW FIFO is full. req_queue_head=%d sw_fifo_len=%d\n", req_mgr_h->req_queue_head, MAX_REQUEST_QUEUE_SIZE); return -EBUSY; } - if ((likely(req_mgr_h->q_free_slots >= total_seq_len)) ) { + if ((likely(req_mgr_h->q_free_slots >= total_seq_len))) return 0; - } + /* Wait for space in HW queue. Poll constant num of iterations. */ - for (poll_queue =0; poll_queue < SSI_MAX_POLL_ITER ; poll_queue ++) { - req_mgr_h->q_free_slots = + for (poll_queue = 0; poll_queue < SSI_MAX_POLL_ITER ; poll_queue++) { + req_mgr_h->q_free_slots = CC_HAL_READ_REGISTER( CC_REG_OFFSET(CRY_KERNEL, DSCRPTR_QUEUE_CONTENT)); - if (unlikely(req_mgr_h->q_free_slots < + if (unlikely(req_mgr_h->q_free_slots < req_mgr_h->min_free_hw_slots)) { req_mgr_h->min_free_hw_slots = req_mgr_h->q_free_slots; } - if (likely (req_mgr_h->q_free_slots >= total_seq_len)) { + if (likely(req_mgr_h->q_free_slots >= total_seq_len)) { /* If there is enough place return */ return 0; } - SSI_LOG_DEBUG("HW FIFO is full. q_free_slots=%d total_seq_len=%d\n", + SSI_LOG_DEBUG("HW FIFO is full. q_free_slots=%d total_seq_len=%d\n", req_mgr_h->q_free_slots, total_seq_len); } /* No room in the HW queue try again later */ SSI_LOG_DEBUG("HW FIFO full, timeout. req_queue_head=%d " - "sw_fifo_len=%d q_free_slots=%d total_seq_len=%d\n", + "sw_fifo_len=%d q_free_slots=%d total_seq_len=%d\n", req_mgr_h->req_queue_head, MAX_REQUEST_QUEUE_SIZE, req_mgr_h->q_free_slots, @@ -344,38 +249,37 @@ static inline int request_mgr_queues_status_check( /*! * Enqueue caller request to crypto hardware. - * - * \param drvdata + * + * \param drvdata * \param ssi_req The request to enqueue * \param desc The crypto sequence * \param len The crypto sequence length - * \param is_dout If "true": completion is handled by the caller - * If "false": this function adds a dummy descriptor completion - * and waits upon completion signal. - * + * \param is_dout If "true": completion is handled by the caller + * If "false": this function adds a dummy descriptor completion + * and waits upon completion signal. + * * \return int Returns -EINPROGRESS if "is_dout=true"; "0" if "is_dout=false" */ int send_request( struct ssi_drvdata *drvdata, struct ssi_crypto_req *ssi_req, - HwDesc_s *desc, unsigned int len, bool is_dout) + struct cc_hw_desc *desc, unsigned int len, bool is_dout) { void __iomem *cc_base = drvdata->cc_base; struct ssi_request_mgr_handle *req_mgr_h = drvdata->request_mgr_handle; unsigned int used_sw_slots; unsigned int iv_seq_len = 0; unsigned int total_seq_len = len; /*initial sequence length*/ - HwDesc_s iv_seq[SSI_IVPOOL_SEQ_LEN]; + struct cc_hw_desc iv_seq[SSI_IVPOOL_SEQ_LEN]; int rc; unsigned int max_required_seq_len = (total_seq_len + ((ssi_req->ivgen_dma_addr_len == 0) ? 0 : - SSI_IVPOOL_SEQ_LEN ) + - ((is_dout == 0 )? 1 : 0)); - DECL_CYCLE_COUNT_RESOURCES; + SSI_IVPOOL_SEQ_LEN) + + ((is_dout == 0) ? 1 : 0)); -#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP) +#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) rc = ssi_power_mgr_runtime_get(&drvdata->plat_dev->dev); if (rc != 0) { - SSI_LOG_ERR("ssi_power_mgr_runtime_get returned %x\n",rc); + SSI_LOG_ERR("ssi_power_mgr_runtime_get returned %x\n", rc); return rc; } #endif @@ -384,21 +288,23 @@ int send_request( spin_lock_bh(&req_mgr_h->hw_lock); /* Check if there is enough place in the SW/HW queues - in case iv gen add the max size and in case of no dout add 1 - for the internal completion descriptor */ + * in case iv gen add the max size and in case of no dout add 1 + * for the internal completion descriptor + */ rc = request_mgr_queues_status_check(req_mgr_h, cc_base, max_required_seq_len); - if (likely(rc == 0 )) + if (likely(rc == 0)) /* There is enough place in the queue */ break; /* something wrong release the spinlock*/ spin_unlock_bh(&req_mgr_h->hw_lock); if (rc != -EAGAIN) { - /* Any error other than HW queue full - (SW queue is full) */ -#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP) + /* Any error other than HW queue full + * (SW queue is full) + */ +#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) ssi_power_mgr_runtime_put_suspend(&drvdata->plat_dev->dev); #endif return rc; @@ -409,7 +315,8 @@ int send_request( } while (1); /* Additional completion descriptor is needed incase caller did not - enabled any DLLI/MLLI DOUT bit in the given sequence */ + * enabled any DLLI/MLLI DOUT bit in the given sequence + */ if (!is_dout) { init_completion(&ssi_req->seq_compl); ssi_req->user_cb = request_mgr_complete; @@ -432,7 +339,7 @@ int send_request( if (unlikely(rc != 0)) { SSI_LOG_ERR("Failed to generate IV (rc=%d)\n", rc); spin_unlock_bh(&req_mgr_h->hw_lock); -#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP) +#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) ssi_power_mgr_runtime_put_suspend(&drvdata->plat_dev->dev); #endif return rc; @@ -440,18 +347,13 @@ int send_request( total_seq_len += iv_seq_len; } - - used_sw_slots = ((req_mgr_h->req_queue_head - req_mgr_h->req_queue_tail) & (MAX_REQUEST_QUEUE_SIZE-1)); - if (unlikely(used_sw_slots > req_mgr_h->max_used_sw_slots)) { + + used_sw_slots = ((req_mgr_h->req_queue_head - req_mgr_h->req_queue_tail) & (MAX_REQUEST_QUEUE_SIZE - 1)); + if (unlikely(used_sw_slots > req_mgr_h->max_used_sw_slots)) req_mgr_h->max_used_sw_slots = used_sw_slots; - } - - CC_CYCLE_DESC_HEAD(cc_base, &req_mgr_h->monitor_desc, - &req_mgr_h->monitor_lock, &ssi_req->is_monitored_p); /* Enqueue request - must be locked with HW lock*/ req_mgr_h->req_queue[req_mgr_h->req_queue_head] = *ssi_req; - START_CYCLE_COUNT_AT(req_mgr_h->req_queue[req_mgr_h->req_queue_head].submit_cycle); req_mgr_h->req_queue_head = (req_mgr_h->req_queue_head + 1) & (MAX_REQUEST_QUEUE_SIZE - 1); /* TODO: Use circ_buf.h ? */ @@ -462,13 +364,9 @@ int send_request( #endif /* STAT_PHASE_4: Push sequence */ - START_CYCLE_COUNT(); enqueue_seq(cc_base, iv_seq, iv_seq_len); enqueue_seq(cc_base, desc, len); enqueue_seq(cc_base, &req_mgr_h->compl_desc, (is_dout ? 0 : 1)); - END_CYCLE_COUNT(ssi_req->op_type, STAT_PHASE_4); - - CC_CYCLE_DESC_TAIL(cc_base, &req_mgr_h->monitor_desc, ssi_req->is_monitored_p); if (unlikely(req_mgr_h->q_free_slots < total_seq_len)) { /*This means that there was a problem with the resume*/ @@ -481,28 +379,29 @@ int send_request( if (!is_dout) { /* Wait upon sequence completion. - * Return "0" -Operation done successfully. */ - return wait_for_completion_interruptible(&ssi_req->seq_compl); + * Return "0" -Operation done successfully. + */ + wait_for_completion(&ssi_req->seq_compl); + return 0; } else { /* Operation still in process */ return -EINPROGRESS; } } - /*! * Enqueue caller request to crypto hardware during init process. * assume this function is not called in middle of a flow, * since we set QUEUE_LAST_IND flag in the last descriptor. - * - * \param drvdata + * + * \param drvdata * \param desc The crypto sequence * \param len The crypto sequence length - * + * * \return int Returns "0" upon success */ int send_request_init( - struct ssi_drvdata *drvdata, HwDesc_s *desc, unsigned int len) + struct ssi_drvdata *drvdata, struct cc_hw_desc *desc, unsigned int len) { void __iomem *cc_base = drvdata->cc_base; struct ssi_request_mgr_handle *req_mgr_h = drvdata->request_mgr_handle; @@ -511,10 +410,10 @@ int send_request_init( /* Wait for space in HW and SW FIFO. Poll for as much as FIFO_TIMEOUT. */ rc = request_mgr_queues_status_check(req_mgr_h, cc_base, total_seq_len); - if (unlikely(rc != 0 )) { + if (unlikely(rc != 0)) return rc; - } - HW_DESC_SET_QUEUE_LAST_IND(&desc[len-1]); + + set_queue_last_ind(&desc[(len - 1)]); enqueue_seq(cc_base, desc, len); @@ -526,10 +425,9 @@ int send_request_init( return 0; } - void complete_request(struct ssi_drvdata *drvdata) { - struct ssi_request_mgr_handle *request_mgr_handle = + struct ssi_request_mgr_handle *request_mgr_handle = drvdata->request_mgr_handle; #ifdef COMP_IN_WQ queue_delayed_work(request_mgr_handle->workq, &request_mgr_handle->compwork, 0); @@ -552,14 +450,13 @@ static void proc_completions(struct ssi_drvdata *drvdata) { struct ssi_crypto_req *ssi_req; struct platform_device *plat_dev = drvdata->plat_dev; - struct ssi_request_mgr_handle * request_mgr_handle = + struct ssi_request_mgr_handle *request_mgr_handle = drvdata->request_mgr_handle; -#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP) +#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) int rc = 0; #endif - DECL_CYCLE_COUNT_RESOURCES; - while(request_mgr_handle->axi_completed) { + while (request_mgr_handle->axi_completed) { request_mgr_handle->axi_completed--; /* Dequeue request */ @@ -569,9 +466,6 @@ static void proc_completions(struct ssi_drvdata *drvdata) } ssi_req = &request_mgr_handle->req_queue[request_mgr_handle->req_queue_tail]; - END_CYCLE_COUNT_AT(ssi_req->submit_cycle, ssi_req->op_type, STAT_PHASE_5); /* Seq. Comp. */ - END_CC_MONITOR_COUNT(drvdata->cc_base, ssi_req->op_type, STAT_PHASE_6, - drvdata->monitor_null_cycles, &request_mgr_handle->monitor_lock, ssi_req->is_monitored_p); #ifdef FLUSH_CACHE_ALL flush_cache_all(); @@ -580,116 +474,109 @@ static void proc_completions(struct ssi_drvdata *drvdata) #ifdef COMPLETION_DELAY /* Delay */ { - uint32_t axi_err; + u32 axi_err; int i; + SSI_LOG_INFO("Delay\n"); - for (i=0;i<1000000;i++) { + for (i = 0; i < 1000000; i++) axi_err = READ_REGISTER(drvdata->cc_base + CC_REG_OFFSET(CRY_KERNEL, AXIM_MON_ERR)); - } } #endif /* COMPLETION_DELAY */ - if (likely(ssi_req->user_cb != NULL)) { - START_CYCLE_COUNT(); + if (likely(ssi_req->user_cb)) ssi_req->user_cb(&plat_dev->dev, ssi_req->user_arg, drvdata->cc_base); - END_CYCLE_COUNT(STAT_OP_TYPE_GENERIC, STAT_PHASE_3); - } request_mgr_handle->req_queue_tail = (request_mgr_handle->req_queue_tail + 1) & (MAX_REQUEST_QUEUE_SIZE - 1); SSI_LOG_DEBUG("Dequeue request tail=%u\n", request_mgr_handle->req_queue_tail); SSI_LOG_DEBUG("Request completed. axi_completed=%d\n", request_mgr_handle->axi_completed); -#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP) +#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) rc = ssi_power_mgr_runtime_put_suspend(&plat_dev->dev); - if (rc != 0) { - SSI_LOG_ERR("Failed to set runtime suspension %d\n",rc); - } + if (rc != 0) + SSI_LOG_ERR("Failed to set runtime suspension %d\n", rc); #endif } } +static inline u32 cc_axi_comp_count(void __iomem *cc_base) +{ + /* The CC_HAL_READ_REGISTER macro implictly requires and uses + * a base MMIO register address variable named cc_base. + */ + return FIELD_GET(AXIM_MON_COMP_VALUE, + CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET)); +} + /* Deferred service handler, run as interrupt-fired tasklet */ static void comp_handler(unsigned long devarg) { struct ssi_drvdata *drvdata = (struct ssi_drvdata *)devarg; void __iomem *cc_base = drvdata->cc_base; - struct ssi_request_mgr_handle * request_mgr_handle = + struct ssi_request_mgr_handle *request_mgr_handle = drvdata->request_mgr_handle; - uint32_t irq; - - DECL_CYCLE_COUNT_RESOURCES; - - START_CYCLE_COUNT(); + u32 irq; irq = (drvdata->irq & SSI_COMP_IRQ_MASK); if (irq & SSI_COMP_IRQ_MASK) { /* To avoid the interrupt from firing as we unmask it, we clear it now */ CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_ICR), SSI_COMP_IRQ_MASK); - + /* Avoid race with above clear: Test completion counter once more */ - request_mgr_handle->axi_completed += CC_REG_FLD_GET(CRY_KERNEL, AXIM_MON_COMP, VALUE, - CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET)); - - /* ISR-to-Tasklet latency */ - if (request_mgr_handle->axi_completed) { - /* Only if actually reflects ISR-to-completion-handling latency, i.e., - not duplicate as a result of interrupt after AXIM_MON_ERR clear, before end of loop */ - END_CYCLE_COUNT_AT(drvdata->isr_exit_cycles, STAT_OP_TYPE_GENERIC, STAT_PHASE_1); - } - + request_mgr_handle->axi_completed += + cc_axi_comp_count(cc_base); + while (request_mgr_handle->axi_completed) { do { proc_completions(drvdata); - /* At this point (after proc_completions()), request_mgr_handle->axi_completed is always 0. - The following assignment was changed to = (previously was +=) to conform KW restrictions. */ - request_mgr_handle->axi_completed = CC_REG_FLD_GET(CRY_KERNEL, AXIM_MON_COMP, VALUE, - CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET)); + /* At this point (after proc_completions()), + * request_mgr_handle->axi_completed is 0. + */ + request_mgr_handle->axi_completed = + cc_axi_comp_count(cc_base); } while (request_mgr_handle->axi_completed > 0); - + /* To avoid the interrupt from firing as we unmask it, we clear it now */ CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_ICR), SSI_COMP_IRQ_MASK); - + /* Avoid race with above clear: Test completion counter once more */ - request_mgr_handle->axi_completed += CC_REG_FLD_GET(CRY_KERNEL, AXIM_MON_COMP, VALUE, - CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET)); + request_mgr_handle->axi_completed += + cc_axi_comp_count(cc_base); } - } /* after verifing that there is nothing to do, Unmask AXI completion interrupt */ - CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR), + CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR), CC_HAL_READ_REGISTER( CC_REG_OFFSET(HOST_RGF, HOST_IMR)) & ~irq); - END_CYCLE_COUNT(STAT_OP_TYPE_GENERIC, STAT_PHASE_2); } /* -resume the queue configuration - no need to take the lock as this happens inside -the spin lock protection -*/ -#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP) + * resume the queue configuration - no need to take the lock as this happens inside + * the spin lock protection + */ +#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) int ssi_request_mgr_runtime_resume_queue(struct ssi_drvdata *drvdata) { - struct ssi_request_mgr_handle * request_mgr_handle = drvdata->request_mgr_handle; + struct ssi_request_mgr_handle *request_mgr_handle = drvdata->request_mgr_handle; spin_lock_bh(&request_mgr_handle->hw_lock); request_mgr_handle->is_runtime_suspended = false; spin_unlock_bh(&request_mgr_handle->hw_lock); - return 0 ; + return 0; } /* -suspend the queue configuration. Since it is used for the runtime suspend -only verify that the queue can be suspended. -*/ + * suspend the queue configuration. Since it is used for the runtime suspend + * only verify that the queue can be suspended. + */ int ssi_request_mgr_runtime_suspend_queue(struct ssi_drvdata *drvdata) { - struct ssi_request_mgr_handle * request_mgr_handle = + struct ssi_request_mgr_handle *request_mgr_handle = drvdata->request_mgr_handle; - + /* lock the send_request */ spin_lock_bh(&request_mgr_handle->hw_lock); - if (request_mgr_handle->req_queue_head != + if (request_mgr_handle->req_queue_head != request_mgr_handle->req_queue_tail) { spin_unlock_bh(&request_mgr_handle->hw_lock); return -EBUSY; @@ -702,10 +589,10 @@ int ssi_request_mgr_runtime_suspend_queue(struct ssi_drvdata *drvdata) bool ssi_request_mgr_is_queue_runtime_suspend(struct ssi_drvdata *drvdata) { - struct ssi_request_mgr_handle * request_mgr_handle = + struct ssi_request_mgr_handle *request_mgr_handle = drvdata->request_mgr_handle; - return request_mgr_handle->is_runtime_suspended; + return request_mgr_handle->is_runtime_suspended; } #endif diff --git a/drivers/staging/ccree/ssi_request_mgr.h b/drivers/staging/ccree/ssi_request_mgr.h index c09339b566d0..bdbbf89e5367 100644 --- a/drivers/staging/ccree/ssi_request_mgr.h +++ b/drivers/staging/ccree/ssi_request_mgr.h @@ -1,21 +1,21 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ /* \file request_mgr.h - Request Manager + * Request Manager */ #ifndef __REQUEST_MGR_H__ @@ -27,29 +27,29 @@ int request_mgr_init(struct ssi_drvdata *drvdata); /*! * Enqueue caller request to crypto hardware. - * - * \param drvdata + * + * \param drvdata * \param ssi_req The request to enqueue * \param desc The crypto sequence * \param len The crypto sequence length - * \param is_dout If "true": completion is handled by the caller - * If "false": this function adds a dummy descriptor completion - * and waits upon completion signal. - * + * \param is_dout If "true": completion is handled by the caller + * If "false": this function adds a dummy descriptor completion + * and waits upon completion signal. + * * \return int Returns -EINPROGRESS if "is_dout=ture"; "0" if "is_dout=false" */ int send_request( struct ssi_drvdata *drvdata, struct ssi_crypto_req *ssi_req, - HwDesc_s *desc, unsigned int len, bool is_dout); + struct cc_hw_desc *desc, unsigned int len, bool is_dout); int send_request_init( - struct ssi_drvdata *drvdata, HwDesc_s *desc, unsigned int len); + struct ssi_drvdata *drvdata, struct cc_hw_desc *desc, unsigned int len); void complete_request(struct ssi_drvdata *drvdata); void request_mgr_fini(struct ssi_drvdata *drvdata); -#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP) +#if defined(CONFIG_PM_RUNTIME) || defined(CONFIG_PM_SLEEP) int ssi_request_mgr_runtime_resume_queue(struct ssi_drvdata *drvdata); int ssi_request_mgr_runtime_suspend_queue(struct ssi_drvdata *drvdata); diff --git a/drivers/staging/ccree/ssi_sram_mgr.c b/drivers/staging/ccree/ssi_sram_mgr.c index 50066e17d1d3..e05c0c13c2eb 100644 --- a/drivers/staging/ccree/ssi_sram_mgr.c +++ b/drivers/staging/ccree/ssi_sram_mgr.c @@ -1,15 +1,15 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ @@ -17,7 +17,6 @@ #include "ssi_driver.h" #include "ssi_sram_mgr.h" - /** * struct ssi_sram_mgr_ctx -Internal RAM context manager * @sram_free_offset: the offset to the non-allocated area @@ -26,10 +25,9 @@ struct ssi_sram_mgr_ctx { ssi_sram_addr_t sram_free_offset; }; - /** * ssi_sram_mgr_fini() - Cleanup SRAM pool. - * + * * @drvdata: Associated device driver context */ void ssi_sram_mgr_fini(struct ssi_drvdata *drvdata) @@ -37,17 +35,17 @@ void ssi_sram_mgr_fini(struct ssi_drvdata *drvdata) struct ssi_sram_mgr_ctx *smgr_ctx = drvdata->sram_mgr_handle; /* Free "this" context */ - if (smgr_ctx != NULL) { + if (smgr_ctx) { memset(smgr_ctx, 0, sizeof(struct ssi_sram_mgr_ctx)); kfree(smgr_ctx); } } /** - * ssi_sram_mgr_init() - Initializes SRAM pool. + * ssi_sram_mgr_init() - Initializes SRAM pool. * The pool starts right at the beginning of SRAM. * Returns zero for success, negative value otherwise. - * + * * @drvdata: Associated device driver context */ int ssi_sram_mgr_init(struct ssi_drvdata *drvdata) @@ -77,15 +75,15 @@ out: } /*! - * Allocated buffer from SRAM pool. - * Note: Caller is responsible to free the LAST allocated buffer. - * This function does not taking care of any fragmentation may occur - * by the order of calls to alloc/free. - * - * \param drvdata + * Allocated buffer from SRAM pool. + * Note: Caller is responsible to free the LAST allocated buffer. + * This function does not taking care of any fragmentation may occur + * by the order of calls to alloc/free. + * + * \param drvdata * \param size The requested bytes to allocate */ -ssi_sram_addr_t ssi_sram_mgr_alloc(struct ssi_drvdata *drvdata, uint32_t size) +ssi_sram_addr_t ssi_sram_mgr_alloc(struct ssi_drvdata *drvdata, u32 size) { struct ssi_sram_mgr_ctx *smgr_ctx = drvdata->sram_mgr_handle; ssi_sram_addr_t p; @@ -100,7 +98,7 @@ ssi_sram_addr_t ssi_sram_mgr_alloc(struct ssi_drvdata *drvdata, uint32_t size) size, smgr_ctx->sram_free_offset); return NULL_SRAM_ADDR; } - + p = smgr_ctx->sram_free_offset; smgr_ctx->sram_free_offset += size; SSI_LOG_DEBUG("Allocated %u B @ %u\n", size, (unsigned int)p); @@ -109,9 +107,9 @@ ssi_sram_addr_t ssi_sram_mgr_alloc(struct ssi_drvdata *drvdata, uint32_t size) /** * ssi_sram_mgr_const2sram_desc() - Create const descriptors sequence to - * set values in given array into SRAM. + * set values in given array into SRAM. * Note: each const value can't exceed word size. - * + * * @src: A pointer to array of words to set as consts. * @dst: The target SRAM buffer to set into * @nelements: The number of words in "src" array @@ -119,18 +117,18 @@ ssi_sram_addr_t ssi_sram_mgr_alloc(struct ssi_drvdata *drvdata, uint32_t size) * @seq_len: A pointer to the given IN/OUT sequence length */ void ssi_sram_mgr_const2sram_desc( - const uint32_t *src, ssi_sram_addr_t dst, + const u32 *src, ssi_sram_addr_t dst, unsigned int nelement, - HwDesc_s *seq, unsigned int *seq_len) + struct cc_hw_desc *seq, unsigned int *seq_len) { - uint32_t i; + u32 i; unsigned int idx = *seq_len; for (i = 0; i < nelement; i++, idx++) { - HW_DESC_INIT(&seq[idx]); - HW_DESC_SET_DIN_CONST(&seq[idx], src[i], sizeof(uint32_t)); - HW_DESC_SET_DOUT_SRAM(&seq[idx], dst + (i * sizeof(uint32_t)), sizeof(uint32_t)); - HW_DESC_SET_FLOW_MODE(&seq[idx], BYPASS); + hw_desc_init(&seq[idx]); + set_din_const(&seq[idx], src[i], sizeof(u32)); + set_dout_sram(&seq[idx], dst + (i * sizeof(u32)), sizeof(u32)); + set_flow_mode(&seq[idx], BYPASS); } *seq_len = idx; diff --git a/drivers/staging/ccree/ssi_sram_mgr.h b/drivers/staging/ccree/ssi_sram_mgr.h index d71fbaf9ac44..9ba1d59a0bae 100644 --- a/drivers/staging/ccree/ssi_sram_mgr.h +++ b/drivers/staging/ccree/ssi_sram_mgr.h @@ -1,15 +1,15 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ @@ -17,7 +17,6 @@ #ifndef __SSI_SRAM_MGR_H__ #define __SSI_SRAM_MGR_H__ - #ifndef SSI_CC_SRAM_SIZE #define SSI_CC_SRAM_SIZE 4096 #endif @@ -28,44 +27,44 @@ struct ssi_drvdata; * Address (offset) within CC internal SRAM */ -typedef uint64_t ssi_sram_addr_t; +typedef u64 ssi_sram_addr_t; #define NULL_SRAM_ADDR ((ssi_sram_addr_t)-1) /*! - * Initializes SRAM pool. - * The first X bytes of SRAM are reserved for ROM usage, hence, pool - * starts right after X bytes. - * - * \param drvdata - * + * Initializes SRAM pool. + * The first X bytes of SRAM are reserved for ROM usage, hence, pool + * starts right after X bytes. + * + * \param drvdata + * * \return int Zero for success, negative value otherwise. */ int ssi_sram_mgr_init(struct ssi_drvdata *drvdata); /*! * Uninits SRAM pool. - * - * \param drvdata + * + * \param drvdata */ void ssi_sram_mgr_fini(struct ssi_drvdata *drvdata); /*! - * Allocated buffer from SRAM pool. - * Note: Caller is responsible to free the LAST allocated buffer. - * This function does not taking care of any fragmentation may occur - * by the order of calls to alloc/free. - * - * \param drvdata + * Allocated buffer from SRAM pool. + * Note: Caller is responsible to free the LAST allocated buffer. + * This function does not taking care of any fragmentation may occur + * by the order of calls to alloc/free. + * + * \param drvdata * \param size The requested bytes to allocate */ -ssi_sram_addr_t ssi_sram_mgr_alloc(struct ssi_drvdata *drvdata, uint32_t size); +ssi_sram_addr_t ssi_sram_mgr_alloc(struct ssi_drvdata *drvdata, u32 size); /** * ssi_sram_mgr_const2sram_desc() - Create const descriptors sequence to - * set values in given array into SRAM. + * set values in given array into SRAM. * Note: each const value can't exceed word size. - * + * * @src: A pointer to array of words to set as consts. * @dst: The target SRAM buffer to set into * @nelements: The number of words in "src" array @@ -73,8 +72,8 @@ ssi_sram_addr_t ssi_sram_mgr_alloc(struct ssi_drvdata *drvdata, uint32_t size); * @seq_len: A pointer to the given IN/OUT sequence length */ void ssi_sram_mgr_const2sram_desc( - const uint32_t *src, ssi_sram_addr_t dst, + const u32 *src, ssi_sram_addr_t dst, unsigned int nelement, - HwDesc_s *seq, unsigned int *seq_len); + struct cc_hw_desc *seq, unsigned int *seq_len); #endif /*__SSI_SRAM_MGR_H__*/ diff --git a/drivers/staging/ccree/ssi_sysfs.c b/drivers/staging/ccree/ssi_sysfs.c index 7c514c1072a9..dbcd1634aad1 100644 --- a/drivers/staging/ccree/ssi_sysfs.c +++ b/drivers/staging/ccree/ssi_sysfs.c @@ -1,15 +1,15 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ @@ -40,7 +40,7 @@ struct stat_name { const char *stat_phase_name[MAX_STAT_PHASES]; }; -static struct stat_name stat_name_db[MAX_STAT_OP_TYPES] = +static struct stat_name stat_name_db[MAX_STAT_OP_TYPES] = { { /* STAT_OP_TYPE_NULL */ @@ -50,8 +50,8 @@ static struct stat_name stat_name_db[MAX_STAT_OP_TYPES] = { .op_type_name = "Encode", .stat_phase_name[STAT_PHASE_0] = "Init and sanity checks", - .stat_phase_name[STAT_PHASE_1] = "Map buffers", - .stat_phase_name[STAT_PHASE_2] = "Create sequence", + .stat_phase_name[STAT_PHASE_1] = "Map buffers", + .stat_phase_name[STAT_PHASE_2] = "Create sequence", .stat_phase_name[STAT_PHASE_3] = "Send Request", .stat_phase_name[STAT_PHASE_4] = "HW-Q push", .stat_phase_name[STAT_PHASE_5] = "Sequence completion", @@ -59,14 +59,14 @@ static struct stat_name stat_name_db[MAX_STAT_OP_TYPES] = }, { .op_type_name = "Decode", .stat_phase_name[STAT_PHASE_0] = "Init and sanity checks", - .stat_phase_name[STAT_PHASE_1] = "Map buffers", - .stat_phase_name[STAT_PHASE_2] = "Create sequence", + .stat_phase_name[STAT_PHASE_1] = "Map buffers", + .stat_phase_name[STAT_PHASE_2] = "Create sequence", .stat_phase_name[STAT_PHASE_3] = "Send Request", .stat_phase_name[STAT_PHASE_4] = "HW-Q push", .stat_phase_name[STAT_PHASE_5] = "Sequence completion", .stat_phase_name[STAT_PHASE_6] = "HW cycles", }, - { .op_type_name = "Setkey", + { .op_type_name = "Setkey", .stat_phase_name[STAT_PHASE_0] = "Init and sanity checks", .stat_phase_name[STAT_PHASE_1] = "Copy key to ctx", .stat_phase_name[STAT_PHASE_2] = "Create sequence", @@ -88,14 +88,14 @@ static struct stat_name stat_name_db[MAX_STAT_OP_TYPES] = }; /* - * Structure used to create a directory + * Structure used to create a directory * and its attributes in sysfs. */ struct sys_dir { struct kobject *sys_dir_kobj; struct attribute_group sys_dir_attr_group; struct attribute **sys_dir_attr_list; - uint32_t num_of_attrs; + u32 num_of_attrs; struct ssi_drvdata *drvdata; /* Associated driver context */ }; @@ -108,14 +108,13 @@ static DEFINE_SPINLOCK(stat_lock); static struct stat_item stat_host_db[MAX_STAT_OP_TYPES][MAX_STAT_PHASES]; static struct stat_item stat_cc_db[MAX_STAT_OP_TYPES][MAX_STAT_PHASES]; - static void init_db(struct stat_item item[MAX_STAT_OP_TYPES][MAX_STAT_PHASES]) { unsigned int i, j; /* Clear db */ - for (i=0; i<MAX_STAT_OP_TYPES; i++) { - for (j=0; j<MAX_STAT_PHASES; j++) { + for (i = 0; i < MAX_STAT_OP_TYPES; i++) { + for (j = 0; j < MAX_STAT_PHASES; j++) { item[i][j].min = 0xFFFFFFFF; item[i][j].max = 0; item[i][j].sum = 0; @@ -130,29 +129,28 @@ static void update_db(struct stat_item *item, unsigned int result) item->sum += result; if (result < item->min) item->min = result; - if (result > item->max ) + if (result > item->max) item->max = result; } static void display_db(struct stat_item item[MAX_STAT_OP_TYPES][MAX_STAT_PHASES]) { unsigned int i, j; - uint64_t avg; + u64 avg; - for (i=STAT_OP_TYPE_ENCODE; i<MAX_STAT_OP_TYPES; i++) { - for (j=0; j<MAX_STAT_PHASES; j++) { + for (i = STAT_OP_TYPE_ENCODE; i < MAX_STAT_OP_TYPES; i++) { + for (j = 0; j < MAX_STAT_PHASES; j++) { if (item[i][j].count > 0) { - avg = (uint64_t)item[i][j].sum; + avg = (u64)item[i][j].sum; do_div(avg, item[i][j].count); - SSI_LOG_ERR("%s, %s: min=%d avg=%d max=%d sum=%lld count=%d\n", - stat_name_db[i].op_type_name, stat_name_db[i].stat_phase_name[j], + SSI_LOG_ERR("%s, %s: min=%d avg=%d max=%d sum=%lld count=%d\n", + stat_name_db[i].op_type_name, stat_name_db[i].stat_phase_name[j], item[i][j].min, (int)avg, item[i][j].max, (long long)item[i][j].sum, item[i][j].count); } } } } - /************************************** * Attributes show functions section * **************************************/ @@ -174,38 +172,38 @@ static ssize_t ssi_sys_stats_cc_db_clear(struct kobject *kobj, static ssize_t ssi_sys_stat_host_db_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) { - int i, j ; + int i, j; char line[512]; - uint32_t min_cyc, max_cyc; - uint64_t avg; - ssize_t buf_len, tmp_len=0; + u32 min_cyc, max_cyc; + u64 avg; + ssize_t buf_len, tmp_len = 0; - buf_len = scnprintf(buf,PAGE_SIZE, + buf_len = scnprintf(buf, PAGE_SIZE, "phase\t\t\t\t\t\t\tmin[cy]\tavg[cy]\tmax[cy]\t#samples\n"); - if ( buf_len <0 )/* scnprintf shouldn't return negative value according to its implementation*/ + if (buf_len < 0)/* scnprintf shouldn't return negative value according to its implementation*/ return buf_len; - for (i=STAT_OP_TYPE_ENCODE; i<MAX_STAT_OP_TYPES; i++) { - for (j=0; j<MAX_STAT_PHASES-1; j++) { + for (i = STAT_OP_TYPE_ENCODE; i < MAX_STAT_OP_TYPES; i++) { + for (j = 0; j < MAX_STAT_PHASES - 1; j++) { if (stat_host_db[i][j].count > 0) { - avg = (uint64_t)stat_host_db[i][j].sum; + avg = (u64)stat_host_db[i][j].sum; do_div(avg, stat_host_db[i][j].count); min_cyc = stat_host_db[i][j].min; max_cyc = stat_host_db[i][j].max; } else { avg = min_cyc = max_cyc = 0; } - tmp_len = scnprintf(line,512, + tmp_len = scnprintf(line, 512, "%s::%s\t\t\t\t\t%6u\t%6u\t%6u\t%7u\n", stat_name_db[i].op_type_name, stat_name_db[i].stat_phase_name[j], min_cyc, (unsigned int)avg, max_cyc, stat_host_db[i][j].count); - if ( tmp_len <0 )/* scnprintf shouldn't return negative value according to its implementation*/ + if (tmp_len < 0)/* scnprintf shouldn't return negative value according to its implementation*/ return buf_len; - if ( buf_len + tmp_len >= PAGE_SIZE) + if (buf_len + tmp_len >= PAGE_SIZE) return buf_len; buf_len += tmp_len; - strncat(buf, line,512); + strncat(buf, line, 512); } } return buf_len; @@ -216,24 +214,24 @@ static ssize_t ssi_sys_stat_cc_db_show(struct kobject *kobj, { int i; char line[256]; - uint32_t min_cyc, max_cyc; - uint64_t avg; - ssize_t buf_len,tmp_len=0; + u32 min_cyc, max_cyc; + u64 avg; + ssize_t buf_len, tmp_len = 0; - buf_len = scnprintf(buf,PAGE_SIZE, + buf_len = scnprintf(buf, PAGE_SIZE, "phase\tmin[cy]\tavg[cy]\tmax[cy]\t#samples\n"); - if ( buf_len <0 )/* scnprintf shouldn't return negative value according to its implementation*/ + if (buf_len < 0)/* scnprintf shouldn't return negative value according to its implementation*/ return buf_len; - for (i=STAT_OP_TYPE_ENCODE; i<MAX_STAT_OP_TYPES; i++) { + for (i = STAT_OP_TYPE_ENCODE; i < MAX_STAT_OP_TYPES; i++) { if (stat_cc_db[i][STAT_PHASE_6].count > 0) { - avg = (uint64_t)stat_cc_db[i][STAT_PHASE_6].sum; + avg = (u64)stat_cc_db[i][STAT_PHASE_6].sum; do_div(avg, stat_cc_db[i][STAT_PHASE_6].count); min_cyc = stat_cc_db[i][STAT_PHASE_6].min; max_cyc = stat_cc_db[i][STAT_PHASE_6].max; } else { avg = min_cyc = max_cyc = 0; } - tmp_len = scnprintf(line,256, + tmp_len = scnprintf(line, 256, "%s\t%6u\t%6u\t%6u\t%7u\n", stat_name_db[i].op_type_name, min_cyc, @@ -241,13 +239,13 @@ static ssize_t ssi_sys_stat_cc_db_show(struct kobject *kobj, max_cyc, stat_cc_db[i][STAT_PHASE_6].count); - if ( tmp_len < 0 )/* scnprintf shouldn't return negative value according to its implementation*/ + if (tmp_len < 0)/* scnprintf shouldn't return negative value according to its implementation*/ return buf_len; - if ( buf_len + tmp_len >= PAGE_SIZE) + if (buf_len + tmp_len >= PAGE_SIZE) return buf_len; buf_len += tmp_len; - strncat(buf, line,256); + strncat(buf, line, 256); } return buf_len; } @@ -271,21 +269,19 @@ void update_cc_stat( void display_all_stat_db(void) { - SSI_LOG_ERR("\n======= CYCLE COUNT STATS =======\n"); + SSI_LOG_ERR("\n======= CYCLE COUNT STATS =======\n"); display_db(stat_host_db); - SSI_LOG_ERR("\n======= CC HW CYCLE COUNT STATS =======\n"); + SSI_LOG_ERR("\n======= CC HW CYCLE COUNT STATS =======\n"); display_db(stat_cc_db); } #endif /*CC_CYCLE_COUNT*/ - - static ssize_t ssi_sys_regdump_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) { struct ssi_drvdata *drvdata = sys_get_drvdata(); - uint32_t register_value; - void __iomem* cc_base = drvdata->cc_base; + u32 register_value; + void __iomem *cc_base = drvdata->cc_base; int offset = 0; register_value = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_SIGNATURE)); @@ -304,7 +300,7 @@ static ssize_t ssi_sys_regdump_show(struct kobject *kobj, static ssize_t ssi_sys_help_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) { - char* help_str[]={ + char *help_str[] = { "cat reg_dump ", "Print several of CC register values", #if defined CC_CYCLE_COUNT "cat stats_host ", "Print host statistics", @@ -313,12 +309,12 @@ static ssize_t ssi_sys_help_show(struct kobject *kobj, "echo <number> > stats_cc ", "Clear CC statistics database", #endif }; - int i=0, offset = 0; + int i = 0, offset = 0; offset += scnprintf(buf + offset, PAGE_SIZE - offset, "Usage:\n"); - for ( i = 0; i < ARRAY_SIZE(help_str); i+=2) { - offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s\t\t%s\n", help_str[i], help_str[i+1]); - } + for (i = 0; i < ARRAY_SIZE(help_str); i += 2) + offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s\t\t%s\n", help_str[i], help_str[i + 1]); + return offset; } @@ -333,7 +329,7 @@ struct sys_dir { struct kobject *sys_dir_kobj; struct attribute_group sys_dir_attr_group; struct attribute **sys_dir_attr_list; - uint32_t num_of_attrs; + u32 num_of_attrs; struct ssi_drvdata *drvdata; /* Associated driver context */ }; @@ -355,13 +351,14 @@ static struct ssi_drvdata *sys_get_drvdata(void) { /* TODO: supporting multiple SeP devices would require avoiding * global "top_dir" and finding associated "top_dir" by traversing - * up the tree to the kobject which matches one of the top_dir's */ + * up the tree to the kobject which matches one of the top_dir's + */ return sys_top_dir.drvdata; } static int sys_init_dir(struct sys_dir *sys_dir, struct ssi_drvdata *drvdata, struct kobject *parent_dir_kobj, const char *dir_name, - struct kobj_attribute *attrs, uint32_t num_of_attrs) + struct kobj_attribute *attrs, u32 num_of_attrs) { int i; @@ -407,7 +404,7 @@ static void sys_free_dir(struct sys_dir *sys_dir) kfree(sys_dir->sys_dir_attr_list); - if (sys_dir->sys_dir_kobj != NULL) + if (sys_dir->sys_dir_kobj) kobject_put(sys_dir->sys_dir_kobj); } diff --git a/drivers/staging/ccree/ssi_sysfs.h b/drivers/staging/ccree/ssi_sysfs.h index baeac1d99c07..44ae3d4c40b3 100644 --- a/drivers/staging/ccree/ssi_sysfs.h +++ b/drivers/staging/ccree/ssi_sysfs.h @@ -1,21 +1,21 @@ /* * Copyright (C) 2012-2017 ARM Limited or its affiliates. - * + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * + * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + * * You should have received a copy of the GNU General Public License * along with this program; if not, see <http://www.gnu.org/licenses/>. */ /* \file ssi_sysfs.h - ARM CryptoCell sysfs APIs + * ARM CryptoCell sysfs APIs */ #ifndef __SSI_SYSFS_H__ @@ -36,6 +36,7 @@ enum stat_phase { STAT_PHASE_6, MAX_STAT_PHASES, }; + enum stat_op { STAT_OP_TYPE_NULL = 0, STAT_OP_TYPE_ENCODE, diff --git a/drivers/staging/comedi/comedi_fops.c b/drivers/staging/comedi/comedi_fops.c index f191c2a75732..ca11be21f64b 100644 --- a/drivers/staging/comedi/comedi_fops.c +++ b/drivers/staging/comedi/comedi_fops.c @@ -2881,29 +2881,25 @@ static int __init comedi_init(void) retval = register_chrdev_region(MKDEV(COMEDI_MAJOR, 0), COMEDI_NUM_MINORS, "comedi"); if (retval) - return -EIO; + return retval; + cdev_init(&comedi_cdev, &comedi_fops); comedi_cdev.owner = THIS_MODULE; retval = kobject_set_name(&comedi_cdev.kobj, "comedi"); - if (retval) { - unregister_chrdev_region(MKDEV(COMEDI_MAJOR, 0), - COMEDI_NUM_MINORS); - return retval; - } + if (retval) + goto out_unregister_chrdev_region; + + retval = cdev_add(&comedi_cdev, MKDEV(COMEDI_MAJOR, 0), + COMEDI_NUM_MINORS); + if (retval) + goto out_unregister_chrdev_region; - if (cdev_add(&comedi_cdev, MKDEV(COMEDI_MAJOR, 0), COMEDI_NUM_MINORS)) { - unregister_chrdev_region(MKDEV(COMEDI_MAJOR, 0), - COMEDI_NUM_MINORS); - return -EIO; - } comedi_class = class_create(THIS_MODULE, "comedi"); if (IS_ERR(comedi_class)) { + retval = PTR_ERR(comedi_class); pr_err("failed to create class\n"); - cdev_del(&comedi_cdev); - unregister_chrdev_region(MKDEV(COMEDI_MAJOR, 0), - COMEDI_NUM_MINORS); - return PTR_ERR(comedi_class); + goto out_cdev_del; } comedi_class->dev_groups = comedi_dev_groups; @@ -2914,11 +2910,8 @@ static int __init comedi_init(void) dev = comedi_alloc_board_minor(NULL); if (IS_ERR(dev)) { - comedi_cleanup_board_minors(); - cdev_del(&comedi_cdev); - unregister_chrdev_region(MKDEV(COMEDI_MAJOR, 0), - COMEDI_NUM_MINORS); - return PTR_ERR(dev); + retval = PTR_ERR(dev); + goto out_cleanup_board_minors; } /* comedi_alloc_board_minor() locked the mutex */ mutex_unlock(&dev->mutex); @@ -2928,6 +2921,15 @@ static int __init comedi_init(void) comedi_proc_init(); return 0; + +out_cleanup_board_minors: + comedi_cleanup_board_minors(); + class_destroy(comedi_class); +out_cdev_del: + cdev_del(&comedi_cdev); +out_unregister_chrdev_region: + unregister_chrdev_region(MKDEV(COMEDI_MAJOR, 0), COMEDI_NUM_MINORS); + return retval; } module_init(comedi_init); diff --git a/drivers/staging/comedi/drivers/ni_labpc_isadma.h b/drivers/staging/comedi/drivers/ni_labpc_isadma.h index b8a1b0ee6290..e93f79050e60 100644 --- a/drivers/staging/comedi/drivers/ni_labpc_isadma.h +++ b/drivers/staging/comedi/drivers/ni_labpc_isadma.h @@ -1,6 +1,6 @@ /* * ni_labpc ISA DMA support. -*/ + */ #ifndef _NI_LABPC_ISADMA_H #define _NI_LABPC_ISADMA_H diff --git a/drivers/staging/comedi/drivers/ni_labpc_regs.h b/drivers/staging/comedi/drivers/ni_labpc_regs.h index 8c52179e36fc..6003e9d5fe37 100644 --- a/drivers/staging/comedi/drivers/ni_labpc_regs.h +++ b/drivers/staging/comedi/drivers/ni_labpc_regs.h @@ -1,6 +1,6 @@ /* * ni_labpc register definitions. -*/ + */ #ifndef _NI_LABPC_REGS_H #define _NI_LABPC_REGS_H diff --git a/drivers/staging/comedi/drivers/s626.c b/drivers/staging/comedi/drivers/s626.c index 4b9c22665748..c906c9a5d944 100644 --- a/drivers/staging/comedi/drivers/s626.c +++ b/drivers/staging/comedi/drivers/s626.c @@ -580,11 +580,14 @@ static int s626_set_dac(struct comedi_device *dev, * running after the packet has been sent to the target DAC. */ val = 0x0F000000; /* Continue clock after target DAC data - * (write to non-existent trimdac). */ + * (write to non-existent trimdac). + */ val |= 0x00004000; /* Address the two main dual-DAC devices - * (TSL's chip select enables target device). */ + * (TSL's chip select enables target device). + */ val |= ((u32)(chan & 1) << 15); /* Address the DAC channel - * within the device. */ + * within the device. + */ val |= (u32)dacdata; /* Include DAC setpoint data. */ return s626_send_dac(dev, val); } diff --git a/drivers/staging/dgnc/dgnc_driver.c b/drivers/staging/dgnc/dgnc_driver.c index 253f38b25a54..c1b6079384e9 100644 --- a/drivers/staging/dgnc/dgnc_driver.c +++ b/drivers/staging/dgnc/dgnc_driver.c @@ -96,7 +96,6 @@ static int dgnc_do_remap(struct dgnc_board *brd) return 0; } - /* A board has been found, initialize it. */ static struct dgnc_board *dgnc_found_board(struct pci_dev *pdev, int id) { @@ -287,7 +286,6 @@ static void dgnc_free_irq(struct dgnc_board *brd) free_irq(brd->irq, brd); } - /* * As each timer expires, it determines (a) whether the "transmit" * waiter needs to be woken up, and (b) whether the poller needs to diff --git a/drivers/staging/dgnc/dgnc_driver.h b/drivers/staging/dgnc/dgnc_driver.h index 980410fc4801..764d6fe0d030 100644 --- a/drivers/staging/dgnc/dgnc_driver.h +++ b/drivers/staging/dgnc/dgnc_driver.h @@ -52,19 +52,6 @@ #define dgnc_jiffies_from_ms(a) (((a) * HZ) / 1000) -/* - * Define a local default termios struct. All ports will be created - * with this termios initially. This is the same structure that is defined - * as the default in tty_io.c with the same settings overridden as in serial.c - * - * In short, this should match the internal serial ports' defaults. - */ -#define DEFAULT_IFLAGS (ICRNL | IXON) -#define DEFAULT_OFLAGS (OPOST | ONLCR) -#define DEFAULT_CFLAGS (B9600 | CS8 | CREAD | HUPCL | CLOCAL) -#define DEFAULT_LFLAGS (ISIG | ICANON | ECHO | ECHOE | ECHOK | \ - ECHOCTL | ECHOKE | IEXTEN) - #ifndef _POSIX_VDISABLE #define _POSIX_VDISABLE '\0' #endif diff --git a/drivers/staging/dgnc/dgnc_tty.c b/drivers/staging/dgnc/dgnc_tty.c index 9e98781ca6fe..d3736daf8cf2 100644 --- a/drivers/staging/dgnc/dgnc_tty.c +++ b/drivers/staging/dgnc/dgnc_tty.c @@ -51,22 +51,6 @@ static const struct digi_t dgnc_digi_init = { .digi_term = "ansi" /* default terminal type */ }; -/* - * Define a local default termios struct. All ports will be created - * with this termios initially. - * - * This defines a raw port at 9600 baud, 8 data bits, no parity, - * 1 stop bit. - */ -static const struct ktermios default_termios = { - .c_iflag = (DEFAULT_IFLAGS), - .c_oflag = (DEFAULT_OFLAGS), - .c_cflag = (DEFAULT_CFLAGS), - .c_lflag = (DEFAULT_LFLAGS), - .c_cc = INIT_C_CC, - .c_line = 0, -}; - static int dgnc_tty_open(struct tty_struct *tty, struct file *file); static void dgnc_tty_close(struct tty_struct *tty, struct file *file); static int dgnc_block_til_ready(struct tty_struct *tty, struct file *file, @@ -129,6 +113,49 @@ static const struct tty_operations dgnc_tty_ops = { /* TTY Initialization/Cleanup Functions */ +static struct tty_driver *dgnc_tty_create(char *serial_name, uint maxports, + int major, int minor) +{ + int rc; + struct tty_driver *drv; + + drv = tty_alloc_driver(maxports, + TTY_DRIVER_REAL_RAW | + TTY_DRIVER_DYNAMIC_DEV | + TTY_DRIVER_HARDWARE_BREAK); + if (IS_ERR(drv)) + return drv; + + drv->name = serial_name; + drv->name_base = 0; + drv->major = major; + drv->minor_start = minor; + drv->type = TTY_DRIVER_TYPE_SERIAL; + drv->subtype = SERIAL_TYPE_NORMAL; + drv->init_termios = tty_std_termios; + drv->init_termios.c_cflag = (B9600 | CS8 | CREAD | HUPCL | CLOCAL); + drv->init_termios.c_ispeed = 9600; + drv->init_termios.c_ospeed = 9600; + drv->driver_name = DRVSTR; + /* + * Entry points for driver. Called by the kernel from + * tty_io.c and n_tty.c. + */ + tty_set_operations(drv, &dgnc_tty_ops); + rc = tty_register_driver(drv); + if (rc < 0) { + put_tty_driver(drv); + return ERR_PTR(rc); + } + return drv; +} + +static void dgnc_tty_free(struct tty_driver *drv) +{ + tty_unregister_driver(drv); + put_tty_driver(drv); +} + /** * dgnc_tty_register() - Init the tty subsystem for this board. */ @@ -136,95 +163,36 @@ int dgnc_tty_register(struct dgnc_board *brd) { int rc; - brd->serial_driver = tty_alloc_driver(brd->maxports, - TTY_DRIVER_REAL_RAW | - TTY_DRIVER_DYNAMIC_DEV | - TTY_DRIVER_HARDWARE_BREAK); - if (IS_ERR(brd->serial_driver)) - return PTR_ERR(brd->serial_driver); - snprintf(brd->serial_name, MAXTTYNAMELEN, "tty_dgnc_%d_", brd->boardnum); - brd->serial_driver->name = brd->serial_name; - brd->serial_driver->name_base = 0; - brd->serial_driver->major = 0; - brd->serial_driver->minor_start = 0; - brd->serial_driver->type = TTY_DRIVER_TYPE_SERIAL; - brd->serial_driver->subtype = SERIAL_TYPE_NORMAL; - brd->serial_driver->init_termios = default_termios; - brd->serial_driver->driver_name = DRVSTR; - - /* - * Entry points for driver. Called by the kernel from - * tty_io.c and n_tty.c. - */ - tty_set_operations(brd->serial_driver, &dgnc_tty_ops); - - rc = tty_register_driver(brd->serial_driver); - if (rc < 0) { - dev_dbg(&brd->pdev->dev, - "Can't register tty device (%d)\n", rc); - goto free_serial_driver; + brd->serial_driver = dgnc_tty_create(brd->serial_name, + brd->maxports, 0, 0); + if (IS_ERR(brd->serial_driver)) { + rc = PTR_ERR(brd->serial_driver); + dev_dbg(&brd->pdev->dev, "Can't register tty device (%d)\n", + rc); + return rc; } - /* - * If we're doing transparent print, we have to do all of the above - * again, separately so we don't get the LD confused about what major - * we are when we get into the dgnc_tty_open() routine. - */ - brd->print_driver = tty_alloc_driver(brd->maxports, - TTY_DRIVER_REAL_RAW | - TTY_DRIVER_DYNAMIC_DEV | - TTY_DRIVER_HARDWARE_BREAK); + snprintf(brd->print_name, MAXTTYNAMELEN, "pr_dgnc_%d_", brd->boardnum); + brd->print_driver = dgnc_tty_create(brd->print_name, brd->maxports, + 0x80, + brd->serial_driver->major); if (IS_ERR(brd->print_driver)) { rc = PTR_ERR(brd->print_driver); - goto unregister_serial_driver; - } - - snprintf(brd->print_name, MAXTTYNAMELEN, "pr_dgnc_%d_", brd->boardnum); - - brd->print_driver->name = brd->print_name; - brd->print_driver->name_base = 0; - brd->print_driver->major = brd->serial_driver->major; - brd->print_driver->minor_start = 0x80; - brd->print_driver->type = TTY_DRIVER_TYPE_SERIAL; - brd->print_driver->subtype = SERIAL_TYPE_NORMAL; - brd->print_driver->init_termios = default_termios; - brd->print_driver->driver_name = DRVSTR; - - /* - * Entry points for driver. Called by the kernel from - * tty_io.c and n_tty.c. - */ - tty_set_operations(brd->print_driver, &dgnc_tty_ops); - - rc = tty_register_driver(brd->print_driver); - if (rc < 0) { dev_dbg(&brd->pdev->dev, - "Can't register Transparent Print device(%d)\n", - rc); - goto free_print_driver; + "Can't register Transparent Print device(%d)\n", rc); + dgnc_tty_free(brd->serial_driver); + return rc; } - return 0; - -free_print_driver: - put_tty_driver(brd->print_driver); -unregister_serial_driver: - tty_unregister_driver(brd->serial_driver); -free_serial_driver: - put_tty_driver(brd->serial_driver); - - return rc; } void dgnc_tty_unregister(struct dgnc_board *brd) { - tty_unregister_driver(brd->print_driver); - tty_unregister_driver(brd->serial_driver); - put_tty_driver(brd->print_driver); - put_tty_driver(brd->serial_driver); + dgnc_tty_free(brd->print_driver); + dgnc_tty_free(brd->serial_driver); } /** diff --git a/drivers/staging/emxx_udc/emxx_udc.c b/drivers/staging/emxx_udc/emxx_udc.c index 77b242e09932..bb010cb98a1c 100644 --- a/drivers/staging/emxx_udc/emxx_udc.c +++ b/drivers/staging/emxx_udc/emxx_udc.c @@ -200,13 +200,13 @@ static u32 _nbu2ss_get_begin_ram_address(struct nbu2ss_udc *udc) for (num = 0; num < NUM_ENDPOINTS - 1; num++) { p_ep_regs = &udc->p_regs->EP_REGS[num]; data = _nbu2ss_readl(&p_ep_regs->EP_PCKT_ADRS); - buf_type = _nbu2ss_readl(&p_ep_regs->EP_CONTROL) & EPn_BUF_TYPE; + buf_type = _nbu2ss_readl(&p_ep_regs->EP_CONTROL) & EPN_BUF_TYPE; if (buf_type == 0) { /* Single Buffer */ - use_ram_size += (data & EPn_MPKT) / sizeof(u32); + use_ram_size += (data & EPN_MPKT) / sizeof(u32); } else { /* Double Buffer */ - use_ram_size += ((data & EPn_MPKT) / sizeof(u32)) * 2; + use_ram_size += ((data & EPN_MPKT) / sizeof(u32)) * 2; } if ((data >> 16) > last_ram_adr) @@ -245,15 +245,15 @@ static int _nbu2ss_ep_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) /* Bulk, Interrupt, ISO */ switch (ep->ep_type) { case USB_ENDPOINT_XFER_BULK: - data = EPn_BULK; + data = EPN_BULK; break; case USB_ENDPOINT_XFER_INT: - data = EPn_BUF_SINGLE | EPn_INTERRUPT; + data = EPN_BUF_SINGLE | EPN_INTERRUPT; break; case USB_ENDPOINT_XFER_ISOC: - data = EPn_ISO; + data = EPN_ISO; break; default: @@ -267,24 +267,24 @@ static int _nbu2ss_ep_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) if (ep->direct == USB_DIR_OUT) { /*---------------------------------------------------------*/ /* OUT */ - data = EPn_EN | EPn_BCLR | EPn_DIR0; + data = EPN_EN | EPN_BCLR | EPN_DIR0; _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); - data = EPn_ONAK | EPn_OSTL_EN | EPn_OSTL; + data = EPN_ONAK | EPN_OSTL_EN | EPN_OSTL; _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); - data = EPn_OUT_EN | EPn_OUT_END_EN; + data = EPN_OUT_EN | EPN_OUT_END_EN; _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data); } else { /*---------------------------------------------------------*/ /* IN */ - data = EPn_EN | EPn_BCLR | EPn_AUTO; + data = EPN_EN | EPN_BCLR | EPN_AUTO; _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); - data = EPn_ISTL; + data = EPN_ISTL; _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); - data = EPn_IN_EN | EPn_IN_END_EN; + data = EPN_IN_EN | EPN_IN_END_EN; _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data); } @@ -315,24 +315,24 @@ static int _nbu2ss_epn_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) if (ep->direct == USB_DIR_OUT) { /*---------------------------------------------------------*/ /* OUT */ - data = EPn_ONAK | EPn_BCLR; + data = EPN_ONAK | EPN_BCLR; _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); - data = EPn_EN | EPn_DIR0; + data = EPN_EN | EPN_DIR0; _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); - data = EPn_OUT_EN | EPn_OUT_END_EN; + data = EPN_OUT_EN | EPN_OUT_END_EN; _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data); } else { /*---------------------------------------------------------*/ /* IN */ - data = EPn_BCLR; + data = EPN_BCLR; _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); - data = EPn_EN | EPn_AUTO; + data = EPN_EN | EPN_AUTO; _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); - data = EPn_IN_EN | EPn_IN_END_EN; + data = EPN_IN_EN | EPN_IN_END_EN; _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data); } @@ -360,21 +360,21 @@ static void _nbu2ss_ep_dma_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) /*---------------------------------------------------------*/ /* Transfer Direct */ - data = DCR1_EPn_DIR0; + data = DCR1_EPN_DIR0; _nbu2ss_bitset(&udc->p_regs->EP_DCR[num].EP_DCR1, data); /*---------------------------------------------------------*/ /* DMA Mode etc. */ - data = EPn_STOP_MODE | EPn_STOP_SET | EPn_DMAMODE0; + data = EPN_STOP_MODE | EPN_STOP_SET | EPN_DMAMODE0; _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data); } else { /*---------------------------------------------------------*/ /* IN */ - _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, EPn_AUTO); + _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, EPN_AUTO); /*---------------------------------------------------------*/ /* DMA Mode etc. */ - data = EPn_BURST_SET | EPn_DMAMODE0; + data = EPN_BURST_SET | EPN_DMAMODE0; _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data); } } @@ -402,12 +402,12 @@ static void _nbu2ss_ep_dma_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) /*---------------------------------------------------------*/ /* OUT */ _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, 0); - _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPn_DIR0); + _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPN_DIR0); _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0); } else { /*---------------------------------------------------------*/ /* IN */ - _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPn_AUTO); + _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO); _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0); } } @@ -418,9 +418,9 @@ static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) { struct fc_regs *preg = udc->p_regs; - _nbu2ss_bitclr(&preg->EP_DCR[ep->epnum - 1].EP_DCR1, DCR1_EPn_REQEN); - mdelay(DMA_DISABLE_TIME); /* DCR1_EPn_REQEN Clear */ - _nbu2ss_bitclr(&preg->EP_REGS[ep->epnum - 1].EP_DMA_CTRL, EPn_DMA_EN); + _nbu2ss_bitclr(&preg->EP_DCR[ep->epnum - 1].EP_DCR1, DCR1_EPN_REQEN); + mdelay(DMA_DISABLE_TIME); /* DCR1_EPN_REQEN Clear */ + _nbu2ss_bitclr(&preg->EP_REGS[ep->epnum - 1].EP_DMA_CTRL, EPN_DMA_EN); } /*-------------------------------------------------------------------------*/ @@ -453,16 +453,16 @@ static void _nbu2ss_ep_in_end( } else { num = epnum - 1; - _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPn_AUTO); + _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO); /* Writing of 1-4 bytes */ if (length) _nbu2ss_writel(&preg->EP_REGS[num].EP_WRITE, data32); - data = (((length) << 5) & EPn_DW) | EPn_DEND; + data = (((length) << 5) & EPN_DW) | EPN_DEND; _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data); - _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, EPn_AUTO); + _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, EPN_AUTO); } } @@ -526,12 +526,13 @@ static void _nbu2ss_dma_unmap_single( if (direct == USB_DIR_OUT) memcpy(req->req.buf, ep->virt_buf, req->req.actual & 0xfffffffc); - } else + } else { dma_unmap_single(udc->gadget.dev.parent, req->req.dma, req->req.length, (direct == USB_DIR_IN) ? DMA_TO_DEVICE : DMA_FROM_DEVICE); + } req->req.dma = DMA_ADDR_INVALID; req->mapped = 0; } else { @@ -573,65 +574,67 @@ static int ep0_out_pio(struct nbu2ss_udc *udc, u8 *buf, u32 length) /*-------------------------------------------------------------------------*/ /* Endpoint 0 OUT Transfer (PIO, OverBytes) */ -static int EP0_out_OverBytes(struct nbu2ss_udc *udc, u8 *pBuf, u32 length) +static int ep0_out_overbytes(struct nbu2ss_udc *udc, u8 *p_buf, u32 length) { u32 i; - u32 iReadSize = 0; - union usb_reg_access Temp32; - union usb_reg_access *pBuf32 = (union usb_reg_access *)pBuf; + u32 i_read_size = 0; + union usb_reg_access temp_32; + union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf; if ((length > 0) && (length < sizeof(u32))) { - Temp32.dw = _nbu2ss_readl(&udc->p_regs->EP0_READ); + temp_32.dw = _nbu2ss_readl(&udc->p_regs->EP0_READ); for (i = 0 ; i < length ; i++) - pBuf32->byte.DATA[i] = Temp32.byte.DATA[i]; - iReadSize += length; + p_buf_32->byte.DATA[i] = temp_32.byte.DATA[i]; + i_read_size += length; } - return iReadSize; + return i_read_size; } /*-------------------------------------------------------------------------*/ /* Endpoint 0 IN Transfer (PIO) */ -static int EP0_in_PIO(struct nbu2ss_udc *udc, u8 *pBuf, u32 length) +static int EP0_in_PIO(struct nbu2ss_udc *udc, u8 *p_buf, u32 length) { u32 i; - u32 iMaxLength = EP0_PACKETSIZE; - u32 iWordLength = 0; - u32 iWriteLength = 0; - union usb_reg_access *pBuf32 = (union usb_reg_access *)pBuf; + u32 i_max_length = EP0_PACKETSIZE; + u32 i_word_length = 0; + u32 i_write_length = 0; + union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf; /*------------------------------------------------------------*/ /* Transfer Length */ - if (iMaxLength < length) - iWordLength = iMaxLength / sizeof(u32); + if (i_max_length < length) + i_word_length = i_max_length / sizeof(u32); else - iWordLength = length / sizeof(u32); + i_word_length = length / sizeof(u32); /*------------------------------------------------------------*/ /* PIO */ - for (i = 0; i < iWordLength; i++) { - _nbu2ss_writel(&udc->p_regs->EP0_WRITE, pBuf32->dw); - pBuf32++; - iWriteLength += sizeof(u32); + for (i = 0; i < i_word_length; i++) { + _nbu2ss_writel(&udc->p_regs->EP0_WRITE, p_buf_32->dw); + p_buf_32++; + i_write_length += sizeof(u32); } - return iWriteLength; + return i_write_length; } /*-------------------------------------------------------------------------*/ /* Endpoint 0 IN Transfer (PIO, OverBytes) */ -static int EP0_in_OverBytes(struct nbu2ss_udc *udc, u8 *pBuf, u32 iRemainSize) +static int ep0_in_overbytes(struct nbu2ss_udc *udc, + u8 *p_buf, + u32 i_remain_size) { u32 i; - union usb_reg_access Temp32; - union usb_reg_access *pBuf32 = (union usb_reg_access *)pBuf; + union usb_reg_access temp_32; + union usb_reg_access *p_buf_32 = (union usb_reg_access *)p_buf; - if ((iRemainSize > 0) && (iRemainSize < sizeof(u32))) { - for (i = 0 ; i < iRemainSize ; i++) - Temp32.byte.DATA[i] = pBuf32->byte.DATA[i]; - _nbu2ss_ep_in_end(udc, 0, Temp32.dw, iRemainSize); + if ((i_remain_size > 0) && (i_remain_size < sizeof(u32))) { + for (i = 0 ; i < i_remain_size ; i++) + temp_32.byte.DATA[i] = p_buf_32->byte.DATA[i]; + _nbu2ss_ep_in_end(udc, 0, temp_32.dw, i_remain_size); - return iRemainSize; + return i_remain_size; } return 0; @@ -679,9 +682,9 @@ static int _nbu2ss_ep0_in_transfer( struct nbu2ss_req *req ) { - u8 *pBuffer; /* IN Data Buffer */ + u8 *p_buffer; /* IN Data Buffer */ u32 data; - u32 iRemainSize = 0; + u32 i_remain_size = 0; int result = 0; /*-------------------------------------------------------------*/ @@ -705,25 +708,25 @@ static int _nbu2ss_ep0_in_transfer( data &= ~(u32)EP0_INAK; _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data); - iRemainSize = req->req.length - req->req.actual; - pBuffer = (u8 *)req->req.buf; - pBuffer += req->req.actual; + i_remain_size = req->req.length - req->req.actual; + p_buffer = (u8 *)req->req.buf; + p_buffer += req->req.actual; /*-------------------------------------------------------------*/ /* Data transfer */ - result = EP0_in_PIO(udc, pBuffer, iRemainSize); + result = EP0_in_PIO(udc, p_buffer, i_remain_size); req->div_len = result; - iRemainSize -= result; + i_remain_size -= result; - if (iRemainSize == 0) { + if (i_remain_size == 0) { EP0_send_NULL(udc, FALSE); return result; } - if ((iRemainSize < sizeof(u32)) && (result != EP0_PACKETSIZE)) { - pBuffer += result; - result += EP0_in_OverBytes(udc, pBuffer, iRemainSize); + if ((i_remain_size < sizeof(u32)) && (result != EP0_PACKETSIZE)) { + p_buffer += result; + result += ep0_in_overbytes(udc, p_buffer, i_remain_size); req->div_len = result; } @@ -736,40 +739,40 @@ static int _nbu2ss_ep0_out_transfer( struct nbu2ss_req *req ) { - u8 *pBuffer; - u32 iRemainSize; - u32 iRecvLength; + u8 *p_buffer; + u32 i_remain_size; + u32 i_recv_length; int result = 0; - int fRcvZero; + int f_rcv_zero; /*-------------------------------------------------------------*/ /* Receive data confirmation */ - iRecvLength = _nbu2ss_readl(&udc->p_regs->EP0_LENGTH) & EP0_LDATA; - if (iRecvLength != 0) { - fRcvZero = 0; + i_recv_length = _nbu2ss_readl(&udc->p_regs->EP0_LENGTH) & EP0_LDATA; + if (i_recv_length != 0) { + f_rcv_zero = 0; - iRemainSize = req->req.length - req->req.actual; - pBuffer = (u8 *)req->req.buf; - pBuffer += req->req.actual; + i_remain_size = req->req.length - req->req.actual; + p_buffer = (u8 *)req->req.buf; + p_buffer += req->req.actual; - result = ep0_out_pio(udc, pBuffer - , min(iRemainSize, iRecvLength)); + result = ep0_out_pio(udc, p_buffer + , min(i_remain_size, i_recv_length)); if (result < 0) return result; req->req.actual += result; - iRecvLength -= result; + i_recv_length -= result; - if ((iRecvLength > 0) && (iRecvLength < sizeof(u32))) { - pBuffer += result; - iRemainSize -= result; + if ((i_recv_length > 0) && (i_recv_length < sizeof(u32))) { + p_buffer += result; + i_remain_size -= result; - result = EP0_out_OverBytes(udc, pBuffer - , min(iRemainSize, iRecvLength)); + result = ep0_out_overbytes(udc, p_buffer + , min(i_remain_size, i_recv_length)); req->req.actual += result; } } else { - fRcvZero = 1; + f_rcv_zero = 1; } /*-------------------------------------------------------------*/ @@ -794,9 +797,9 @@ static int _nbu2ss_ep0_out_transfer( return -EOVERFLOW; } - if (fRcvZero != 0) { - iRemainSize = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL); - if (iRemainSize & EP0_ONAK) { + if (f_rcv_zero != 0) { + i_remain_size = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL); + if (i_remain_size & EP0_ONAK) { /*---------------------------------------------------*/ /* NACK release */ _nbu2ss_bitclr(&udc->p_regs->EP0_CONTROL, EP0_ONAK); @@ -815,7 +818,7 @@ static int _nbu2ss_out_dma( u32 length ) { - dma_addr_t pBuffer; + dma_addr_t p_buffer; u32 mpkt; u32 lmpkt; u32 dmacnt; @@ -828,14 +831,14 @@ static int _nbu2ss_out_dma( return 1; /* DMA is forwarded */ req->dma_flag = TRUE; - pBuffer = req->req.dma; - pBuffer += req->req.actual; + p_buffer = req->req.dma; + p_buffer += req->req.actual; /* DMA Address */ - _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)pBuffer); + _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)p_buffer); /* Number of transfer packets */ - mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPn_MPKT; + mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPN_MPKT; dmacnt = length / mpkt; lmpkt = (length % mpkt) & ~(u32)0x03; @@ -851,18 +854,18 @@ static int _nbu2ss_out_dma( data = mpkt | (lmpkt << 16); _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data); - data = ((dmacnt & 0xff) << 16) | DCR1_EPn_DIR0 | DCR1_EPn_REQEN; + data = ((dmacnt & 0xff) << 16) | DCR1_EPN_DIR0 | DCR1_EPN_REQEN; _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data); if (burst == 0) { _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, 0); - _nbu2ss_bitclr(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_BURST_SET); + _nbu2ss_bitclr(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_BURST_SET); } else { _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT , (dmacnt << 16)); - _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_BURST_SET); + _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_BURST_SET); } - _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_DMA_EN); + _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_DMA_EN); result = length & ~(u32)0x03; req->div_len = result; @@ -878,12 +881,12 @@ static int _nbu2ss_epn_out_pio( u32 length ) { - u8 *pBuffer; + u8 *p_buffer; u32 i; u32 data; - u32 iWordLength; - union usb_reg_access Temp32; - union usb_reg_access *pBuf32; + u32 i_word_length; + union usb_reg_access temp_32; + union usb_reg_access *p_buf_32; int result = 0; struct fc_regs *preg = udc->p_regs; @@ -893,28 +896,29 @@ static int _nbu2ss_epn_out_pio( if (length == 0) return 0; - pBuffer = (u8 *)req->req.buf; - pBuf32 = (union usb_reg_access *)(pBuffer + req->req.actual); + p_buffer = (u8 *)req->req.buf; + p_buf_32 = (union usb_reg_access *)(p_buffer + req->req.actual); - iWordLength = length / sizeof(u32); - if (iWordLength > 0) { + i_word_length = length / sizeof(u32); + if (i_word_length > 0) { /*---------------------------------------------------------*/ /* Copy of every four bytes */ - for (i = 0; i < iWordLength; i++) { - pBuf32->dw = + for (i = 0; i < i_word_length; i++) { + p_buf_32->dw = _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ); - pBuf32++; + p_buf_32++; } - result = iWordLength * sizeof(u32); + result = i_word_length * sizeof(u32); } data = length - result; if (data > 0) { /*---------------------------------------------------------*/ /* Copy of fraction byte */ - Temp32.dw = _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ); + temp_32.dw = + _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_READ); for (i = 0 ; i < data ; i++) - pBuf32->byte.DATA[i] = Temp32.byte.DATA[i]; + p_buf_32->byte.DATA[i] = temp_32.byte.DATA[i]; result += data; } @@ -937,7 +941,7 @@ static int _nbu2ss_epn_out_data( ) { u32 num; - u32 iBufSize; + u32 i_buf_size; int nret = 1; if (ep->epnum == 0) @@ -945,14 +949,14 @@ static int _nbu2ss_epn_out_data( num = ep->epnum - 1; - iBufSize = min((req->req.length - req->req.actual), data_size); + i_buf_size = min((req->req.length - req->req.actual), data_size); if ((ep->ep_type != USB_ENDPOINT_XFER_INT) && (req->req.dma != 0) && - (iBufSize >= sizeof(u32))) { - nret = _nbu2ss_out_dma(udc, req, num, iBufSize); + (i_buf_size >= sizeof(u32))) { + nret = _nbu2ss_out_dma(udc, req, num, i_buf_size); } else { - iBufSize = min_t(u32, iBufSize, ep->ep.maxpacket); - nret = _nbu2ss_epn_out_pio(udc, ep, req, iBufSize); + i_buf_size = min_t(u32, i_buf_size, ep->ep.maxpacket); + nret = _nbu2ss_epn_out_pio(udc, ep, req, i_buf_size); } return nret; @@ -966,7 +970,7 @@ static int _nbu2ss_epn_out_transfer( ) { u32 num; - u32 iRecvLength; + u32 i_recv_length; int result = 1; struct fc_regs *preg = udc->p_regs; @@ -977,13 +981,13 @@ static int _nbu2ss_epn_out_transfer( /*-------------------------------------------------------------*/ /* Receive Length */ - iRecvLength - = _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT) & EPn_LDATA; + i_recv_length + = _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT) & EPN_LDATA; - if (iRecvLength != 0) { - result = _nbu2ss_epn_out_data(udc, ep, req, iRecvLength); - if (iRecvLength < ep->ep.maxpacket) { - if (iRecvLength == result) { + if (i_recv_length != 0) { + result = _nbu2ss_epn_out_data(udc, ep, req, i_recv_length); + if (i_recv_length < ep->ep.maxpacket) { + if (i_recv_length == result) { req->req.actual += result; result = 0; } @@ -1023,11 +1027,11 @@ static int _nbu2ss_in_dma( u32 length ) { - dma_addr_t pBuffer; + dma_addr_t p_buffer; u32 mpkt; /* MaxPacketSize */ u32 lmpkt; /* Last Packet Data Size */ u32 dmacnt; /* IN Data Size */ - u32 iWriteLength; + u32 i_write_length; u32 data; int result = -EINVAL; struct fc_regs *preg = udc->p_regs; @@ -1042,18 +1046,18 @@ static int _nbu2ss_in_dma( req->dma_flag = TRUE; /* MAX Packet Size */ - mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPn_MPKT; + mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPN_MPKT; if ((DMA_MAX_COUNT * mpkt) < length) - iWriteLength = DMA_MAX_COUNT * mpkt; + i_write_length = DMA_MAX_COUNT * mpkt; else - iWriteLength = length; + i_write_length = length; /*------------------------------------------------------------*/ /* Number of transmission packets */ - if (mpkt < iWriteLength) { - dmacnt = iWriteLength / mpkt; - lmpkt = (iWriteLength % mpkt) & ~(u32)0x3; + if (mpkt < i_write_length) { + dmacnt = i_write_length / mpkt; + lmpkt = (i_write_length % mpkt) & ~(u32)0x3; if (lmpkt != 0) dmacnt++; else @@ -1061,7 +1065,7 @@ static int _nbu2ss_in_dma( } else { dmacnt = 1; - lmpkt = iWriteLength & ~(u32)0x3; + lmpkt = i_write_length & ~(u32)0x3; } /* Packet setting */ @@ -1069,12 +1073,12 @@ static int _nbu2ss_in_dma( _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data); /* Address setting */ - pBuffer = req->req.dma; - pBuffer += req->req.actual; - _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)pBuffer); + p_buffer = req->req.dma; + p_buffer += req->req.actual; + _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)p_buffer); /* Packet and DMA setting */ - data = ((dmacnt & 0xff) << 16) | DCR1_EPn_REQEN; + data = ((dmacnt & 0xff) << 16) | DCR1_EPN_REQEN; _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data); /* Packet setting of EPC */ @@ -1082,9 +1086,9 @@ static int _nbu2ss_in_dma( _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, data); /*DMA setting of EPC */ - _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_DMA_EN); + _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPN_DMA_EN); - result = iWriteLength & ~(u32)0x3; + result = i_write_length & ~(u32)0x3; req->div_len = result; return result; @@ -1098,12 +1102,12 @@ static int _nbu2ss_epn_in_pio( u32 length ) { - u8 *pBuffer; + u8 *p_buffer; u32 i; u32 data; - u32 iWordLength; - union usb_reg_access Temp32; - union usb_reg_access *pBuf32 = NULL; + u32 i_word_length; + union usb_reg_access temp_32; + union usb_reg_access *p_buf_32 = NULL; int result = 0; struct fc_regs *preg = udc->p_regs; @@ -1111,30 +1115,30 @@ static int _nbu2ss_epn_in_pio( return 1; /* DMA is forwarded */ if (length > 0) { - pBuffer = (u8 *)req->req.buf; - pBuf32 = (union usb_reg_access *)(pBuffer + req->req.actual); + p_buffer = (u8 *)req->req.buf; + p_buf_32 = (union usb_reg_access *)(p_buffer + req->req.actual); - iWordLength = length / sizeof(u32); - if (iWordLength > 0) { - for (i = 0; i < iWordLength; i++) { + i_word_length = length / sizeof(u32); + if (i_word_length > 0) { + for (i = 0; i < i_word_length; i++) { _nbu2ss_writel( &preg->EP_REGS[ep->epnum - 1].EP_WRITE - , pBuf32->dw + , p_buf_32->dw ); - pBuf32++; + p_buf_32++; } - result = iWordLength * sizeof(u32); + result = i_word_length * sizeof(u32); } } if (result != ep->ep.maxpacket) { data = length - result; - Temp32.dw = 0; + temp_32.dw = 0; for (i = 0 ; i < data ; i++) - Temp32.byte.DATA[i] = pBuf32->byte.DATA[i]; + temp_32.byte.DATA[i] = p_buf_32->byte.DATA[i]; - _nbu2ss_ep_in_end(udc, ep->epnum, Temp32.dw, data); + _nbu2ss_ep_in_end(udc, ep->epnum, temp_32.dw, data); result += data; } @@ -1178,7 +1182,7 @@ static int _nbu2ss_epn_in_transfer( ) { u32 num; - u32 iBufSize; + u32 i_buf_size; int result = 0; u32 status; @@ -1192,19 +1196,19 @@ static int _nbu2ss_epn_in_transfer( /*-------------------------------------------------------------*/ /* State confirmation of FIFO */ if (req->req.actual == 0) { - if ((status & EPn_IN_EMPTY) == 0) + if ((status & EPN_IN_EMPTY) == 0) return 1; /* Not Empty */ } else { - if ((status & EPn_IN_FULL) != 0) + if ((status & EPN_IN_FULL) != 0) return 1; /* Not Empty */ } /*-------------------------------------------------------------*/ /* Start transfer */ - iBufSize = req->req.length - req->req.actual; - if (iBufSize > 0) - result = _nbu2ss_epn_in_data(udc, ep, req, iBufSize); + i_buf_size = req->req.length - req->req.actual; + if (i_buf_size > 0) + result = _nbu2ss_epn_in_data(udc, ep, req, i_buf_size); else if (req->req.length == 0) _nbu2ss_zero_len_pkt(udc, ep->epnum); @@ -1252,7 +1256,7 @@ static int _nbu2ss_start_transfer( } } else { - /* EPn */ + /* EPN */ if (ep->direct == USB_DIR_OUT) { /* OUT */ if (!bflag) @@ -1281,7 +1285,7 @@ static void _nbu2ss_restert_transfer(struct nbu2ss_ep *ep) length = _nbu2ss_readl( &ep->udc->p_regs->EP_REGS[ep->epnum - 1].EP_LEN_DCNT); - length &= EPn_LDATA; + length &= EPN_LDATA; if (length < ep->ep.maxpacket) bflag = TRUE; } @@ -1304,9 +1308,9 @@ static void _nbu2ss_endpoint_toggle_reset( num = (ep_adrs & 0x7F) - 1; if (ep_adrs & USB_DIR_IN) - data = EPn_IPIDCLR; + data = EPN_IPIDCLR; else - data = EPn_BCLR | EPn_OPIDCLR; + data = EPN_BCLR | EPN_OPIDCLR; _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); } @@ -1341,9 +1345,9 @@ static void _nbu2ss_set_endpoint_stall( ep->halted = TRUE; if (ep_adrs & USB_DIR_IN) - data = EPn_BCLR | EPn_ISTL; + data = EPN_BCLR | EPN_ISTL; else - data = EPn_OSTL_EN | EPn_OSTL; + data = EPN_OSTL_EN | EPN_OSTL; _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data); } else { @@ -1351,13 +1355,13 @@ static void _nbu2ss_set_endpoint_stall( ep->stalled = FALSE; if (ep_adrs & USB_DIR_IN) { _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL - , EPn_ISTL); + , EPN_ISTL); } else { data = _nbu2ss_readl(&preg->EP_REGS[num].EP_CONTROL); - data &= ~EPn_OSTL; - data |= EPn_OSTL_EN; + data &= ~EPN_OSTL; + data |= EPN_OSTL_EN; _nbu2ss_writel(&preg->EP_REGS[num].EP_CONTROL , data); @@ -1453,13 +1457,13 @@ static int _nbu2ss_get_ep_stall(struct nbu2ss_udc *udc, u8 ep_adrs) } else { data = _nbu2ss_readl(&preg->EP_REGS[epnum - 1].EP_CONTROL); - if ((data & EPn_EN) == 0) + if ((data & EPN_EN) == 0) return -1; if (ep_adrs & USB_ENDPOINT_DIR_MASK) - bit_data = EPn_ISTL; + bit_data = EPN_ISTL; else - bit_data = EPn_OSTL; + bit_data = EPN_OSTL; } if ((data & bit_data) == 0) @@ -1548,7 +1552,7 @@ static void _nbu2ss_epn_set_stall( regdata = _nbu2ss_readl( &preg->EP_REGS[ep->epnum - 1].EP_STATUS); - if ((regdata & EPn_IN_DATA) == 0) + if ((regdata & EPN_IN_DATA) == 0) break; mdelay(1); @@ -1651,7 +1655,7 @@ static int std_req_set_address(struct nbu2ss_udc *udc) /*-------------------------------------------------------------------------*/ static int std_req_set_configuration(struct nbu2ss_udc *udc) { - u32 ConfigValue = (u32)(udc->ctrl.wValue & 0x00ff); + u32 config_value = (u32)(udc->ctrl.wValue & 0x00ff); if ((udc->ctrl.wIndex != 0x0000) || (udc->ctrl.wLength != 0x0000) || @@ -1659,9 +1663,9 @@ static int std_req_set_configuration(struct nbu2ss_udc *udc) return -EINVAL; } - udc->curr_config = ConfigValue; + udc->curr_config = config_value; - if (ConfigValue > 0) { + if (config_value > 0) { _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, CONF); udc->devstate = USB_STATE_CONFIGURED; @@ -1968,7 +1972,7 @@ static inline void _nbu2ss_epn_in_int( status = _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_STATUS); - if ((status & EPn_IN_FULL) == 0) { + if ((status & EPN_IN_FULL) == 0) { /*-----------------------------------------*/ /* 0 Length Packet */ req->zero = false; @@ -2059,18 +2063,18 @@ static inline void _nbu2ss_epn_out_dma_int( } ep_dmacnt = _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT) - & EPn_DMACNT; + & EPN_DMACNT; ep_dmacnt >>= 16; for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) { dmacnt = _nbu2ss_readl(&preg->EP_DCR[num].EP_DCR1) - & DCR1_EPn_DMACNT; + & DCR1_EPN_DMACNT; dmacnt >>= 16; if (ep_dmacnt == dmacnt) break; } - _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPn_REQEN); + _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPN_REQEN); if (dmacnt != 0) { mpkt = ep->ep.maxpacket; @@ -2117,20 +2121,20 @@ static inline void _nbu2ss_epn_int(struct nbu2ss_udc *udc, u32 epnum) return; } - if (status & EPn_OUT_END_INT) { - status &= ~EPn_OUT_INT; + if (status & EPN_OUT_END_INT) { + status &= ~EPN_OUT_INT; _nbu2ss_epn_out_dma_int(udc, ep, req); } - if (status & EPn_OUT_INT) + if (status & EPN_OUT_INT) _nbu2ss_epn_out_int(udc, ep, req); - if (status & EPn_IN_END_INT) { - status &= ~EPn_IN_INT; + if (status & EPN_IN_END_INT) { + status &= ~EPN_IN_INT; _nbu2ss_epn_in_dma_int(udc, ep, req); } - if (status & EPn_IN_INT) + if (status & EPN_IN_INT) _nbu2ss_epn_in_int(udc, ep, req); } @@ -2231,9 +2235,9 @@ static void _nbu2ss_fifo_flush(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) _nbu2ss_bitset(&p->EP0_CONTROL, EP0_BCLR); } else { - /* EPn */ + /* EPN */ _nbu2ss_ep_dma_abort(udc, ep); - _nbu2ss_bitset(&p->EP_REGS[ep->epnum - 1].EP_CONTROL, EPn_BCLR); + _nbu2ss_bitset(&p->EP_REGS[ep->epnum - 1].EP_CONTROL, EPN_BCLR); } } @@ -2478,7 +2482,7 @@ static irqreturn_t _nbu2ss_udc_irq(int irq, void *_udc) suspend_flag = 1; } - if (status & EPn_INT) { + if (status & EPN_INT) { /* EP INT */ int_bit = status >> 8; @@ -2651,7 +2655,9 @@ static int nbu2ss_ep_queue( } req = container_of(_req, struct nbu2ss_req, req); - if (unlikely(!_req->complete || !_req->buf || !list_empty(&req->queue))) { + if (unlikely(!_req->complete || + !_req->buf || + !list_empty(&req->queue))) { if (!_req->complete) pr_err("udc: %s --- !_req->complete\n", __func__); @@ -2868,7 +2874,7 @@ static int nbu2ss_ep_fifo_status(struct usb_ep *_ep) } else { data = _nbu2ss_readl(&preg->EP_REGS[ep->epnum - 1].EP_LEN_DCNT) - & EPn_LDATA; + & EPN_LDATA; } spin_unlock_irqrestore(&udc->lock, flags); diff --git a/drivers/staging/emxx_udc/emxx_udc.h b/drivers/staging/emxx_udc/emxx_udc.h index 78c08e15a1f9..928d531a5115 100644 --- a/drivers/staging/emxx_udc/emxx_udc.h +++ b/drivers/staging/emxx_udc/emxx_udc.h @@ -144,7 +144,7 @@ /*------- (0x001C) Setup Data 1 Register */ /*------- (0x0020) USB Interrupt Status Register */ -#define EPn_INT 0x00FFFF00 +#define EPN_INT 0x00FFFF00 #define EP15_INT BIT23 #define EP14_INT BIT22 #define EP13_INT BIT21 @@ -264,102 +264,102 @@ /*------- (0x0038) EP0 Read Register */ /*------- (0x003C) EP0 Write Register */ -/*------- (0x0040:) EPn Control Register */ -#define EPn_EN BIT31 -#define EPn_BUF_TYPE BIT30 -#define EPn_BUF_SINGLE BIT30 - -#define EPn_DIR0 BIT26 -#define EPn_MODE (BIT25 + BIT24) -#define EPn_BULK 0 -#define EPn_INTERRUPT BIT24 -#define EPn_ISO BIT25 - -#define EPn_OVERSEL BIT17 -#define EPn_AUTO BIT16 - -#define EPn_IPIDCLR BIT11 -#define EPn_OPIDCLR BIT10 -#define EPn_BCLR BIT09 -#define EPn_CBCLR BIT08 -#define EPn_DEND BIT07 -#define EPn_DW (BIT06 + BIT05) -#define EPn_DW4 0 -#define EPn_DW3 (BIT06 + BIT05) -#define EPn_DW2 BIT06 -#define EPn_DW1 BIT05 - -#define EPn_OSTL_EN BIT04 -#define EPn_ISTL BIT03 -#define EPn_OSTL BIT02 - -#define EPn_ONAK BIT00 - -/*------- (0x0044:) EPn Status Register */ -#define EPn_ISO_PIDERR BIT29 /* R */ -#define EPn_OPID BIT28 /* R */ -#define EPn_OUT_NOTKN BIT27 /* R */ -#define EPn_ISO_OR BIT26 /* R */ - -#define EPn_ISO_CRC BIT24 /* R */ -#define EPn_OUT_END_INT BIT23 /* RW */ -#define EPn_OUT_OR_INT BIT22 /* RW */ -#define EPn_OUT_NAK_ERR_INT BIT21 /* RW */ -#define EPn_OUT_STALL_INT BIT20 /* RW */ -#define EPn_OUT_INT BIT19 /* RW */ -#define EPn_OUT_NULL_INT BIT18 /* RW */ -#define EPn_OUT_FULL BIT17 /* R */ -#define EPn_OUT_EMPTY BIT16 /* R */ - -#define EPn_IPID BIT10 /* R */ -#define EPn_IN_NOTKN BIT09 /* R */ -#define EPn_ISO_UR BIT08 /* R */ -#define EPn_IN_END_INT BIT07 /* RW */ - -#define EPn_IN_NAK_ERR_INT BIT05 /* RW */ -#define EPn_IN_STALL_INT BIT04 /* RW */ -#define EPn_IN_INT BIT03 /* RW */ -#define EPn_IN_DATA BIT02 /* R */ -#define EPn_IN_FULL BIT01 /* R */ -#define EPn_IN_EMPTY BIT00 /* R */ - -#define EPn_INT_EN \ - (EPn_OUT_END_INT | EPn_OUT_INT | EPn_IN_END_INT | EPn_IN_INT) - -/*------- (0x0048:) EPn Interrupt Enable Register */ -#define EPn_OUT_END_EN BIT23 /* RW */ -#define EPn_OUT_OR_EN BIT22 /* RW */ -#define EPn_OUT_NAK_ERR_EN BIT21 /* RW */ -#define EPn_OUT_STALL_EN BIT20 /* RW */ -#define EPn_OUT_EN BIT19 /* RW */ -#define EPn_OUT_NULL_EN BIT18 /* RW */ - -#define EPn_IN_END_EN BIT07 /* RW */ - -#define EPn_IN_NAK_ERR_EN BIT05 /* RW */ -#define EPn_IN_STALL_EN BIT04 /* RW */ -#define EPn_IN_EN BIT03 /* RW */ - -/*------- (0x004C:) EPn Interrupt Enable Register */ -#define EPn_STOP_MODE BIT11 -#define EPn_DEND_SET BIT10 -#define EPn_BURST_SET BIT09 -#define EPn_STOP_SET BIT08 - -#define EPn_DMA_EN BIT04 - -#define EPn_DMAMODE0 BIT00 - -/*------- (0x0050:) EPn MaxPacket & BaseAddress Register */ -#define EPn_BASEAD 0x1FFF0000 -#define EPn_MPKT 0x000007FF - -/*------- (0x0054:) EPn Length & DMA Count Register */ -#define EPn_DMACNT 0x01FF0000 -#define EPn_LDATA 0x000007FF - -/*------- (0x0058:) EPn Read Register */ -/*------- (0x005C:) EPn Write Register */ +/*------- (0x0040:) EPN Control Register */ +#define EPN_EN BIT31 +#define EPN_BUF_TYPE BIT30 +#define EPN_BUF_SINGLE BIT30 + +#define EPN_DIR0 BIT26 +#define EPN_MODE (BIT25 + BIT24) +#define EPN_BULK 0 +#define EPN_INTERRUPT BIT24 +#define EPN_ISO BIT25 + +#define EPN_OVERSEL BIT17 +#define EPN_AUTO BIT16 + +#define EPN_IPIDCLR BIT11 +#define EPN_OPIDCLR BIT10 +#define EPN_BCLR BIT09 +#define EPN_CBCLR BIT08 +#define EPN_DEND BIT07 +#define EPN_DW (BIT06 + BIT05) +#define EPN_DW4 0 +#define EPN_DW3 (BIT06 + BIT05) +#define EPN_DW2 BIT06 +#define EPN_DW1 BIT05 + +#define EPN_OSTL_EN BIT04 +#define EPN_ISTL BIT03 +#define EPN_OSTL BIT02 + +#define EPN_ONAK BIT00 + +/*------- (0x0044:) EPN Status Register */ +#define EPN_ISO_PIDERR BIT29 /* R */ +#define EPN_OPID BIT28 /* R */ +#define EPN_OUT_NOTKN BIT27 /* R */ +#define EPN_ISO_OR BIT26 /* R */ + +#define EPN_ISO_CRC BIT24 /* R */ +#define EPN_OUT_END_INT BIT23 /* RW */ +#define EPN_OUT_OR_INT BIT22 /* RW */ +#define EPN_OUT_NAK_ERR_INT BIT21 /* RW */ +#define EPN_OUT_STALL_INT BIT20 /* RW */ +#define EPN_OUT_INT BIT19 /* RW */ +#define EPN_OUT_NULL_INT BIT18 /* RW */ +#define EPN_OUT_FULL BIT17 /* R */ +#define EPN_OUT_EMPTY BIT16 /* R */ + +#define EPN_IPID BIT10 /* R */ +#define EPN_IN_NOTKN BIT09 /* R */ +#define EPN_ISO_UR BIT08 /* R */ +#define EPN_IN_END_INT BIT07 /* RW */ + +#define EPN_IN_NAK_ERR_INT BIT05 /* RW */ +#define EPN_IN_STALL_INT BIT04 /* RW */ +#define EPN_IN_INT BIT03 /* RW */ +#define EPN_IN_DATA BIT02 /* R */ +#define EPN_IN_FULL BIT01 /* R */ +#define EPN_IN_EMPTY BIT00 /* R */ + +#define EPN_INT_EN \ + (EPN_OUT_END_INT | EPN_OUT_INT | EPN_IN_END_INT | EPN_IN_INT) + +/*------- (0x0048:) EPN Interrupt Enable Register */ +#define EPN_OUT_END_EN BIT23 /* RW */ +#define EPN_OUT_OR_EN BIT22 /* RW */ +#define EPN_OUT_NAK_ERR_EN BIT21 /* RW */ +#define EPN_OUT_STALL_EN BIT20 /* RW */ +#define EPN_OUT_EN BIT19 /* RW */ +#define EPN_OUT_NULL_EN BIT18 /* RW */ + +#define EPN_IN_END_EN BIT07 /* RW */ + +#define EPN_IN_NAK_ERR_EN BIT05 /* RW */ +#define EPN_IN_STALL_EN BIT04 /* RW */ +#define EPN_IN_EN BIT03 /* RW */ + +/*------- (0x004C:) EPN Interrupt Enable Register */ +#define EPN_STOP_MODE BIT11 +#define EPN_DEND_SET BIT10 +#define EPN_BURST_SET BIT09 +#define EPN_STOP_SET BIT08 + +#define EPN_DMA_EN BIT04 + +#define EPN_DMAMODE0 BIT00 + +/*------- (0x0050:) EPN MaxPacket & BaseAddress Register */ +#define EPN_BASEAD 0x1FFF0000 +#define EPN_MPKT 0x000007FF + +/*------- (0x0054:) EPN Length & DMA Count Register */ +#define EPN_DMACNT 0x01FF0000 +#define EPN_LDATA 0x000007FF + +/*------- (0x0058:) EPN Read Register */ +/*------- (0x005C:) EPN Write Register */ /*------- (0x1000) AHBSCTR Register */ #define WAIT_MODE BIT00 @@ -428,19 +428,19 @@ #define EP_AVAILABLE 0xFFFF0000 /* R */ #define DMA_AVAILABLE 0x0000FFFF /* R */ -/*------- (0x1110:) EPnDCR1 Register */ -#define DCR1_EPn_DMACNT 0x00FF0000 /* RW */ +/*------- (0x1110:) EPNDCR1 Register */ +#define DCR1_EPN_DMACNT 0x00FF0000 /* RW */ -#define DCR1_EPn_DIR0 BIT01 /* RW */ -#define DCR1_EPn_REQEN BIT00 /* RW */ +#define DCR1_EPN_DIR0 BIT01 /* RW */ +#define DCR1_EPN_REQEN BIT00 /* RW */ -/*------- (0x1114:) EPnDCR2 Register */ -#define DCR2_EPn_LMPKT 0x07FF0000 /* RW */ +/*------- (0x1114:) EPNDCR2 Register */ +#define DCR2_EPN_LMPKT 0x07FF0000 /* RW */ -#define DCR2_EPn_MPKT 0x000007FF /* RW */ +#define DCR2_EPN_MPKT 0x000007FF /* RW */ -/*------- (0x1118:) EPnTADR Register */ -#define EPn_TADR 0xFFFFFFFF /* RW */ +/*------- (0x1118:) EPNTADR Register */ +#define EPN_TADR 0xFFFFFFFF /* RW */ /*===========================================================================*/ /* Struct */ @@ -471,7 +471,7 @@ struct fc_regs { u32 USB_ADDRESS; /* (0x0008) USB Address */ u32 UTMI_CHARACTER_1; /* (0x000C) UTMI Setting */ u32 TEST_CONTROL; /* (0x0010) TEST Control */ - u32 Reserved_14; /* (0x0014) Reserved */ + u32 reserved_14; /* (0x0014) Reserved */ u32 SETUP_DATA0; /* (0x0018) Setup Data0 */ u32 SETUP_DATA1; /* (0x001C) Setup Data1 */ u32 USB_INT_STA; /* (0x0020) USB Interrupt Status */ @@ -485,7 +485,7 @@ struct fc_regs { struct ep_regs EP_REGS[REG_EP_NUM]; /* Endpoint Register */ - u8 Reserved220[0x1000 - 0x220]; /* (0x0220:0x0FFF) Reserved */ + u8 reserved_220[0x1000 - 0x220]; /* (0x0220:0x0FFF) Reserved */ u32 AHBSCTR; /* (0x1000) AHBSCTR */ u32 AHBMCTR; /* (0x1004) AHBMCTR */ @@ -494,25 +494,25 @@ struct fc_regs { u32 EPCTR; /* (0x1010) EPCTR */ u32 USBF_EPTEST; /* (0x1014) USBF_EPTEST */ - u8 Reserved1018[0x20 - 0x18]; /* (0x1018:0x101F) Reserved */ + u8 reserved_1018[0x20 - 0x18]; /* (0x1018:0x101F) Reserved */ u32 USBSSVER; /* (0x1020) USBSSVER */ u32 USBSSCONF; /* (0x1024) USBSSCONF */ - u8 Reserved1028[0x110 - 0x28]; /* (0x1028:0x110F) Reserved */ + u8 reserved_1028[0x110 - 0x28]; /* (0x1028:0x110F) Reserved */ struct ep_dcr EP_DCR[REG_EP_NUM]; /* */ - u8 Reserved1200[0x1000 - 0x200]; /* Reserved */ + u8 reserved_1200[0x1000 - 0x200]; /* Reserved */ } __aligned(32); #define EP0_PACKETSIZE 64 #define EP_PACKETSIZE 1024 -/* EPn RAM SIZE */ +/* EPN RAM SIZE */ #define D_RAM_SIZE_CTRL 64 -/* EPn Bulk Endpoint Max Packet Size */ +/* EPN Bulk Endpoint Max Packet Size */ #define D_FS_RAM_SIZE_BULK 64 #define D_HS_RAM_SIZE_BULK 512 diff --git a/drivers/staging/fbtft/fb_agm1264k-fl.c b/drivers/staging/fbtft/fb_agm1264k-fl.c index 489151a6bf80..456a8dd65caf 100644 --- a/drivers/staging/fbtft/fb_agm1264k-fl.c +++ b/drivers/staging/fbtft/fb_agm1264k-fl.c @@ -282,10 +282,10 @@ static void iterate_diffusion_matrix(u32 xres, u32 yres, int x, continue; write_pos = &convert_buf[(y + j) * xres + x + i]; coeff = diffusing_matrix[i][j]; - if (-1 == coeff) + if (-1 == coeff) { /* pixel itself */ *write_pos = pixel; - else { + } else { signed short p = *write_pos + error * coeff; if (p > WHITE) diff --git a/drivers/staging/fbtft/fb_hx8340bn.c b/drivers/staging/fbtft/fb_hx8340bn.c index 1ca1fcd353d6..fbd5ef525243 100644 --- a/drivers/staging/fbtft/fb_hx8340bn.c +++ b/drivers/staging/fbtft/fb_hx8340bn.c @@ -157,7 +157,7 @@ static int set_var(struct fbtft_par *par) * OP0 OP1 CP0 CP1 CP2 CP3 CP4 MP0 MP1 MP2 MP3 MP4 MP5 CGM0 CGM1 * ON0 ON1 CN0 CN1 CN2 CN3 CN4 MN0 MN1 MN2 MN3 MN4 MN5 XXXX GC */ -#define CURVE(num, idx) curves[num * par->gamma.num_values + idx] +#define CURVE(num, idx) curves[(num) * par->gamma.num_values + (idx)] static int set_gamma(struct fbtft_par *par, u32 *curves) { unsigned long mask[] = { diff --git a/drivers/staging/fbtft/fbtft-io.c b/drivers/staging/fbtft/fbtft-io.c index d86840548b74..ffb9a3b4d454 100644 --- a/drivers/staging/fbtft/fbtft-io.c +++ b/drivers/staging/fbtft/fbtft-io.c @@ -71,7 +71,7 @@ int fbtft_write_spi_emulate_9(struct fbtft_par *par, void *buf, size_t len) src++; } tmp |= ((*src & 0x0100) ? 1 : 0); - *(u64 *)dst = cpu_to_be64(tmp); + *(__be64 *)dst = cpu_to_be64(tmp); dst += 8; *dst++ = (u8)(*src++ & 0x00FF); added++; diff --git a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c index 6f9eed66c64d..b9a0a315e6fb 100644 --- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c +++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c @@ -37,9 +37,9 @@ #include <linux/interrupt.h> #include <linux/msi.h> #include <linux/kthread.h> +#include <linux/iommu.h> #include "../../fsl-mc/include/mc.h" -#include "../../fsl-mc/include/mc-sys.h" #include "dpaa2-eth.h" /* CREATE_TRACE_POINTS only needs to be defined once. Other dpa files @@ -54,6 +54,16 @@ MODULE_DESCRIPTION("Freescale DPAA2 Ethernet Driver"); const char dpaa2_eth_drv_version[] = "0.1"; +static void *dpaa2_iova_to_virt(struct iommu_domain *domain, + dma_addr_t iova_addr) +{ + phys_addr_t phys_addr; + + phys_addr = domain ? iommu_iova_to_phys(domain, iova_addr) : iova_addr; + + return phys_to_virt(phys_addr); +} + static void validate_rx_csum(struct dpaa2_eth_priv *priv, u32 fd_status, struct sk_buff *skb) @@ -98,12 +108,11 @@ static void free_rx_fd(struct dpaa2_eth_priv *priv, sgt = vaddr + dpaa2_fd_get_offset(fd); for (i = 0; i < DPAA2_ETH_MAX_SG_ENTRIES; i++) { addr = dpaa2_sg_get_addr(&sgt[i]); + sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr); dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUF_SIZE, DMA_FROM_DEVICE); - sg_vaddr = phys_to_virt(addr); skb_free_frag(sg_vaddr); - if (dpaa2_sg_is_final(&sgt[i])) break; } @@ -159,10 +168,10 @@ static struct sk_buff *build_frag_skb(struct dpaa2_eth_priv *priv, /* Get the address and length from the S/G entry */ sg_addr = dpaa2_sg_get_addr(sge); + sg_vaddr = dpaa2_iova_to_virt(priv->iommu_domain, sg_addr); dma_unmap_single(dev, sg_addr, DPAA2_ETH_RX_BUF_SIZE, DMA_FROM_DEVICE); - sg_vaddr = phys_to_virt(sg_addr); sg_length = dpaa2_sg_get_len(sge); if (i == 0) { @@ -217,16 +226,19 @@ static void dpaa2_eth_rx(struct dpaa2_eth_priv *priv, struct dpaa2_eth_drv_stats *percpu_extras; struct device *dev = priv->net_dev->dev.parent; struct dpaa2_fas *fas; + void *buf_data; u32 status = 0; /* Tracing point */ trace_dpaa2_rx_fd(priv->net_dev, fd); + vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr); dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUF_SIZE, DMA_FROM_DEVICE); - vaddr = phys_to_virt(addr); - prefetch(vaddr + priv->buf_layout.private_data_size); - prefetch(vaddr + dpaa2_fd_get_offset(fd)); + fas = dpaa2_get_fas(vaddr); + prefetch(fas); + buf_data = vaddr + dpaa2_fd_get_offset(fd); + prefetch(buf_data); percpu_stats = this_cpu_ptr(priv->percpu_stats); percpu_extras = this_cpu_ptr(priv->percpu_extras); @@ -234,9 +246,7 @@ static void dpaa2_eth_rx(struct dpaa2_eth_priv *priv, if (fd_format == dpaa2_fd_single) { skb = build_linear_skb(priv, ch, fd, vaddr); } else if (fd_format == dpaa2_fd_sg) { - struct dpaa2_sg_entry *sgt = - vaddr + dpaa2_fd_get_offset(fd); - skb = build_frag_skb(priv, ch, sgt); + skb = build_frag_skb(priv, ch, buf_data); skb_free_frag(vaddr); percpu_extras->rx_sg_frames++; percpu_extras->rx_sg_bytes += dpaa2_fd_get_len(fd); @@ -252,8 +262,6 @@ static void dpaa2_eth_rx(struct dpaa2_eth_priv *priv, /* Check if we need to validate the L4 csum */ if (likely(dpaa2_fd_get_frc(fd) & DPAA2_FD_FRC_FASV)) { - fas = (struct dpaa2_fas *) - (vaddr + priv->buf_layout.private_data_size); status = le32_to_cpu(fas->status); validate_rx_csum(priv, status, skb); } @@ -263,10 +271,7 @@ static void dpaa2_eth_rx(struct dpaa2_eth_priv *priv, percpu_stats->rx_packets++; percpu_stats->rx_bytes += dpaa2_fd_get_len(fd); - if (priv->net_dev->features & NETIF_F_GRO) - napi_gro_receive(napi, skb); - else - netif_receive_skb(skb); + napi_gro_receive(napi, skb); return; @@ -320,7 +325,6 @@ static int build_sg_fd(struct dpaa2_eth_priv *priv, { struct device *dev = priv->net_dev->dev.parent; void *sgt_buf = NULL; - void *hwa; dma_addr_t addr; int nr_frags = skb_shinfo(skb)->nr_frags; struct dpaa2_sg_entry *sgt; @@ -330,6 +334,7 @@ static int build_sg_fd(struct dpaa2_eth_priv *priv, int num_sg; int num_dma_bufs; struct dpaa2_eth_swa *swa; + struct dpaa2_fas *fas; /* Create and map scatterlist. * We don't advertise NETIF_F_FRAGLIST, so skb_to_sgvec() will not have @@ -345,7 +350,7 @@ static int build_sg_fd(struct dpaa2_eth_priv *priv, sg_init_table(scl, nr_frags + 1); num_sg = skb_to_sgvec(skb, scl, 0, skb->len); - num_dma_bufs = dma_map_sg(dev, scl, num_sg, DMA_TO_DEVICE); + num_dma_bufs = dma_map_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL); if (unlikely(!num_dma_bufs)) { err = -ENOMEM; goto dma_map_sg_failed; @@ -366,8 +371,8 @@ static int build_sg_fd(struct dpaa2_eth_priv *priv, * on TX confirmation. We are clearing FAS (Frame Annotation Status) * field from the hardware annotation area */ - hwa = sgt_buf + priv->buf_layout.private_data_size; - memset(hwa + DPAA2_FAS_OFFSET, 0, DPAA2_FAS_SIZE); + fas = dpaa2_get_fas(sgt_buf); + memset(fas, 0, DPAA2_FAS_SIZE); sgt = (struct dpaa2_sg_entry *)(sgt_buf + priv->tx_data_offset); @@ -396,7 +401,7 @@ static int build_sg_fd(struct dpaa2_eth_priv *priv, swa->num_dma_bufs = num_dma_bufs; /* Separately map the SGT buffer */ - addr = dma_map_single(dev, sgt_buf, sgt_buf_size, DMA_TO_DEVICE); + addr = dma_map_single(dev, sgt_buf, sgt_buf_size, DMA_BIDIRECTIONAL); if (unlikely(dma_mapping_error(dev, addr))) { err = -ENOMEM; goto dma_map_single_failed; @@ -413,7 +418,7 @@ static int build_sg_fd(struct dpaa2_eth_priv *priv, dma_map_single_failed: kfree(sgt_buf); sgt_buf_alloc_failed: - dma_unmap_sg(dev, scl, num_sg, DMA_TO_DEVICE); + dma_unmap_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL); dma_map_sg_failed: kfree(scl); return err; @@ -426,7 +431,7 @@ static int build_single_fd(struct dpaa2_eth_priv *priv, { struct device *dev = priv->net_dev->dev.parent; u8 *buffer_start; - void *hwa; + struct dpaa2_fas *fas; struct sk_buff **skbh; dma_addr_t addr; @@ -439,8 +444,8 @@ static int build_single_fd(struct dpaa2_eth_priv *priv, * on TX confirmation. We are clearing FAS (Frame Annotation Status) * field from the hardware annotation area */ - hwa = buffer_start + priv->buf_layout.private_data_size; - memset(hwa + DPAA2_FAS_OFFSET, 0, DPAA2_FAS_SIZE); + fas = dpaa2_get_fas(buffer_start); + memset(fas, 0, DPAA2_FAS_SIZE); /* Store a backpointer to the skb at the beginning of the buffer * (in the private data area) such that we can release it @@ -451,7 +456,7 @@ static int build_single_fd(struct dpaa2_eth_priv *priv, addr = dma_map_single(dev, buffer_start, skb_tail_pointer(skb) - buffer_start, - DMA_TO_DEVICE); + DMA_BIDIRECTIONAL); if (unlikely(dma_mapping_error(dev, addr))) return -ENOMEM; @@ -490,7 +495,8 @@ static void free_tx_fd(const struct dpaa2_eth_priv *priv, struct dpaa2_fas *fas; fd_addr = dpaa2_fd_get_addr(fd); - skbh = phys_to_virt(fd_addr); + skbh = dpaa2_iova_to_virt(priv->iommu_domain, fd_addr); + fas = dpaa2_get_fas(skbh); if (fd_format == dpaa2_fd_single) { skb = *skbh; @@ -500,7 +506,7 @@ static void free_tx_fd(const struct dpaa2_eth_priv *priv, */ dma_unmap_single(dev, fd_addr, skb_tail_pointer(skb) - buffer_start, - DMA_TO_DEVICE); + DMA_BIDIRECTIONAL); } else if (fd_format == dpaa2_fd_sg) { swa = (struct dpaa2_eth_swa *)skbh; skb = swa->skb; @@ -509,13 +515,13 @@ static void free_tx_fd(const struct dpaa2_eth_priv *priv, num_dma_bufs = swa->num_dma_bufs; /* Unmap the scatterlist */ - dma_unmap_sg(dev, scl, num_sg, DMA_TO_DEVICE); + dma_unmap_sg(dev, scl, num_sg, DMA_BIDIRECTIONAL); kfree(scl); /* Unmap the SGT buffer */ unmap_size = priv->tx_data_offset + sizeof(struct dpaa2_sg_entry) * (1 + num_dma_bufs); - dma_unmap_single(dev, fd_addr, unmap_size, DMA_TO_DEVICE); + dma_unmap_single(dev, fd_addr, unmap_size, DMA_BIDIRECTIONAL); } else { /* Unsupported format, mark it as errored and give up */ if (status) @@ -527,11 +533,8 @@ static void free_tx_fd(const struct dpaa2_eth_priv *priv, * buffer but before we free it. The caller function is responsible * for checking the status value. */ - if (status && (dpaa2_fd_get_frc(fd) & DPAA2_FD_FRC_FASV)) { - fas = (struct dpaa2_fas *) - ((void *)skbh + priv->buf_layout.private_data_size); + if (status) *status = le32_to_cpu(fas->status); - } /* Free SGT buffer kmalloc'ed on tx */ if (fd_format != dpaa2_fd_single) @@ -541,7 +544,7 @@ static void free_tx_fd(const struct dpaa2_eth_priv *priv, dev_kfree_skb(skb); } -static int dpaa2_eth_tx(struct sk_buff *skb, struct net_device *net_dev) +static netdev_tx_t dpaa2_eth_tx(struct sk_buff *skb, struct net_device *net_dev) { struct dpaa2_eth_priv *priv = netdev_priv(net_dev); struct dpaa2_fd fd; @@ -634,6 +637,8 @@ static void dpaa2_eth_tx_conf(struct dpaa2_eth_priv *priv, struct rtnl_link_stats64 *percpu_stats; struct dpaa2_eth_drv_stats *percpu_extras; u32 status = 0; + u32 fd_errors; + bool has_fas_errors = false; /* Tracing point */ trace_dpaa2_tx_conf_fd(priv->net_dev, fd); @@ -642,13 +647,31 @@ static void dpaa2_eth_tx_conf(struct dpaa2_eth_priv *priv, percpu_extras->tx_conf_frames++; percpu_extras->tx_conf_bytes += dpaa2_fd_get_len(fd); - free_tx_fd(priv, fd, &status); - - if (unlikely(status & DPAA2_ETH_TXCONF_ERR_MASK)) { - percpu_stats = this_cpu_ptr(priv->percpu_stats); - /* Tx-conf logically pertains to the egress path. */ - percpu_stats->tx_errors++; + /* Check frame errors in the FD field */ + fd_errors = dpaa2_fd_get_ctrl(fd) & DPAA2_FD_TX_ERR_MASK; + if (unlikely(fd_errors)) { + /* We only check error bits in the FAS field if corresponding + * FAERR bit is set in FD and the FAS field is marked as valid + */ + has_fas_errors = (fd_errors & DPAA2_FD_CTRL_FAERR) && + !!(dpaa2_fd_get_frc(fd) & DPAA2_FD_FRC_FASV); + if (net_ratelimit()) + netdev_dbg(priv->net_dev, "TX frame FD error: %x08\n", + fd_errors); } + + free_tx_fd(priv, fd, has_fas_errors ? &status : NULL); + + if (likely(!fd_errors)) + return; + + percpu_stats = this_cpu_ptr(priv->percpu_stats); + /* Tx-conf logically pertains to the egress path. */ + percpu_stats->tx_errors++; + + if (has_fas_errors && net_ratelimit()) + netdev_dbg(priv->net_dev, "TX frame FAS error: %x08\n", + status & DPAA2_FAS_TX_ERR_MASK); } static int set_rx_csum(struct dpaa2_eth_priv *priv, bool enable) @@ -794,7 +817,7 @@ static void drain_bufs(struct dpaa2_eth_priv *priv, int count) int ret, i; do { - ret = dpaa2_io_service_acquire(NULL, priv->dpbp_attrs.bpid, + ret = dpaa2_io_service_acquire(NULL, priv->bpid, buf_array, count); if (ret < 0) { netdev_err(priv->net_dev, "dpaa2_io_service_acquire() failed\n"); @@ -802,10 +825,11 @@ static void drain_bufs(struct dpaa2_eth_priv *priv, int count) } for (i = 0; i < ret; i++) { /* Same logic as on regular Rx path */ + vaddr = dpaa2_iova_to_virt(priv->iommu_domain, + buf_array[i]); dma_unmap_single(dev, buf_array[i], DPAA2_ETH_RX_BUF_SIZE, DMA_FROM_DEVICE); - vaddr = phys_to_virt(buf_array[i]); skb_free_frag(vaddr); } } while (ret); @@ -890,7 +914,7 @@ static int dpaa2_eth_poll(struct napi_struct *napi, int budget) break; /* Refill pool if appropriate */ - refill_pool(priv, ch, priv->dpbp_attrs.bpid); + refill_pool(priv, ch, priv->bpid); store_cleaned = consume_frames(ch); cleaned += store_cleaned; @@ -964,7 +988,7 @@ static int link_state_update(struct dpaa2_eth_priv *priv) netif_carrier_off(priv->net_dev); } - netdev_info(priv->net_dev, "Link Event: state %s", + netdev_info(priv->net_dev, "Link Event: state %s\n", state.up ? "up" : "down"); return 0; @@ -975,14 +999,14 @@ static int dpaa2_eth_open(struct net_device *net_dev) struct dpaa2_eth_priv *priv = netdev_priv(net_dev); int err; - err = seed_pool(priv, priv->dpbp_attrs.bpid); + err = seed_pool(priv, priv->bpid); if (err) { /* Not much to do; the buffer pool, though not filled up, * may still contain some buffers which would enable us * to limp on. */ netdev_err(net_dev, "Buffer seeding failed for DPBP %d (bpid=%d)\n", - priv->dpbp_dev->obj_desc.id, priv->dpbp_attrs.bpid); + priv->dpbp_dev->obj_desc.id, priv->bpid); } /* We'll only start the txqs when the link is actually ready; make sure @@ -1151,8 +1175,8 @@ static int dpaa2_eth_set_addr(struct net_device *net_dev, void *addr) /** Fill in counters maintained by the GPP driver. These may be different from * the hardware counters obtained by ethtool. */ -void dpaa2_eth_get_stats(struct net_device *net_dev, - struct rtnl_link_stats64 *stats) +static void dpaa2_eth_get_stats(struct net_device *net_dev, + struct rtnl_link_stats64 *stats) { struct dpaa2_eth_priv *priv = netdev_priv(net_dev); struct rtnl_link_stats64 *percpu_stats; @@ -1502,6 +1526,7 @@ static int setup_dpio(struct dpaa2_eth_priv *priv) if (!channel) { dev_info(dev, "No affine channel for cpu %d and above\n", i); + err = -ENODEV; goto err_alloc_ch; } @@ -1516,10 +1541,13 @@ static int setup_dpio(struct dpaa2_eth_priv *priv) /* Register the new context */ err = dpaa2_io_service_register(NULL, nctx); if (err) { - dev_info(dev, "No affine DPIO for cpu %d\n", i); + dev_dbg(dev, "No affine DPIO for cpu %d\n", i); /* If no affine DPIO for this core, there's probably - * none available for next cores either. + * none available for next cores either. Signal we want + * to retry later, in case the DPIO devices weren't + * probed yet. */ + err = -EPROBE_DEFER; goto err_service_reg; } @@ -1557,7 +1585,7 @@ err_service_reg: err_alloc_ch: if (cpumask_empty(&priv->dpio_cpumask)) { dev_err(dev, "No cpu with an affine DPIO/DPCON\n"); - return -ENODEV; + return err; } dev_info(dev, "Cores %*pbl available for processing ingress traffic\n", @@ -1662,6 +1690,7 @@ static int setup_dpbp(struct dpaa2_eth_priv *priv) int err; struct fsl_mc_device *dpbp_dev; struct device *dev = priv->net_dev->dev.parent; + struct dpbp_attr dpbp_attrs; err = fsl_mc_object_allocate(to_fsl_mc_device(dev), FSL_MC_POOL_DPBP, &dpbp_dev); @@ -1679,6 +1708,12 @@ static int setup_dpbp(struct dpaa2_eth_priv *priv) goto err_open; } + err = dpbp_reset(priv->mc_io, 0, dpbp_dev->mc_handle); + if (err) { + dev_err(dev, "dpbp_reset() failed\n"); + goto err_reset; + } + err = dpbp_enable(priv->mc_io, 0, dpbp_dev->mc_handle); if (err) { dev_err(dev, "dpbp_enable() failed\n"); @@ -1686,17 +1721,19 @@ static int setup_dpbp(struct dpaa2_eth_priv *priv) } err = dpbp_get_attributes(priv->mc_io, 0, dpbp_dev->mc_handle, - &priv->dpbp_attrs); + &dpbp_attrs); if (err) { dev_err(dev, "dpbp_get_attributes() failed\n"); goto err_get_attr; } + priv->bpid = dpbp_attrs.bpid; return 0; err_get_attr: dpbp_disable(priv->mc_io, 0, dpbp_dev->mc_handle); err_enable: +err_reset: dpbp_close(priv->mc_io, 0, dpbp_dev->mc_handle); err_open: fsl_mc_object_free(dpbp_dev); @@ -1718,15 +1755,14 @@ static int setup_dpni(struct fsl_mc_device *ls_dev) struct device *dev = &ls_dev->dev; struct dpaa2_eth_priv *priv; struct net_device *net_dev; + struct dpni_buffer_layout buf_layout = {0}; int err; net_dev = dev_get_drvdata(dev); priv = netdev_priv(net_dev); - priv->dpni_id = ls_dev->obj_desc.id; - /* get a handle for the DPNI object */ - err = dpni_open(priv->mc_io, 0, priv->dpni_id, &priv->mc_token); + err = dpni_open(priv->mc_io, 0, ls_dev->obj_desc.id, &priv->mc_token); if (err) { dev_err(dev, "dpni_open() failed\n"); goto err_open; @@ -1750,35 +1786,35 @@ static int setup_dpni(struct fsl_mc_device *ls_dev) /* Configure buffer layouts */ /* rx buffer */ - priv->buf_layout.pass_parser_result = true; - priv->buf_layout.pass_frame_status = true; - priv->buf_layout.private_data_size = DPAA2_ETH_SWA_SIZE; - priv->buf_layout.data_align = DPAA2_ETH_RX_BUF_ALIGN; - priv->buf_layout.options = DPNI_BUF_LAYOUT_OPT_PARSER_RESULT | - DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | - DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE | - DPNI_BUF_LAYOUT_OPT_DATA_ALIGN; + buf_layout.pass_parser_result = true; + buf_layout.pass_frame_status = true; + buf_layout.private_data_size = DPAA2_ETH_SWA_SIZE; + buf_layout.data_align = DPAA2_ETH_RX_BUF_ALIGN; + buf_layout.options = DPNI_BUF_LAYOUT_OPT_PARSER_RESULT | + DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | + DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE | + DPNI_BUF_LAYOUT_OPT_DATA_ALIGN; err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token, - DPNI_QUEUE_RX, &priv->buf_layout); + DPNI_QUEUE_RX, &buf_layout); if (err) { dev_err(dev, "dpni_set_buffer_layout(RX) failed\n"); goto err_buf_layout; } /* tx buffer */ - priv->buf_layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | - DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE; + buf_layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | + DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE; err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token, - DPNI_QUEUE_TX, &priv->buf_layout); + DPNI_QUEUE_TX, &buf_layout); if (err) { dev_err(dev, "dpni_set_buffer_layout(TX) failed\n"); goto err_buf_layout; } /* tx-confirm buffer */ - priv->buf_layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; + buf_layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; err = dpni_set_buffer_layout(priv->mc_io, 0, priv->mc_token, - DPNI_QUEUE_TX_CONFIRM, &priv->buf_layout); + DPNI_QUEUE_TX_CONFIRM, &buf_layout); if (err) { dev_err(dev, "dpni_set_buffer_layout(TX_CONF) failed\n"); goto err_buf_layout; @@ -1795,7 +1831,7 @@ static int setup_dpni(struct fsl_mc_device *ls_dev) } if ((priv->tx_data_offset % 64) != 0) - dev_warn(dev, "Tx data offset (%d) not a multiple of 64B", + dev_warn(dev, "Tx data offset (%d) not a multiple of 64B\n", priv->tx_data_offset); /* Accommodate software annotation space (SWA) */ @@ -1947,7 +1983,7 @@ static const struct dpaa2_eth_hash_fields hash_fields[] = { /* Set RX hash options * flags is a combination of RXH_ bits */ -int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags) +static int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags) { struct device *dev = net_dev->dev.parent; struct dpaa2_eth_priv *priv = netdev_priv(net_dev); @@ -1958,8 +1994,8 @@ int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags) int err = 0; if (!dpaa2_eth_hash_enabled(priv)) { - dev_err(dev, "Hashing support is not enabled\n"); - return -EOPNOTSUPP; + dev_dbg(dev, "Hashing support is not enabled\n"); + return 0; } memset(&cls_cfg, 0, sizeof(cls_cfg)); @@ -1985,23 +2021,23 @@ int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags) priv->rx_hash_fields |= hash_fields[i].rxnfc_field; } - dma_mem = kzalloc(DPAA2_CLASSIFIER_DMA_SIZE, GFP_DMA | GFP_KERNEL); + dma_mem = kzalloc(DPAA2_CLASSIFIER_DMA_SIZE, GFP_KERNEL); if (!dma_mem) return -ENOMEM; err = dpni_prepare_key_cfg(&cls_cfg, dma_mem); if (err) { - dev_err(dev, "dpni_prepare_key_cfg error %d", err); + dev_err(dev, "dpni_prepare_key_cfg error %d\n", err); goto err_prep_key; } memset(&dist_cfg, 0, sizeof(dist_cfg)); /* Prepare for setting the rx dist */ - dist_cfg.key_cfg_iova = dma_map_single(net_dev->dev.parent, dma_mem, + dist_cfg.key_cfg_iova = dma_map_single(dev, dma_mem, DPAA2_CLASSIFIER_DMA_SIZE, DMA_TO_DEVICE); - if (dma_mapping_error(net_dev->dev.parent, dist_cfg.key_cfg_iova)) { + if (dma_mapping_error(dev, dist_cfg.key_cfg_iova)) { dev_err(dev, "DMA mapping failed\n"); err = -ENOMEM; goto err_dma_map; @@ -2011,7 +2047,7 @@ int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags) dist_cfg.dist_mode = DPNI_DIST_MODE_HASH; err = dpni_set_rx_tc_dist(priv->mc_io, 0, priv->mc_token, 0, &dist_cfg); - dma_unmap_single(net_dev->dev.parent, dist_cfg.key_cfg_iova, + dma_unmap_single(dev, dist_cfg.key_cfg_iova, DPAA2_CLASSIFIER_DMA_SIZE, DMA_TO_DEVICE); if (err) dev_err(dev, "dpni_set_rx_tc_dist() error %d\n", err); @@ -2052,7 +2088,7 @@ static int bind_dpni(struct dpaa2_eth_priv *priv) netdev_err(net_dev, "Failed to configure hashing\n"); /* Configure handling of error frames */ - err_cfg.errors = DPAA2_ETH_RX_ERR_MASK; + err_cfg.errors = DPAA2_FAS_RX_ERR_MASK; err_cfg.set_frame_annotation = 1; err_cfg.error_action = DPNI_ERROR_ACTION_DISCARD; err = dpni_set_errors_behavior(priv->mc_io, 0, priv->mc_token, @@ -2125,15 +2161,12 @@ static void free_rings(struct dpaa2_eth_priv *priv) dpaa2_io_store_destroy(priv->channel[i]->store); } -static int netdev_init(struct net_device *net_dev) +static int set_mac_addr(struct dpaa2_eth_priv *priv) { - int err; + struct net_device *net_dev = priv->net_dev; struct device *dev = net_dev->dev.parent; - struct dpaa2_eth_priv *priv = netdev_priv(net_dev); u8 mac_addr[ETH_ALEN], dpni_mac_addr[ETH_ALEN]; - u8 bcast_addr[ETH_ALEN]; - - net_dev->netdev_ops = &dpaa2_eth_ops; + int err; /* Get firmware address, if any */ err = dpni_get_port_mac_addr(priv->mc_io, 0, priv->mc_token, mac_addr); @@ -2146,7 +2179,7 @@ static int netdev_init(struct net_device *net_dev) err = dpni_get_primary_mac_addr(priv->mc_io, 0, priv->mc_token, dpni_mac_addr); if (err) { - dev_err(dev, "dpni_get_primary_mac_addr() failed (%d)\n", err); + dev_err(dev, "dpni_get_primary_mac_addr() failed\n"); return err; } @@ -2164,18 +2197,19 @@ static int netdev_init(struct net_device *net_dev) } memcpy(net_dev->dev_addr, mac_addr, net_dev->addr_len); } else if (is_zero_ether_addr(dpni_mac_addr)) { - /* Fills in net_dev->dev_addr, as required by - * register_netdevice() + /* No MAC address configured, fill in net_dev->dev_addr + * with a random one */ eth_hw_addr_random(net_dev); - /* Make the user aware, without cluttering the boot log */ - dev_dbg_once(dev, " device(s) have all-zero hwaddr, replaced with random\n"); + dev_dbg_once(dev, "device(s) have all-zero hwaddr, replaced with random\n"); + err = dpni_set_primary_mac_addr(priv->mc_io, 0, priv->mc_token, net_dev->dev_addr); if (err) { - dev_err(dev, "dpni_set_primary_mac_addr(): %d\n", err); + dev_err(dev, "dpni_set_primary_mac_addr() failed\n"); return err; } + /* Override NET_ADDR_RANDOM set by eth_hw_addr_random(); for all * practical purposes, this will be our "permanent" mac address, * at least until the next reboot. This move will also permit @@ -2189,14 +2223,29 @@ static int netdev_init(struct net_device *net_dev) memcpy(net_dev->dev_addr, dpni_mac_addr, net_dev->addr_len); } - /* Explicitly add the broadcast address to the MAC filtering table; - * the MC won't do that for us. - */ + return 0; +} + +static int netdev_init(struct net_device *net_dev) +{ + struct device *dev = net_dev->dev.parent; + struct dpaa2_eth_priv *priv = netdev_priv(net_dev); + u8 bcast_addr[ETH_ALEN]; + u8 num_queues; + int err; + + net_dev->netdev_ops = &dpaa2_eth_ops; + + err = set_mac_addr(priv); + if (err) + return err; + + /* Explicitly add the broadcast address to the MAC filtering table */ eth_broadcast_addr(bcast_addr); err = dpni_add_mac_addr(priv->mc_io, 0, priv->mc_token, bcast_addr); if (err) { - dev_warn(dev, "dpni_add_mac_addr() failed (%d)\n", err); - /* Won't return an error; at least, we'd have egress traffic */ + dev_err(dev, "dpni_add_mac_addr() failed\n"); + return err; } /* Reserve enough space to align buffer as per hardware requirement; @@ -2208,6 +2257,19 @@ static int netdev_init(struct net_device *net_dev) net_dev->min_mtu = 68; net_dev->max_mtu = DPAA2_ETH_MAX_MTU; + /* Set actual number of queues in the net device */ + num_queues = dpaa2_eth_queue_count(priv); + err = netif_set_real_num_tx_queues(net_dev, num_queues); + if (err) { + dev_err(dev, "netif_set_real_num_tx_queues() failed\n"); + return err; + } + err = netif_set_real_num_rx_queues(net_dev, num_queues); + if (err) { + dev_err(dev, "netif_set_real_num_rx_queues() failed\n"); + return err; + } + /* Our .ndo_init will be called herein */ err = register_netdev(net_dev); if (err < 0) { @@ -2241,7 +2303,7 @@ static irqreturn_t dpni_irq0_handler(int irq_num, void *arg) static irqreturn_t dpni_irq0_handler_thread(int irq_num, void *arg) { - u32 status, clear = 0; + u32 status = 0, clear = 0; struct device *dev = (struct device *)arg; struct fsl_mc_device *dpni_dev = to_fsl_mc_device(dev); struct net_device *net_dev = dev_get_drvdata(dev); @@ -2250,7 +2312,7 @@ static irqreturn_t dpni_irq0_handler_thread(int irq_num, void *arg) err = dpni_get_irq_status(dpni_dev->mc_io, 0, dpni_dev->mc_handle, DPNI_IRQ_INDEX, &status); if (unlikely(err)) { - netdev_err(net_dev, "Can't get irq status (err %d)", err); + netdev_err(net_dev, "Can't get irq status (err %d)\n", err); clear = 0xffffffff; goto out; } @@ -2284,21 +2346,21 @@ static int setup_irqs(struct fsl_mc_device *ls_dev) IRQF_NO_SUSPEND | IRQF_ONESHOT, dev_name(&ls_dev->dev), &ls_dev->dev); if (err < 0) { - dev_err(&ls_dev->dev, "devm_request_threaded_irq(): %d", err); + dev_err(&ls_dev->dev, "devm_request_threaded_irq(): %d\n", err); goto free_mc_irq; } err = dpni_set_irq_mask(ls_dev->mc_io, 0, ls_dev->mc_handle, DPNI_IRQ_INDEX, DPNI_IRQ_EVENT_LINK_CHANGED); if (err < 0) { - dev_err(&ls_dev->dev, "dpni_set_irq_mask(): %d", err); + dev_err(&ls_dev->dev, "dpni_set_irq_mask(): %d\n", err); goto free_irq; } err = dpni_set_irq_enable(ls_dev->mc_io, 0, ls_dev->mc_handle, DPNI_IRQ_INDEX, 1); if (err < 0) { - dev_err(&ls_dev->dev, "dpni_set_irq_enable(): %d", err); + dev_err(&ls_dev->dev, "dpni_set_irq_enable(): %d\n", err); goto free_irq; } @@ -2358,6 +2420,8 @@ static int dpaa2_eth_probe(struct fsl_mc_device *dpni_dev) priv = netdev_priv(net_dev); priv->net_dev = net_dev; + priv->iommu_domain = iommu_get_domain_for_dev(dev); + /* Obtain a MC portal */ err = fsl_mc_portal_allocate(dpni_dev, FSL_MC_IO_ATOMIC_CONTEXT_PORTAL, &priv->mc_io); diff --git a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h index c67cced55b72..e6d28a249fc1 100644 --- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h +++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h @@ -120,6 +120,19 @@ struct dpaa2_eth_swa { #define DPAA2_FD_FRC_FASWOV 0x0800 #define DPAA2_FD_FRC_FAICFDV 0x0400 +/* Error bits in FD CTRL */ +#define DPAA2_FD_CTRL_UFD 0x00000004 +#define DPAA2_FD_CTRL_SBE 0x00000008 +#define DPAA2_FD_CTRL_FSE 0x00000010 +#define DPAA2_FD_CTRL_FAERR 0x00000020 + +#define DPAA2_FD_RX_ERR_MASK (DPAA2_FD_CTRL_SBE | \ + DPAA2_FD_CTRL_FAERR) +#define DPAA2_FD_TX_ERR_MASK (DPAA2_FD_CTRL_UFD | \ + DPAA2_FD_CTRL_SBE | \ + DPAA2_FD_CTRL_FSE | \ + DPAA2_FD_CTRL_FAERR) + /* Annotation bits in FD CTRL */ #define DPAA2_FD_CTRL_ASAL 0x00020000 /* ASAL = 128 */ #define DPAA2_FD_CTRL_PTA 0x00800000 @@ -139,6 +152,12 @@ struct dpaa2_fas { #define DPAA2_FAS_OFFSET 0 #define DPAA2_FAS_SIZE (sizeof(struct dpaa2_fas)) +/* Accessors for the hardware annotation fields that we use */ +#define dpaa2_get_hwa(buf_addr) \ + ((void *)(buf_addr) + DPAA2_ETH_SWA_SIZE) +#define dpaa2_get_fas(buf_addr) \ + (struct dpaa2_fas *)(dpaa2_get_hwa(buf_addr) + DPAA2_FAS_OFFSET) + /* Error and status bits in the frame annotation status word */ /* Debug frame, otherwise supposed to be discarded */ #define DPAA2_FAS_DISC 0x80000000 @@ -171,7 +190,7 @@ struct dpaa2_fas { /* L4 csum error */ #define DPAA2_FAS_L4CE 0x00000001 /* Possible errors on the ingress path */ -#define DPAA2_ETH_RX_ERR_MASK (DPAA2_FAS_KSE | \ +#define DPAA2_FAS_RX_ERR_MASK (DPAA2_FAS_KSE | \ DPAA2_FAS_EOFHE | \ DPAA2_FAS_MNLE | \ DPAA2_FAS_TIDE | \ @@ -185,7 +204,7 @@ struct dpaa2_fas { DPAA2_FAS_L3CE | \ DPAA2_FAS_L4CE) /* Tx errors */ -#define DPAA2_ETH_TXCONF_ERR_MASK (DPAA2_FAS_KSE | \ +#define DPAA2_FAS_TX_ERR_MASK (DPAA2_FAS_KSE | \ DPAA2_FAS_EOFHE | \ DPAA2_FAS_MNLE | \ DPAA2_FAS_TIDE) @@ -291,16 +310,12 @@ struct dpaa2_eth_priv { u8 num_channels; struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS]; - int dpni_id; struct dpni_attr dpni_attrs; - /* Insofar as the MC is concerned, we're using one layout on all 3 types - * of buffers (Rx, Tx, Tx-Conf). - */ - struct dpni_buffer_layout buf_layout; u16 tx_data_offset; struct fsl_mc_device *dpbp_dev; - struct dpbp_attr dpbp_attrs; + u16 bpid; + struct iommu_domain *iommu_domain; u16 tx_qdid; struct fsl_mc_io *mc_io; @@ -338,8 +353,6 @@ struct dpaa2_eth_priv { extern const struct ethtool_ops dpaa2_ethtool_ops; extern const char dpaa2_eth_drv_version[]; -int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags); - static int dpaa2_eth_queue_count(struct dpaa2_eth_priv *priv) { return priv->dpni_attrs.num_queues; diff --git a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-ethtool.c b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-ethtool.c index dd0cffa908ef..5312edc26f01 100644 --- a/drivers/staging/fsl-dpaa2/ethernet/dpaa2-ethtool.c +++ b/drivers/staging/fsl-dpaa2/ethernet/dpaa2-ethtool.c @@ -34,41 +34,41 @@ #include "dpaa2-eth.h" /* To be kept in sync with DPNI statistics */ -char dpaa2_ethtool_stats[][ETH_GSTRING_LEN] = { - "rx frames", - "rx bytes", - "rx mcast frames", - "rx mcast bytes", - "rx bcast frames", - "rx bcast bytes", - "tx frames", - "tx bytes", - "tx mcast frames", - "tx mcast bytes", - "tx bcast frames", - "tx bcast bytes", - "rx filtered frames", - "rx discarded frames", - "rx nobuffer discards", - "tx discarded frames", - "tx confirmed frames", +static char dpaa2_ethtool_stats[][ETH_GSTRING_LEN] = { + "[hw] rx frames", + "[hw] rx bytes", + "[hw] rx mcast frames", + "[hw] rx mcast bytes", + "[hw] rx bcast frames", + "[hw] rx bcast bytes", + "[hw] tx frames", + "[hw] tx bytes", + "[hw] tx mcast frames", + "[hw] tx mcast bytes", + "[hw] tx bcast frames", + "[hw] tx bcast bytes", + "[hw] rx filtered frames", + "[hw] rx discarded frames", + "[hw] rx nobuffer discards", + "[hw] tx discarded frames", + "[hw] tx confirmed frames", }; #define DPAA2_ETH_NUM_STATS ARRAY_SIZE(dpaa2_ethtool_stats) -char dpaa2_ethtool_extras[][ETH_GSTRING_LEN] = { +static char dpaa2_ethtool_extras[][ETH_GSTRING_LEN] = { /* per-cpu stats */ - "tx conf frames", - "tx conf bytes", - "tx sg frames", - "tx sg bytes", - "rx sg frames", - "rx sg bytes", - "enqueue portal busy", + "[drv] tx conf frames", + "[drv] tx conf bytes", + "[drv] tx sg frames", + "[drv] tx sg bytes", + "[drv] rx sg frames", + "[drv] rx sg bytes", + "[drv] enqueue portal busy", /* Channel stats */ - "dequeue portal busy", - "channel pull errors", - "cdan", + "[drv] dequeue portal busy", + "[drv] channel pull errors", + "[drv] cdan", }; #define DPAA2_ETH_NUM_EXTRA_STATS ARRAY_SIZE(dpaa2_ethtool_extras) @@ -94,7 +94,7 @@ dpaa2_eth_get_link_ksettings(struct net_device *net_dev, err = dpni_get_link_state(priv->mc_io, 0, priv->mc_token, &state); if (err) { - netdev_err(net_dev, "ERROR %d getting link state", err); + netdev_err(net_dev, "ERROR %d getting link state\n", err); goto out; } @@ -147,7 +147,7 @@ dpaa2_eth_set_link_ksettings(struct net_device *net_dev, /* ethtool will be loud enough if we return an error; no point * in putting our own error message on the console by default */ - netdev_dbg(net_dev, "ERROR %d setting link cfg", err); + netdev_dbg(net_dev, "ERROR %d setting link cfg\n", err); return err; } @@ -206,7 +206,7 @@ static void dpaa2_eth_get_ethtool_stats(struct net_device *net_dev, err = dpni_get_statistics(priv->mc_io, 0, priv->mc_token, j, &dpni_stats); if (err != 0) - netdev_warn(net_dev, "dpni_get_stats(%d) failed", j); + netdev_warn(net_dev, "dpni_get_stats(%d) failed\n", j); switch (j) { case 0: num_cnt = sizeof(dpni_stats.page_0) / sizeof(u64); diff --git a/drivers/staging/fsl-dpaa2/ethernet/dpni.c b/drivers/staging/fsl-dpaa2/ethernet/dpni.c index cea46edec6a2..5b9d4424e4fb 100644 --- a/drivers/staging/fsl-dpaa2/ethernet/dpni.c +++ b/drivers/staging/fsl-dpaa2/ethernet/dpni.c @@ -30,8 +30,9 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ -#include "../../fsl-mc/include/mc-sys.h" -#include "../../fsl-mc/include/mc-cmd.h" +#include <linux/kernel.h> +#include <linux/errno.h> +#include "../../fsl-mc/include/mc.h" #include "dpni.h" #include "dpni-cmd.h" diff --git a/drivers/staging/fsl-mc/README.txt b/drivers/staging/fsl-mc/README.txt index 179536a9b7a1..524eda1de04f 100644 --- a/drivers/staging/fsl-mc/README.txt +++ b/drivers/staging/fsl-mc/README.txt @@ -131,9 +131,7 @@ in creating a network interfaces. DPRCs can be defined statically and populated with objects via a config file passed to the MC when firmware starts - it. There is also a Linux user space tool called "restool" - that can be used to create/destroy containers and objects - dynamically. + it. -DPAA2 Objects for an Ethernet Network Interface @@ -322,6 +320,8 @@ A brief description of each driver is provided below. -creates an MSI IRQ domain -doing a 'device add' to expose the 'root' DPRC, in turn triggering a bind of the root DPRC to the DPRC driver + The binding for the MC-bus device-tree node can be consulted here: + Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt DPRC driver ----------- diff --git a/drivers/staging/fsl-mc/bus/Makefile b/drivers/staging/fsl-mc/bus/Makefile index 659eccf52a4f..6df407edfade 100644 --- a/drivers/staging/fsl-mc/bus/Makefile +++ b/drivers/staging/fsl-mc/bus/Makefile @@ -11,7 +11,6 @@ mc-bus-driver-objs := fsl-mc-bus.o \ mc-sys.o \ mc-io.o \ dprc.o \ - dpmng.o \ dprc-driver.o \ fsl-mc-allocator.o \ fsl-mc-msi.o \ diff --git a/drivers/staging/fsl-mc/bus/dpbp-cmd.h b/drivers/staging/fsl-mc/bus/dpbp-cmd.h index 8aa65452c872..5904836fd741 100644 --- a/drivers/staging/fsl-mc/bus/dpbp-cmd.h +++ b/drivers/staging/fsl-mc/bus/dpbp-cmd.h @@ -40,7 +40,7 @@ #define DPBP_CMD_BASE_VERSION 1 #define DPBP_CMD_ID_OFFSET 4 -#define DPBP_CMD(id) ((id << DPBP_CMD_ID_OFFSET) | DPBP_CMD_BASE_VERSION) +#define DPBP_CMD(id) (((id) << DPBP_CMD_ID_OFFSET) | DPBP_CMD_BASE_VERSION) /* Command IDs */ #define DPBP_CMDID_CLOSE DPBP_CMD(0x800) diff --git a/drivers/staging/fsl-mc/bus/dpbp.c b/drivers/staging/fsl-mc/bus/dpbp.c index d9e450a6bad6..363730a80cbb 100644 --- a/drivers/staging/fsl-mc/bus/dpbp.c +++ b/drivers/staging/fsl-mc/bus/dpbp.c @@ -29,8 +29,8 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ -#include "../include/mc-sys.h" -#include "../include/mc-cmd.h" +#include <linux/kernel.h> +#include "../include/mc.h" #include "../include/dpbp.h" #include "dpbp-cmd.h" diff --git a/drivers/staging/fsl-mc/bus/dpcon.c b/drivers/staging/fsl-mc/bus/dpcon.c index eb713578b817..ca1da85c6dda 100644 --- a/drivers/staging/fsl-mc/bus/dpcon.c +++ b/drivers/staging/fsl-mc/bus/dpcon.c @@ -29,8 +29,8 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ -#include "../include/mc-sys.h" -#include "../include/mc-cmd.h" +#include <linux/kernel.h> +#include "../include/mc.h" #include "../include/dpcon.h" #include "dpcon-cmd.h" diff --git a/drivers/staging/fsl-mc/bus/dpio/dpio-service.c b/drivers/staging/fsl-mc/bus/dpio/dpio-service.c index e5d66749614c..f8096828f5b7 100644 --- a/drivers/staging/fsl-mc/bus/dpio/dpio-service.c +++ b/drivers/staging/fsl-mc/bus/dpio/dpio-service.c @@ -260,9 +260,9 @@ int dpaa2_io_service_register(struct dpaa2_io *d, /* Enable the generation of CDAN notifications */ if (ctx->is_cdan) - qbman_swp_CDAN_set_context_enable(d->swp, - (u16)ctx->id, - ctx->qman64); + return qbman_swp_CDAN_set_context_enable(d->swp, + (u16)ctx->id, + ctx->qman64); return 0; } EXPORT_SYMBOL(dpaa2_io_service_register); @@ -514,7 +514,7 @@ EXPORT_SYMBOL(dpaa2_io_service_acquire); * The size of the storage is "max_frames*sizeof(struct dpaa2_dq)". * The 'dpaa2_io_store' returned is a DPIO service managed object. * - * Return pointer to dpaa2_io_store struct for successfuly created storage + * Return pointer to dpaa2_io_store struct for successfully created storage * memory, or NULL on error. */ struct dpaa2_io_store *dpaa2_io_store_create(unsigned int max_frames, diff --git a/drivers/staging/fsl-mc/bus/dpio/dpio.c b/drivers/staging/fsl-mc/bus/dpio/dpio.c index d81e0232f6c1..00eb22186f42 100644 --- a/drivers/staging/fsl-mc/bus/dpio/dpio.c +++ b/drivers/staging/fsl-mc/bus/dpio/dpio.c @@ -30,8 +30,8 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ -#include "../../include/mc-sys.h" -#include "../../include/mc-cmd.h" +#include <linux/kernel.h> +#include "../../include/mc.h" #include "dpio.h" #include "dpio-cmd.h" diff --git a/drivers/staging/fsl-mc/bus/dpmcp-cmd.h b/drivers/staging/fsl-mc/bus/dpmcp-cmd.h index 384a13d0b07f..861b2a708af8 100644 --- a/drivers/staging/fsl-mc/bus/dpmcp-cmd.h +++ b/drivers/staging/fsl-mc/bus/dpmcp-cmd.h @@ -40,7 +40,7 @@ #define DPMCP_CMD_BASE_VERSION 1 #define DPMCP_CMD_ID_OFFSET 4 -#define DPMCP_CMD(id) ((id << DPMCP_CMD_ID_OFFSET) | DPMCP_CMD_BASE_VERSION) +#define DPMCP_CMD(id) (((id) << DPMCP_CMD_ID_OFFSET) | DPMCP_CMD_BASE_VERSION) /* Command IDs */ #define DPMCP_CMDID_CLOSE DPMCP_CMD(0x800) diff --git a/drivers/staging/fsl-mc/bus/dpmcp.c b/drivers/staging/fsl-mc/bus/dpmcp.c index ad4c8b43f065..eea42f61af86 100644 --- a/drivers/staging/fsl-mc/bus/dpmcp.c +++ b/drivers/staging/fsl-mc/bus/dpmcp.c @@ -29,8 +29,8 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ -#include "../include/mc-sys.h" -#include "../include/mc-cmd.h" +#include <linux/kernel.h> +#include "../include/mc.h" #include "dpmcp.h" #include "dpmcp-cmd.h" diff --git a/drivers/staging/fsl-mc/bus/dpmng-cmd.h b/drivers/staging/fsl-mc/bus/dpmng-cmd.h index cdddfb80eecc..d1f04ac18b78 100644 --- a/drivers/staging/fsl-mc/bus/dpmng-cmd.h +++ b/drivers/staging/fsl-mc/bus/dpmng-cmd.h @@ -44,7 +44,7 @@ #define DPMNG_CMD_BASE_VERSION 1 #define DPMNG_CMD_ID_OFFSET 4 -#define DPMNG_CMD(id) ((id << DPMNG_CMD_ID_OFFSET) | DPMNG_CMD_BASE_VERSION) +#define DPMNG_CMD(id) (((id) << DPMNG_CMD_ID_OFFSET) | DPMNG_CMD_BASE_VERSION) /* Command IDs */ #define DPMNG_CMDID_GET_VERSION DPMNG_CMD(0x831) diff --git a/drivers/staging/fsl-mc/bus/dpmng.c b/drivers/staging/fsl-mc/bus/dpmng.c deleted file mode 100644 index ad5d5bbec529..000000000000 --- a/drivers/staging/fsl-mc/bus/dpmng.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright 2013-2016 Freescale Semiconductor Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the above-listed copyright holders nor the - * names of any contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * ALTERNATIVELY, this software may be distributed under the terms of the - * GNU General Public License ("GPL") as published by the Free Software - * Foundation, either version 2 of that License or (at your option) any - * later version. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ -#include "../include/mc-sys.h" -#include "../include/mc-cmd.h" -#include "../include/dpmng.h" - -#include "dpmng-cmd.h" - -/** - * mc_get_version() - Retrieves the Management Complex firmware - * version information - * @mc_io: Pointer to opaque I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @mc_ver_info: Returned version information structure - * - * Return: '0' on Success; Error code otherwise. - */ -int mc_get_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - struct mc_version *mc_ver_info) -{ - struct mc_command cmd = { 0 }; - struct dpmng_rsp_get_version *rsp_params; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPMNG_CMDID_GET_VERSION, - cmd_flags, - 0); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - rsp_params = (struct dpmng_rsp_get_version *)cmd.params; - mc_ver_info->revision = le32_to_cpu(rsp_params->revision); - mc_ver_info->major = le32_to_cpu(rsp_params->version_major); - mc_ver_info->minor = le32_to_cpu(rsp_params->version_minor); - - return 0; -} -EXPORT_SYMBOL(mc_get_version); - diff --git a/drivers/staging/fsl-mc/bus/dprc-cmd.h b/drivers/staging/fsl-mc/bus/dprc-cmd.h index e9fdca41f324..d9b2dcde468e 100644 --- a/drivers/staging/fsl-mc/bus/dprc-cmd.h +++ b/drivers/staging/fsl-mc/bus/dprc-cmd.h @@ -48,7 +48,7 @@ #define DPRC_CMD_BASE_VERSION 1 #define DPRC_CMD_ID_OFFSET 4 -#define DPRC_CMD(id) ((id << DPRC_CMD_ID_OFFSET) | DPRC_CMD_BASE_VERSION) +#define DPRC_CMD(id) (((id) << DPRC_CMD_ID_OFFSET) | DPRC_CMD_BASE_VERSION) /* Command IDs */ #define DPRC_CMDID_CLOSE DPRC_CMD(0x800) diff --git a/drivers/staging/fsl-mc/bus/dprc-driver.c b/drivers/staging/fsl-mc/bus/dprc-driver.c index e4b0341d42d7..4cdd190a338b 100644 --- a/drivers/staging/fsl-mc/bus/dprc-driver.c +++ b/drivers/staging/fsl-mc/bus/dprc-driver.c @@ -13,27 +13,30 @@ #include <linux/slab.h> #include <linux/interrupt.h> #include <linux/msi.h> -#include "../include/mc-bus.h" -#include "../include/mc-sys.h" +#include "../include/mc.h" #include "dprc-cmd.h" #include "fsl-mc-private.h" #define FSL_MC_DPRC_DRIVER_NAME "fsl_mc_dprc" -#define FSL_MC_DEVICE_MATCH(_mc_dev, _obj_desc) \ - (strcmp((_mc_dev)->obj_desc.type, (_obj_desc)->type) == 0 && \ - (_mc_dev)->obj_desc.id == (_obj_desc)->id) - -struct dprc_child_objs { +struct fsl_mc_child_objs { int child_count; - struct dprc_obj_desc *child_array; + struct fsl_mc_obj_desc *child_array; }; +static bool fsl_mc_device_match(struct fsl_mc_device *mc_dev, + struct fsl_mc_obj_desc *obj_desc) +{ + return mc_dev->obj_desc.id == obj_desc->id && + !strcmp(mc_dev->obj_desc.type, obj_desc->type); + +} + static int __fsl_mc_device_remove_if_not_in_mc(struct device *dev, void *data) { int i; - struct dprc_child_objs *objs; + struct fsl_mc_child_objs *objs; struct fsl_mc_device *mc_dev; WARN_ON(!dev); @@ -42,10 +45,10 @@ static int __fsl_mc_device_remove_if_not_in_mc(struct device *dev, void *data) objs = data; for (i = 0; i < objs->child_count; i++) { - struct dprc_obj_desc *obj_desc = &objs->child_array[i]; + struct fsl_mc_obj_desc *obj_desc = &objs->child_array[i]; if (strlen(obj_desc->type) != 0 && - FSL_MC_DEVICE_MATCH(mc_dev, obj_desc)) + fsl_mc_device_match(mc_dev, obj_desc)) break; } @@ -76,7 +79,7 @@ static int __fsl_mc_device_remove(struct device *dev, void *data) * been dynamically removed in the physical DPRC. */ static void dprc_remove_devices(struct fsl_mc_device *mc_bus_dev, - struct dprc_obj_desc *obj_desc_array, + struct fsl_mc_obj_desc *obj_desc_array, int num_child_objects_in_mc) { if (num_child_objects_in_mc != 0) { @@ -84,7 +87,7 @@ static void dprc_remove_devices(struct fsl_mc_device *mc_bus_dev, * Remove child objects that are in the DPRC in Linux, * but not in the MC: */ - struct dprc_child_objs objs; + struct fsl_mc_child_objs objs; objs.child_count = num_child_objects_in_mc; objs.child_array = obj_desc_array; @@ -102,13 +105,13 @@ static void dprc_remove_devices(struct fsl_mc_device *mc_bus_dev, static int __fsl_mc_device_match(struct device *dev, void *data) { - struct dprc_obj_desc *obj_desc = data; + struct fsl_mc_obj_desc *obj_desc = data; struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); - return FSL_MC_DEVICE_MATCH(mc_dev, obj_desc); + return fsl_mc_device_match(mc_dev, obj_desc); } -static struct fsl_mc_device *fsl_mc_device_lookup(struct dprc_obj_desc +static struct fsl_mc_device *fsl_mc_device_lookup(struct fsl_mc_obj_desc *obj_desc, struct fsl_mc_device *mc_bus_dev) @@ -133,16 +136,16 @@ static struct fsl_mc_device *fsl_mc_device_lookup(struct dprc_obj_desc * device is unbound from the corresponding device driver. */ static void check_plugged_state_change(struct fsl_mc_device *mc_dev, - struct dprc_obj_desc *obj_desc) + struct fsl_mc_obj_desc *obj_desc) { int error; u32 plugged_flag_at_mc = - obj_desc->state & DPRC_OBJ_STATE_PLUGGED; + obj_desc->state & FSL_MC_OBJ_STATE_PLUGGED; if (plugged_flag_at_mc != - (mc_dev->obj_desc.state & DPRC_OBJ_STATE_PLUGGED)) { + (mc_dev->obj_desc.state & FSL_MC_OBJ_STATE_PLUGGED)) { if (plugged_flag_at_mc) { - mc_dev->obj_desc.state |= DPRC_OBJ_STATE_PLUGGED; + mc_dev->obj_desc.state |= FSL_MC_OBJ_STATE_PLUGGED; error = device_attach(&mc_dev->dev); if (error < 0) { dev_err(&mc_dev->dev, @@ -150,7 +153,7 @@ static void check_plugged_state_change(struct fsl_mc_device *mc_dev, error); } } else { - mc_dev->obj_desc.state &= ~DPRC_OBJ_STATE_PLUGGED; + mc_dev->obj_desc.state &= ~FSL_MC_OBJ_STATE_PLUGGED; device_release_driver(&mc_dev->dev); } } @@ -169,7 +172,7 @@ static void check_plugged_state_change(struct fsl_mc_device *mc_dev, * in the physical DPRC. */ static void dprc_add_new_devices(struct fsl_mc_device *mc_bus_dev, - struct dprc_obj_desc *obj_desc_array, + struct fsl_mc_obj_desc *obj_desc_array, int num_child_objects_in_mc) { int error; @@ -177,7 +180,7 @@ static void dprc_add_new_devices(struct fsl_mc_device *mc_bus_dev, for (i = 0; i < num_child_objects_in_mc; i++) { struct fsl_mc_device *child_dev; - struct dprc_obj_desc *obj_desc = &obj_desc_array[i]; + struct fsl_mc_obj_desc *obj_desc = &obj_desc_array[i]; if (strlen(obj_desc->type) == 0) continue; @@ -217,14 +220,14 @@ static void dprc_add_new_devices(struct fsl_mc_device *mc_bus_dev, * populated before they can get allocation requests from probe callbacks * of the device drivers for the non-allocatable devices. */ -int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev, - unsigned int *total_irq_count) +static int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev, + unsigned int *total_irq_count) { int num_child_objects; int dprc_get_obj_failures; int error; unsigned int irq_count = mc_bus_dev->obj_desc.irq_count; - struct dprc_obj_desc *child_obj_desc_array = NULL; + struct fsl_mc_obj_desc *child_obj_desc_array = NULL; error = dprc_get_obj_count(mc_bus_dev->mc_io, 0, @@ -251,7 +254,7 @@ int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev, */ dprc_get_obj_failures = 0; for (i = 0; i < num_child_objects; i++) { - struct dprc_obj_desc *obj_desc = + struct fsl_mc_obj_desc *obj_desc = &child_obj_desc_array[i]; error = dprc_get_obj(mc_bus_dev->mc_io, @@ -279,7 +282,7 @@ int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev, if ((strcmp(obj_desc->type, "dpseci") == 0) && (obj_desc->ver_major < 4)) obj_desc->flags |= - DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY; + FSL_MC_OBJ_FLAG_NO_MEM_SHAREABILITY; irq_count += obj_desc->irq_count; dev_dbg(&mc_bus_dev->dev, @@ -306,7 +309,6 @@ int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev, return 0; } -EXPORT_SYMBOL_GPL(dprc_scan_objects); /** * dprc_scan_container - Scans a physical DPRC and synchronizes Linux bus state @@ -317,7 +319,7 @@ EXPORT_SYMBOL_GPL(dprc_scan_objects); * bus driver with the actual state of the MC by adding and removing * devices as appropriate. */ -int dprc_scan_container(struct fsl_mc_device *mc_bus_dev) +static int dprc_scan_container(struct fsl_mc_device *mc_bus_dev) { int error; unsigned int irq_count; @@ -353,7 +355,6 @@ error: fsl_mc_cleanup_all_resource_pools(mc_bus_dev); return error; } -EXPORT_SYMBOL_GPL(dprc_scan_container); /** * dprc_irq0_handler - Regular ISR for DPRC interrupt 0 @@ -681,8 +682,8 @@ static int dprc_probe(struct fsl_mc_device *mc_dev) } if (major_ver < DPRC_MIN_VER_MAJOR || - (major_ver == DPRC_MIN_VER_MAJOR && - minor_ver < DPRC_MIN_VER_MINOR)) { + (major_ver == DPRC_MIN_VER_MAJOR && + minor_ver < DPRC_MIN_VER_MINOR)) { dev_err(&mc_dev->dev, "ERROR: DPRC version %d.%d not supported\n", major_ver, minor_ver); diff --git a/drivers/staging/fsl-mc/bus/dprc.c b/drivers/staging/fsl-mc/bus/dprc.c index fcf7b4767dc0..6f6c65a42166 100644 --- a/drivers/staging/fsl-mc/bus/dprc.c +++ b/drivers/staging/fsl-mc/bus/dprc.c @@ -29,9 +29,9 @@ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ -#include "../include/mc-sys.h" -#include "../include/mc-cmd.h" -#include "../include/dprc.h" +#include <linux/kernel.h> +#include "../include/mc.h" +#include "dprc.h" #include "dprc-cmd.h" @@ -496,7 +496,7 @@ int dprc_get_obj(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, int obj_index, - struct dprc_obj_desc *obj_desc) + struct fsl_mc_obj_desc *obj_desc) { struct mc_command cmd = { 0 }; struct dprc_cmd_get_obj *cmd_params; diff --git a/drivers/staging/fsl-mc/include/dprc.h b/drivers/staging/fsl-mc/bus/dprc.h index dc985cc1246f..21295e4feb04 100644 --- a/drivers/staging/fsl-mc/include/dprc.h +++ b/drivers/staging/fsl-mc/bus/dprc.h @@ -33,14 +33,13 @@ #ifndef _FSL_DPRC_H #define _FSL_DPRC_H -#include "mc-cmd.h" - /* * Data Path Resource Container API * Contains DPRC API for managing and querying DPAA resources */ struct fsl_mc_io; +struct fsl_mc_obj_desc; int dprc_open(struct fsl_mc_io *mc_io, u32 cmd_flags, @@ -51,7 +50,6 @@ int dprc_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); - /* IRQ */ /* IRQ index */ @@ -170,59 +168,18 @@ int dprc_get_obj_count(struct fsl_mc_io *mc_io, u16 token, int *obj_count); -/* Objects Attributes Flags */ - -/* Opened state - Indicates that an object is open by at least one owner */ -#define DPRC_OBJ_STATE_OPEN 0x00000001 -/* Plugged state - Indicates that the object is plugged */ -#define DPRC_OBJ_STATE_PLUGGED 0x00000002 - -/** - * Shareability flag - Object flag indicating no memory shareability. - * the object generates memory accesses that are non coherent with other - * masters; - * user is responsible for proper memory handling through IOMMU configuration. - */ -#define DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY 0x0001 - -/** - * struct dprc_obj_desc - Object descriptor, returned from dprc_get_obj() - * @type: Type of object: NULL terminated string - * @id: ID of logical object resource - * @vendor: Object vendor identifier - * @ver_major: Major version number - * @ver_minor: Minor version number - * @irq_count: Number of interrupts supported by the object - * @region_count: Number of mappable regions supported by the object - * @state: Object state: combination of DPRC_OBJ_STATE_ states - * @label: Object label - * @flags: Object's flags - */ -struct dprc_obj_desc { - char type[16]; - int id; - u16 vendor; - u16 ver_major; - u16 ver_minor; - u8 irq_count; - u8 region_count; - u32 state; - char label[16]; - u16 flags; -}; - int dprc_get_obj(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, int obj_index, - struct dprc_obj_desc *obj_desc); + struct fsl_mc_obj_desc *obj_desc); int dprc_get_obj_desc(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, char *obj_type, int obj_id, - struct dprc_obj_desc *obj_desc); + struct fsl_mc_obj_desc *obj_desc); int dprc_set_obj_irq(struct fsl_mc_io *mc_io, u32 cmd_flags, diff --git a/drivers/staging/fsl-mc/bus/fsl-mc-allocator.c b/drivers/staging/fsl-mc/bus/fsl-mc-allocator.c index ce07096c3b1f..b37a6f48225f 100644 --- a/drivers/staging/fsl-mc/bus/fsl-mc-allocator.c +++ b/drivers/staging/fsl-mc/bus/fsl-mc-allocator.c @@ -10,17 +10,16 @@ #include <linux/module.h> #include <linux/msi.h> -#include "../include/mc-bus.h" -#include "../include/mc-sys.h" +#include "../include/mc.h" -#include "dpbp-cmd.h" -#include "dpcon-cmd.h" #include "fsl-mc-private.h" -#define FSL_MC_IS_ALLOCATABLE(_obj_type) \ - (strcmp(_obj_type, "dpbp") == 0 || \ - strcmp(_obj_type, "dpmcp") == 0 || \ - strcmp(_obj_type, "dpcon") == 0) +static bool __must_check fsl_mc_is_allocatable(const char *obj_type) +{ + return strcmp(obj_type, "dpbp") || + strcmp(obj_type, "dpmcp") || + strcmp(obj_type, "dpcon"); +} /** * fsl_mc_resource_pool_add_device - add allocatable object to a resource @@ -44,7 +43,7 @@ static int __must_check fsl_mc_resource_pool_add_device(struct fsl_mc_bus if (WARN_ON(pool_type < 0 || pool_type >= FSL_MC_NUM_POOL_TYPES)) goto out; - if (WARN_ON(!FSL_MC_IS_ALLOCATABLE(mc_dev->obj_desc.type))) + if (WARN_ON(!fsl_mc_is_allocatable(mc_dev->obj_desc.type))) goto out; if (WARN_ON(mc_dev->resource)) goto out; @@ -106,7 +105,7 @@ static int __must_check fsl_mc_resource_pool_remove_device(struct fsl_mc_device struct fsl_mc_resource *resource; int error = -EINVAL; - if (WARN_ON(!FSL_MC_IS_ALLOCATABLE(mc_dev->obj_desc.type))) + if (WARN_ON(!fsl_mc_is_allocatable(mc_dev->obj_desc.type))) goto out; resource = mc_dev->resource; @@ -586,7 +585,7 @@ static int fsl_mc_allocator_probe(struct fsl_mc_device *mc_dev) struct fsl_mc_bus *mc_bus; int error; - if (WARN_ON(!FSL_MC_IS_ALLOCATABLE(mc_dev->obj_desc.type))) + if (WARN_ON(!fsl_mc_is_allocatable(mc_dev->obj_desc.type))) return -EINVAL; mc_bus_dev = to_fsl_mc_device(mc_dev->dev.parent); @@ -615,7 +614,7 @@ static int fsl_mc_allocator_remove(struct fsl_mc_device *mc_dev) { int error; - if (WARN_ON(!FSL_MC_IS_ALLOCATABLE(mc_dev->obj_desc.type))) + if (WARN_ON(!fsl_mc_is_allocatable(mc_dev->obj_desc.type))) return -EINVAL; if (mc_dev->resource) { diff --git a/drivers/staging/fsl-mc/bus/fsl-mc-bus.c b/drivers/staging/fsl-mc/bus/fsl-mc-bus.c index 3be5f25ff113..19606e8d25dd 100644 --- a/drivers/staging/fsl-mc/bus/fsl-mc-bus.c +++ b/drivers/staging/fsl-mc/bus/fsl-mc-bus.c @@ -20,12 +20,10 @@ #include <linux/bitops.h> #include <linux/msi.h> #include <linux/dma-mapping.h> -#include "../include/mc-bus.h" -#include "../include/dpmng.h" -#include "../include/mc-sys.h" #include "fsl-mc-private.h" #include "dprc-cmd.h" +#include "dpmng-cmd.h" /** * Default DMA mask for devices on a fsl-mc bus @@ -61,6 +59,20 @@ struct fsl_mc_addr_translation_range { }; /** + * struct mc_version + * @major: Major version number: incremented on API compatibility changes + * @minor: Minor version number: incremented on API additions (that are + * backward compatible); reset when major version is incremented + * @revision: Internal revision number: incremented on implementation changes + * and/or bug fixes that have no impact on API + */ +struct mc_version { + u32 major; + u32 minor; + u32 revision; +}; + +/** * fsl_mc_bus_match - device to driver matching callback * @dev: the fsl-mc device to match against * @drv: the device driver to search for matching fsl-mc object type @@ -82,7 +94,7 @@ static int fsl_mc_bus_match(struct device *dev, struct device_driver *drv) * If the object is not 'plugged' don't match. * Only exception is the root DPRC, which is a special case. */ - if ((mc_dev->obj_desc.state & DPRC_OBJ_STATE_PLUGGED) == 0 && + if ((mc_dev->obj_desc.state & FSL_MC_OBJ_STATE_PLUGGED) == 0 && !fsl_mc_is_root_dprc(&mc_dev->dev)) goto out; @@ -239,10 +251,46 @@ void fsl_mc_driver_unregister(struct fsl_mc_driver *mc_driver) EXPORT_SYMBOL_GPL(fsl_mc_driver_unregister); /** + * mc_get_version() - Retrieves the Management Complex firmware + * version information + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @mc_ver_info: Returned version information structure + * + * Return: '0' on Success; Error code otherwise. + */ +static int mc_get_version(struct fsl_mc_io *mc_io, + u32 cmd_flags, + struct mc_version *mc_ver_info) +{ + struct mc_command cmd = { 0 }; + struct dpmng_rsp_get_version *rsp_params; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMNG_CMDID_GET_VERSION, + cmd_flags, + 0); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + rsp_params = (struct dpmng_rsp_get_version *)cmd.params; + mc_ver_info->revision = le32_to_cpu(rsp_params->revision); + mc_ver_info->major = le32_to_cpu(rsp_params->version_major); + mc_ver_info->minor = le32_to_cpu(rsp_params->version_minor); + + return 0; +} + +/** * fsl_mc_get_root_dprc - function to traverse to the root dprc */ -void fsl_mc_get_root_dprc(struct device *dev, - struct device **root_dprc_dev) +static void fsl_mc_get_root_dprc(struct device *dev, + struct device **root_dprc_dev) { if (WARN_ON(!dev)) { *root_dprc_dev = NULL; @@ -254,7 +302,6 @@ void fsl_mc_get_root_dprc(struct device *dev, *root_dprc_dev = (*root_dprc_dev)->parent; } } -EXPORT_SYMBOL_GPL(fsl_mc_get_root_dprc); static int get_dprc_attr(struct fsl_mc_io *mc_io, int container_id, struct dprc_attributes *attr) @@ -339,7 +386,7 @@ static int fsl_mc_device_get_mmio_regions(struct fsl_mc_device *mc_dev, int i; int error; struct resource *regions; - struct dprc_obj_desc *obj_desc = &mc_dev->obj_desc; + struct fsl_mc_obj_desc *obj_desc = &mc_dev->obj_desc; struct device *parent_dev = mc_dev->dev.parent; enum dprc_region_type mc_region_type; @@ -420,15 +467,11 @@ bool fsl_mc_is_root_dprc(struct device *dev) static void fsl_mc_device_release(struct device *dev) { struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev); - struct fsl_mc_bus *mc_bus = NULL; kfree(mc_dev->regions); if (strcmp(mc_dev->obj_desc.type, "dprc") == 0) - mc_bus = to_fsl_mc_bus(mc_dev); - - if (mc_bus) - kfree(mc_bus); + kfree(to_fsl_mc_bus(mc_dev)); else kfree(mc_dev); } @@ -436,7 +479,7 @@ static void fsl_mc_device_release(struct device *dev) /** * Add a newly discovered fsl-mc device to be visible in Linux */ -int fsl_mc_device_add(struct dprc_obj_desc *obj_desc, +int fsl_mc_device_add(struct fsl_mc_obj_desc *obj_desc, struct fsl_mc_io *mc_io, struct device *parent_dev, struct fsl_mc_device **new_mc_dev) @@ -538,7 +581,7 @@ int fsl_mc_device_add(struct dprc_obj_desc *obj_desc, } /* Objects are coherent, unless 'no shareability' flag set. */ - if (!(obj_desc->flags & DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY)) + if (!(obj_desc->flags & FSL_MC_OBJ_FLAG_NO_MEM_SHAREABILITY)) arch_setup_dma_ops(&mc_dev->dev, 0, 0, NULL, true); /* @@ -559,10 +602,8 @@ int fsl_mc_device_add(struct dprc_obj_desc *obj_desc, error_cleanup_dev: kfree(mc_dev->regions); - if (mc_bus) - kfree(mc_bus); - else - kfree(mc_dev); + kfree(mc_bus); + kfree(mc_dev); return error; } @@ -644,10 +685,10 @@ static int get_mc_addr_translation_ranges(struct device *dev, const __be32 *cell; ret = parse_mc_ranges(dev, - &paddr_cells, - &mc_addr_cells, - &mc_size_cells, - &ranges_start); + &paddr_cells, + &mc_addr_cells, + &mc_size_cells, + &ranges_start); if (ret < 0) return ret; @@ -693,7 +734,7 @@ static int get_mc_addr_translation_ranges(struct device *dev, */ static int fsl_mc_bus_probe(struct platform_device *pdev) { - struct dprc_obj_desc obj_desc; + struct fsl_mc_obj_desc obj_desc; int error; struct fsl_mc *mc; struct fsl_mc_device *mc_bus_dev = NULL; @@ -752,7 +793,7 @@ static int fsl_mc_bus_probe(struct platform_device *pdev) goto error_cleanup_mc_io; } - memset(&obj_desc, 0, sizeof(struct dprc_obj_desc)); + memset(&obj_desc, 0, sizeof(struct fsl_mc_obj_desc)); error = dprc_get_api_version(mc_io, 0, &obj_desc.ver_major, &obj_desc.ver_minor); diff --git a/drivers/staging/fsl-mc/bus/fsl-mc-msi.c b/drivers/staging/fsl-mc/bus/fsl-mc-msi.c index 17d5cf9f91d4..c04a2f2b3409 100644 --- a/drivers/staging/fsl-mc/bus/fsl-mc-msi.c +++ b/drivers/staging/fsl-mc/bus/fsl-mc-msi.c @@ -16,7 +16,6 @@ #include <linux/irq.h> #include <linux/irqdomain.h> #include <linux/msi.h> -#include "../include/mc-bus.h" #include "fsl-mc-private.h" /* diff --git a/drivers/staging/fsl-mc/bus/fsl-mc-private.h b/drivers/staging/fsl-mc/bus/fsl-mc-private.h index 5c49c9d2df6a..62d398947605 100644 --- a/drivers/staging/fsl-mc/bus/fsl-mc-private.h +++ b/drivers/staging/fsl-mc/bus/fsl-mc-private.h @@ -11,9 +11,56 @@ #define _FSL_MC_PRIVATE_H_ #include "../include/mc.h" -#include "../include/mc-bus.h" +#include "dprc.h" +#include <linux/mutex.h> -int __must_check fsl_mc_device_add(struct dprc_obj_desc *obj_desc, +/** + * Maximum number of total IRQs that can be pre-allocated for an MC bus' + * IRQ pool + */ +#define FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS 256 + +/** + * struct fsl_mc_resource_pool - Pool of MC resources of a given + * type + * @type: type of resources in the pool + * @max_count: maximum number of resources in the pool + * @free_count: number of free resources in the pool + * @mutex: mutex to serialize access to the pool's free list + * @free_list: anchor node of list of free resources in the pool + * @mc_bus: pointer to the MC bus that owns this resource pool + */ +struct fsl_mc_resource_pool { + enum fsl_mc_pool_type type; + int max_count; + int free_count; + struct mutex mutex; /* serializes access to free_list */ + struct list_head free_list; + struct fsl_mc_bus *mc_bus; +}; + +/** + * struct fsl_mc_bus - logical bus that corresponds to a physical DPRC + * @mc_dev: fsl-mc device for the bus device itself. + * @resource_pools: array of resource pools (one pool per resource type) + * for this MC bus. These resources represent allocatable entities + * from the physical DPRC. + * @irq_resources: Pointer to array of IRQ objects for the IRQ pool + * @scan_mutex: Serializes bus scanning + * @dprc_attr: DPRC attributes + */ +struct fsl_mc_bus { + struct fsl_mc_device mc_dev; + struct fsl_mc_resource_pool resource_pools[FSL_MC_NUM_POOL_TYPES]; + struct fsl_mc_device_irq *irq_resources; + struct mutex scan_mutex; /* serializes bus scanning */ + struct dprc_attributes dprc_attr; +}; + +#define to_fsl_mc_bus(_mc_dev) \ + container_of(_mc_dev, struct fsl_mc_bus, mc_dev) + +int __must_check fsl_mc_device_add(struct fsl_mc_obj_desc *obj_desc, struct fsl_mc_io *mc_io, struct device *parent_dev, struct fsl_mc_device **new_mc_dev); @@ -28,6 +75,10 @@ int __init fsl_mc_allocator_driver_init(void); void fsl_mc_allocator_driver_exit(void); +void fsl_mc_init_all_resource_pools(struct fsl_mc_device *mc_bus_dev); + +void fsl_mc_cleanup_all_resource_pools(struct fsl_mc_device *mc_bus_dev); + int __must_check fsl_mc_resource_allocate(struct fsl_mc_bus *mc_bus, enum fsl_mc_pool_type pool_type, struct fsl_mc_resource @@ -44,6 +95,14 @@ int __init its_fsl_mc_msi_init(void); void its_fsl_mc_msi_cleanup(void); +int fsl_mc_find_msi_domain(struct device *mc_platform_dev, + struct irq_domain **mc_msi_domain); + +int fsl_mc_populate_irq_pool(struct fsl_mc_bus *mc_bus, + unsigned int irq_count); + +void fsl_mc_cleanup_irq_pool(struct fsl_mc_bus *mc_bus); + int __must_check fsl_create_mc_io(struct device *dev, phys_addr_t mc_portal_phys_addr, u32 mc_portal_size, @@ -52,4 +111,6 @@ int __must_check fsl_create_mc_io(struct device *dev, void fsl_destroy_mc_io(struct fsl_mc_io *mc_io); +bool fsl_mc_is_root_dprc(struct device *dev); + #endif /* _FSL_MC_PRIVATE_H_ */ diff --git a/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c b/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c index 49127acb85b2..865d38517508 100644 --- a/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c +++ b/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c @@ -16,7 +16,6 @@ #include <linux/msi.h> #include <linux/of.h> #include <linux/of_irq.h> -#include "../include/mc-bus.h" #include "fsl-mc-private.h" static struct irq_chip its_msi_irq_chip = { diff --git a/drivers/staging/fsl-mc/bus/mc-io.c b/drivers/staging/fsl-mc/bus/mc-io.c index d66b87f0903b..35221a17858b 100644 --- a/drivers/staging/fsl-mc/bus/mc-io.c +++ b/drivers/staging/fsl-mc/bus/mc-io.c @@ -31,8 +31,7 @@ */ #include <linux/io.h> -#include "../include/mc-bus.h" -#include "../include/mc-sys.h" +#include "../include/mc.h" #include "fsl-mc-private.h" #include "dpmcp.h" diff --git a/drivers/staging/fsl-mc/bus/mc-sys.c b/drivers/staging/fsl-mc/bus/mc-sys.c index 4d82802b384d..a1704c3a6a78 100644 --- a/drivers/staging/fsl-mc/bus/mc-sys.c +++ b/drivers/staging/fsl-mc/bus/mc-sys.c @@ -37,8 +37,6 @@ #include <linux/ioport.h> #include <linux/device.h> #include <linux/io.h> -#include "../include/mc-sys.h" -#include "../include/mc-cmd.h" #include "../include/mc.h" #include "dpmcp.h" diff --git a/drivers/staging/fsl-mc/include/dpmng.h b/drivers/staging/fsl-mc/include/dpmng.h deleted file mode 100644 index 170c07dd376a..000000000000 --- a/drivers/staging/fsl-mc/include/dpmng.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright 2013-2016 Freescale Semiconductor Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the above-listed copyright holders nor the - * names of any contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * - * ALTERNATIVELY, this software may be distributed under the terms of the - * GNU General Public License ("GPL") as published by the Free Software - * Foundation, either version 2 of that License or (at your option) any - * later version. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __FSL_DPMNG_H -#define __FSL_DPMNG_H - -/* - * Management Complex General API - * Contains general API for the Management Complex firmware - */ - -struct fsl_mc_io; - -/** - * Management Complex firmware version information - */ -#define MC_VER_MAJOR 8 -#define MC_VER_MINOR 0 - -/** - * struct mc_version - * @major: Major version number: incremented on API compatibility changes - * @minor: Minor version number: incremented on API additions (that are - * backward compatible); reset when major version is incremented - * @revision: Internal revision number: incremented on implementation changes - * and/or bug fixes that have no impact on API - */ -struct mc_version { - u32 major; - u32 minor; - u32 revision; -}; - -int mc_get_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - struct mc_version *mc_ver_info); - -#endif /* __FSL_DPMNG_H */ diff --git a/drivers/staging/fsl-mc/include/mc-bus.h b/drivers/staging/fsl-mc/include/mc-bus.h deleted file mode 100644 index 42700de94d59..000000000000 --- a/drivers/staging/fsl-mc/include/mc-bus.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Freescale Management Complex (MC) bus declarations - * - * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. - * Author: German Rivera <German.Rivera@freescale.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#ifndef _FSL_MC_MCBUS_H_ -#define _FSL_MC_MCBUS_H_ - -#include "../include/mc.h" -#include <linux/mutex.h> - -struct irq_domain; -struct msi_domain_info; - -/** - * Maximum number of total IRQs that can be pre-allocated for an MC bus' - * IRQ pool - */ -#define FSL_MC_IRQ_POOL_MAX_TOTAL_IRQS 256 - -#ifdef CONFIG_FSL_MC_BUS -#define dev_is_fsl_mc(_dev) ((_dev)->bus == &fsl_mc_bus_type) -#else -/* If fsl-mc bus is not present device cannot belong to fsl-mc bus */ -#define dev_is_fsl_mc(_dev) (0) -#endif - -/** - * struct fsl_mc_resource_pool - Pool of MC resources of a given - * type - * @type: type of resources in the pool - * @max_count: maximum number of resources in the pool - * @free_count: number of free resources in the pool - * @mutex: mutex to serialize access to the pool's free list - * @free_list: anchor node of list of free resources in the pool - * @mc_bus: pointer to the MC bus that owns this resource pool - */ -struct fsl_mc_resource_pool { - enum fsl_mc_pool_type type; - int max_count; - int free_count; - struct mutex mutex; /* serializes access to free_list */ - struct list_head free_list; - struct fsl_mc_bus *mc_bus; -}; - -/** - * struct fsl_mc_bus - logical bus that corresponds to a physical DPRC - * @mc_dev: fsl-mc device for the bus device itself. - * @resource_pools: array of resource pools (one pool per resource type) - * for this MC bus. These resources represent allocatable entities - * from the physical DPRC. - * @irq_resources: Pointer to array of IRQ objects for the IRQ pool - * @scan_mutex: Serializes bus scanning - * @dprc_attr: DPRC attributes - */ -struct fsl_mc_bus { - struct fsl_mc_device mc_dev; - struct fsl_mc_resource_pool resource_pools[FSL_MC_NUM_POOL_TYPES]; - struct fsl_mc_device_irq *irq_resources; - struct mutex scan_mutex; /* serializes bus scanning */ - struct dprc_attributes dprc_attr; -}; - -#define to_fsl_mc_bus(_mc_dev) \ - container_of(_mc_dev, struct fsl_mc_bus, mc_dev) - -int dprc_scan_container(struct fsl_mc_device *mc_bus_dev); - -int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev, - unsigned int *total_irq_count); - -int __init dprc_driver_init(void); - -void dprc_driver_exit(void); - -int __init fsl_mc_allocator_driver_init(void); - -void fsl_mc_allocator_driver_exit(void); - -struct irq_domain *fsl_mc_msi_create_irq_domain(struct fwnode_handle *fwnode, - struct msi_domain_info *info, - struct irq_domain *parent); - -int fsl_mc_find_msi_domain(struct device *mc_platform_dev, - struct irq_domain **mc_msi_domain); - -int fsl_mc_populate_irq_pool(struct fsl_mc_bus *mc_bus, - unsigned int irq_count); - -void fsl_mc_cleanup_irq_pool(struct fsl_mc_bus *mc_bus); - -void fsl_mc_init_all_resource_pools(struct fsl_mc_device *mc_bus_dev); - -void fsl_mc_cleanup_all_resource_pools(struct fsl_mc_device *mc_bus_dev); - -bool fsl_mc_bus_exists(void); - -void fsl_mc_get_root_dprc(struct device *dev, - struct device **root_dprc_dev); - -bool fsl_mc_is_root_dprc(struct device *dev); - -extern struct bus_type fsl_mc_bus_type; - -#endif /* _FSL_MC_MCBUS_H_ */ diff --git a/drivers/staging/fsl-mc/include/mc-cmd.h b/drivers/staging/fsl-mc/include/mc-cmd.h deleted file mode 100644 index 2e08aa31b084..000000000000 --- a/drivers/staging/fsl-mc/include/mc-cmd.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright 2013-2016 Freescale Semiconductor Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the above-listed copyright holders nor the - * names of any contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * - * ALTERNATIVELY, this software may be distributed under the terms of the - * GNU General Public License ("GPL") as published by the Free Software - * Foundation, either version 2 of that License or (at your option) any - * later version. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __FSL_MC_CMD_H -#define __FSL_MC_CMD_H - -#define MC_CMD_NUM_OF_PARAMS 7 - -struct mc_cmd_header { - u8 src_id; - u8 flags_hw; - u8 status; - u8 flags_sw; - __le16 token; - __le16 cmd_id; -}; - -struct mc_command { - u64 header; - u64 params[MC_CMD_NUM_OF_PARAMS]; -}; - -struct mc_rsp_create { - __le32 object_id; -}; - -struct mc_rsp_api_ver { - __le16 major_ver; - __le16 minor_ver; -}; - -enum mc_cmd_status { - MC_CMD_STATUS_OK = 0x0, /* Completed successfully */ - MC_CMD_STATUS_READY = 0x1, /* Ready to be processed */ - MC_CMD_STATUS_AUTH_ERR = 0x3, /* Authentication error */ - MC_CMD_STATUS_NO_PRIVILEGE = 0x4, /* No privilege */ - MC_CMD_STATUS_DMA_ERR = 0x5, /* DMA or I/O error */ - MC_CMD_STATUS_CONFIG_ERR = 0x6, /* Configuration error */ - MC_CMD_STATUS_TIMEOUT = 0x7, /* Operation timed out */ - MC_CMD_STATUS_NO_RESOURCE = 0x8, /* No resources */ - MC_CMD_STATUS_NO_MEMORY = 0x9, /* No memory available */ - MC_CMD_STATUS_BUSY = 0xA, /* Device is busy */ - MC_CMD_STATUS_UNSUPPORTED_OP = 0xB, /* Unsupported operation */ - MC_CMD_STATUS_INVALID_STATE = 0xC /* Invalid state */ -}; - -/* - * MC command flags - */ - -/* High priority flag */ -#define MC_CMD_FLAG_PRI 0x80 -/* Command completion flag */ -#define MC_CMD_FLAG_INTR_DIS 0x01 - -static inline u64 mc_encode_cmd_header(u16 cmd_id, - u32 cmd_flags, - u16 token) -{ - u64 header = 0; - struct mc_cmd_header *hdr = (struct mc_cmd_header *)&header; - - hdr->cmd_id = cpu_to_le16(cmd_id); - hdr->token = cpu_to_le16(token); - hdr->status = MC_CMD_STATUS_READY; - if (cmd_flags & MC_CMD_FLAG_PRI) - hdr->flags_hw = MC_CMD_FLAG_PRI; - if (cmd_flags & MC_CMD_FLAG_INTR_DIS) - hdr->flags_sw = MC_CMD_FLAG_INTR_DIS; - - return header; -} - -static inline u16 mc_cmd_hdr_read_token(struct mc_command *cmd) -{ - struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header; - u16 token = le16_to_cpu(hdr->token); - - return token; -} - -static inline u32 mc_cmd_read_object_id(struct mc_command *cmd) -{ - struct mc_rsp_create *rsp_params; - - rsp_params = (struct mc_rsp_create *)cmd->params; - return le32_to_cpu(rsp_params->object_id); -} - -static inline void mc_cmd_read_api_version(struct mc_command *cmd, - u16 *major_ver, - u16 *minor_ver) -{ - struct mc_rsp_api_ver *rsp_params; - - rsp_params = (struct mc_rsp_api_ver *)cmd->params; - *major_ver = le16_to_cpu(rsp_params->major_ver); - *minor_ver = le16_to_cpu(rsp_params->minor_ver); -} - -#endif /* __FSL_MC_CMD_H */ diff --git a/drivers/staging/fsl-mc/include/mc-sys.h b/drivers/staging/fsl-mc/include/mc-sys.h deleted file mode 100644 index dca7f9084e05..000000000000 --- a/drivers/staging/fsl-mc/include/mc-sys.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright 2013-2016 Freescale Semiconductor Inc. - * - * Interface of the I/O services to send MC commands to the MC hardware - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of the above-listed copyright holders nor the - * names of any contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * - * ALTERNATIVELY, this software may be distributed under the terms of the - * GNU General Public License ("GPL") as published by the Free Software - * Foundation, either version 2 of that License or (at your option) any - * later version. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _FSL_MC_SYS_H -#define _FSL_MC_SYS_H - -#include <linux/types.h> -#include <linux/errno.h> -#include <linux/mutex.h> -#include <linux/spinlock.h> - -/** - * Bit masks for a MC I/O object (struct fsl_mc_io) flags - */ -#define FSL_MC_IO_ATOMIC_CONTEXT_PORTAL 0x0001 - -struct fsl_mc_resource; -struct mc_command; - -/** - * struct fsl_mc_io - MC I/O object to be passed-in to mc_send_command() - * @dev: device associated with this Mc I/O object - * @flags: flags for mc_send_command() - * @portal_size: MC command portal size in bytes - * @portal_phys_addr: MC command portal physical address - * @portal_virt_addr: MC command portal virtual address - * @dpmcp_dev: pointer to the DPMCP device associated with the MC portal. - * - * Fields are only meaningful if the FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is not - * set: - * @mutex: Mutex to serialize mc_send_command() calls that use the same MC - * portal, if the fsl_mc_io object was created with the - * FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag off. mc_send_command() calls for this - * fsl_mc_io object must be made only from non-atomic context. - * - * Fields are only meaningful if the FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is - * set: - * @spinlock: Spinlock to serialize mc_send_command() calls that use the same MC - * portal, if the fsl_mc_io object was created with the - * FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag on. mc_send_command() calls for this - * fsl_mc_io object can be made from atomic or non-atomic context. - */ -struct fsl_mc_io { - struct device *dev; - u16 flags; - u16 portal_size; - phys_addr_t portal_phys_addr; - void __iomem *portal_virt_addr; - struct fsl_mc_device *dpmcp_dev; - union { - /* - * This field is only meaningful if the - * FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is not set - */ - struct mutex mutex; /* serializes mc_send_command() */ - - /* - * This field is only meaningful if the - * FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is set - */ - spinlock_t spinlock; /* serializes mc_send_command() */ - }; -}; - -int mc_send_command(struct fsl_mc_io *mc_io, struct mc_command *cmd); - -#endif /* _FSL_MC_SYS_H */ diff --git a/drivers/staging/fsl-mc/include/mc.h b/drivers/staging/fsl-mc/include/mc.h index 1c46c0c2a895..aafe63a21f49 100644 --- a/drivers/staging/fsl-mc/include/mc.h +++ b/drivers/staging/fsl-mc/include/mc.h @@ -14,10 +14,12 @@ #include <linux/device.h> #include <linux/mod_devicetable.h> #include <linux/interrupt.h> -#include "../include/dprc.h" #define FSL_MC_VENDOR_FREESCALE 0x1957 +struct irq_domain; +struct msi_domain_info; + struct fsl_mc_device; struct fsl_mc_io; @@ -104,6 +106,45 @@ struct fsl_mc_device_irq { #define to_fsl_mc_irq(_mc_resource) \ container_of(_mc_resource, struct fsl_mc_device_irq, resource) +/* Opened state - Indicates that an object is open by at least one owner */ +#define FSL_MC_OBJ_STATE_OPEN 0x00000001 +/* Plugged state - Indicates that the object is plugged */ +#define FSL_MC_OBJ_STATE_PLUGGED 0x00000002 + +/** + * Shareability flag - Object flag indicating no memory shareability. + * the object generates memory accesses that are non coherent with other + * masters; + * user is responsible for proper memory handling through IOMMU configuration. + */ +#define FSL_MC_OBJ_FLAG_NO_MEM_SHAREABILITY 0x0001 + +/** + * struct fsl_mc_obj_desc - Object descriptor + * @type: Type of object: NULL terminated string + * @id: ID of logical object resource + * @vendor: Object vendor identifier + * @ver_major: Major version number + * @ver_minor: Minor version number + * @irq_count: Number of interrupts supported by the object + * @region_count: Number of mappable regions supported by the object + * @state: Object state: combination of FSL_MC_OBJ_STATE_ states + * @label: Object label: NULL terminated string + * @flags: Object's flags + */ +struct fsl_mc_obj_desc { + char type[16]; + int id; + u16 vendor; + u16 ver_major; + u16 ver_minor; + u8 irq_count; + u8 region_count; + u32 state; + char label[16]; + u16 flags; +}; + /** * Bit masks for a MC object device (struct fsl_mc_device) flags */ @@ -150,7 +191,7 @@ struct fsl_mc_device { u16 icid; u16 mc_handle; struct fsl_mc_io *mc_io; - struct dprc_obj_desc obj_desc; + struct fsl_mc_obj_desc obj_desc; struct resource *regions; struct fsl_mc_device_irq **irqs; struct fsl_mc_resource *resource; @@ -159,6 +200,159 @@ struct fsl_mc_device { #define to_fsl_mc_device(_dev) \ container_of(_dev, struct fsl_mc_device, dev) +#define MC_CMD_NUM_OF_PARAMS 7 + +struct mc_cmd_header { + u8 src_id; + u8 flags_hw; + u8 status; + u8 flags_sw; + __le16 token; + __le16 cmd_id; +}; + +struct mc_command { + u64 header; + u64 params[MC_CMD_NUM_OF_PARAMS]; +}; + +enum mc_cmd_status { + MC_CMD_STATUS_OK = 0x0, /* Completed successfully */ + MC_CMD_STATUS_READY = 0x1, /* Ready to be processed */ + MC_CMD_STATUS_AUTH_ERR = 0x3, /* Authentication error */ + MC_CMD_STATUS_NO_PRIVILEGE = 0x4, /* No privilege */ + MC_CMD_STATUS_DMA_ERR = 0x5, /* DMA or I/O error */ + MC_CMD_STATUS_CONFIG_ERR = 0x6, /* Configuration error */ + MC_CMD_STATUS_TIMEOUT = 0x7, /* Operation timed out */ + MC_CMD_STATUS_NO_RESOURCE = 0x8, /* No resources */ + MC_CMD_STATUS_NO_MEMORY = 0x9, /* No memory available */ + MC_CMD_STATUS_BUSY = 0xA, /* Device is busy */ + MC_CMD_STATUS_UNSUPPORTED_OP = 0xB, /* Unsupported operation */ + MC_CMD_STATUS_INVALID_STATE = 0xC /* Invalid state */ +}; + +/* + * MC command flags + */ + +/* High priority flag */ +#define MC_CMD_FLAG_PRI 0x80 +/* Command completion flag */ +#define MC_CMD_FLAG_INTR_DIS 0x01 + +static inline u64 mc_encode_cmd_header(u16 cmd_id, + u32 cmd_flags, + u16 token) +{ + u64 header = 0; + struct mc_cmd_header *hdr = (struct mc_cmd_header *)&header; + + hdr->cmd_id = cpu_to_le16(cmd_id); + hdr->token = cpu_to_le16(token); + hdr->status = MC_CMD_STATUS_READY; + if (cmd_flags & MC_CMD_FLAG_PRI) + hdr->flags_hw = MC_CMD_FLAG_PRI; + if (cmd_flags & MC_CMD_FLAG_INTR_DIS) + hdr->flags_sw = MC_CMD_FLAG_INTR_DIS; + + return header; +} + +static inline u16 mc_cmd_hdr_read_token(struct mc_command *cmd) +{ + struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header; + u16 token = le16_to_cpu(hdr->token); + + return token; +} + +struct mc_rsp_create { + __le32 object_id; +}; + +struct mc_rsp_api_ver { + __le16 major_ver; + __le16 minor_ver; +}; + +static inline u32 mc_cmd_read_object_id(struct mc_command *cmd) +{ + struct mc_rsp_create *rsp_params; + + rsp_params = (struct mc_rsp_create *)cmd->params; + return le32_to_cpu(rsp_params->object_id); +} + +static inline void mc_cmd_read_api_version(struct mc_command *cmd, + u16 *major_ver, + u16 *minor_ver) +{ + struct mc_rsp_api_ver *rsp_params; + + rsp_params = (struct mc_rsp_api_ver *)cmd->params; + *major_ver = le16_to_cpu(rsp_params->major_ver); + *minor_ver = le16_to_cpu(rsp_params->minor_ver); +} + +/** + * Bit masks for a MC I/O object (struct fsl_mc_io) flags + */ +#define FSL_MC_IO_ATOMIC_CONTEXT_PORTAL 0x0001 + +/** + * struct fsl_mc_io - MC I/O object to be passed-in to mc_send_command() + * @dev: device associated with this Mc I/O object + * @flags: flags for mc_send_command() + * @portal_size: MC command portal size in bytes + * @portal_phys_addr: MC command portal physical address + * @portal_virt_addr: MC command portal virtual address + * @dpmcp_dev: pointer to the DPMCP device associated with the MC portal. + * + * Fields are only meaningful if the FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is not + * set: + * @mutex: Mutex to serialize mc_send_command() calls that use the same MC + * portal, if the fsl_mc_io object was created with the + * FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag off. mc_send_command() calls for this + * fsl_mc_io object must be made only from non-atomic context. + * + * Fields are only meaningful if the FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is + * set: + * @spinlock: Spinlock to serialize mc_send_command() calls that use the same MC + * portal, if the fsl_mc_io object was created with the + * FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag on. mc_send_command() calls for this + * fsl_mc_io object can be made from atomic or non-atomic context. + */ +struct fsl_mc_io { + struct device *dev; + u16 flags; + u16 portal_size; + phys_addr_t portal_phys_addr; + void __iomem *portal_virt_addr; + struct fsl_mc_device *dpmcp_dev; + union { + /* + * This field is only meaningful if the + * FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is not set + */ + struct mutex mutex; /* serializes mc_send_command() */ + + /* + * This field is only meaningful if the + * FSL_MC_IO_ATOMIC_CONTEXT_PORTAL flag is set + */ + spinlock_t spinlock; /* serializes mc_send_command() */ + }; +}; + +int mc_send_command(struct fsl_mc_io *mc_io, struct mc_command *cmd); + +#ifdef CONFIG_FSL_MC_BUS +#define dev_is_fsl_mc(_dev) ((_dev)->bus == &fsl_mc_bus_type) +#else +/* If fsl-mc bus is not present device cannot belong to fsl-mc bus */ +#define dev_is_fsl_mc(_dev) (0) +#endif + /* * module_fsl_mc_driver() - Helper macro for drivers that don't do * anything special in module init/exit. This eliminates a lot of @@ -194,8 +388,14 @@ int __must_check fsl_mc_object_allocate(struct fsl_mc_device *mc_dev, void fsl_mc_object_free(struct fsl_mc_device *mc_adev); +struct irq_domain *fsl_mc_msi_create_irq_domain(struct fwnode_handle *fwnode, + struct msi_domain_info *info, + struct irq_domain *parent); + int __must_check fsl_mc_allocate_irqs(struct fsl_mc_device *mc_dev); void fsl_mc_free_irqs(struct fsl_mc_device *mc_dev); +extern struct bus_type fsl_mc_bus_type; + #endif /* _FSL_MC_H_ */ diff --git a/drivers/staging/gdm724x/gdm_usb.c b/drivers/staging/gdm724x/gdm_usb.c index 15a7e81ec2d2..87cd1f827455 100644 --- a/drivers/staging/gdm724x/gdm_usb.c +++ b/drivers/staging/gdm724x/gdm_usb.c @@ -738,11 +738,11 @@ static int gdm_usb_sdu_send(void *priv_dev, void *data, int len, sdu->cmd_evt = gdm_cpu_to_dev16(&udev->gdm_ed, LTE_TX_SDU); if (nic_type == NIC_TYPE_ARP) { send_len = len + SDU_PARAM_LEN; - memcpy(sdu->data, data, len); + memcpy(sdu->data, data, len); } else { - send_len = len - ETH_HLEN; - send_len += SDU_PARAM_LEN; - memcpy(sdu->data, data + ETH_HLEN, len - ETH_HLEN); + send_len = len - ETH_HLEN; + send_len += SDU_PARAM_LEN; + memcpy(sdu->data, data + ETH_HLEN, len - ETH_HLEN); } sdu->len = gdm_cpu_to_dev16(&udev->gdm_ed, send_len); diff --git a/drivers/staging/greybus/Kconfig b/drivers/staging/greybus/Kconfig index 50de2d72dde0..ab096bcef98c 100644 --- a/drivers/staging/greybus/Kconfig +++ b/drivers/staging/greybus/Kconfig @@ -216,4 +216,14 @@ config GREYBUS_USB will be called gb-usb.ko endif # GREYBUS_BRIDGED_PHY + +config GREYBUS_ARCHE + tristate "Greybus Arche Platform driver" + depends on USB_HSIC_USB3613 || COMPILE_TEST + ---help--- + Select this option if you have an Arche device. + + To compile this code as a module, chose M here: the module + will be called gb-arche.ko + endif # GREYBUS diff --git a/drivers/staging/greybus/Makefile b/drivers/staging/greybus/Makefile index b26b9a35bdd5..23e1cb7bff8e 100644 --- a/drivers/staging/greybus/Makefile +++ b/drivers/staging/greybus/Makefile @@ -91,4 +91,4 @@ obj-$(CONFIG_GREYBUS_USB) += gb-usb.o # Greybus Platform driver gb-arche-y := arche-platform.o arche-apb-ctrl.o -obj-$(CONFIG_USB_HSIC_USB3613) += gb-arche.o +obj-$(CONFIG_GREYBUS_ARCHE) += gb-arche.o diff --git a/drivers/staging/greybus/arche-apb-ctrl.c b/drivers/staging/greybus/arche-apb-ctrl.c index 02243b4fd898..0412f3d06efb 100644 --- a/drivers/staging/greybus/arche-apb-ctrl.c +++ b/drivers/staging/greybus/arche-apb-ctrl.c @@ -22,6 +22,8 @@ #include "arche_platform.h" +static void apb_bootret_deassert(struct device *dev); + struct arche_apb_ctrl_drvdata { /* Control GPIO signals to and from AP <=> AP Bridges */ int resetn_gpio; @@ -222,14 +224,7 @@ static void poweroff_seq(struct platform_device *pdev) /* TODO: May have to send an event to SVC about this exit */ } -void apb_bootret_assert(struct device *dev) -{ - struct arche_apb_ctrl_drvdata *apb = dev_get_drvdata(dev); - - gpio_set_value(apb->boot_ret_gpio, 1); -} - -void apb_bootret_deassert(struct device *dev) +static void apb_bootret_deassert(struct device *dev) { struct arche_apb_ctrl_drvdata *apb = dev_get_drvdata(dev); diff --git a/drivers/staging/greybus/arche-platform.c b/drivers/staging/greybus/arche-platform.c index aac1145f1983..eced2d26467b 100644 --- a/drivers/staging/greybus/arche-platform.c +++ b/drivers/staging/greybus/arche-platform.c @@ -24,7 +24,14 @@ #include "arche_platform.h" #include "greybus.h" +#if IS_ENABLED(CONFIG_USB_HSIC_USB3613) #include <linux/usb/usb3613.h> +#else +static inline int usb3613_hub_mode_ctrl(bool unused) +{ + return 0; +} +#endif #define WD_COLDBOOT_PULSE_WIDTH_MS 30 @@ -35,7 +42,6 @@ enum svc_wakedetect_state { WD_STATE_STANDBYBOOT_TRIG, /* As of now not used ?? */ WD_STATE_COLDBOOT_START, /* Cold boot process started */ WD_STATE_STANDBYBOOT_START, /* Not used */ - WD_STATE_TIMESYNC, }; struct arche_platform_drvdata { @@ -59,26 +65,12 @@ struct arche_platform_drvdata { int wake_detect_irq; spinlock_t wake_lock; /* Protect wake_detect_state */ struct mutex platform_state_mutex; /* Protect state */ - wait_queue_head_t wq; /* WQ for arche_pdata->state */ unsigned long wake_detect_start; struct notifier_block pm_notifier; struct device *dev; - struct gb_timesync_svc *timesync_svc_pdata; }; -static int arche_apb_bootret_assert(struct device *dev, void *data) -{ - apb_bootret_assert(dev); - return 0; -} - -static int arche_apb_bootret_deassert(struct device *dev, void *data) -{ - apb_bootret_deassert(dev); - return 0; -} - /* Requires calling context to hold arche_pdata->platform_state_mutex */ static void arche_platform_set_state(struct arche_platform_drvdata *arche_pdata, enum arche_platform_state state) @@ -86,112 +78,6 @@ static void arche_platform_set_state(struct arche_platform_drvdata *arche_pdata, arche_pdata->state = state; } -/* - * arche_platform_change_state: Change the operational state - * - * This exported function allows external drivers to change the state - * of the arche-platform driver. - * Note that this function only supports transitions between two states - * with limited functionality. - * - * - ARCHE_PLATFORM_STATE_TIME_SYNC: - * Once set, allows timesync operations between SVC <=> AP and makes - * sure that arche-platform driver ignores any subsequent events/pulses - * from SVC over wake/detect. - * - * - ARCHE_PLATFORM_STATE_ACTIVE: - * Puts back driver to active state, where any pulse from SVC on wake/detect - * line would trigger either cold/standby boot. - * Note: Transition request from this function does not trigger cold/standby - * boot. It just puts back driver book keeping variable back to ACTIVE - * state and restores the interrupt. - * - * Returns -ENODEV if device not found, -EAGAIN if the driver cannot currently - * satisfy the requested state-transition or -EINVAL for all other - * state-transition requests. - */ -int arche_platform_change_state(enum arche_platform_state state, - struct gb_timesync_svc *timesync_svc_pdata) -{ - struct arche_platform_drvdata *arche_pdata; - struct platform_device *pdev; - struct device_node *np; - int ret = -EAGAIN; - unsigned long flags; - - np = of_find_compatible_node(NULL, NULL, "google,arche-platform"); - if (!np) { - pr_err("google,arche-platform device node not found\n"); - return -ENODEV; - } - - pdev = of_find_device_by_node(np); - if (!pdev) { - pr_err("arche-platform device not found\n"); - of_node_put(np); - return -ENODEV; - } - - arche_pdata = platform_get_drvdata(pdev); - - mutex_lock(&arche_pdata->platform_state_mutex); - spin_lock_irqsave(&arche_pdata->wake_lock, flags); - - if (arche_pdata->state == state) { - ret = 0; - goto exit; - } - - switch (state) { - case ARCHE_PLATFORM_STATE_TIME_SYNC: - if (arche_pdata->state != ARCHE_PLATFORM_STATE_ACTIVE) { - ret = -EINVAL; - goto exit; - } - if (arche_pdata->wake_detect_state != WD_STATE_IDLE) { - dev_err(arche_pdata->dev, - "driver busy with wake/detect line ops\n"); - goto exit; - } - device_for_each_child(arche_pdata->dev, NULL, - arche_apb_bootret_assert); - arche_pdata->wake_detect_state = WD_STATE_TIMESYNC; - break; - case ARCHE_PLATFORM_STATE_ACTIVE: - if (arche_pdata->state != ARCHE_PLATFORM_STATE_TIME_SYNC) { - ret = -EINVAL; - goto exit; - } - device_for_each_child(arche_pdata->dev, NULL, - arche_apb_bootret_deassert); - arche_pdata->wake_detect_state = WD_STATE_IDLE; - break; - case ARCHE_PLATFORM_STATE_OFF: - case ARCHE_PLATFORM_STATE_STANDBY: - case ARCHE_PLATFORM_STATE_FW_FLASHING: - dev_err(arche_pdata->dev, "busy, request to retry later\n"); - goto exit; - default: - ret = -EINVAL; - dev_err(arche_pdata->dev, - "invalid state transition request\n"); - goto exit; - } - arche_pdata->timesync_svc_pdata = timesync_svc_pdata; - arche_platform_set_state(arche_pdata, state); - if (state == ARCHE_PLATFORM_STATE_ACTIVE) - wake_up(&arche_pdata->wq); - - ret = 0; -exit: - spin_unlock_irqrestore(&arche_pdata->wake_lock, flags); - mutex_unlock(&arche_pdata->platform_state_mutex); - put_device(&pdev->dev); - of_node_put(np); - return ret; -} -EXPORT_SYMBOL_GPL(arche_platform_change_state); - /* Requires arche_pdata->wake_lock is held by calling context */ static void arche_platform_set_wake_detect_state( struct arche_platform_drvdata *arche_pdata, @@ -275,11 +161,6 @@ static irqreturn_t arche_platform_wd_irq(int irq, void *devid) spin_lock_irqsave(&arche_pdata->wake_lock, flags); - if (arche_pdata->wake_detect_state == WD_STATE_TIMESYNC) { - gb_timesync_irq(arche_pdata->timesync_svc_pdata); - goto exit; - } - if (gpio_get_value(arche_pdata->wake_detect_gpio)) { /* wake/detect rising */ @@ -323,7 +204,6 @@ static irqreturn_t arche_platform_wd_irq(int irq, void *devid) } } -exit: spin_unlock_irqrestore(&arche_pdata->wake_lock, flags); return IRQ_HANDLED; @@ -436,17 +316,7 @@ static ssize_t state_store(struct device *dev, struct arche_platform_drvdata *arche_pdata = platform_get_drvdata(pdev); int ret = 0; -retry: mutex_lock(&arche_pdata->platform_state_mutex); - if (arche_pdata->state == ARCHE_PLATFORM_STATE_TIME_SYNC) { - mutex_unlock(&arche_pdata->platform_state_mutex); - ret = wait_event_interruptible( - arche_pdata->wq, - arche_pdata->state != ARCHE_PLATFORM_STATE_TIME_SYNC); - if (ret) - return ret; - goto retry; - } if (sysfs_streq(buf, "off")) { if (arche_pdata->state == ARCHE_PLATFORM_STATE_OFF) @@ -517,8 +387,6 @@ static ssize_t state_show(struct device *dev, return sprintf(buf, "standby\n"); case ARCHE_PLATFORM_STATE_FW_FLASHING: return sprintf(buf, "fw_flashing\n"); - case ARCHE_PLATFORM_STATE_TIME_SYNC: - return sprintf(buf, "time_sync\n"); default: return sprintf(buf, "unknown state\n"); } @@ -665,7 +533,6 @@ static int arche_platform_probe(struct platform_device *pdev) spin_lock_init(&arche_pdata->wake_lock); mutex_init(&arche_pdata->platform_state_mutex); - init_waitqueue_head(&arche_pdata->wq); arche_pdata->wake_detect_irq = gpio_to_irq(arche_pdata->wake_detect_gpio); @@ -701,9 +568,6 @@ static int arche_platform_probe(struct platform_device *pdev) goto err_device_remove; } - /* Register callback pointer */ - arche_platform_change_state_cb = arche_platform_change_state; - /* Explicitly power off if requested */ if (!of_property_read_bool(pdev->dev.of_node, "arche,init-off")) { mutex_lock(&arche_pdata->platform_state_mutex); @@ -751,7 +615,7 @@ static int arche_platform_remove(struct platform_device *pdev) return 0; } -static int arche_platform_suspend(struct device *dev) +static __maybe_unused int arche_platform_suspend(struct device *dev) { /* * If timing profile premits, we may shutdown bridge @@ -765,7 +629,7 @@ static int arche_platform_suspend(struct device *dev) return 0; } -static int arche_platform_resume(struct device *dev) +static __maybe_unused int arche_platform_resume(struct device *dev) { /* * Atleast for ES2 we have to meet the delay requirement between diff --git a/drivers/staging/greybus/arche_platform.h b/drivers/staging/greybus/arche_platform.h index c0591df9b9d6..bcffc69d0960 100644 --- a/drivers/staging/greybus/arche_platform.h +++ b/drivers/staging/greybus/arche_platform.h @@ -15,14 +15,8 @@ enum arche_platform_state { ARCHE_PLATFORM_STATE_ACTIVE, ARCHE_PLATFORM_STATE_STANDBY, ARCHE_PLATFORM_STATE_FW_FLASHING, - ARCHE_PLATFORM_STATE_TIME_SYNC, }; -int arche_platform_change_state(enum arche_platform_state state, - struct gb_timesync_svc *pdata); - -extern int (*arche_platform_change_state_cb)(enum arche_platform_state state, - struct gb_timesync_svc *pdata); int __init arche_apb_init(void); void __exit arche_apb_exit(void); @@ -31,7 +25,5 @@ int apb_ctrl_coldboot(struct device *dev); int apb_ctrl_fw_flashing(struct device *dev); int apb_ctrl_standby_boot(struct device *dev); void apb_ctrl_poweroff(struct device *dev); -void apb_bootret_assert(struct device *dev); -void apb_bootret_deassert(struct device *dev); #endif /* __ARCHE_PLATFORM_H */ diff --git a/drivers/staging/greybus/light.c b/drivers/staging/greybus/light.c index 16813628eda1..861a249e6ef1 100644 --- a/drivers/staging/greybus/light.c +++ b/drivers/staging/greybus/light.c @@ -1030,7 +1030,7 @@ static int gb_lights_light_config(struct gb_lights *glights, u8 id) light->channels_count = conf.channel_count; light->name = kstrndup(conf.name, NAMES_MAX, GFP_KERNEL); - light->channels = kzalloc(light->channels_count * + light->channels = kcalloc(light->channels_count, sizeof(struct gb_channel), GFP_KERNEL); if (!light->channels) return -ENOMEM; @@ -1167,7 +1167,7 @@ static int gb_lights_create_all(struct gb_lights *glights) if (ret < 0) goto out; - glights->lights = kzalloc(glights->lights_count * + glights->lights = kcalloc(glights->lights_count, sizeof(struct gb_light), GFP_KERNEL); if (!glights->lights) { ret = -ENOMEM; diff --git a/drivers/staging/greybus/power_supply.c b/drivers/staging/greybus/power_supply.c index e85c988b7034..20cac20518d7 100644 --- a/drivers/staging/greybus/power_supply.c +++ b/drivers/staging/greybus/power_supply.c @@ -944,7 +944,7 @@ static int gb_power_supplies_setup(struct gb_power_supplies *supplies) if (ret < 0) goto out; - supplies->supply = kzalloc(supplies->supplies_count * + supplies->supply = kcalloc(supplies->supplies_count, sizeof(struct gb_power_supply), GFP_KERNEL); diff --git a/drivers/staging/iio/frequency/ad9834.c b/drivers/staging/iio/frequency/ad9834.c index af108e96b3ec..995acdd7c942 100644 --- a/drivers/staging/iio/frequency/ad9834.c +++ b/drivers/staging/iio/frequency/ad9834.c @@ -292,7 +292,7 @@ ssize_t ad9834_show_out0_wavetype_available(struct device *dev, return sprintf(buf, "%s\n", str); } -static IIO_DEVICE_ATTR(out_altvoltage0_out0_wavetype_available, S_IRUGO, +static IIO_DEVICE_ATTR(out_altvoltage0_out0_wavetype_available, 0444, ad9834_show_out0_wavetype_available, NULL, 0); static @@ -312,27 +312,27 @@ ssize_t ad9834_show_out1_wavetype_available(struct device *dev, return sprintf(buf, "%s\n", str); } -static IIO_DEVICE_ATTR(out_altvoltage0_out1_wavetype_available, S_IRUGO, +static IIO_DEVICE_ATTR(out_altvoltage0_out1_wavetype_available, 0444, ad9834_show_out1_wavetype_available, NULL, 0); /** * see dds.h for further information */ -static IIO_DEV_ATTR_FREQ(0, 0, S_IWUSR, NULL, ad9834_write, AD9834_REG_FREQ0); -static IIO_DEV_ATTR_FREQ(0, 1, S_IWUSR, NULL, ad9834_write, AD9834_REG_FREQ1); -static IIO_DEV_ATTR_FREQSYMBOL(0, S_IWUSR, NULL, ad9834_write, AD9834_FSEL); +static IIO_DEV_ATTR_FREQ(0, 0, 0200, NULL, ad9834_write, AD9834_REG_FREQ0); +static IIO_DEV_ATTR_FREQ(0, 1, 0200, NULL, ad9834_write, AD9834_REG_FREQ1); +static IIO_DEV_ATTR_FREQSYMBOL(0, 0200, NULL, ad9834_write, AD9834_FSEL); static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */ -static IIO_DEV_ATTR_PHASE(0, 0, S_IWUSR, NULL, ad9834_write, AD9834_REG_PHASE0); -static IIO_DEV_ATTR_PHASE(0, 1, S_IWUSR, NULL, ad9834_write, AD9834_REG_PHASE1); -static IIO_DEV_ATTR_PHASESYMBOL(0, S_IWUSR, NULL, ad9834_write, AD9834_PSEL); +static IIO_DEV_ATTR_PHASE(0, 0, 0200, NULL, ad9834_write, AD9834_REG_PHASE0); +static IIO_DEV_ATTR_PHASE(0, 1, 0200, NULL, ad9834_write, AD9834_REG_PHASE1); +static IIO_DEV_ATTR_PHASESYMBOL(0, 0200, NULL, ad9834_write, AD9834_PSEL); static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/ -static IIO_DEV_ATTR_PINCONTROL_EN(0, S_IWUSR, NULL, +static IIO_DEV_ATTR_PINCONTROL_EN(0, 0200, NULL, ad9834_write, AD9834_PIN_SW); -static IIO_DEV_ATTR_OUT_ENABLE(0, S_IWUSR, NULL, ad9834_write, AD9834_RESET); -static IIO_DEV_ATTR_OUTY_ENABLE(0, 1, S_IWUSR, NULL, +static IIO_DEV_ATTR_OUT_ENABLE(0, 0200, NULL, ad9834_write, AD9834_RESET); +static IIO_DEV_ATTR_OUTY_ENABLE(0, 1, 0200, NULL, ad9834_write, AD9834_OPBITEN); static IIO_DEV_ATTR_OUT_WAVETYPE(0, 0, ad9834_store_wavetype, 0); static IIO_DEV_ATTR_OUT_WAVETYPE(0, 1, ad9834_store_wavetype, 1); diff --git a/drivers/staging/iio/frequency/dds.h b/drivers/staging/iio/frequency/dds.h index fe53e7324c94..d6ccd99c14d7 100644 --- a/drivers/staging/iio/frequency/dds.h +++ b/drivers/staging/iio/frequency/dds.h @@ -101,7 +101,7 @@ #define IIO_DEV_ATTR_OUT_WAVETYPE(_channel, _output, _store, _addr) \ IIO_DEVICE_ATTR(out_altvoltage##_channel##_out##_output##_wavetype,\ - S_IWUSR, NULL, _store, _addr) + 0200, NULL, _store, _addr) /** * /sys/bus/iio/devices/.../out_altvoltageX_outY_wavetype_available diff --git a/drivers/staging/iio/light/Kconfig b/drivers/staging/iio/light/Kconfig index 4fbf6298c0f3..aacb0ae58c0e 100644 --- a/drivers/staging/iio/light/Kconfig +++ b/drivers/staging/iio/light/Kconfig @@ -3,16 +3,6 @@ # menu "Light sensors" -config SENSORS_ISL29028 - tristate "Intersil ISL29028 Concurrent Light and Proximity Sensor" - depends on I2C - select REGMAP_I2C - help - Provides driver for the Intersil's ISL29028 device. - This driver supports the sysfs interface to get the ALS, IR intensity, - Proximity value via iio. The ISL29028 provides the concurrent sensing - of ambient light and proximity. - config TSL2x7x tristate "TAOS TSL/TMD2x71 and TSL/TMD2x72 Family of light and proximity sensors" depends on I2C diff --git a/drivers/staging/iio/light/Makefile b/drivers/staging/iio/light/Makefile index f8693e9fdc94..ab8dc3a3d10b 100644 --- a/drivers/staging/iio/light/Makefile +++ b/drivers/staging/iio/light/Makefile @@ -2,5 +2,4 @@ # Makefile for industrial I/O Light sensors # -obj-$(CONFIG_SENSORS_ISL29028) += isl29028.o -obj-$(CONFIG_TSL2x7x) += tsl2x7x_core.o +obj-$(CONFIG_TSL2x7x) += tsl2x7x.o diff --git a/drivers/staging/iio/light/tsl2x7x_core.c b/drivers/staging/iio/light/tsl2x7x.c index af3910bc1b4f..146719928fb3 100644 --- a/drivers/staging/iio/light/tsl2x7x_core.c +++ b/drivers/staging/iio/light/tsl2x7x.c @@ -13,10 +13,6 @@ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ #include <linux/kernel.h> @@ -919,7 +915,7 @@ static void tsl2x7x_prox_cal(struct iio_dev *indio_dev) tsl2x7x_chip_on(indio_dev); } -static ssize_t tsl2x7x_power_state_show(struct device *dev, +static ssize_t power_state_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -928,7 +924,7 @@ static ssize_t tsl2x7x_power_state_show(struct device *dev, return snprintf(buf, PAGE_SIZE, "%d\n", chip->tsl2x7x_chip_status); } -static ssize_t tsl2x7x_power_state_store(struct device *dev, +static ssize_t power_state_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) { @@ -946,7 +942,7 @@ static ssize_t tsl2x7x_power_state_store(struct device *dev, return len; } -static ssize_t tsl2x7x_gain_available_show(struct device *dev, +static ssize_t in_illuminance0_calibscale_available_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -964,14 +960,14 @@ static ssize_t tsl2x7x_gain_available_show(struct device *dev, return snprintf(buf, PAGE_SIZE, "%s\n", "1 8 16 120"); } -static ssize_t tsl2x7x_prox_gain_available_show(struct device *dev, +static ssize_t in_proximity0_calibscale_available_show(struct device *dev, struct device_attribute *attr, char *buf) { return snprintf(buf, PAGE_SIZE, "%s\n", "1 2 4 8"); } -static ssize_t tsl2x7x_als_time_show(struct device *dev, +static ssize_t in_illuminance0_integration_time_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -986,7 +982,7 @@ static ssize_t tsl2x7x_als_time_show(struct device *dev, return snprintf(buf, PAGE_SIZE, "%d.%03d\n", y, z); } -static ssize_t tsl2x7x_als_time_store(struct device *dev, +static ssize_t in_illuminance0_integration_time_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) { @@ -1014,7 +1010,7 @@ static ssize_t tsl2x7x_als_time_store(struct device *dev, static IIO_CONST_ATTR(in_illuminance0_integration_time_available, ".00272 - .696"); -static ssize_t tsl2x7x_als_cal_target_show(struct device *dev, +static ssize_t in_illuminance0_target_input_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -1024,7 +1020,7 @@ static ssize_t tsl2x7x_als_cal_target_show(struct device *dev, chip->tsl2x7x_settings.als_cal_target); } -static ssize_t tsl2x7x_als_cal_target_store(struct device *dev, +static ssize_t in_illuminance0_target_input_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) { @@ -1044,7 +1040,7 @@ static ssize_t tsl2x7x_als_cal_target_store(struct device *dev, } /* persistence settings */ -static ssize_t tsl2x7x_als_persistence_show(struct device *dev, +static ssize_t in_intensity0_thresh_period_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -1061,7 +1057,7 @@ static ssize_t tsl2x7x_als_persistence_show(struct device *dev, return snprintf(buf, PAGE_SIZE, "%d.%03d\n", y, z); } -static ssize_t tsl2x7x_als_persistence_store(struct device *dev, +static ssize_t in_intensity0_thresh_period_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) { @@ -1092,7 +1088,7 @@ static ssize_t tsl2x7x_als_persistence_store(struct device *dev, return IIO_VAL_INT_PLUS_MICRO; } -static ssize_t tsl2x7x_prox_persistence_show(struct device *dev, +static ssize_t in_proximity0_thresh_period_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -1109,7 +1105,7 @@ static ssize_t tsl2x7x_prox_persistence_show(struct device *dev, return snprintf(buf, PAGE_SIZE, "%d.%03d\n", y, z); } -static ssize_t tsl2x7x_prox_persistence_store(struct device *dev, +static ssize_t in_proximity0_thresh_period_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) { @@ -1140,7 +1136,7 @@ static ssize_t tsl2x7x_prox_persistence_store(struct device *dev, return IIO_VAL_INT_PLUS_MICRO; } -static ssize_t tsl2x7x_do_calibrate(struct device *dev, +static ssize_t in_illuminance0_calibrate_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) { @@ -1158,7 +1154,7 @@ static ssize_t tsl2x7x_do_calibrate(struct device *dev, return len; } -static ssize_t tsl2x7x_luxtable_show(struct device *dev, +static ssize_t in_illuminance0_lux_table_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -1186,7 +1182,7 @@ static ssize_t tsl2x7x_luxtable_show(struct device *dev, return offset; } -static ssize_t tsl2x7x_luxtable_store(struct device *dev, +static ssize_t in_illuminance0_lux_table_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) { @@ -1226,7 +1222,7 @@ static ssize_t tsl2x7x_luxtable_store(struct device *dev, return len; } -static ssize_t tsl2x7x_do_prox_calibrate(struct device *dev, +static ssize_t in_proximity0_calibrate_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) { @@ -1498,35 +1494,25 @@ static int tsl2x7x_write_raw(struct iio_dev *indio_dev, return 0; } -static DEVICE_ATTR(power_state, S_IRUGO | S_IWUSR, - tsl2x7x_power_state_show, tsl2x7x_power_state_store); +static DEVICE_ATTR_RW(power_state); -static DEVICE_ATTR(in_proximity0_calibscale_available, S_IRUGO, - tsl2x7x_prox_gain_available_show, NULL); +static DEVICE_ATTR_RO(in_proximity0_calibscale_available); -static DEVICE_ATTR(in_illuminance0_calibscale_available, S_IRUGO, - tsl2x7x_gain_available_show, NULL); +static DEVICE_ATTR_RO(in_illuminance0_calibscale_available); -static DEVICE_ATTR(in_illuminance0_integration_time, S_IRUGO | S_IWUSR, - tsl2x7x_als_time_show, tsl2x7x_als_time_store); +static DEVICE_ATTR_RW(in_illuminance0_integration_time); -static DEVICE_ATTR(in_illuminance0_target_input, S_IRUGO | S_IWUSR, - tsl2x7x_als_cal_target_show, tsl2x7x_als_cal_target_store); +static DEVICE_ATTR_RW(in_illuminance0_target_input); -static DEVICE_ATTR(in_illuminance0_calibrate, S_IWUSR, NULL, - tsl2x7x_do_calibrate); +static DEVICE_ATTR_WO(in_illuminance0_calibrate); -static DEVICE_ATTR(in_proximity0_calibrate, S_IWUSR, NULL, - tsl2x7x_do_prox_calibrate); +static DEVICE_ATTR_WO(in_proximity0_calibrate); -static DEVICE_ATTR(in_illuminance0_lux_table, S_IRUGO | S_IWUSR, - tsl2x7x_luxtable_show, tsl2x7x_luxtable_store); +static DEVICE_ATTR_RW(in_illuminance0_lux_table); -static DEVICE_ATTR(in_intensity0_thresh_period, S_IRUGO | S_IWUSR, - tsl2x7x_als_persistence_show, tsl2x7x_als_persistence_store); +static DEVICE_ATTR_RW(in_intensity0_thresh_period); -static DEVICE_ATTR(in_proximity0_thresh_period, S_IRUGO | S_IWUSR, - tsl2x7x_prox_persistence_show, tsl2x7x_prox_persistence_store); +static DEVICE_ATTR_RW(in_proximity0_thresh_period); /* Use the default register values to identify the Taos device */ static int tsl2x7x_device_id(unsigned char *id, int target) diff --git a/drivers/staging/iio/meter/ade7753.c b/drivers/staging/iio/meter/ade7753.c index b71fbd313778..ce26abdeab92 100644 --- a/drivers/staging/iio/meter/ade7753.c +++ b/drivers/staging/iio/meter/ade7753.c @@ -107,9 +107,8 @@ static int ade7753_spi_write_reg_8(struct device *dev, return ret; } -static int ade7753_spi_write_reg_16(struct device *dev, - u8 reg_address, - u16 value) +static int ade7753_spi_write_reg_16(struct device *dev, u8 reg_address, + u16 value) { int ret; struct iio_dev *indio_dev = dev_to_iio_dev(dev); @@ -126,8 +125,8 @@ static int ade7753_spi_write_reg_16(struct device *dev, } static int ade7753_spi_read_reg_8(struct device *dev, - u8 reg_address, - u8 *val) + u8 reg_address, + u8 *val) { struct iio_dev *indio_dev = dev_to_iio_dev(dev); struct ade7753_state *st = iio_priv(indio_dev); @@ -136,7 +135,7 @@ static int ade7753_spi_read_reg_8(struct device *dev, ret = spi_w8r8(st->us, ADE7753_READ_REG(reg_address)); if (ret < 0) { dev_err(&st->us->dev, "problem when reading 8 bit register 0x%02X", - reg_address); + reg_address); return ret; } *val = ret; @@ -145,8 +144,8 @@ static int ade7753_spi_read_reg_8(struct device *dev, } static int ade7753_spi_read_reg_16(struct device *dev, - u8 reg_address, - u16 *val) + u8 reg_address, + u16 *val) { struct iio_dev *indio_dev = dev_to_iio_dev(dev); struct ade7753_state *st = iio_priv(indio_dev); @@ -165,8 +164,8 @@ static int ade7753_spi_read_reg_16(struct device *dev, } static int ade7753_spi_read_reg_24(struct device *dev, - u8 reg_address, - u32 *val) + u8 reg_address, + u32 *val) { struct iio_dev *indio_dev = dev_to_iio_dev(dev); struct ade7753_state *st = iio_priv(indio_dev); @@ -189,7 +188,7 @@ static int ade7753_spi_read_reg_24(struct device *dev, ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers)); if (ret) { dev_err(&st->us->dev, "problem when reading 24 bit register 0x%02X", - reg_address); + reg_address); goto error_ret; } *val = (st->rx[0] << 16) | (st->rx[1] << 8) | st->rx[2]; @@ -200,8 +199,8 @@ error_ret: } static ssize_t ade7753_read_8bit(struct device *dev, - struct device_attribute *attr, - char *buf) + struct device_attribute *attr, + char *buf) { int ret; u8 val; @@ -215,8 +214,8 @@ static ssize_t ade7753_read_8bit(struct device *dev, } static ssize_t ade7753_read_16bit(struct device *dev, - struct device_attribute *attr, - char *buf) + struct device_attribute *attr, + char *buf) { int ret; u16 val; @@ -230,8 +229,8 @@ static ssize_t ade7753_read_16bit(struct device *dev, } static ssize_t ade7753_read_24bit(struct device *dev, - struct device_attribute *attr, - char *buf) + struct device_attribute *attr, + char *buf) { int ret; u32 val; @@ -245,9 +244,9 @@ static ssize_t ade7753_read_24bit(struct device *dev, } static ssize_t ade7753_write_8bit(struct device *dev, - struct device_attribute *attr, - const char *buf, - size_t len) + struct device_attribute *attr, + const char *buf, + size_t len) { struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); int ret; @@ -263,9 +262,9 @@ error_ret: } static ssize_t ade7753_write_16bit(struct device *dev, - struct device_attribute *attr, - const char *buf, - size_t len) + struct device_attribute *attr, + const char *buf, + size_t len) { struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); int ret; @@ -298,92 +297,92 @@ static IIO_DEV_ATTR_AENERGY(ade7753_read_24bit, ADE7753_AENERGY); static IIO_DEV_ATTR_LAENERGY(ade7753_read_24bit, ADE7753_LAENERGY); static IIO_DEV_ATTR_VAENERGY(ade7753_read_24bit, ADE7753_VAENERGY); static IIO_DEV_ATTR_LVAENERGY(ade7753_read_24bit, ADE7753_LVAENERGY); -static IIO_DEV_ATTR_CFDEN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_CFDEN(0644, ade7753_read_16bit, ade7753_write_16bit, ADE7753_CFDEN); -static IIO_DEV_ATTR_CFNUM(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_CFNUM(0644, ade7753_read_8bit, ade7753_write_8bit, ADE7753_CFNUM); static IIO_DEV_ATTR_CHKSUM(ade7753_read_8bit, ADE7753_CHKSUM); -static IIO_DEV_ATTR_PHCAL(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_PHCAL(0644, ade7753_read_16bit, ade7753_write_16bit, ADE7753_PHCAL); -static IIO_DEV_ATTR_APOS(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_APOS(0644, ade7753_read_16bit, ade7753_write_16bit, ADE7753_APOS); -static IIO_DEV_ATTR_SAGCYC(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_SAGCYC(0644, ade7753_read_8bit, ade7753_write_8bit, ADE7753_SAGCYC); -static IIO_DEV_ATTR_SAGLVL(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_SAGLVL(0644, ade7753_read_8bit, ade7753_write_8bit, ADE7753_SAGLVL); -static IIO_DEV_ATTR_LINECYC(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_LINECYC(0644, ade7753_read_8bit, ade7753_write_8bit, ADE7753_LINECYC); -static IIO_DEV_ATTR_WDIV(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_WDIV(0644, ade7753_read_8bit, ade7753_write_8bit, ADE7753_WDIV); -static IIO_DEV_ATTR_IRMS(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_IRMS(0644, ade7753_read_24bit, NULL, ADE7753_IRMS); -static IIO_DEV_ATTR_VRMS(S_IRUGO, +static IIO_DEV_ATTR_VRMS(0444, ade7753_read_24bit, NULL, ADE7753_VRMS); -static IIO_DEV_ATTR_IRMSOS(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_IRMSOS(0644, ade7753_read_16bit, ade7753_write_16bit, ADE7753_IRMSOS); -static IIO_DEV_ATTR_VRMSOS(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_VRMSOS(0644, ade7753_read_16bit, ade7753_write_16bit, ADE7753_VRMSOS); -static IIO_DEV_ATTR_WGAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_WGAIN(0644, ade7753_read_16bit, ade7753_write_16bit, ADE7753_WGAIN); -static IIO_DEV_ATTR_VAGAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_VAGAIN(0644, ade7753_read_16bit, ade7753_write_16bit, ADE7753_VAGAIN); -static IIO_DEV_ATTR_PGA_GAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_PGA_GAIN(0644, ade7753_read_16bit, ade7753_write_16bit, ADE7753_GAIN); -static IIO_DEV_ATTR_IPKLVL(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_IPKLVL(0644, ade7753_read_8bit, ade7753_write_8bit, ADE7753_IPKLVL); -static IIO_DEV_ATTR_VPKLVL(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_VPKLVL(0644, ade7753_read_8bit, ade7753_write_8bit, ADE7753_VPKLVL); -static IIO_DEV_ATTR_IPEAK(S_IRUGO, +static IIO_DEV_ATTR_IPEAK(0444, ade7753_read_24bit, NULL, ADE7753_IPEAK); -static IIO_DEV_ATTR_VPEAK(S_IRUGO, +static IIO_DEV_ATTR_VPEAK(0444, ade7753_read_24bit, NULL, ADE7753_VPEAK); -static IIO_DEV_ATTR_VPERIOD(S_IRUGO, +static IIO_DEV_ATTR_VPERIOD(0444, ade7753_read_16bit, NULL, ADE7753_PERIOD); -static IIO_DEV_ATTR_CH_OFF(1, S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_CH_OFF(1, 0644, ade7753_read_8bit, ade7753_write_8bit, ADE7753_CH1OS); -static IIO_DEV_ATTR_CH_OFF(2, S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_CH_OFF(2, 0644, ade7753_read_8bit, ade7753_write_8bit, ADE7753_CH2OS); @@ -450,8 +449,8 @@ err_ret: } static ssize_t ade7753_read_frequency(struct device *dev, - struct device_attribute *attr, - char *buf) + struct device_attribute *attr, + char *buf) { int ret; u16 t; @@ -468,9 +467,9 @@ static ssize_t ade7753_read_frequency(struct device *dev, } static ssize_t ade7753_write_frequency(struct device *dev, - struct device_attribute *attr, - const char *buf, - size_t len) + struct device_attribute *attr, + const char *buf, + size_t len) { struct iio_dev *indio_dev = dev_to_iio_dev(dev); struct ade7753_state *st = iio_priv(indio_dev); @@ -514,7 +513,7 @@ static IIO_DEV_ATTR_TEMP_RAW(ade7753_read_8bit); static IIO_CONST_ATTR(in_temp_offset, "-25 C"); static IIO_CONST_ATTR(in_temp_scale, "0.67 C"); -static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_SAMP_FREQ(0644, ade7753_read_frequency, ade7753_write_frequency); diff --git a/drivers/staging/iio/meter/ade7754.c b/drivers/staging/iio/meter/ade7754.c index 32dc50341746..be0df3fe4230 100644 --- a/drivers/staging/iio/meter/ade7754.c +++ b/drivers/staging/iio/meter/ade7754.c @@ -316,111 +316,111 @@ static IIO_DEV_ATTR_AENERGY(ade7754_read_24bit, ADE7754_AENERGY); static IIO_DEV_ATTR_LAENERGY(ade7754_read_24bit, ADE7754_LAENERGY); static IIO_DEV_ATTR_VAENERGY(ade7754_read_24bit, ADE7754_VAENERGY); static IIO_DEV_ATTR_LVAENERGY(ade7754_read_24bit, ADE7754_LVAENERGY); -static IIO_DEV_ATTR_VPEAK(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_VPEAK(0644, ade7754_read_8bit, ade7754_write_8bit, ADE7754_VPEAK); -static IIO_DEV_ATTR_IPEAK(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_IPEAK(0644, ade7754_read_8bit, ade7754_write_8bit, ADE7754_VPEAK); -static IIO_DEV_ATTR_APHCAL(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_APHCAL(0644, ade7754_read_8bit, ade7754_write_8bit, ADE7754_APHCAL); -static IIO_DEV_ATTR_BPHCAL(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_BPHCAL(0644, ade7754_read_8bit, ade7754_write_8bit, ADE7754_BPHCAL); -static IIO_DEV_ATTR_CPHCAL(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_CPHCAL(0644, ade7754_read_8bit, ade7754_write_8bit, ADE7754_CPHCAL); -static IIO_DEV_ATTR_AAPOS(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_AAPOS(0644, ade7754_read_16bit, ade7754_write_16bit, ADE7754_AAPOS); -static IIO_DEV_ATTR_BAPOS(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_BAPOS(0644, ade7754_read_16bit, ade7754_write_16bit, ADE7754_BAPOS); -static IIO_DEV_ATTR_CAPOS(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_CAPOS(0644, ade7754_read_16bit, ade7754_write_16bit, ADE7754_CAPOS); -static IIO_DEV_ATTR_WDIV(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_WDIV(0644, ade7754_read_8bit, ade7754_write_8bit, ADE7754_WDIV); -static IIO_DEV_ATTR_VADIV(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_VADIV(0644, ade7754_read_8bit, ade7754_write_8bit, ADE7754_VADIV); -static IIO_DEV_ATTR_CFNUM(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_CFNUM(0644, ade7754_read_16bit, ade7754_write_16bit, ADE7754_CFNUM); -static IIO_DEV_ATTR_CFDEN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_CFDEN(0644, ade7754_read_16bit, ade7754_write_16bit, ADE7754_CFDEN); -static IIO_DEV_ATTR_ACTIVE_POWER_A_GAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_ACTIVE_POWER_A_GAIN(0644, ade7754_read_16bit, ade7754_write_16bit, ADE7754_AAPGAIN); -static IIO_DEV_ATTR_ACTIVE_POWER_B_GAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_ACTIVE_POWER_B_GAIN(0644, ade7754_read_16bit, ade7754_write_16bit, ADE7754_BAPGAIN); -static IIO_DEV_ATTR_ACTIVE_POWER_C_GAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_ACTIVE_POWER_C_GAIN(0644, ade7754_read_16bit, ade7754_write_16bit, ADE7754_CAPGAIN); -static IIO_DEV_ATTR_AIRMS(S_IRUGO, +static IIO_DEV_ATTR_AIRMS(0444, ade7754_read_24bit, NULL, ADE7754_AIRMS); -static IIO_DEV_ATTR_BIRMS(S_IRUGO, +static IIO_DEV_ATTR_BIRMS(0444, ade7754_read_24bit, NULL, ADE7754_BIRMS); -static IIO_DEV_ATTR_CIRMS(S_IRUGO, +static IIO_DEV_ATTR_CIRMS(0444, ade7754_read_24bit, NULL, ADE7754_CIRMS); -static IIO_DEV_ATTR_AVRMS(S_IRUGO, +static IIO_DEV_ATTR_AVRMS(0444, ade7754_read_24bit, NULL, ADE7754_AVRMS); -static IIO_DEV_ATTR_BVRMS(S_IRUGO, +static IIO_DEV_ATTR_BVRMS(0444, ade7754_read_24bit, NULL, ADE7754_BVRMS); -static IIO_DEV_ATTR_CVRMS(S_IRUGO, +static IIO_DEV_ATTR_CVRMS(0444, ade7754_read_24bit, NULL, ADE7754_CVRMS); -static IIO_DEV_ATTR_AIRMSOS(S_IRUGO, +static IIO_DEV_ATTR_AIRMSOS(0444, ade7754_read_16bit, ade7754_write_16bit, ADE7754_AIRMSOS); -static IIO_DEV_ATTR_BIRMSOS(S_IRUGO, +static IIO_DEV_ATTR_BIRMSOS(0444, ade7754_read_16bit, ade7754_write_16bit, ADE7754_BIRMSOS); -static IIO_DEV_ATTR_CIRMSOS(S_IRUGO, +static IIO_DEV_ATTR_CIRMSOS(0444, ade7754_read_16bit, ade7754_write_16bit, ADE7754_CIRMSOS); -static IIO_DEV_ATTR_AVRMSOS(S_IRUGO, +static IIO_DEV_ATTR_AVRMSOS(0444, ade7754_read_16bit, ade7754_write_16bit, ADE7754_AVRMSOS); -static IIO_DEV_ATTR_BVRMSOS(S_IRUGO, +static IIO_DEV_ATTR_BVRMSOS(0444, ade7754_read_16bit, ade7754_write_16bit, ADE7754_BVRMSOS); -static IIO_DEV_ATTR_CVRMSOS(S_IRUGO, +static IIO_DEV_ATTR_CVRMSOS(0444, ade7754_read_16bit, ade7754_write_16bit, ADE7754_CVRMSOS); @@ -549,7 +549,7 @@ static IIO_DEV_ATTR_TEMP_RAW(ade7754_read_8bit); static IIO_CONST_ATTR(in_temp_offset, "129 C"); static IIO_CONST_ATTR(in_temp_scale, "4 C"); -static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_SAMP_FREQ(0644, ade7754_read_frequency, ade7754_write_frequency); diff --git a/drivers/staging/iio/meter/ade7758_core.c b/drivers/staging/iio/meter/ade7758_core.c index 99c89e606c8d..40498af4dc46 100644 --- a/drivers/staging/iio/meter/ade7758_core.c +++ b/drivers/staging/iio/meter/ade7758_core.c @@ -301,103 +301,103 @@ static int ade7758_reset(struct device *dev) return ret; } -static IIO_DEV_ATTR_VPEAK(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_VPEAK(0644, ade7758_read_8bit, ade7758_write_8bit, ADE7758_VPEAK); -static IIO_DEV_ATTR_IPEAK(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_IPEAK(0644, ade7758_read_8bit, ade7758_write_8bit, ADE7758_VPEAK); -static IIO_DEV_ATTR_APHCAL(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_APHCAL(0644, ade7758_read_8bit, ade7758_write_8bit, ADE7758_APHCAL); -static IIO_DEV_ATTR_BPHCAL(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_BPHCAL(0644, ade7758_read_8bit, ade7758_write_8bit, ADE7758_BPHCAL); -static IIO_DEV_ATTR_CPHCAL(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_CPHCAL(0644, ade7758_read_8bit, ade7758_write_8bit, ADE7758_CPHCAL); -static IIO_DEV_ATTR_WDIV(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_WDIV(0644, ade7758_read_8bit, ade7758_write_8bit, ADE7758_WDIV); -static IIO_DEV_ATTR_VADIV(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_VADIV(0644, ade7758_read_8bit, ade7758_write_8bit, ADE7758_VADIV); -static IIO_DEV_ATTR_AIRMS(S_IRUGO, +static IIO_DEV_ATTR_AIRMS(0444, ade7758_read_24bit, NULL, ADE7758_AIRMS); -static IIO_DEV_ATTR_BIRMS(S_IRUGO, +static IIO_DEV_ATTR_BIRMS(0444, ade7758_read_24bit, NULL, ADE7758_BIRMS); -static IIO_DEV_ATTR_CIRMS(S_IRUGO, +static IIO_DEV_ATTR_CIRMS(0444, ade7758_read_24bit, NULL, ADE7758_CIRMS); -static IIO_DEV_ATTR_AVRMS(S_IRUGO, +static IIO_DEV_ATTR_AVRMS(0444, ade7758_read_24bit, NULL, ADE7758_AVRMS); -static IIO_DEV_ATTR_BVRMS(S_IRUGO, +static IIO_DEV_ATTR_BVRMS(0444, ade7758_read_24bit, NULL, ADE7758_BVRMS); -static IIO_DEV_ATTR_CVRMS(S_IRUGO, +static IIO_DEV_ATTR_CVRMS(0444, ade7758_read_24bit, NULL, ADE7758_CVRMS); -static IIO_DEV_ATTR_AIRMSOS(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_AIRMSOS(0644, ade7758_read_16bit, ade7758_write_16bit, ADE7758_AIRMSOS); -static IIO_DEV_ATTR_BIRMSOS(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_BIRMSOS(0644, ade7758_read_16bit, ade7758_write_16bit, ADE7758_BIRMSOS); -static IIO_DEV_ATTR_CIRMSOS(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_CIRMSOS(0644, ade7758_read_16bit, ade7758_write_16bit, ADE7758_CIRMSOS); -static IIO_DEV_ATTR_AVRMSOS(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_AVRMSOS(0644, ade7758_read_16bit, ade7758_write_16bit, ADE7758_AVRMSOS); -static IIO_DEV_ATTR_BVRMSOS(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_BVRMSOS(0644, ade7758_read_16bit, ade7758_write_16bit, ADE7758_BVRMSOS); -static IIO_DEV_ATTR_CVRMSOS(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_CVRMSOS(0644, ade7758_read_16bit, ade7758_write_16bit, ADE7758_CVRMSOS); -static IIO_DEV_ATTR_AIGAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_AIGAIN(0644, ade7758_read_16bit, ade7758_write_16bit, ADE7758_AIGAIN); -static IIO_DEV_ATTR_BIGAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_BIGAIN(0644, ade7758_read_16bit, ade7758_write_16bit, ADE7758_BIGAIN); -static IIO_DEV_ATTR_CIGAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_CIGAIN(0644, ade7758_read_16bit, ade7758_write_16bit, ADE7758_CIGAIN); -static IIO_DEV_ATTR_AVRMSGAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_AVRMSGAIN(0644, ade7758_read_16bit, ade7758_write_16bit, ADE7758_AVRMSGAIN); -static IIO_DEV_ATTR_BVRMSGAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_BVRMSGAIN(0644, ade7758_read_16bit, ade7758_write_16bit, ADE7758_BVRMSGAIN); -static IIO_DEV_ATTR_CVRMSGAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_CVRMSGAIN(0644, ade7758_read_16bit, ade7758_write_16bit, ADE7758_CVRMSGAIN); diff --git a/drivers/staging/iio/meter/ade7854.c b/drivers/staging/iio/meter/ade7854.c index c6cffc11b0ba..70612da64a8b 100644 --- a/drivers/staging/iio/meter/ade7854.c +++ b/drivers/staging/iio/meter/ade7854.c @@ -186,127 +186,127 @@ static int ade7854_reset(struct device *dev) return st->write_reg_16(dev, ADE7854_CONFIG, val); } -static IIO_DEV_ATTR_AIGAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_AIGAIN(0644, ade7854_read_24bit, ade7854_write_24bit, ADE7854_AIGAIN); -static IIO_DEV_ATTR_BIGAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_BIGAIN(0644, ade7854_read_24bit, ade7854_write_24bit, ADE7854_BIGAIN); -static IIO_DEV_ATTR_CIGAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_CIGAIN(0644, ade7854_read_24bit, ade7854_write_24bit, ADE7854_CIGAIN); -static IIO_DEV_ATTR_NIGAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_NIGAIN(0644, ade7854_read_24bit, ade7854_write_24bit, ADE7854_NIGAIN); -static IIO_DEV_ATTR_AVGAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_AVGAIN(0644, ade7854_read_24bit, ade7854_write_24bit, ADE7854_AVGAIN); -static IIO_DEV_ATTR_BVGAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_BVGAIN(0644, ade7854_read_24bit, ade7854_write_24bit, ADE7854_BVGAIN); -static IIO_DEV_ATTR_CVGAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_CVGAIN(0644, ade7854_read_24bit, ade7854_write_24bit, ADE7854_CVGAIN); -static IIO_DEV_ATTR_APPARENT_POWER_A_GAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_APPARENT_POWER_A_GAIN(0644, ade7854_read_24bit, ade7854_write_24bit, ADE7854_AVAGAIN); -static IIO_DEV_ATTR_APPARENT_POWER_B_GAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_APPARENT_POWER_B_GAIN(0644, ade7854_read_24bit, ade7854_write_24bit, ADE7854_BVAGAIN); -static IIO_DEV_ATTR_APPARENT_POWER_C_GAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_APPARENT_POWER_C_GAIN(0644, ade7854_read_24bit, ade7854_write_24bit, ADE7854_CVAGAIN); -static IIO_DEV_ATTR_ACTIVE_POWER_A_OFFSET(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_ACTIVE_POWER_A_OFFSET(0644, ade7854_read_24bit, ade7854_write_24bit, ADE7854_AWATTOS); -static IIO_DEV_ATTR_ACTIVE_POWER_B_OFFSET(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_ACTIVE_POWER_B_OFFSET(0644, ade7854_read_24bit, ade7854_write_24bit, ADE7854_BWATTOS); -static IIO_DEV_ATTR_ACTIVE_POWER_C_OFFSET(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_ACTIVE_POWER_C_OFFSET(0644, ade7854_read_24bit, ade7854_write_24bit, ADE7854_CWATTOS); -static IIO_DEV_ATTR_REACTIVE_POWER_A_GAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_REACTIVE_POWER_A_GAIN(0644, ade7854_read_24bit, ade7854_write_24bit, ADE7854_AVARGAIN); -static IIO_DEV_ATTR_REACTIVE_POWER_B_GAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_REACTIVE_POWER_B_GAIN(0644, ade7854_read_24bit, ade7854_write_24bit, ADE7854_BVARGAIN); -static IIO_DEV_ATTR_REACTIVE_POWER_C_GAIN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_REACTIVE_POWER_C_GAIN(0644, ade7854_read_24bit, ade7854_write_24bit, ADE7854_CVARGAIN); -static IIO_DEV_ATTR_REACTIVE_POWER_A_OFFSET(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_REACTIVE_POWER_A_OFFSET(0644, ade7854_read_24bit, ade7854_write_24bit, ADE7854_AVAROS); -static IIO_DEV_ATTR_REACTIVE_POWER_B_OFFSET(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_REACTIVE_POWER_B_OFFSET(0644, ade7854_read_24bit, ade7854_write_24bit, ADE7854_BVAROS); -static IIO_DEV_ATTR_REACTIVE_POWER_C_OFFSET(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_REACTIVE_POWER_C_OFFSET(0644, ade7854_read_24bit, ade7854_write_24bit, ADE7854_CVAROS); -static IIO_DEV_ATTR_VPEAK(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_VPEAK(0644, ade7854_read_32bit, ade7854_write_32bit, ADE7854_VPEAK); -static IIO_DEV_ATTR_IPEAK(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_IPEAK(0644, ade7854_read_32bit, ade7854_write_32bit, ADE7854_VPEAK); -static IIO_DEV_ATTR_APHCAL(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_APHCAL(0644, ade7854_read_16bit, ade7854_write_16bit, ADE7854_APHCAL); -static IIO_DEV_ATTR_BPHCAL(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_BPHCAL(0644, ade7854_read_16bit, ade7854_write_16bit, ADE7854_BPHCAL); -static IIO_DEV_ATTR_CPHCAL(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_CPHCAL(0644, ade7854_read_16bit, ade7854_write_16bit, ADE7854_CPHCAL); -static IIO_DEV_ATTR_CF1DEN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_CF1DEN(0644, ade7854_read_16bit, ade7854_write_16bit, ADE7854_CF1DEN); -static IIO_DEV_ATTR_CF2DEN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_CF2DEN(0644, ade7854_read_16bit, ade7854_write_16bit, ADE7854_CF2DEN); -static IIO_DEV_ATTR_CF3DEN(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_CF3DEN(0644, ade7854_read_16bit, ade7854_write_16bit, ADE7854_CF3DEN); -static IIO_DEV_ATTR_LINECYC(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_LINECYC(0644, ade7854_read_16bit, ade7854_write_16bit, ADE7854_LINECYC); -static IIO_DEV_ATTR_SAGCYC(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_SAGCYC(0644, ade7854_read_8bit, ade7854_write_8bit, ADE7854_SAGCYC); -static IIO_DEV_ATTR_CFCYC(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_CFCYC(0644, ade7854_read_8bit, ade7854_write_8bit, ADE7854_CFCYC); -static IIO_DEV_ATTR_PEAKCYC(S_IWUSR | S_IRUGO, +static IIO_DEV_ATTR_PEAKCYC(0644, ade7854_read_8bit, ade7854_write_8bit, ADE7854_PEAKCYC); @@ -318,55 +318,55 @@ static IIO_DEV_ATTR_ANGLE1(ade7854_read_24bit, ADE7854_ANGLE1); static IIO_DEV_ATTR_ANGLE2(ade7854_read_24bit, ADE7854_ANGLE2); -static IIO_DEV_ATTR_AIRMS(S_IRUGO, +static IIO_DEV_ATTR_AIRMS(0444, ade7854_read_24bit, NULL, ADE7854_AIRMS); -static IIO_DEV_ATTR_BIRMS(S_IRUGO, +static IIO_DEV_ATTR_BIRMS(0444, ade7854_read_24bit, NULL, ADE7854_BIRMS); -static IIO_DEV_ATTR_CIRMS(S_IRUGO, +static IIO_DEV_ATTR_CIRMS(0444, ade7854_read_24bit, NULL, ADE7854_CIRMS); -static IIO_DEV_ATTR_NIRMS(S_IRUGO, +static IIO_DEV_ATTR_NIRMS(0444, ade7854_read_24bit, NULL, ADE7854_NIRMS); -static IIO_DEV_ATTR_AVRMS(S_IRUGO, +static IIO_DEV_ATTR_AVRMS(0444, ade7854_read_24bit, NULL, ADE7854_AVRMS); -static IIO_DEV_ATTR_BVRMS(S_IRUGO, +static IIO_DEV_ATTR_BVRMS(0444, ade7854_read_24bit, NULL, ADE7854_BVRMS); -static IIO_DEV_ATTR_CVRMS(S_IRUGO, +static IIO_DEV_ATTR_CVRMS(0444, ade7854_read_24bit, NULL, ADE7854_CVRMS); -static IIO_DEV_ATTR_AIRMSOS(S_IRUGO, +static IIO_DEV_ATTR_AIRMSOS(0444, ade7854_read_16bit, ade7854_write_16bit, ADE7854_AIRMSOS); -static IIO_DEV_ATTR_BIRMSOS(S_IRUGO, +static IIO_DEV_ATTR_BIRMSOS(0444, ade7854_read_16bit, ade7854_write_16bit, ADE7854_BIRMSOS); -static IIO_DEV_ATTR_CIRMSOS(S_IRUGO, +static IIO_DEV_ATTR_CIRMSOS(0444, ade7854_read_16bit, ade7854_write_16bit, ADE7854_CIRMSOS); -static IIO_DEV_ATTR_AVRMSOS(S_IRUGO, +static IIO_DEV_ATTR_AVRMSOS(0444, ade7854_read_16bit, ade7854_write_16bit, ADE7854_AVRMSOS); -static IIO_DEV_ATTR_BVRMSOS(S_IRUGO, +static IIO_DEV_ATTR_BVRMSOS(0444, ade7854_read_16bit, ade7854_write_16bit, ADE7854_BVRMSOS); -static IIO_DEV_ATTR_CVRMSOS(S_IRUGO, +static IIO_DEV_ATTR_CVRMSOS(0444, ade7854_read_16bit, ade7854_write_16bit, ADE7854_CVRMSOS); diff --git a/drivers/staging/ks7010/eap_packet.h b/drivers/staging/ks7010/eap_packet.h index b2d25ef1cd6b..ae03f7477324 100644 --- a/drivers/staging/ks7010/eap_packet.h +++ b/drivers/staging/ks7010/eap_packet.h @@ -18,7 +18,7 @@ struct ether_hdr { unsigned char h_source_snap; unsigned char h_command; unsigned char h_vendor_id[3]; - unsigned short h_proto; /* packet type ID field */ + __be16 h_proto; /* packet type ID field */ #define ETHER_PROTOCOL_TYPE_EAP 0x888e #define ETHER_PROTOCOL_TYPE_IP 0x0800 #define ETHER_PROTOCOL_TYPE_ARP 0x0806 @@ -91,7 +91,7 @@ struct ieee802_1x_eapol_key { struct wpa_eapol_key { unsigned char type; - unsigned short key_info; + __be16 key_info; unsigned short key_length; unsigned char replay_counter[WPA_REPLAY_COUNTER_LEN]; unsigned char key_nonce[WPA_NONCE_LEN]; diff --git a/drivers/staging/ks7010/ks7010_sdio.c b/drivers/staging/ks7010/ks7010_sdio.c index c325f4846209..9b28ee1cfb1e 100644 --- a/drivers/staging/ks7010/ks7010_sdio.c +++ b/drivers/staging/ks7010/ks7010_sdio.c @@ -269,7 +269,8 @@ static int write_to_device(struct ks_wlan_private *priv, unsigned char *buffer, hdr = (struct hostif_hdr *)buffer; DPRINTK(4, "size=%d\n", hdr->size); - if (hdr->event < HIF_DATA_REQ || HIF_REQ_MAX < hdr->event) { + if (le16_to_cpu(hdr->event) < HIF_DATA_REQ || + le16_to_cpu(hdr->event) > HIF_REQ_MAX) { DPRINTK(1, "unknown event=%04X\n", hdr->event); return 0; } @@ -327,13 +328,14 @@ int ks_wlan_hw_tx(struct ks_wlan_private *priv, void *p, unsigned long size, hdr = (struct hostif_hdr *)p; - if (hdr->event < HIF_DATA_REQ || HIF_REQ_MAX < hdr->event) { + if (le16_to_cpu(hdr->event) < HIF_DATA_REQ || + le16_to_cpu(hdr->event) > HIF_REQ_MAX) { DPRINTK(1, "unknown event=%04X\n", hdr->event); return 0; } /* add event to hostt buffer */ - priv->hostt.buff[priv->hostt.qtail] = hdr->event; + priv->hostt.buff[priv->hostt.qtail] = le16_to_cpu(hdr->event); priv->hostt.qtail = (priv->hostt.qtail + 1) % SME_EVENT_BUFF_SIZE; DPRINTK(4, "event=%04X\n", hdr->event); @@ -403,7 +405,7 @@ static void ks_wlan_hw_rx(struct ks_wlan_private *priv, uint16_t size) hdr = (struct hostif_hdr *)&rx_buffer->data[0]; rx_buffer->size = le16_to_cpu(hdr->size) + sizeof(hdr->size); - event = hdr->event; + event = le16_to_cpu(hdr->event); inc_rxqtail(priv); ret = ks7010_sdio_writeb(priv, READ_STATUS, REG_STATUS_IDLE); diff --git a/drivers/staging/ks7010/ks_hostif.c b/drivers/staging/ks7010/ks_hostif.c index 49e95426ac30..db01a486a5a4 100644 --- a/drivers/staging/ks7010/ks_hostif.c +++ b/drivers/staging/ks7010/ks_hostif.c @@ -147,7 +147,7 @@ int get_current_ap(struct ks_wlan_private *priv, struct link_ap_info_t *ap_info) /* noise */ ap->noise = ap_info->noise; /* capability */ - ap->capability = ap_info->capability; + ap->capability = le16_to_cpu(ap_info->capability); /* rsn */ if ((ap_info->rsn_mode & RSN_MODE_WPA2) && (priv->wpa.version == IW_AUTH_WPA_VERSION_WPA2)) { @@ -233,12 +233,12 @@ int get_ap_information(struct ks_wlan_private *priv, struct ap_info_t *ap_info, /* noise */ ap->noise = ap_info->noise; /* capability */ - ap->capability = ap_info->capability; + ap->capability = le16_to_cpu(ap_info->capability); /* channel */ ap->channel = ap_info->ch_info; bp = ap_info->body; - bsize = ap_info->body_size; + bsize = le16_to_cpu(ap_info->body_size); offset = 0; while (bsize > offset) { @@ -567,9 +567,9 @@ void hostif_mib_get_confirm(struct ks_wlan_private *priv) break; case LOCAL_GAIN: memcpy(&priv->gain, priv->rxp, sizeof(priv->gain)); - DPRINTK(3, "TxMode=%d, RxMode=%d, TxGain=%d, RxGain=%d\n", - priv->gain.TxMode, priv->gain.RxMode, priv->gain.TxGain, - priv->gain.RxGain); + DPRINTK(3, "tx_mode=%d, rx_mode=%d, tx_gain=%d, rx_gain=%d\n", + priv->gain.tx_mode, priv->gain.rx_mode, + priv->gain.tx_gain, priv->gain.rx_gain); break; case LOCAL_EEPROM_SUM: memcpy(&priv->eeprom_sum, priv->rxp, sizeof(priv->eeprom_sum)); @@ -948,18 +948,18 @@ void hostif_associate_indication(struct ks_wlan_private *priv) wrqu.data.length += sizeof(associnfo_leader0) - 1; pbuf += sizeof(associnfo_leader0) - 1; - for (i = 0; i < assoc_req->reqIEs_size; i++) + for (i = 0; i < le16_to_cpu(assoc_req->req_ies_size); i++) pbuf += sprintf(pbuf, "%02x", *(pb + i)); - wrqu.data.length += (assoc_req->reqIEs_size) * 2; + wrqu.data.length += (le16_to_cpu(assoc_req->req_ies_size)) * 2; memcpy(pbuf, associnfo_leader1, sizeof(associnfo_leader1) - 1); wrqu.data.length += sizeof(associnfo_leader1) - 1; pbuf += sizeof(associnfo_leader1) - 1; - pb += assoc_req->reqIEs_size; - for (i = 0; i < assoc_resp->respIEs_size; i++) + pb += le16_to_cpu(assoc_req->req_ies_size); + for (i = 0; i < le16_to_cpu(assoc_resp->resp_ies_size); i++) pbuf += sprintf(pbuf, "%02x", *(pb + i)); - wrqu.data.length += (assoc_resp->respIEs_size) * 2; + wrqu.data.length += (le16_to_cpu(assoc_resp->resp_ies_size)) * 2; pbuf += sprintf(pbuf, ")"); wrqu.data.length += 1; @@ -994,22 +994,22 @@ void hostif_phy_information_confirm(struct ks_wlan_private *priv) { struct iw_statistics *wstats = &priv->wstats; unsigned char rssi, signal, noise; - unsigned char LinkSpeed; - unsigned int TransmittedFrameCount, ReceivedFragmentCount; - unsigned int FailedCount, FCSErrorCount; + unsigned char link_speed; + unsigned int transmitted_frame_count, received_fragment_count; + unsigned int failed_count, fcs_error_count; DPRINTK(3, "\n"); rssi = get_BYTE(priv); signal = get_BYTE(priv); noise = get_BYTE(priv); - LinkSpeed = get_BYTE(priv); - TransmittedFrameCount = get_DWORD(priv); - ReceivedFragmentCount = get_DWORD(priv); - FailedCount = get_DWORD(priv); - FCSErrorCount = get_DWORD(priv); + link_speed = get_BYTE(priv); + transmitted_frame_count = get_DWORD(priv); + received_fragment_count = get_DWORD(priv); + failed_count = get_DWORD(priv); + fcs_error_count = get_DWORD(priv); DPRINTK(4, "phyinfo confirm rssi=%d signal=%d\n", rssi, signal); - priv->current_rate = (LinkSpeed & RATE_MASK); + priv->current_rate = (link_speed & RATE_MASK); wstats->qual.qual = signal; wstats->qual.level = 256 - rssi; wstats->qual.noise = 0; /* invalid noise value */ @@ -1017,14 +1017,13 @@ void hostif_phy_information_confirm(struct ks_wlan_private *priv) DPRINTK(3, "\n rssi=%u\n" " signal=%u\n" - " LinkSpeed=%ux500Kbps\n" - " TransmittedFrameCount=%u\n" - " ReceivedFragmentCount=%u\n" - " FailedCount=%u\n" - " FCSErrorCount=%u\n", - rssi, signal, LinkSpeed, TransmittedFrameCount, - ReceivedFragmentCount, FailedCount, FCSErrorCount); - + " link_speed=%ux500Kbps\n" + " transmitted_frame_count=%u\n" + " received_fragment_count=%u\n" + " failed_count=%u\n" + " fcs_error_count=%u\n", + rssi, signal, link_speed, transmitted_frame_count, + received_fragment_count, failed_count, fcs_error_count); /* wake_up_interruptible_all(&priv->confirm_wait); */ complete(&priv->confirm_wait); } @@ -1660,13 +1659,13 @@ void hostif_phy_information_request(struct ks_wlan_private *priv) static void hostif_power_mgmt_request(struct ks_wlan_private *priv, - unsigned long mode, unsigned long wake_up, - unsigned long receiveDTIMs) + unsigned long mode, unsigned long wake_up, + unsigned long receive_dtims) { struct hostif_power_mgmt_request_t *pp; - DPRINTK(3, "mode=%lu wake_up=%lu receiveDTIMs=%lu\n", mode, wake_up, - receiveDTIMs); + DPRINTK(3, "mode=%lu wake_up=%lu receive_dtims=%lu\n", mode, wake_up, + receive_dtims); pp = hostif_generic_request(sizeof(*pp), HIF_POWER_MGMT_REQ); if (!pp) @@ -1674,7 +1673,7 @@ void hostif_power_mgmt_request(struct ks_wlan_private *priv, pp->mode = cpu_to_le32((uint32_t)mode); pp->wake_up = cpu_to_le32((uint32_t)wake_up); - pp->receiveDTIMs = cpu_to_le32((uint32_t)receiveDTIMs); + pp->receive_dtims = cpu_to_le32((uint32_t)receive_dtims); /* send to device request */ ps_confirm_wait_inc(priv); @@ -1822,7 +1821,7 @@ void hostif_receive(struct ks_wlan_private *priv, unsigned char *p, static void hostif_sme_set_wep(struct ks_wlan_private *priv, int type) { - u32 val; + __le32 val; switch (type) { case SME_WEP_INDEX_REQUEST: @@ -1871,13 +1870,13 @@ void hostif_sme_set_wep(struct ks_wlan_private *priv, int type) } struct wpa_suite_t { - unsigned short size; + __le16 size; unsigned char suite[4][CIPHER_ID_LEN]; } __packed; struct rsn_mode_t { - u32 rsn_mode; - u16 rsn_capability; + __le32 rsn_mode; + __le16 rsn_capability; } __packed; static @@ -1885,7 +1884,7 @@ void hostif_sme_set_rsn(struct ks_wlan_private *priv, int type) { struct wpa_suite_t wpa_suite; struct rsn_mode_t rsn_mode; - u32 val; + __le32 val; memset(&wpa_suite, 0, sizeof(wpa_suite)); @@ -1937,7 +1936,8 @@ void hostif_sme_set_rsn(struct ks_wlan_private *priv, int type) hostif_mib_set_request(priv, DOT11_RSN_CONFIG_UNICAST_CIPHER, sizeof(wpa_suite.size) + - CIPHER_ID_LEN * wpa_suite.size, + CIPHER_ID_LEN * + le16_to_cpu(wpa_suite.size), MIB_VALUE_TYPE_OSTRING, &wpa_suite); break; case SME_RSN_MCAST_REQUEST: @@ -2029,7 +2029,8 @@ void hostif_sme_set_rsn(struct ks_wlan_private *priv, int type) hostif_mib_set_request(priv, DOT11_RSN_CONFIG_AUTH_SUITE, sizeof(wpa_suite.size) + - KEY_MGMT_ID_LEN * wpa_suite.size, + KEY_MGMT_ID_LEN * + le16_to_cpu(wpa_suite.size), MIB_VALUE_TYPE_OSTRING, &wpa_suite); break; case SME_RSN_ENABLED_REQUEST: @@ -2166,7 +2167,7 @@ void hostif_sme_multicast_set(struct ks_wlan_private *priv) int mc_count; struct netdev_hw_addr *ha; char set_address[NIC_MAX_MCAST_LIST * ETH_ALEN]; - unsigned long filter_type; + __le32 filter_type; int i = 0; DPRINTK(3, "\n"); @@ -2218,44 +2219,44 @@ spin_unlock: static void hostif_sme_power_mgmt_set(struct ks_wlan_private *priv) { - unsigned long mode, wake_up, receiveDTIMs; + unsigned long mode, wake_up, receive_dtims; DPRINTK(3, "\n"); switch (priv->reg.power_mgmt) { case POWER_MGMT_ACTIVE: mode = POWER_ACTIVE; wake_up = 0; - receiveDTIMs = 0; + receive_dtims = 0; break; case POWER_MGMT_SAVE1: if (priv->reg.operation_mode == MODE_INFRASTRUCTURE) { mode = POWER_SAVE; wake_up = 0; - receiveDTIMs = 0; + receive_dtims = 0; } else { mode = POWER_ACTIVE; wake_up = 0; - receiveDTIMs = 0; + receive_dtims = 0; } break; case POWER_MGMT_SAVE2: if (priv->reg.operation_mode == MODE_INFRASTRUCTURE) { mode = POWER_SAVE; wake_up = 0; - receiveDTIMs = 1; + receive_dtims = 1; } else { mode = POWER_ACTIVE; wake_up = 0; - receiveDTIMs = 0; + receive_dtims = 0; } break; default: mode = POWER_ACTIVE; wake_up = 0; - receiveDTIMs = 0; + receive_dtims = 0; break; } - hostif_power_mgmt_request(priv, mode, wake_up, receiveDTIMs); + hostif_power_mgmt_request(priv, mode, wake_up, receive_dtims); } static @@ -2277,7 +2278,7 @@ void hostif_sme_sleep_set(struct ks_wlan_private *priv) static void hostif_sme_set_key(struct ks_wlan_private *priv, int type) { - u32 val; + __le32 val; switch (type) { case SME_SET_FLAG: @@ -2336,7 +2337,7 @@ static void hostif_sme_set_pmksa(struct ks_wlan_private *priv) { struct pmk_cache_t { - u16 size; + __le16 size; struct { u8 bssid[ETH_ALEN]; u8 pmkid[IW_PMKID_LEN]; @@ -2367,7 +2368,7 @@ void hostif_sme_set_pmksa(struct ks_wlan_private *priv) static void hostif_sme_execute(struct ks_wlan_private *priv, int event) { - u32 val; + __le32 val; DPRINTK(3, "event=%d\n", event); switch (event) { diff --git a/drivers/staging/ks7010/ks_hostif.h b/drivers/staging/ks7010/ks_hostif.h index d758076d419d..5bae8d468e23 100644 --- a/drivers/staging/ks7010/ks_hostif.h +++ b/drivers/staging/ks7010/ks_hostif.h @@ -62,27 +62,27 @@ */ struct hostif_hdr { - u16 size; - u16 event; + __le16 size; + __le16 event; } __packed; struct hostif_data_request_t { struct hostif_hdr header; - u16 auth_type; + __le16 auth_type; #define TYPE_DATA 0x0000 #define TYPE_AUTH 0x0001 - u16 reserved; + __le16 reserved; u8 data[0]; } __packed; struct hostif_data_indication_t { struct hostif_hdr header; - u16 auth_type; + __le16 auth_type; /* #define TYPE_DATA 0x0000 */ #define TYPE_PMK1 0x0001 #define TYPE_GMK1 0x0002 #define TYPE_GMK2 0x0003 - u16 reserved; + __le16 reserved; u8 data[0]; } __packed; @@ -143,12 +143,12 @@ struct channel_list_t { struct hostif_mib_get_request_t { struct hostif_hdr header; - u32 mib_attribute; + __le32 mib_attribute; } __packed; struct hostif_mib_value_t { - u16 size; - u16 type; + __le16 size; + __le16 type; #define MIB_VALUE_TYPE_NULL 0 #define MIB_VALUE_TYPE_INT 1 #define MIB_VALUE_TYPE_BOOL 2 @@ -159,36 +159,36 @@ struct hostif_mib_value_t { struct hostif_mib_get_confirm_t { struct hostif_hdr header; - u32 mib_status; + __le32 mib_status; #define MIB_SUCCESS 0 #define MIB_INVALID 1 #define MIB_READ_ONLY 2 #define MIB_WRITE_ONLY 3 - u32 mib_attribute; + __le32 mib_attribute; struct hostif_mib_value_t mib_value; } __packed; struct hostif_mib_set_request_t { struct hostif_hdr header; - u32 mib_attribute; + __le32 mib_attribute; struct hostif_mib_value_t mib_value; } __packed; struct hostif_mib_set_confirm_t { struct hostif_hdr header; - u32 mib_status; - u32 mib_attribute; + __le32 mib_status; + __le32 mib_attribute; } __packed; struct hostif_power_mgmt_request_t { struct hostif_hdr header; - u32 mode; + __le32 mode; #define POWER_ACTIVE 1 #define POWER_SAVE 2 - u32 wake_up; + __le32 wake_up; #define SLEEP_FALSE 0 #define SLEEP_TRUE 1 /* not used */ - u32 receiveDTIMs; + __le32 receive_dtims; #define DTIM_FALSE 0 #define DTIM_TRUE 1 } __packed; @@ -207,12 +207,12 @@ enum power_mgmt_mode_type { struct hostif_power_mgmt_confirm_t { struct hostif_hdr header; - u16 result_code; + __le16 result_code; } __packed; struct hostif_start_request_t { struct hostif_hdr header; - u16 mode; + __le16 mode; #define MODE_PSEUDO_ADHOC 0 #define MODE_INFRASTRUCTURE 1 #define MODE_AP 2 /* not used */ @@ -221,7 +221,7 @@ struct hostif_start_request_t { struct hostif_start_confirm_t { struct hostif_hdr header; - u16 result_code; + __le16 result_code; } __packed; #define SSID_MAX_SIZE 32 @@ -238,26 +238,26 @@ struct rate_set8_t { u8 rate_pad; } __packed; -struct FhParms_t { - u16 dwellTime; - u8 hopSet; - u8 hopPattern; - u8 hopIndex; +struct fh_parms_t { + __le16 dwell_time; + u8 hop_set; + u8 hop_pattern; + u8 hop_index; } __packed; -struct DsParms_t { +struct ds_parms_t { u8 channel; } __packed; -struct CfParms_t { +struct cf_parms_t { u8 count; u8 period; - u16 maxDuration; - u16 durRemaining; + __le16 max_duration; + __le16 dur_remaining; } __packed; -struct IbssParms_t { - u16 atimWindow; +struct ibss_parms_t { + __le16 atim_window; } __packed; struct rsn_t { @@ -266,7 +266,7 @@ struct rsn_t { u8 body[RSN_BODY_SIZE]; } __packed; -struct ErpParams_t { +struct erp_params_t { u8 erp_info; } __packed; @@ -282,8 +282,8 @@ struct ap_info_t { u8 sq; /* +07 */ u8 noise; /* +08 */ u8 pad0; /* +09 */ - u16 beacon_period; /* +10 */ - u16 capability; /* +12 */ + __le16 beacon_period; /* +10 */ + __le16 capability; /* +12 */ #define BSS_CAP_ESS BIT(0) #define BSS_CAP_IBSS BIT(1) #define BSS_CAP_CF_POLABLE BIT(2) @@ -298,7 +298,7 @@ struct ap_info_t { u8 ch_info; /* +15 */ #define FRAME_TYPE_BEACON 0x80 #define FRAME_TYPE_PROBE_RESP 0x50 - u16 body_size; /* +16 */ + __le16 body_size; /* +16 */ u8 body[1024]; /* +18 */ /* +1032 */ } __packed; @@ -309,14 +309,14 @@ struct link_ap_info_t { u8 sq; /* +07 */ u8 noise; /* +08 */ u8 pad0; /* +09 */ - u16 beacon_period; /* +10 */ - u16 capability; /* +12 */ + __le16 beacon_period; /* +10 */ + __le16 capability; /* +12 */ struct rate_set8_t rate_set; /* +14 */ - struct FhParms_t fh_parameter; /* +24 */ - struct DsParms_t ds_parameter; /* +29 */ - struct CfParms_t cf_parameter; /* +30 */ - struct IbssParms_t ibss_parameter; /* +36 */ - struct ErpParams_t erp_parameter; /* +38 */ + struct fh_parms_t fh_parameter; /* +24 */ + struct ds_parms_t ds_parameter; /* +29 */ + struct cf_parms_t cf_parameter; /* +30 */ + struct ibss_parms_t ibss_parameter; /* +36 */ + struct erp_params_t erp_parameter; /* +38 */ u8 pad1; /* +39 */ struct rate_set8_t ext_rate_set; /* +40 */ u8 DTIM_period; /* +50 */ @@ -332,7 +332,7 @@ struct link_ap_info_t { struct hostif_connect_indication_t { struct hostif_hdr header; - u16 connect_code; + __le16 connect_code; #define RESULT_CONNECT 0 #define RESULT_DISCONNECT 1 struct link_ap_info_t link_ap_info; @@ -344,7 +344,7 @@ struct hostif_stop_request_t { struct hostif_stop_confirm_t { struct hostif_hdr header; - u16 result_code; + __le16 result_code; } __packed; /** @@ -356,23 +356,23 @@ struct hostif_stop_confirm_t { */ struct hostif_ps_adhoc_set_request_t { struct hostif_hdr header; - u16 phy_type; + __le16 phy_type; #define D_11B_ONLY_MODE 0 #define D_11G_ONLY_MODE 1 #define D_11BG_COMPATIBLE_MODE 2 #define D_11A_ONLY_MODE 3 - u16 cts_mode; + __le16 cts_mode; #define CTS_MODE_FALSE 0 #define CTS_MODE_TRUE 1 - u16 channel; + __le16 channel; struct rate_set16_t rate_set; - u16 capability; - u16 scan_type; + __le16 capability; + __le16 scan_type; } __packed; struct hostif_ps_adhoc_set_confirm_t { struct hostif_hdr header; - u16 result_code; + __le16 result_code; } __packed; /** @@ -384,17 +384,17 @@ struct hostif_ps_adhoc_set_confirm_t { */ struct hostif_infrastructure_set_request_t { struct hostif_hdr header; - u16 phy_type; - u16 cts_mode; + __le16 phy_type; + __le16 cts_mode; struct rate_set16_t rate_set; struct ssid_t ssid; - u16 capability; - u16 beacon_lost_count; - u16 auth_type; + __le16 capability; + __le16 beacon_lost_count; + __le16 auth_type; #define AUTH_TYPE_OPEN_SYSTEM 0 #define AUTH_TYPE_SHARED_KEY 1 struct channel_list_t channel_list; - u16 scan_type; + __le16 scan_type; } __packed; /** @@ -406,23 +406,23 @@ struct hostif_infrastructure_set_request_t { */ struct hostif_infrastructure_set2_request_t { struct hostif_hdr header; - u16 phy_type; - u16 cts_mode; + __le16 phy_type; + __le16 cts_mode; struct rate_set16_t rate_set; struct ssid_t ssid; - u16 capability; - u16 beacon_lost_count; - u16 auth_type; + __le16 capability; + __le16 beacon_lost_count; + __le16 auth_type; #define AUTH_TYPE_OPEN_SYSTEM 0 #define AUTH_TYPE_SHARED_KEY 1 struct channel_list_t channel_list; - u16 scan_type; + __le16 scan_type; u8 bssid[ETH_ALEN]; } __packed; struct hostif_infrastructure_set_confirm_t { struct hostif_hdr header; - u16 result_code; + __le16 result_code; } __packed; /** @@ -434,13 +434,13 @@ struct hostif_infrastructure_set_confirm_t { */ struct hostif_adhoc_set_request_t { struct hostif_hdr header; - u16 phy_type; - u16 cts_mode; - u16 channel; + __le16 phy_type; + __le16 cts_mode; + __le16 channel; struct rate_set16_t rate_set; struct ssid_t ssid; - u16 capability; - u16 scan_type; + __le16 capability; + __le16 scan_type; } __packed; /** @@ -452,20 +452,20 @@ struct hostif_adhoc_set_request_t { */ struct hostif_adhoc_set2_request_t { struct hostif_hdr header; - u16 phy_type; - u16 cts_mode; - u16 reserved; + __le16 phy_type; + __le16 cts_mode; + __le16 reserved; struct rate_set16_t rate_set; struct ssid_t ssid; - u16 capability; - u16 scan_type; + __le16 capability; + __le16 scan_type; struct channel_list_t channel_list; u8 bssid[ETH_ALEN]; } __packed; struct hostif_adhoc_set_confirm_t { struct hostif_hdr header; - u16 result_code; + __le16 result_code; } __packed; struct last_associate_t { @@ -478,10 +478,10 @@ struct association_request_t { #define FRAME_TYPE_ASSOC_REQ 0x00 #define FRAME_TYPE_REASSOC_REQ 0x20 u8 pad; - u16 capability; - u16 listen_interval; + __le16 capability; + __le16 listen_interval; u8 ap_address[6]; - u16 reqIEs_size; + __le16 req_ies_size; } __packed; struct association_response_t { @@ -489,17 +489,17 @@ struct association_response_t { #define FRAME_TYPE_ASSOC_RESP 0x10 #define FRAME_TYPE_REASSOC_RESP 0x30 u8 pad; - u16 capability; - u16 status; - u16 association_id; - u16 respIEs_size; + __le16 capability; + __le16 status; + __le16 association_id; + __le16 resp_ies_size; } __packed; struct hostif_associate_indication_t { struct hostif_hdr header; struct association_request_t assoc_req; struct association_response_t assoc_resp; - /* followed by (reqIEs_size + respIEs_size) octets of data */ + /* followed by (req_ies_size + resp_ies_size) octets of data */ /* reqIEs data *//* respIEs data */ } __packed; @@ -509,24 +509,24 @@ struct hostif_bss_scan_request_t { #define ACTIVE_SCAN 0 #define PASSIVE_SCAN 1 u8 pad[3]; - u32 ch_time_min; - u32 ch_time_max; + __le32 ch_time_min; + __le32 ch_time_max; struct channel_list_t channel_list; struct ssid_t ssid; } __packed; struct hostif_bss_scan_confirm_t { struct hostif_hdr header; - u16 result_code; - u16 reserved; + __le16 result_code; + __le16 reserved; } __packed; struct hostif_phy_information_request_t { struct hostif_hdr header; - u16 type; + __le16 type; #define NORMAL_TYPE 0 #define TIME_TYPE 1 - u16 time; /* unit 100ms */ + __le16 time; /* unit 100ms */ } __packed; struct hostif_phy_information_confirm_t { @@ -535,10 +535,10 @@ struct hostif_phy_information_confirm_t { u8 sq; u8 noise; u8 link_speed; - u32 tx_frame; - u32 rx_frame; - u32 tx_error; - u32 rx_error; + __le32 tx_frame; + __le32 rx_frame; + __le32 tx_error; + __le32 rx_error; } __packed; enum sleep_mode_type { @@ -552,18 +552,18 @@ struct hostif_sleep_request_t { struct hostif_sleep_confirm_t { struct hostif_hdr header; - u16 result_code; + __le16 result_code; } __packed; struct hostif_mic_failure_request_t { struct hostif_hdr header; - u16 failure_count; - u16 timer; + __le16 failure_count; + __le16 timer; } __packed; struct hostif_mic_failure_confirm_t { struct hostif_hdr header; - u16 result_code; + __le16 result_code; } __packed; #define BASIC_RATE 0x80 diff --git a/drivers/staging/ks7010/ks_wlan.h b/drivers/staging/ks7010/ks_wlan.h index cd4f56ddbea8..3767079be00d 100644 --- a/drivers/staging/ks7010/ks_wlan.h +++ b/drivers/staging/ks7010/ks_wlan.h @@ -264,10 +264,10 @@ struct local_aplist_t { }; struct local_gain_t { - u8 TxMode; - u8 RxMode; - u8 TxGain; - u8 RxGain; + u8 tx_mode; + u8 rx_mode; + u8 tx_gain; + u8 rx_gain; }; struct local_eeprom_sum_t { diff --git a/drivers/staging/ks7010/ks_wlan_net.c b/drivers/staging/ks7010/ks_wlan_net.c index 5a43f193dcc8..8aa12e813bd7 100644 --- a/drivers/staging/ks7010/ks_wlan_net.c +++ b/drivers/staging/ks7010/ks_wlan_net.c @@ -2273,7 +2273,7 @@ static int ks_wlan_set_sleep_mode(struct net_device *dev, netdev_info(dev, "SET_SLEEP_MODE %d\n", priv->sleep_mode); hostif_sme_enqueue(priv, SME_SLEEP_REQUEST); } else { - netdev_err(dev, "SET_SLEEP_MODE %d errror\n", *uwrq); + netdev_err(dev, "SET_SLEEP_MODE %d error\n", *uwrq); return -EINVAL; } @@ -2378,14 +2378,14 @@ static int ks_wlan_set_tx_gain(struct net_device *dev, return -EPERM; /* for SLEEP MODE */ if (*uwrq >= 0 && *uwrq <= 0xFF) /* 0-255 */ - priv->gain.TxGain = (uint8_t)*uwrq; + priv->gain.tx_gain = (uint8_t)*uwrq; else return -EINVAL; - if (priv->gain.TxGain < 0xFF) - priv->gain.TxMode = 1; + if (priv->gain.tx_gain < 0xFF) + priv->gain.tx_mode = 1; else - priv->gain.TxMode = 0; + priv->gain.tx_mode = 0; hostif_sme_enqueue(priv, SME_SET_GAIN); return 0; @@ -2400,7 +2400,7 @@ static int ks_wlan_get_tx_gain(struct net_device *dev, if (priv->sleep_mode == SLP_SLEEP) return -EPERM; /* for SLEEP MODE */ - *uwrq = priv->gain.TxGain; + *uwrq = priv->gain.tx_gain; hostif_sme_enqueue(priv, SME_GET_GAIN); return 0; } @@ -2415,14 +2415,14 @@ static int ks_wlan_set_rx_gain(struct net_device *dev, return -EPERM; /* for SLEEP MODE */ if (*uwrq >= 0 && *uwrq <= 0xFF) /* 0-255 */ - priv->gain.RxGain = (uint8_t)*uwrq; + priv->gain.rx_gain = (uint8_t)*uwrq; else return -EINVAL; - if (priv->gain.RxGain < 0xFF) - priv->gain.RxMode = 1; + if (priv->gain.rx_gain < 0xFF) + priv->gain.rx_mode = 1; else - priv->gain.RxMode = 0; + priv->gain.rx_mode = 0; hostif_sme_enqueue(priv, SME_SET_GAIN); return 0; @@ -2437,7 +2437,7 @@ static int ks_wlan_get_rx_gain(struct net_device *dev, if (priv->sleep_mode == SLP_SLEEP) return -EPERM; /* for SLEEP MODE */ - *uwrq = priv->gain.RxGain; + *uwrq = priv->gain.rx_gain; hostif_sme_enqueue(priv, SME_GET_GAIN); return 0; } diff --git a/drivers/staging/lustre/lnet/klnds/o2iblnd/o2iblnd.c b/drivers/staging/lustre/lnet/klnds/o2iblnd/o2iblnd.c index 79321e4aaf30..0520f02f670d 100644 --- a/drivers/staging/lustre/lnet/klnds/o2iblnd/o2iblnd.c +++ b/drivers/staging/lustre/lnet/klnds/o2iblnd/o2iblnd.c @@ -2306,7 +2306,7 @@ static int kiblnd_dev_need_failover(struct kib_dev *dev) memset(&srcaddr, 0, sizeof(srcaddr)); srcaddr.sin_family = AF_INET; - srcaddr.sin_addr.s_addr = (__force u32)htonl(dev->ibd_ifip); + srcaddr.sin_addr.s_addr = htonl(dev->ibd_ifip); memset(&dstaddr, 0, sizeof(dstaddr)); dstaddr.sin_family = AF_INET; @@ -2378,7 +2378,7 @@ int kiblnd_dev_failover(struct kib_dev *dev) memset(&addr, 0, sizeof(addr)); addr.sin_family = AF_INET; - addr.sin_addr.s_addr = (__force u32)htonl(dev->ibd_ifip); + addr.sin_addr.s_addr = htonl(dev->ibd_ifip); addr.sin_port = htons(*kiblnd_tunables.kib_service); /* Bind to failover device or port */ diff --git a/drivers/staging/lustre/lnet/libcfs/linux/linux-tracefile.c b/drivers/staging/lustre/lnet/libcfs/linux/linux-tracefile.c index 75eb84e7f0f8..a5a94788f11f 100644 --- a/drivers/staging/lustre/lnet/libcfs/linux/linux-tracefile.c +++ b/drivers/staging/lustre/lnet/libcfs/linux/linux-tracefile.c @@ -57,8 +57,9 @@ int cfs_tracefile_init_arch(void) memset(cfs_trace_data, 0, sizeof(cfs_trace_data)); for (i = 0; i < CFS_TCD_TYPE_MAX; i++) { cfs_trace_data[i] = - kmalloc(sizeof(union cfs_trace_data_union) * - num_possible_cpus(), GFP_KERNEL); + kmalloc_array(num_possible_cpus(), + sizeof(union cfs_trace_data_union), + GFP_KERNEL); if (!cfs_trace_data[i]) goto out; } diff --git a/drivers/staging/lustre/lnet/libcfs/tracefile.c b/drivers/staging/lustre/lnet/libcfs/tracefile.c index 27082d2f7938..d1aa79bb2017 100644 --- a/drivers/staging/lustre/lnet/libcfs/tracefile.c +++ b/drivers/staging/lustre/lnet/libcfs/tracefile.c @@ -191,10 +191,9 @@ cfs_trace_get_tage_try(struct cfs_trace_cpu_data *tcd, unsigned long len) } else { tage = cfs_tage_alloc(GFP_ATOMIC); if (unlikely(!tage)) { - if ((!memory_pressure_get() || - in_interrupt()) && printk_ratelimit()) - pr_warn("cannot allocate a tage (%ld)\n", - tcd->tcd_cur_pages); + if (!memory_pressure_get() || in_interrupt()) + pr_warn_ratelimited("cannot allocate a tage (%ld)\n", + tcd->tcd_cur_pages); return NULL; } } @@ -229,9 +228,8 @@ static void cfs_tcd_shrink(struct cfs_trace_cpu_data *tcd) * from here: this will lead to infinite recursion. */ - if (printk_ratelimit()) - pr_warn("debug daemon buffer overflowed; discarding 10%% of pages (%d of %ld)\n", - pgcount + 1, tcd->tcd_cur_pages); + pr_warn_ratelimited("debug daemon buffer overflowed; discarding 10%% of pages (%d of %ld)\n", + pgcount + 1, tcd->tcd_cur_pages); INIT_LIST_HEAD(&pc.pc_pages); diff --git a/drivers/staging/lustre/lnet/lnet/lib-move.c b/drivers/staging/lustre/lnet/lnet/lib-move.c index a99c5c0aa672..20ebe247071f 100644 --- a/drivers/staging/lustre/lnet/lnet/lib-move.c +++ b/drivers/staging/lustre/lnet/lnet/lib-move.c @@ -1274,9 +1274,9 @@ lnet_parse_put(struct lnet_ni *ni, struct lnet_msg *msg) int rc; /* Convert put fields to host byte order */ - hdr->msg.put.match_bits = le64_to_cpu(hdr->msg.put.match_bits); - hdr->msg.put.ptl_index = le32_to_cpu(hdr->msg.put.ptl_index); - hdr->msg.put.offset = le32_to_cpu(hdr->msg.put.offset); + le64_to_cpus(&hdr->msg.put.match_bits); + le32_to_cpus(&hdr->msg.put.ptl_index); + le32_to_cpus(&hdr->msg.put.offset); info.mi_id.nid = hdr->src_nid; info.mi_id.pid = hdr->src_pid; @@ -1332,10 +1332,10 @@ lnet_parse_get(struct lnet_ni *ni, struct lnet_msg *msg, int rdma_get) int rc; /* Convert get fields to host byte order */ - hdr->msg.get.match_bits = le64_to_cpu(hdr->msg.get.match_bits); - hdr->msg.get.ptl_index = le32_to_cpu(hdr->msg.get.ptl_index); - hdr->msg.get.sink_length = le32_to_cpu(hdr->msg.get.sink_length); - hdr->msg.get.src_offset = le32_to_cpu(hdr->msg.get.src_offset); + le64_to_cpus(&hdr->msg.get.match_bits); + le32_to_cpus(&hdr->msg.get.ptl_index); + le32_to_cpus(&hdr->msg.get.sink_length); + le32_to_cpus(&hdr->msg.get.src_offset); info.mi_id.nid = hdr->src_nid; info.mi_id.pid = hdr->src_pid; @@ -1464,8 +1464,8 @@ lnet_parse_ack(struct lnet_ni *ni, struct lnet_msg *msg) src.pid = hdr->src_pid; /* Convert ack fields to host byte order */ - hdr->msg.ack.match_bits = le64_to_cpu(hdr->msg.ack.match_bits); - hdr->msg.ack.mlength = le32_to_cpu(hdr->msg.ack.mlength); + le64_to_cpus(&hdr->msg.ack.match_bits); + le32_to_cpus(&hdr->msg.ack.mlength); cpt = lnet_cpt_of_cookie(hdr->msg.ack.dst_wmd.wh_object_cookie); lnet_res_lock(cpt); @@ -1798,7 +1798,7 @@ lnet_parse(struct lnet_ni *ni, struct lnet_hdr *hdr, lnet_nid_t from_nid, /* convert common msg->hdr fields to host byteorder */ msg->msg_hdr.type = type; msg->msg_hdr.src_nid = src_nid; - msg->msg_hdr.src_pid = le32_to_cpu(msg->msg_hdr.src_pid); + le32_to_cpus(&msg->msg_hdr.src_pid); msg->msg_hdr.dest_nid = dest_nid; msg->msg_hdr.dest_pid = dest_pid; msg->msg_hdr.payload_length = payload_length; diff --git a/drivers/staging/lustre/lnet/lnet/lib-socket.c b/drivers/staging/lustre/lnet/lnet/lib-socket.c index f075706bba6d..800f4f6c6593 100644 --- a/drivers/staging/lustre/lnet/lnet/lib-socket.c +++ b/drivers/staging/lustre/lnet/lnet/lib-socket.c @@ -89,7 +89,7 @@ lnet_ipif_query(char *name, int *up, __u32 *ip, __u32 *mask) struct ifreq ifr; int nob; int rc; - __u32 val; + __be32 val; nob = strnlen(name, IFNAMSIZ); if (nob == IFNAMSIZ) { diff --git a/drivers/staging/lustre/lustre/fid/fid_request.c b/drivers/staging/lustre/lustre/fid/fid_request.c index bf31bc200d27..19895faf7626 100644 --- a/drivers/staging/lustre/lustre/fid/fid_request.c +++ b/drivers/staging/lustre/lustre/fid/fid_request.c @@ -259,7 +259,7 @@ int seq_client_alloc_fid(const struct lu_env *env, return rc; } - CDEBUG(D_INFO, "%s: Switch to sequence [0x%16.16Lx]\n", + CDEBUG(D_INFO, "%s: Switch to sequence [0x%16.16llx]\n", seq->lcs_name, seqnr); seq->lcs_fid.f_oid = LUSTRE_FID_INIT_OID; @@ -279,7 +279,7 @@ int seq_client_alloc_fid(const struct lu_env *env, *fid = seq->lcs_fid; mutex_unlock(&seq->lcs_mutex); - CDEBUG(D_INFO, "%s: Allocated FID "DFID"\n", seq->lcs_name, PFID(fid)); + CDEBUG(D_INFO, "%s: Allocated FID " DFID "\n", seq->lcs_name, PFID(fid)); return rc; } EXPORT_SYMBOL(seq_client_alloc_fid); diff --git a/drivers/staging/lustre/lustre/fld/fld_cache.c b/drivers/staging/lustre/lustre/fld/fld_cache.c index 11f697496180..b852fed0b10f 100644 --- a/drivers/staging/lustre/lustre/fld/fld_cache.c +++ b/drivers/staging/lustre/lustre/fld/fld_cache.c @@ -151,7 +151,7 @@ restart_fixup: continue; LASSERTF(c_range->lsr_start <= n_range->lsr_start, - "cur lsr_start "DRANGE" next lsr_start "DRANGE"\n", + "cur lsr_start " DRANGE " next lsr_start " DRANGE "\n", PRANGE(c_range), PRANGE(n_range)); /* check merge possibility with next range */ @@ -349,7 +349,7 @@ static void fld_cache_overlap_handle(struct fld_cache *cache, f_curr->fce_range.lsr_end = new_start; fld_cache_entry_add(cache, f_new, &f_curr->fce_list); } else - CERROR("NEW range ="DRANGE" curr = "DRANGE"\n", + CERROR("NEW range =" DRANGE " curr = " DRANGE "\n", PRANGE(range), PRANGE(&f_curr->fce_range)); } @@ -415,7 +415,7 @@ static int fld_cache_insert_nolock(struct fld_cache *cache, if (!prev) prev = head; - CDEBUG(D_INFO, "insert range "DRANGE"\n", PRANGE(&f_new->fce_range)); + CDEBUG(D_INFO, "insert range " DRANGE "\n", PRANGE(&f_new->fce_range)); /* Add new entry to cache and lru list. */ fld_cache_entry_add(cache, f_new, prev); out: diff --git a/drivers/staging/lustre/lustre/fld/lproc_fld.c b/drivers/staging/lustre/lustre/fld/lproc_fld.c index 61ac420798af..b83d7ebb2d18 100644 --- a/drivers/staging/lustre/lustre/fld/lproc_fld.c +++ b/drivers/staging/lustre/lustre/fld/lproc_fld.c @@ -136,7 +136,7 @@ fld_debugfs_cache_flush_release(struct inode *inode, struct file *file) return 0; } -static struct file_operations fld_debugfs_cache_flush_fops = { +static const struct file_operations fld_debugfs_cache_flush_fops = { .owner = THIS_MODULE, .open = simple_open, .write = fld_debugfs_cache_flush_write, diff --git a/drivers/staging/lustre/lustre/include/cl_object.h b/drivers/staging/lustre/lustre/include/cl_object.h index 2bc3ee51b069..90a0c501e1ea 100644 --- a/drivers/staging/lustre/lustre/include/cl_object.h +++ b/drivers/staging/lustre/lustre/include/cl_object.h @@ -1287,7 +1287,7 @@ do { \ * @{ */ struct cl_page_list { - unsigned pl_nr; + unsigned int pl_nr; struct list_head pl_pages; struct task_struct *pl_owner; }; @@ -1842,7 +1842,7 @@ struct cl_io { /** * Number of pages owned by this IO. For invariant checking. */ - unsigned ci_owned_nr; + unsigned int ci_owned_nr; }; /** @} cl_io */ diff --git a/drivers/staging/lustre/lustre/include/lprocfs_status.h b/drivers/staging/lustre/lustre/include/lprocfs_status.h index 242abb881766..915283c04094 100644 --- a/drivers/staging/lustre/lustre/include/lprocfs_status.h +++ b/drivers/staging/lustre/lustre/include/lprocfs_status.h @@ -49,7 +49,7 @@ struct lprocfs_vars { const char *name; - struct file_operations *fops; + const struct file_operations *fops; void *data; /** * sysfs file mode. @@ -449,7 +449,7 @@ int lprocfs_exp_cleanup(struct obd_export *exp); struct dentry *ldebugfs_add_simple(struct dentry *root, char *name, void *data, - struct file_operations *fops); + const struct file_operations *fops); int ldebugfs_register_stats(struct dentry *parent, const char *name, @@ -523,8 +523,8 @@ unsigned long lprocfs_oh_sum(struct obd_histogram *oh); void lprocfs_stats_collect(struct lprocfs_stats *stats, int idx, struct lprocfs_counter *cnt); -int lprocfs_single_release(struct inode *, struct file *); -int lprocfs_seq_release(struct inode *, struct file *); +int lprocfs_single_release(struct inode *inode, struct file *file); +int lprocfs_seq_release(struct inode *inode, struct file *file); /* write the name##_seq_show function, call LPROC_SEQ_FOPS_RO for read-only * proc entries; otherwise, you will define name##_seq_write function also for @@ -536,7 +536,7 @@ static int name##_single_open(struct inode *inode, struct file *file) \ { \ return single_open(file, name##_seq_show, inode->i_private); \ } \ -static struct file_operations name##_fops = { \ +static const struct file_operations name##_fops = { \ .owner = THIS_MODULE, \ .open = name##_single_open, \ .read = seq_read, \ @@ -581,7 +581,7 @@ static struct file_operations name##_fops = { \ { \ return single_open(file, NULL, inode->i_private); \ } \ - static struct file_operations name##_##type##_fops = { \ + static const struct file_operations name##_##type##_fops = { \ .open = name##_##type##_open, \ .write = name##_##type##_write, \ .release = lprocfs_single_release, \ diff --git a/drivers/staging/lustre/lustre/include/lu_object.h b/drivers/staging/lustre/lustre/include/lu_object.h index 73ecc232967b..2e70602dc2e2 100644 --- a/drivers/staging/lustre/lustre/include/lu_object.h +++ b/drivers/staging/lustre/lustre/include/lu_object.h @@ -968,11 +968,11 @@ struct lu_context { * Version counter used to skip calls to lu_context_refill() when no * keys were registered. */ - unsigned lc_version; + unsigned int lc_version; /** * Debugging cookie. */ - unsigned lc_cookie; + unsigned int lc_cookie; }; /** diff --git a/drivers/staging/lustre/lustre/include/lustre/lustre_idl.h b/drivers/staging/lustre/lustre/include/lustre/lustre_idl.h index df48b8d6fe52..77995fa47691 100644 --- a/drivers/staging/lustre/lustre/include/lustre/lustre_idl.h +++ b/drivers/staging/lustre/lustre/include/lustre/lustre_idl.h @@ -546,7 +546,7 @@ static inline void ostid_set_id(struct ost_id *oi, __u64 oid) static inline int fid_set_id(struct lu_fid *fid, __u64 oid) { if (unlikely(fid_seq_is_igif(fid->f_seq))) { - CERROR("bad IGIF, "DFID"\n", PFID(fid)); + CERROR("bad IGIF, " DFID "\n", PFID(fid)); return -EBADF; } @@ -585,7 +585,7 @@ static inline int ostid_to_fid(struct lu_fid *fid, struct ost_id *ostid, __u64 seq = ostid_seq(ostid); if (ost_idx > 0xffff) { - CERROR("bad ost_idx, "DOSTID" ost_idx:%u\n", POSTID(ostid), + CERROR("bad ost_idx, " DOSTID " ost_idx:%u\n", POSTID(ostid), ost_idx); return -EBADF; } @@ -630,7 +630,7 @@ static inline int ostid_to_fid(struct lu_fid *fid, struct ost_id *ostid, static inline int fid_to_ostid(const struct lu_fid *fid, struct ost_id *ostid) { if (unlikely(fid_seq_is_igif(fid->f_seq))) { - CERROR("bad IGIF, "DFID"\n", PFID(fid)); + CERROR("bad IGIF, " DFID "\n", PFID(fid)); return -EBADF; } diff --git a/drivers/staging/lustre/lustre/include/lustre/lustre_user.h b/drivers/staging/lustre/lustre/include/lustre/lustre_user.h index 7d8628ce0d3b..edff8dc34430 100644 --- a/drivers/staging/lustre/lustre/include/lustre/lustre_user.h +++ b/drivers/staging/lustre/lustre/include/lustre/lustre_user.h @@ -532,7 +532,7 @@ static inline void obd_uuid2fsname(char *buf, char *uuid, int buflen) #define FID_NOBRACE_LEN 40 #define FID_LEN (FID_NOBRACE_LEN + 2) #define DFID_NOBRACE "%#llx:0x%x:0x%x" -#define DFID "["DFID_NOBRACE"]" +#define DFID "[" DFID_NOBRACE "]" #define PFID(fid) (unsigned long long)(fid)->f_seq, (fid)->f_oid, (fid)->f_ver /* scanf input parse format for fids in DFID_NOBRACE format diff --git a/drivers/staging/lustre/lustre/include/lustre_fid.h b/drivers/staging/lustre/lustre/include/lustre_fid.h index b5a1aadbcb93..6dc24a76ddb6 100644 --- a/drivers/staging/lustre/lustre/include/lustre_fid.h +++ b/drivers/staging/lustre/lustre/include/lustre_fid.h @@ -606,7 +606,7 @@ static inline __u32 fid_flatten32(const struct lu_fid *fid) static inline int lu_fid_diff(const struct lu_fid *fid1, const struct lu_fid *fid2) { - LASSERTF(fid_seq(fid1) == fid_seq(fid2), "fid1:"DFID", fid2:"DFID"\n", + LASSERTF(fid_seq(fid1) == fid_seq(fid2), "fid1:" DFID ", fid2:" DFID "\n", PFID(fid1), PFID(fid2)); if (fid_is_idif(fid1) && fid_is_idif(fid2)) diff --git a/drivers/staging/lustre/lustre/ldlm/ldlm_internal.h b/drivers/staging/lustre/lustre/ldlm/ldlm_internal.h index 5d24b4825796..ec3b23cd09ec 100644 --- a/drivers/staging/lustre/lustre/ldlm/ldlm_internal.h +++ b/drivers/staging/lustre/lustre/ldlm/ldlm_internal.h @@ -79,11 +79,11 @@ static inline int ldlm_ns_empty(struct ldlm_namespace *ns) return atomic_read(&ns->ns_bref) == 0; } -void ldlm_namespace_move_to_active_locked(struct ldlm_namespace *, - enum ldlm_side); -void ldlm_namespace_move_to_inactive_locked(struct ldlm_namespace *, - enum ldlm_side); -struct ldlm_namespace *ldlm_namespace_first_locked(enum ldlm_side); +void ldlm_namespace_move_to_active_locked(struct ldlm_namespace *ns, + enum ldlm_side client); +void ldlm_namespace_move_to_inactive_locked(struct ldlm_namespace *ns, + enum ldlm_side client); +struct ldlm_namespace *ldlm_namespace_first_locked(enum ldlm_side client); /* ldlm_request.c */ /* Cancel lru flag, it indicates we cancel aged locks. */ @@ -130,16 +130,19 @@ void ldlm_grant_lock(struct ldlm_lock *lock, struct list_head *work_list); int ldlm_fill_lvb(struct ldlm_lock *lock, struct req_capsule *pill, enum req_location loc, void *data, int size); struct ldlm_lock * -ldlm_lock_create(struct ldlm_namespace *ns, const struct ldlm_res_id *, +ldlm_lock_create(struct ldlm_namespace *ns, const struct ldlm_res_id *id, enum ldlm_type type, enum ldlm_mode mode, const struct ldlm_callback_suite *cbs, void *data, __u32 lvb_len, enum lvb_type lvb_type); -enum ldlm_error ldlm_lock_enqueue(struct ldlm_namespace *, struct ldlm_lock **, - void *cookie, __u64 *flags); -void ldlm_lock_addref_internal(struct ldlm_lock *, enum ldlm_mode mode); -void ldlm_lock_addref_internal_nolock(struct ldlm_lock *, enum ldlm_mode mode); -void ldlm_lock_decref_internal(struct ldlm_lock *, enum ldlm_mode mode); -void ldlm_lock_decref_internal_nolock(struct ldlm_lock *, enum ldlm_mode mode); +enum ldlm_error ldlm_lock_enqueue(struct ldlm_namespace *ns, + struct ldlm_lock **lock, void *cookie, + __u64 *flags); +void ldlm_lock_addref_internal(struct ldlm_lock *lock, enum ldlm_mode mode); +void ldlm_lock_addref_internal_nolock(struct ldlm_lock *lock, + enum ldlm_mode mode); +void ldlm_lock_decref_internal(struct ldlm_lock *lock, enum ldlm_mode mode); +void ldlm_lock_decref_internal_nolock(struct ldlm_lock *lock, + enum ldlm_mode mode); int ldlm_run_ast_work(struct ldlm_namespace *ns, struct list_head *rpc_list, enum ldlm_desc_ast_t ast_type); int ldlm_lock_remove_from_lru_check(struct ldlm_lock *lock, time_t last_use); diff --git a/drivers/staging/lustre/lustre/ldlm/ldlm_lib.c b/drivers/staging/lustre/lustre/ldlm/ldlm_lib.c index 3663c5cdb051..4dc7baee1f28 100644 --- a/drivers/staging/lustre/lustre/ldlm/ldlm_lib.c +++ b/drivers/staging/lustre/lustre/ldlm/ldlm_lib.c @@ -363,17 +363,16 @@ int client_obd_setup(struct obd_device *obddev, struct lustre_cfg *lcfg) */ cli->cl_chunkbits = PAGE_SHIFT; - if (!strcmp(name, LUSTRE_MDC_NAME)) { + if (!strcmp(name, LUSTRE_MDC_NAME)) cli->cl_max_rpcs_in_flight = OBD_MAX_RIF_DEFAULT; - } else if (totalram_pages >> (20 - PAGE_SHIFT) <= 128 /* MB */) { + else if (totalram_pages >> (20 - PAGE_SHIFT) <= 128 /* MB */) cli->cl_max_rpcs_in_flight = 2; - } else if (totalram_pages >> (20 - PAGE_SHIFT) <= 256 /* MB */) { + else if (totalram_pages >> (20 - PAGE_SHIFT) <= 256 /* MB */) cli->cl_max_rpcs_in_flight = 3; - } else if (totalram_pages >> (20 - PAGE_SHIFT) <= 512 /* MB */) { + else if (totalram_pages >> (20 - PAGE_SHIFT) <= 512 /* MB */) cli->cl_max_rpcs_in_flight = 4; - } else { + else cli->cl_max_rpcs_in_flight = OBD_MAX_RIF_DEFAULT; - } spin_lock_init(&cli->cl_mod_rpcs_lock); spin_lock_init(&cli->cl_mod_rpcs_hist.oh_lock); diff --git a/drivers/staging/lustre/lustre/ldlm/ldlm_request.c b/drivers/staging/lustre/lustre/ldlm/ldlm_request.c index 84eeaa552113..4028e11249a2 100644 --- a/drivers/staging/lustre/lustre/ldlm/ldlm_request.c +++ b/drivers/staging/lustre/lustre/ldlm/ldlm_request.c @@ -445,8 +445,8 @@ int ldlm_cli_enqueue_fini(struct obd_export *exp, struct ptlrpc_request *req, if (!ldlm_res_eq(&reply->lock_desc.l_resource.lr_name, &lock->l_resource->lr_name)) { - CDEBUG(D_INFO, "remote intent success, locking "DLDLMRES - " instead of "DLDLMRES"\n", + CDEBUG(D_INFO, "remote intent success, locking " DLDLMRES + " instead of " DLDLMRES "\n", PLDLMRES(&reply->lock_desc.l_resource), PLDLMRES(lock->l_resource)); @@ -1677,7 +1677,7 @@ int ldlm_cli_cancel_unused_resource(struct ldlm_namespace *ns, 0, flags | LCF_BL_AST, opaque); rc = ldlm_cli_cancel_list(&cancels, count, NULL, flags); if (rc != ELDLM_OK) - CERROR("canceling unused lock "DLDLMRES": rc = %d\n", + CERROR("canceling unused lock " DLDLMRES ": rc = %d\n", PLDLMRES(res), rc); LDLM_RESOURCE_DELREF(res); diff --git a/drivers/staging/lustre/lustre/ldlm/ldlm_resource.c b/drivers/staging/lustre/lustre/ldlm/ldlm_resource.c index 633f65b078eb..c9ef247d9be4 100644 --- a/drivers/staging/lustre/lustre/ldlm/ldlm_resource.c +++ b/drivers/staging/lustre/lustre/ldlm/ldlm_resource.c @@ -78,7 +78,25 @@ lprocfs_wr_dump_ns(struct file *file, const char __user *buffer, LPROC_SEQ_FOPS_WR_ONLY(ldlm, dump_ns); -LPROC_SEQ_FOPS_RW_TYPE(ldlm_rw, uint); +static int ldlm_rw_uint_seq_show(struct seq_file *m, void *v) +{ + seq_printf(m, "%u\n", *(unsigned int *)m->private); + return 0; +} + +static ssize_t +ldlm_rw_uint_seq_write(struct file *file, const char __user *buffer, + size_t count, loff_t *off) +{ + struct seq_file *seq = file->private_data; + + if (count == 0) + return 0; + return kstrtouint_from_user(buffer, count, 0, + (unsigned int *)seq->private); +} + +LPROC_SEQ_FOPS(ldlm_rw_uint); static struct lprocfs_vars ldlm_debugfs_list[] = { { "dump_namespaces", &ldlm_dump_ns_fops, NULL, 0222 }, @@ -831,7 +849,7 @@ static int ldlm_resource_complain(struct cfs_hash *hs, struct cfs_hash_bd *bd, struct ldlm_resource *res = cfs_hash_object(hs, hnode); lock_res(res); - CERROR("%s: namespace resource "DLDLMRES + CERROR("%s: namespace resource " DLDLMRES " (%p) refcount nonzero (%d) after lock cleanup; forcing cleanup.\n", ldlm_ns_name(ldlm_res_to_ns(res)), PLDLMRES(res), res, atomic_read(&res->lr_refcount) - 1); @@ -1373,7 +1391,7 @@ void ldlm_resource_dump(int level, struct ldlm_resource *res) if (!((libcfs_debug | D_ERROR) & level)) return; - CDEBUG(level, "--- Resource: "DLDLMRES" (%p) refcount = %d\n", + CDEBUG(level, "--- Resource: " DLDLMRES " (%p) refcount = %d\n", PLDLMRES(res), res, atomic_read(&res->lr_refcount)); if (!list_empty(&res->lr_granted)) { diff --git a/drivers/staging/lustre/lustre/llite/dcache.c b/drivers/staging/lustre/lustre/llite/dcache.c index 38f84662cf02..d20425fb8cbe 100644 --- a/drivers/staging/lustre/lustre/llite/dcache.c +++ b/drivers/staging/lustre/lustre/llite/dcache.c @@ -180,7 +180,7 @@ void ll_invalidate_aliases(struct inode *inode) { struct dentry *dentry; - CDEBUG(D_INODE, "marking dentries for ino "DFID"(%p) invalid\n", + CDEBUG(D_INODE, "marking dentries for ino " DFID "(%p) invalid\n", PFID(ll_inode2fid(inode)), inode); spin_lock(&inode->i_lock); @@ -216,7 +216,7 @@ void ll_lookup_finish_locks(struct lookup_intent *it, struct inode *inode) if (it->it_lock_mode && inode) { struct ll_sb_info *sbi = ll_i2sbi(inode); - CDEBUG(D_DLMTRACE, "setting l_data to inode "DFID"(%p)\n", + CDEBUG(D_DLMTRACE, "setting l_data to inode " DFID "(%p)\n", PFID(ll_inode2fid(inode)), inode); ll_set_lock_data(sbi->ll_md_exp, inode, it, NULL); } diff --git a/drivers/staging/lustre/lustre/llite/dir.c b/drivers/staging/lustre/lustre/llite/dir.c index 13b35922a4ca..03a72c07f57c 100644 --- a/drivers/staging/lustre/lustre/llite/dir.c +++ b/drivers/staging/lustre/lustre/llite/dir.c @@ -303,7 +303,7 @@ static int ll_readdir(struct file *filp, struct dir_context *ctx) struct md_op_data *op_data; int rc; - CDEBUG(D_VFSTRACE, "VFS Op:inode="DFID"(%p) pos/size %lu/%llu 32bit_api %d\n", + CDEBUG(D_VFSTRACE, "VFS Op:inode=" DFID "(%p) pos/size %lu/%llu 32bit_api %d\n", PFID(ll_inode2fid(inode)), inode, (unsigned long)pos, i_size_read(inode), api32); @@ -419,7 +419,7 @@ static int ll_dir_setdirstripe(struct inode *parent, struct lmv_user_md *lump, if (unlikely(lump->lum_magic != LMV_USER_MAGIC)) return -EINVAL; - CDEBUG(D_VFSTRACE, "VFS Op:inode="DFID"(%p) name %s stripe_offset %d, stripe_count: %u\n", + CDEBUG(D_VFSTRACE, "VFS Op:inode=" DFID "(%p) name %s stripe_offset %d, stripe_count: %u\n", PFID(ll_inode2fid(parent)), parent, dirname, (int)lump->lum_stripe_offset, lump->lum_stripe_count); @@ -606,7 +606,7 @@ int ll_dir_getstripe(struct inode *inode, void **plmm, int *plmm_size, rc = md_getattr(sbi->ll_md_exp, op_data, &req); ll_finish_md_op_data(op_data); if (rc < 0) { - CDEBUG(D_INFO, "md_getattr failed on inode "DFID": rc %d\n", + CDEBUG(D_INFO, "md_getattr failed on inode " DFID ": rc %d\n", PFID(ll_inode2fid(inode)), rc); goto out; } @@ -733,7 +733,7 @@ static int ll_ioc_copy_start(struct super_block *sb, struct hsm_copy *copy) iput(inode); if (rc != 0) { CDEBUG(D_HSM, "Could not read file data version of " - DFID" (rc = %d). Archive request (%#llx) could not be done.\n", + DFID " (rc = %d). Archive request (%#llx) could not be done.\n", PFID(©->hc_hai.hai_fid), rc, copy->hc_hai.hai_cookie); hpk.hpk_flags |= HP_FLAG_RETRY; @@ -833,7 +833,7 @@ static int ll_ioc_copy_end(struct super_block *sb, struct hsm_copy *copy) if ((copy->hc_hai.hai_action == HSMA_ARCHIVE) && (copy->hc_data_version != data_version)) { CDEBUG(D_HSM, "File data version mismatched. File content was changed during archiving. " - DFID", start:%#llx current:%#llx\n", + DFID ", start:%#llx current:%#llx\n", PFID(©->hc_hai.hai_fid), copy->hc_data_version, data_version); /* File was changed, send error to cdt. Do not ask for @@ -1037,7 +1037,7 @@ static long ll_dir_ioctl(struct file *file, unsigned int cmd, unsigned long arg) struct obd_ioctl_data *data; int rc = 0; - CDEBUG(D_VFSTRACE, "VFS Op:inode="DFID"(%p), cmd=%#x\n", + CDEBUG(D_VFSTRACE, "VFS Op:inode=" DFID "(%p), cmd=%#x\n", PFID(ll_inode2fid(inode)), inode, cmd); /* asm-ppc{,64} declares TCGETS, et. al. as type 't' not 'T' */ @@ -1141,7 +1141,7 @@ out_free: } #if OBD_OCD_VERSION(2, 9, 50, 0) > LUSTRE_VERSION_CODE - mode = data->ioc_type != 0 ? data->ioc_type : S_IRWXUGO; + mode = data->ioc_type != 0 ? data->ioc_type : 0777; #else mode = data->ioc_type; #endif diff --git a/drivers/staging/lustre/lustre/llite/file.c b/drivers/staging/lustre/lustre/llite/file.c index 67c4b9cc6e75..ab1c85c1ed38 100644 --- a/drivers/staging/lustre/lustre/llite/file.c +++ b/drivers/staging/lustre/lustre/llite/file.c @@ -316,7 +316,7 @@ int ll_file_release(struct inode *inode, struct file *file) struct ll_inode_info *lli = ll_i2info(inode); int rc; - CDEBUG(D_VFSTRACE, "VFS Op:inode="DFID"(%p)\n", + CDEBUG(D_VFSTRACE, "VFS Op:inode=" DFID "(%p)\n", PFID(ll_inode2fid(inode)), inode); if (!is_root_inode(inode)) @@ -494,7 +494,7 @@ int ll_file_open(struct inode *inode, struct file *file) struct ll_file_data *fd; int rc = 0; - CDEBUG(D_VFSTRACE, "VFS Op:inode="DFID"(%p), flags %o\n", + CDEBUG(D_VFSTRACE, "VFS Op:inode=" DFID "(%p), flags %o\n", PFID(ll_inode2fid(inode)), inode, file->f_flags); it = file->private_data; /* XXX: compat macro */ @@ -834,7 +834,7 @@ out_close: } rc2 = ll_close_inode_openhandle(inode, och, 0, NULL); if (rc2 < 0) - CERROR("%s: error closing file "DFID": %d\n", + CERROR("%s: error closing file " DFID ": %d\n", ll_get_fsname(inode->i_sb, NULL, 0), PFID(&ll_i2info(inode)->lli_fid), rc2); och = NULL; /* och has been freed in ll_close_inode_openhandle() */ @@ -1665,7 +1665,7 @@ int ll_hsm_release(struct inode *inode) int rc; u16 refcheck; - CDEBUG(D_INODE, "%s: Releasing file "DFID".\n", + CDEBUG(D_INODE, "%s: Releasing file " DFID ".\n", ll_get_fsname(inode->i_sb, NULL, 0), PFID(&ll_i2info(inode)->lli_fid)); @@ -1928,7 +1928,7 @@ ll_file_ioctl(struct file *file, unsigned int cmd, unsigned long arg) struct ll_file_data *fd = LUSTRE_FPRIVATE(file); int flags, rc; - CDEBUG(D_VFSTRACE, "VFS Op:inode="DFID"(%p),cmd=%x\n", + CDEBUG(D_VFSTRACE, "VFS Op:inode=" DFID "(%p),cmd=%x\n", PFID(ll_inode2fid(inode)), inode, cmd); ll_stats_ops_tally(ll_i2sbi(inode), LPROC_LL_IOCTL, 1); @@ -2263,7 +2263,7 @@ static loff_t ll_file_seek(struct file *file, loff_t offset, int origin) retval = offset + ((origin == SEEK_END) ? i_size_read(inode) : (origin == SEEK_CUR) ? file->f_pos : 0); - CDEBUG(D_VFSTRACE, "VFS Op:inode="DFID"(%p), to=%llu=%#llx(%d)\n", + CDEBUG(D_VFSTRACE, "VFS Op:inode=" DFID "(%p), to=%llu=%#llx(%d)\n", PFID(ll_inode2fid(inode)), inode, retval, retval, origin); ll_stats_ops_tally(ll_i2sbi(inode), LPROC_LL_LLSEEK, 1); @@ -2360,7 +2360,7 @@ int ll_fsync(struct file *file, loff_t start, loff_t end, int datasync) struct ptlrpc_request *req; int rc, err; - CDEBUG(D_VFSTRACE, "VFS Op:inode="DFID"(%p)\n", + CDEBUG(D_VFSTRACE, "VFS Op:inode=" DFID "(%p)\n", PFID(ll_inode2fid(inode)), inode); ll_stats_ops_tally(ll_i2sbi(inode), LPROC_LL_FSYNC, 1); @@ -2422,7 +2422,7 @@ ll_file_flock(struct file *file, int cmd, struct file_lock *file_lock) int rc; int rc2 = 0; - CDEBUG(D_VFSTRACE, "VFS Op:inode="DFID" file_lock=%p\n", + CDEBUG(D_VFSTRACE, "VFS Op:inode=" DFID " file_lock=%p\n", PFID(ll_inode2fid(inode)), file_lock); ll_stats_ops_tally(ll_i2sbi(inode), LPROC_LL_FLOCK, 1); @@ -2507,7 +2507,7 @@ ll_file_flock(struct file *file, int cmd, struct file_lock *file_lock) if (IS_ERR(op_data)) return PTR_ERR(op_data); - CDEBUG(D_DLMTRACE, "inode="DFID", pid=%u, flags=%#llx, mode=%u, start=%llu, end=%llu\n", + CDEBUG(D_DLMTRACE, "inode=" DFID ", pid=%u, flags=%#llx, mode=%u, start=%llu, end=%llu\n", PFID(ll_inode2fid(inode)), flock.l_flock.pid, flags, einfo.ei_mode, flock.l_flock.start, flock.l_flock.end); @@ -2582,7 +2582,7 @@ int ll_migrate(struct inode *parent, struct file *file, int mdtidx, struct qstr qstr; int rc; - CDEBUG(D_VFSTRACE, "migrate %s under "DFID" to MDT%d\n", + CDEBUG(D_VFSTRACE, "migrate %s under " DFID " to MDT%d\n", name, PFID(ll_inode2fid(parent)), mdtidx); op_data = ll_prep_md_op_data(NULL, parent, NULL, name, namelen, @@ -2617,7 +2617,7 @@ int ll_migrate(struct inode *parent, struct file *file, int mdtidx, inode_lock(child_inode); op_data->op_fid3 = *ll_inode2fid(child_inode); if (!fid_is_sane(&op_data->op_fid3)) { - CERROR("%s: migrate %s, but fid "DFID" is insane\n", + CERROR("%s: migrate %s, but fid " DFID " is insane\n", ll_get_fsname(parent->i_sb, NULL, 0), name, PFID(&op_data->op_fid3)); rc = -EINVAL; @@ -2629,7 +2629,7 @@ int ll_migrate(struct inode *parent, struct file *file, int mdtidx, goto out_unlock; if (rc == mdtidx) { - CDEBUG(D_INFO, "%s:"DFID" is already on MDT%d.\n", name, + CDEBUG(D_INFO, "%s: " DFID " is already on MDT%d.\n", name, PFID(&op_data->op_fid3), mdtidx); rc = 0; goto out_unlock; @@ -2733,7 +2733,7 @@ int ll_have_md_lock(struct inode *inode, __u64 *bits, return 0; fid = &ll_i2info(inode)->lli_fid; - CDEBUG(D_INFO, "trying to match res "DFID" mode %s\n", PFID(fid), + CDEBUG(D_INFO, "trying to match res " DFID " mode %s\n", PFID(fid), ldlm_lockname[mode]); flags = LDLM_FL_BLOCK_GRANTED | LDLM_FL_CBPENDING | LDLM_FL_TEST_LOCK; @@ -2767,7 +2767,7 @@ enum ldlm_mode ll_take_md_lock(struct inode *inode, __u64 bits, struct lu_fid *fid; fid = &ll_i2info(inode)->lli_fid; - CDEBUG(D_INFO, "trying to match res "DFID"\n", PFID(fid)); + CDEBUG(D_INFO, "trying to match res " DFID "\n", PFID(fid)); return md_lock_match(ll_i2mdexp(inode), flags | LDLM_FL_BLOCK_GRANTED, fid, LDLM_IBITS, &policy, mode, lockh); @@ -2792,7 +2792,7 @@ static int ll_inode_revalidate_fini(struct inode *inode, int rc) return 0; } else if (rc != 0) { CDEBUG_LIMIT((rc == -EACCES || rc == -EIDRM) ? D_INFO : D_ERROR, - "%s: revalidate FID "DFID" error: rc = %d\n", + "%s: revalidate FID " DFID " error: rc = %d\n", ll_get_fsname(inode->i_sb, NULL, 0), PFID(ll_inode2fid(inode)), rc); } @@ -2807,7 +2807,7 @@ static int __ll_inode_revalidate(struct dentry *dentry, __u64 ibits) struct obd_export *exp; int rc = 0; - CDEBUG(D_VFSTRACE, "VFS Op:inode="DFID"(%p),name=%pd\n", + CDEBUG(D_VFSTRACE, "VFS Op:inode=" DFID "(%p),name=%pd\n", PFID(ll_inode2fid(inode)), inode, dentry); exp = ll_i2mdexp(inode); @@ -3067,7 +3067,7 @@ int ll_inode_permission(struct inode *inode, int mask) return rc; } - CDEBUG(D_VFSTRACE, "VFS Op:inode="DFID"(%p), inode mode %x mask %o\n", + CDEBUG(D_VFSTRACE, "VFS Op:inode=" DFID "(%p), inode mode %x mask %o\n", PFID(ll_inode2fid(inode)), inode, inode->i_mode, mask); /* squash fsuid/fsgid if needed */ @@ -3114,7 +3114,7 @@ int ll_inode_permission(struct inode *inode, int mask) } /* -o localflock - only provides locally consistent flock locks */ -struct file_operations ll_file_operations = { +const struct file_operations ll_file_operations = { .read_iter = ll_file_read_iter, .write_iter = ll_file_write_iter, .unlocked_ioctl = ll_file_ioctl, @@ -3127,7 +3127,7 @@ struct file_operations ll_file_operations = { .flush = ll_flush }; -struct file_operations ll_file_operations_flock = { +const struct file_operations ll_file_operations_flock = { .read_iter = ll_file_read_iter, .write_iter = ll_file_write_iter, .unlocked_ioctl = ll_file_ioctl, @@ -3143,7 +3143,7 @@ struct file_operations ll_file_operations_flock = { }; /* These are for -o noflock - to return ENOSYS on flock calls */ -struct file_operations ll_file_operations_noflock = { +const struct file_operations ll_file_operations_noflock = { .read_iter = ll_file_read_iter, .write_iter = ll_file_write_iter, .unlocked_ioctl = ll_file_ioctl, @@ -3322,7 +3322,7 @@ static int ll_layout_fetch(struct inode *inode, struct ldlm_lock *lock) int lmmsize; int rc; - CDEBUG(D_INODE, DFID" LVB_READY=%d l_lvb_data=%p l_lvb_len=%d\n", + CDEBUG(D_INODE, DFID " LVB_READY=%d l_lvb_data=%p l_lvb_len=%d\n", PFID(ll_inode2fid(inode)), ldlm_is_lvb_ready(lock), lock->l_lvb_data, lock->l_lvb_len); @@ -3447,7 +3447,7 @@ out: /* wait for IO to complete if it's still being used. */ if (wait_layout) { - CDEBUG(D_INODE, "%s: "DFID"(%p) wait for layout reconf\n", + CDEBUG(D_INODE, "%s: " DFID "(%p) wait for layout reconf\n", ll_get_fsname(inode->i_sb, NULL, 0), PFID(&lli->lli_fid), inode); @@ -3458,7 +3458,7 @@ out: if (rc == 0) rc = -EAGAIN; - CDEBUG(D_INODE, "%s: file="DFID" waiting layout return: %d.\n", + CDEBUG(D_INODE, "%s: file=" DFID " waiting layout return: %d.\n", ll_get_fsname(inode->i_sb, NULL, 0), PFID(&lli->lli_fid), rc); } @@ -3504,7 +3504,7 @@ again: it.it_op = IT_LAYOUT; lockh.cookie = 0ULL; - LDLM_DEBUG_NOLOCK("%s: requeue layout lock for file "DFID"(%p)", + LDLM_DEBUG_NOLOCK("%s: requeue layout lock for file " DFID "(%p)", ll_get_fsname(inode->i_sb, NULL, 0), PFID(&lli->lli_fid), inode); diff --git a/drivers/staging/lustre/lustre/llite/llite_internal.h b/drivers/staging/lustre/lustre/llite/llite_internal.h index d2a0fabd8a69..cd3311abf999 100644 --- a/drivers/staging/lustre/lustre/llite/llite_internal.h +++ b/drivers/staging/lustre/lustre/llite/llite_internal.h @@ -470,7 +470,7 @@ struct ll_sb_info { struct ll_ra_info ll_ra_info; unsigned int ll_namelen; - struct file_operations *ll_fop; + const struct file_operations *ll_fop; unsigned int ll_md_brw_pages; /* readdir pages per RPC */ @@ -718,14 +718,14 @@ extern const struct inode_operations ll_special_inode_operations; struct inode *ll_iget(struct super_block *sb, ino_t hash, struct lustre_md *lic); int ll_test_inode_by_fid(struct inode *inode, void *opaque); -int ll_md_blocking_ast(struct ldlm_lock *, struct ldlm_lock_desc *, +int ll_md_blocking_ast(struct ldlm_lock *lock, struct ldlm_lock_desc *desc, void *data, int flag); struct dentry *ll_splice_alias(struct inode *inode, struct dentry *de); void ll_update_times(struct ptlrpc_request *request, struct inode *inode); /* llite/rw.c */ int ll_writepage(struct page *page, struct writeback_control *wbc); -int ll_writepages(struct address_space *, struct writeback_control *wbc); +int ll_writepages(struct address_space *mapping, struct writeback_control *wbc); int ll_readpage(struct file *file, struct page *page); void ll_readahead_init(struct inode *inode, struct ll_readahead_state *ras); int vvp_io_write_commit(const struct lu_env *env, struct cl_io *io); @@ -736,9 +736,9 @@ void ll_cl_remove(struct file *file, const struct lu_env *env); extern const struct address_space_operations ll_aops; /* llite/file.c */ -extern struct file_operations ll_file_operations; -extern struct file_operations ll_file_operations_flock; -extern struct file_operations ll_file_operations_noflock; +extern const struct file_operations ll_file_operations; +extern const struct file_operations ll_file_operations_flock; +extern const struct file_operations ll_file_operations_noflock; extern const struct inode_operations ll_file_inode_operations; int ll_have_md_lock(struct inode *inode, __u64 *bits, enum ldlm_mode l_req_mode); @@ -747,7 +747,7 @@ enum ldlm_mode ll_take_md_lock(struct inode *inode, __u64 bits, enum ldlm_mode mode); int ll_file_open(struct inode *inode, struct file *file); int ll_file_release(struct inode *inode, struct file *file); -int ll_release_openhandle(struct inode *, struct lookup_intent *); +int ll_release_openhandle(struct inode *inode, struct lookup_intent *it); int ll_md_real_close(struct inode *inode, fmode_t fmode); int ll_getattr(const struct path *path, struct kstat *stat, u32 request_mask, unsigned int flags); @@ -778,9 +778,9 @@ int ll_hsm_state_set(struct inode *inode, struct hsm_state_set *hss); /* llite/dcache.c */ extern const struct dentry_operations ll_d_ops; -void ll_intent_drop_lock(struct lookup_intent *); -void ll_intent_release(struct lookup_intent *); -void ll_invalidate_aliases(struct inode *); +void ll_intent_drop_lock(struct lookup_intent *it); +void ll_intent_release(struct lookup_intent *it); +void ll_invalidate_aliases(struct inode *inode); void ll_lookup_finish_locks(struct lookup_intent *it, struct inode *inode); int ll_revalidate_it_finish(struct ptlrpc_request *request, struct lookup_intent *it, struct inode *inode); @@ -811,7 +811,7 @@ int ll_remount_fs(struct super_block *sb, int *flags, char *data); int ll_show_options(struct seq_file *seq, struct dentry *dentry); void ll_dirty_page_discard_warn(struct page *page, int ioret); int ll_prep_inode(struct inode **inode, struct ptlrpc_request *req, - struct super_block *, struct lookup_intent *); + struct super_block *sb, struct lookup_intent *it); int ll_obd_statfs(struct inode *inode, void __user *arg); int ll_get_max_mdsize(struct ll_sb_info *sbi, int *max_mdsize); int ll_get_default_mdsize(struct ll_sb_info *sbi, int *default_mdsize); @@ -1253,7 +1253,7 @@ static inline void ll_set_lock_data(struct obd_export *exp, struct inode *inode, */ if (it->it_remote_lock_mode) { handle.cookie = it->it_remote_lock_handle; - CDEBUG(D_DLMTRACE, "setting l_data to inode "DFID"%p for remote lock %#llx\n", + CDEBUG(D_DLMTRACE, "setting l_data to inode " DFID "%p for remote lock %#llx\n", PFID(ll_inode2fid(inode)), inode, handle.cookie); md_set_lock_data(exp, &handle, inode, NULL); @@ -1261,7 +1261,7 @@ static inline void ll_set_lock_data(struct obd_export *exp, struct inode *inode, handle.cookie = it->it_lock_handle; - CDEBUG(D_DLMTRACE, "setting l_data to inode "DFID"%p for lock %#llx\n", + CDEBUG(D_DLMTRACE, "setting l_data to inode " DFID "%p for lock %#llx\n", PFID(ll_inode2fid(inode)), inode, handle.cookie); md_set_lock_data(exp, &handle, inode, &it->it_lock_bits); diff --git a/drivers/staging/lustre/lustre/llite/llite_lib.c b/drivers/staging/lustre/lustre/llite/llite_lib.c index ca5040c69217..974a05d6c969 100644 --- a/drivers/staging/lustre/lustre/llite/llite_lib.c +++ b/drivers/staging/lustre/lustre/llite/llite_lib.c @@ -427,13 +427,13 @@ static int client_common_fill_super(struct super_block *sb, char *md, char *dt, goto out_lock_cn_cb; } if (!fid_is_sane(&sbi->ll_root_fid)) { - CERROR("%s: Invalid root fid "DFID" during mount\n", + CERROR("%s: Invalid root fid " DFID " during mount\n", sbi->ll_md_exp->exp_obd->obd_name, PFID(&sbi->ll_root_fid)); err = -EINVAL; goto out_lock_cn_cb; } - CDEBUG(D_SUPER, "rootfid "DFID"\n", PFID(&sbi->ll_root_fid)); + CDEBUG(D_SUPER, "rootfid " DFID "\n", PFID(&sbi->ll_root_fid)); sb->s_op = &lustre_super_operations; sb->s_xattr = ll_xattr_handlers; @@ -1079,7 +1079,7 @@ static struct inode *ll_iget_anon_dir(struct super_block *sb, ino = cl_fid_build_ino(fid, sbi->ll_flags & LL_SBI_32BIT_API); inode = iget_locked(sb, ino); if (!inode) { - CERROR("%s: failed get simple inode "DFID": rc = -ENOENT\n", + CERROR("%s: failed get simple inode " DFID ": rc = -ENOENT\n", ll_get_fsname(sb, NULL, 0), PFID(fid)); return ERR_PTR(-ENOENT); } @@ -1090,7 +1090,7 @@ static struct inode *ll_iget_anon_dir(struct super_block *sb, inode->i_mode = (inode->i_mode & ~S_IFMT) | (body->mbo_mode & S_IFMT); - LASSERTF(S_ISDIR(inode->i_mode), "Not slave inode "DFID"\n", + LASSERTF(S_ISDIR(inode->i_mode), "Not slave inode " DFID "\n", PFID(fid)); LTIME_S(inode->i_mtime) = 0; @@ -1106,7 +1106,7 @@ static struct inode *ll_iget_anon_dir(struct super_block *sb, LASSERT(lsm); /* master object FID */ lli->lli_pfid = body->mbo_fid1; - CDEBUG(D_INODE, "lli %p slave "DFID" master "DFID"\n", + CDEBUG(D_INODE, "lli %p slave " DFID " master " DFID "\n", lli, PFID(fid), PFID(&lli->lli_pfid)); unlock_new_inode(inode); } @@ -1174,7 +1174,7 @@ static int ll_update_lsm_md(struct inode *inode, struct lustre_md *md) int rc; LASSERT(S_ISDIR(inode->i_mode)); - CDEBUG(D_INODE, "update lsm %p of "DFID"\n", lli->lli_lsm_md, + CDEBUG(D_INODE, "update lsm %p of " DFID "\n", lli->lli_lsm_md, PFID(ll_inode2fid(inode))); /* no striped information from request. */ @@ -1187,7 +1187,7 @@ static int ll_update_lsm_md(struct inode *inode, struct lustre_md *md) * migration is done, the temporay MIGRATE layout has * been removed */ - CDEBUG(D_INODE, DFID" finish migration.\n", + CDEBUG(D_INODE, DFID " finish migration.\n", PFID(ll_inode2fid(inode))); lmv_free_memmd(lli->lli_lsm_md); lli->lli_lsm_md = NULL; @@ -1241,7 +1241,7 @@ static int ll_update_lsm_md(struct inode *inode, struct lustre_md *md) kfree(attr); - CDEBUG(D_INODE, "Set lsm %p magic %x to "DFID"\n", lsm, + CDEBUG(D_INODE, "Set lsm %p magic %x to " DFID "\n", lsm, lsm->lsm_md_magic, PFID(ll_inode2fid(inode))); return 0; } @@ -1251,7 +1251,7 @@ static int ll_update_lsm_md(struct inode *inode, struct lustre_md *md) struct lmv_stripe_md *old_lsm = lli->lli_lsm_md; int idx; - CERROR("%s: inode "DFID"(%p)'s lmv layout mismatch (%p)/(%p) magic:0x%x/0x%x stripe count: %d/%d master_mdt: %d/%d hash_type:0x%x/0x%x layout: 0x%x/0x%x pool:%s/%s\n", + CERROR("%s: inode " DFID "(%p)'s lmv layout mismatch (%p)/(%p) magic:0x%x/0x%x stripe count: %d/%d master_mdt: %d/%d hash_type:0x%x/0x%x layout: 0x%x/0x%x pool:%s/%s\n", ll_get_fsname(inode->i_sb, NULL, 0), PFID(&lli->lli_fid), inode, lsm, old_lsm, lsm->lsm_md_magic, old_lsm->lsm_md_magic, @@ -1266,13 +1266,13 @@ static int ll_update_lsm_md(struct inode *inode, struct lustre_md *md) old_lsm->lsm_md_pool_name); for (idx = 0; idx < old_lsm->lsm_md_stripe_count; idx++) { - CERROR("%s: sub FIDs in old lsm idx %d, old: "DFID"\n", + CERROR("%s: sub FIDs in old lsm idx %d, old: " DFID "\n", ll_get_fsname(inode->i_sb, NULL, 0), idx, PFID(&old_lsm->lsm_md_oinfo[idx].lmo_fid)); } for (idx = 0; idx < lsm->lsm_md_stripe_count; idx++) { - CERROR("%s: sub FIDs in new lsm idx %d, new: "DFID"\n", + CERROR("%s: sub FIDs in new lsm idx %d, new: " DFID "\n", ll_get_fsname(inode->i_sb, NULL, 0), idx, PFID(&lsm->lsm_md_oinfo[idx].lmo_fid)); } @@ -1288,7 +1288,7 @@ void ll_clear_inode(struct inode *inode) struct ll_inode_info *lli = ll_i2info(inode); struct ll_sb_info *sbi = ll_i2sbi(inode); - CDEBUG(D_VFSTRACE, "VFS Op:inode="DFID"(%p)\n", + CDEBUG(D_VFSTRACE, "VFS Op:inode=" DFID "(%p)\n", PFID(ll_inode2fid(inode)), inode); if (S_ISDIR(inode->i_mode)) { @@ -1421,7 +1421,7 @@ int ll_setattr_raw(struct dentry *dentry, struct iattr *attr, bool hsm_import) struct md_op_data *op_data = NULL; int rc = 0; - CDEBUG(D_VFSTRACE, "%s: setattr inode "DFID"(%p) from %llu to %llu, valid %x, hsm_import %d\n", + CDEBUG(D_VFSTRACE, "%s: setattr inode " DFID "(%p) from %llu to %llu, valid %x, hsm_import %d\n", ll_get_fsname(inode->i_sb, NULL, 0), PFID(&lli->lli_fid), inode, i_size_read(inode), attr->ia_size, attr->ia_valid, hsm_import); @@ -1436,7 +1436,7 @@ int ll_setattr_raw(struct dentry *dentry, struct iattr *attr, bool hsm_import) * needs another check in addition to the VFS check above. */ if (attr->ia_size > ll_file_maxbytes(inode)) { - CDEBUG(D_INODE, "file "DFID" too large %llu > %llu\n", + CDEBUG(D_INODE, "file " DFID " too large %llu > %llu\n", PFID(&lli->lli_fid), attr->ia_size, ll_file_maxbytes(inode)); return -EFBIG; @@ -1785,7 +1785,7 @@ int ll_update_inode(struct inode *inode, struct lustre_md *md) /* FID shouldn't be changed! */ if (fid_is_sane(&lli->lli_fid)) { LASSERTF(lu_fid_eq(&lli->lli_fid, &body->mbo_fid1), - "Trying to change FID "DFID" to the "DFID", inode "DFID"(%p)\n", + "Trying to change FID " DFID " to the " DFID ", inode " DFID "(%p)\n", PFID(&lli->lli_fid), PFID(&body->mbo_fid1), PFID(ll_inode2fid(inode)), inode); } else { @@ -1820,7 +1820,7 @@ int ll_read_inode2(struct inode *inode, void *opaque) struct ll_inode_info *lli = ll_i2info(inode); int rc; - CDEBUG(D_VFSTRACE, "VFS Op:inode="DFID"(%p)\n", + CDEBUG(D_VFSTRACE, "VFS Op:inode=" DFID "(%p)\n", PFID(&lli->lli_fid), inode); /* Core attributes from the MDS first. This is a new inode, and @@ -1902,7 +1902,7 @@ int ll_iocontrol(struct inode *inode, struct file *file, rc = md_getattr(sbi->ll_md_exp, op_data, &req); ll_finish_md_op_data(op_data); if (rc) { - CERROR("%s: failure inode "DFID": rc = %d\n", + CERROR("%s: failure inode " DFID ": rc = %d\n", sbi->ll_md_exp->exp_obd->obd_name, PFID(ll_inode2fid(inode)), rc); return -abs(rc); diff --git a/drivers/staging/lustre/lustre/llite/llite_mmap.c b/drivers/staging/lustre/lustre/llite/llite_mmap.c index cbbfdaf127a7..ccc7ae15a943 100644 --- a/drivers/staging/lustre/lustre/llite/llite_mmap.c +++ b/drivers/staging/lustre/lustre/llite/llite_mmap.c @@ -378,7 +378,7 @@ static int ll_page_mkwrite(struct vm_fault *vmf) if (!printed && ++count > 16) { const struct dentry *de = vma->vm_file->f_path.dentry; - CWARN("app(%s): the page %lu of file "DFID" is under heavy contention\n", + CWARN("app(%s): the page %lu of file " DFID " is under heavy contention\n", current->comm, vmf->pgoff, PFID(ll_inode2fid(de->d_inode))); printed = true; diff --git a/drivers/staging/lustre/lustre/llite/llite_nfs.c b/drivers/staging/lustre/lustre/llite/llite_nfs.c index 49a930f0fc5d..e50c637fab54 100644 --- a/drivers/staging/lustre/lustre/llite/llite_nfs.c +++ b/drivers/staging/lustre/lustre/llite/llite_nfs.c @@ -84,7 +84,7 @@ struct inode *search_inode_for_lustre(struct super_block *sb, struct md_op_data *op_data; int rc; - CDEBUG(D_INFO, "searching inode for:(%lu,"DFID")\n", hash, PFID(fid)); + CDEBUG(D_INFO, "searching inode for:(%lu," DFID ")\n", hash, PFID(fid)); inode = ilookup5(sb, hash, ll_test_inode_by_fid, (void *)fid); if (inode) @@ -109,7 +109,7 @@ struct inode *search_inode_for_lustre(struct super_block *sb, rc = md_getattr(sbi->ll_md_exp, op_data, &req); kfree(op_data); if (rc) { - CDEBUG(D_INFO, "can't get object attrs, fid "DFID", rc %d\n", + CDEBUG(D_INFO, "can't get object attrs, fid " DFID ", rc %d\n", PFID(fid), rc); return ERR_PTR(rc); } @@ -195,7 +195,7 @@ static int ll_encode_fh(struct inode *inode, __u32 *fh, int *plen, int fileid_len = sizeof(struct lustre_nfs_fid) / 4; struct lustre_nfs_fid *nfs_fid = (void *)fh; - CDEBUG(D_INFO, "%s: encoding for ("DFID") maxlen=%d minlen=%d\n", + CDEBUG(D_INFO, "%s: encoding for (" DFID ") maxlen=%d minlen=%d\n", ll_get_fsname(inode->i_sb, NULL, 0), PFID(ll_inode2fid(inode)), *plen, fileid_len); @@ -312,7 +312,7 @@ int ll_dir_get_parent_fid(struct inode *dir, struct lu_fid *parent_fid) sbi = ll_s2sbi(dir->i_sb); - CDEBUG(D_INFO, "%s: getting parent for ("DFID")\n", + CDEBUG(D_INFO, "%s: getting parent for (" DFID ")\n", ll_get_fsname(dir->i_sb, NULL, 0), PFID(ll_inode2fid(dir))); @@ -329,7 +329,7 @@ int ll_dir_get_parent_fid(struct inode *dir, struct lu_fid *parent_fid) rc = md_getattr_name(sbi->ll_md_exp, op_data, &req); ll_finish_md_op_data(op_data); if (rc) { - CERROR("%s: failure inode "DFID" get parent: rc = %d\n", + CERROR("%s: failure inode " DFID " get parent: rc = %d\n", ll_get_fsname(dir->i_sb, NULL, 0), PFID(ll_inode2fid(dir)), rc); return rc; diff --git a/drivers/staging/lustre/lustre/llite/lproc_llite.c b/drivers/staging/lustre/lustre/llite/lproc_llite.c index c742cba60199..aeae6670e262 100644 --- a/drivers/staging/lustre/lustre/llite/lproc_llite.c +++ b/drivers/staging/lustre/lustre/llite/lproc_llite.c @@ -39,9 +39,9 @@ #include "vvp_internal.h" /* debugfs llite mount point registration */ -static struct file_operations ll_rw_extents_stats_fops; -static struct file_operations ll_rw_extents_stats_pp_fops; -static struct file_operations ll_rw_offset_stats_fops; +static const struct file_operations ll_rw_extents_stats_fops; +static const struct file_operations ll_rw_extents_stats_pp_fops; +static const struct file_operations ll_rw_offset_stats_fops; static ssize_t blocksize_show(struct kobject *kobj, struct attribute *attr, char *buf) diff --git a/drivers/staging/lustre/lustre/llite/namei.c b/drivers/staging/lustre/lustre/llite/namei.c index d583696e8378..a208a8b02c2c 100644 --- a/drivers/staging/lustre/lustre/llite/namei.c +++ b/drivers/staging/lustre/lustre/llite/namei.c @@ -86,7 +86,7 @@ static int ll_set_inode(struct inode *inode, void *opaque) inode->i_mode = (inode->i_mode & ~S_IFMT) | (body->mbo_mode & S_IFMT); if (unlikely(inode->i_mode == 0)) { - CERROR("Invalid inode "DFID" type\n", PFID(&lli->lli_fid)); + CERROR("Invalid inode " DFID " type\n", PFID(&lli->lli_fid)); return -EINVAL; } @@ -134,7 +134,7 @@ struct inode *ll_iget(struct super_block *sb, ino_t hash, } } else if (!(inode->i_state & (I_FREEING | I_CLEAR))) { rc = ll_update_inode(inode, md); - CDEBUG(D_VFSTRACE, "got inode: "DFID"(%p): rc = %d\n", + CDEBUG(D_VFSTRACE, "got inode: " DFID "(%p): rc = %d\n", PFID(&md->body->mbo_fid1), inode, rc); if (rc) { if (S_ISDIR(inode->i_mode)) @@ -205,7 +205,7 @@ int ll_md_blocking_ast(struct ldlm_lock *lock, struct ldlm_lock_desc *desc, if (!fid_res_name_eq(ll_inode2fid(inode), &lock->l_resource->lr_name)) { - LDLM_ERROR(lock, "data mismatch with object "DFID"(%p)", + LDLM_ERROR(lock, "data mismatch with object " DFID "(%p)", PFID(ll_inode2fid(inode)), inode); LBUG(); } @@ -257,7 +257,7 @@ int ll_md_blocking_ast(struct ldlm_lock *lock, struct ldlm_lock_desc *desc, rc = ll_layout_conf(inode, &conf); if (rc < 0) CDEBUG(D_INODE, "cannot invalidate layout of " - DFID": rc = %d\n", + DFID ": rc = %d\n", PFID(ll_inode2fid(inode)), rc); } @@ -274,7 +274,7 @@ int ll_md_blocking_ast(struct ldlm_lock *lock, struct ldlm_lock_desc *desc, if ((bits & MDS_INODELOCK_UPDATE) && S_ISDIR(inode->i_mode)) { struct ll_inode_info *lli = ll_i2info(inode); - CDEBUG(D_INODE, "invalidating inode "DFID" lli = %p, pfid = "DFID"\n", + CDEBUG(D_INODE, "invalidating inode " DFID " lli = %p, pfid = " DFID "\n", PFID(ll_inode2fid(inode)), lli, PFID(&lli->lli_pfid)); @@ -290,7 +290,7 @@ int ll_md_blocking_ast(struct ldlm_lock *lock, struct ldlm_lock_desc *desc, * we have to invalidate the negative children * on master inode */ - CDEBUG(D_INODE, "Invalidate s"DFID" m"DFID"\n", + CDEBUG(D_INODE, "Invalidate s" DFID " m" DFID "\n", PFID(ll_inode2fid(inode)), PFID(&lli->lli_pfid)); @@ -542,7 +542,7 @@ static struct dentry *ll_lookup_it(struct inode *parent, struct dentry *dentry, if (dentry->d_name.len > ll_i2sbi(parent)->ll_namelen) return ERR_PTR(-ENAMETOOLONG); - CDEBUG(D_VFSTRACE, "VFS Op:name=%pd, dir="DFID"(%p),intent=%s\n", + CDEBUG(D_VFSTRACE, "VFS Op:name=%pd, dir=" DFID "(%p),intent=%s\n", dentry, PFID(ll_inode2fid(parent)), parent, LL_IT2STR(it)); if (d_mountpoint(dentry)) @@ -650,7 +650,7 @@ static struct dentry *ll_lookup_nd(struct inode *parent, struct dentry *dentry, struct lookup_intent *itp, it = { .it_op = IT_GETATTR }; struct dentry *de; - CDEBUG(D_VFSTRACE, "VFS Op:name=%pd, dir="DFID"(%p),flags=%u\n", + CDEBUG(D_VFSTRACE, "VFS Op:name=%pd, dir=" DFID "(%p),flags=%u\n", dentry, PFID(ll_inode2fid(parent)), parent, flags); /* Optimize away (CREATE && !OPEN). Let .create handle the race. @@ -678,14 +678,14 @@ static struct dentry *ll_lookup_nd(struct inode *parent, struct dentry *dentry, * together. */ static int ll_atomic_open(struct inode *dir, struct dentry *dentry, - struct file *file, unsigned open_flags, + struct file *file, unsigned int open_flags, umode_t mode, int *opened) { struct lookup_intent *it; struct dentry *de; int rc = 0; - CDEBUG(D_VFSTRACE, "VFS Op:name=%pd, dir="DFID"(%p),file %p,open_flags %x,mode %x opened %d\n", + CDEBUG(D_VFSTRACE, "VFS Op:name=%pd, dir=" DFID "(%p),file %p,open_flags %x,mode %x opened %d\n", dentry, PFID(ll_inode2fid(dir)), dir, file, open_flags, mode, *opened); @@ -792,7 +792,7 @@ static struct inode *ll_create_node(struct inode *dir, struct lookup_intent *it) * lock on the inode. Since we finally have an inode pointer, * stuff it in the lock. */ - CDEBUG(D_DLMTRACE, "setting l_ast_data to inode "DFID"(%p)\n", + CDEBUG(D_DLMTRACE, "setting l_ast_data to inode " DFID "(%p)\n", PFID(ll_inode2fid(dir)), inode); ll_set_lock_data(sbi->ll_md_exp, inode, it, NULL); out: @@ -820,7 +820,7 @@ static int ll_create_it(struct inode *dir, struct dentry *dentry, struct inode *inode; int rc = 0; - CDEBUG(D_VFSTRACE, "VFS Op:name=%pd, dir="DFID"(%p), intent=%s\n", + CDEBUG(D_VFSTRACE, "VFS Op:name=%pd, dir=" DFID "(%p), intent=%s\n", dentry, PFID(ll_inode2fid(dir)), dir, LL_IT2STR(it)); rc = it_open_error(DISP_OPEN_CREATE, it); @@ -844,7 +844,7 @@ void ll_update_times(struct ptlrpc_request *request, struct inode *inode) LASSERT(body); if (body->mbo_valid & OBD_MD_FLMTIME && body->mbo_mtime > LTIME_S(inode->i_mtime)) { - CDEBUG(D_INODE, "setting fid "DFID" mtime from %lu to %llu\n", + CDEBUG(D_INODE, "setting fid " DFID " mtime from %lu to %llu\n", PFID(ll_inode2fid(inode)), LTIME_S(inode->i_mtime), body->mbo_mtime); LTIME_S(inode->i_mtime) = body->mbo_mtime; @@ -942,7 +942,7 @@ static int ll_mknod(struct inode *dir, struct dentry *dchild, { int err; - CDEBUG(D_VFSTRACE, "VFS Op:name=%pd, dir="DFID"(%p) mode %o dev %x\n", + CDEBUG(D_VFSTRACE, "VFS Op:name=%pd, dir=" DFID "(%p) mode %o dev %x\n", dchild, PFID(ll_inode2fid(dir)), dir, mode, old_encode_dev(rdev)); @@ -982,7 +982,7 @@ static int ll_create_nd(struct inode *dir, struct dentry *dentry, { int rc; - CDEBUG(D_VFSTRACE, "VFS Op:name=%pd, dir="DFID"(%p), flags=%u, excl=%d\n", + CDEBUG(D_VFSTRACE, "VFS Op:name=%pd, dir=" DFID "(%p), flags=%u, excl=%d\n", dentry, PFID(ll_inode2fid(dir)), dir, mode, want_excl); rc = ll_mknod(dir, dentry, mode, 0); @@ -1032,7 +1032,7 @@ static int ll_mkdir(struct inode *dir, struct dentry *dentry, umode_t mode) { int err; - CDEBUG(D_VFSTRACE, "VFS Op:name=%pd, dir"DFID"(%p)\n", + CDEBUG(D_VFSTRACE, "VFS Op:name=%pd, dir" DFID "(%p)\n", dentry, PFID(ll_inode2fid(dir)), dir); if (!IS_POSIXACL(dir) || !exp_connect_umask(ll_i2mdexp(dir))) @@ -1052,7 +1052,7 @@ static int ll_rmdir(struct inode *dir, struct dentry *dchild) struct md_op_data *op_data; int rc; - CDEBUG(D_VFSTRACE, "VFS Op:name=%pd, dir="DFID"(%p)\n", + CDEBUG(D_VFSTRACE, "VFS Op:name=%pd, dir=" DFID "(%p)\n", dchild, PFID(ll_inode2fid(dir)), dir); op_data = ll_prep_md_op_data(NULL, dir, NULL, @@ -1082,7 +1082,7 @@ static int ll_symlink(struct inode *dir, struct dentry *dentry, { int err; - CDEBUG(D_VFSTRACE, "VFS Op:name=%pd, dir="DFID"(%p),target=%.*s\n", + CDEBUG(D_VFSTRACE, "VFS Op:name=%pd, dir=" DFID "(%p),target=%.*s\n", dentry, PFID(ll_inode2fid(dir)), dir, 3000, oldname); err = ll_new_node(dir, dentry, oldname, S_IFLNK | 0777, @@ -1103,7 +1103,7 @@ static int ll_link(struct dentry *old_dentry, struct inode *dir, struct md_op_data *op_data; int err; - CDEBUG(D_VFSTRACE, "VFS Op: inode="DFID"(%p), dir="DFID"(%p), target=%pd\n", + CDEBUG(D_VFSTRACE, "VFS Op: inode=" DFID "(%p), dir=" DFID "(%p), target=%pd\n", PFID(ll_inode2fid(src)), src, PFID(ll_inode2fid(dir)), dir, new_dentry); @@ -1138,7 +1138,7 @@ static int ll_rename(struct inode *src, struct dentry *src_dchild, return -EINVAL; CDEBUG(D_VFSTRACE, - "VFS Op:oldname=%pd, src_dir="DFID"(%p), newname=%pd, tgt_dir="DFID"(%p)\n", + "VFS Op:oldname=%pd, src_dir=" DFID "(%p), newname=%pd, tgt_dir=" DFID "(%p)\n", src_dchild, PFID(ll_inode2fid(src)), src, tgt_dchild, PFID(ll_inode2fid(tgt)), tgt); diff --git a/drivers/staging/lustre/lustre/llite/rw26.c b/drivers/staging/lustre/lustre/llite/rw26.c index 420f296f9658..3619cd8bb5f3 100644 --- a/drivers/staging/lustre/lustre/llite/rw26.c +++ b/drivers/staging/lustre/lustre/llite/rw26.c @@ -327,7 +327,7 @@ static ssize_t ll_direct_IO_26(struct kiocb *iocb, struct iov_iter *iter) if ((file_offset & ~PAGE_MASK) || (count & ~PAGE_MASK)) return -EINVAL; - CDEBUG(D_VFSTRACE, "VFS Op:inode="DFID"(%p), size=%zd (max %lu), offset=%lld=%llx, pages %zd (max %lu)\n", + CDEBUG(D_VFSTRACE, "VFS Op:inode=" DFID "(%p), size=%zd (max %lu), offset=%lld=%llx, pages %zd (max %lu)\n", PFID(ll_inode2fid(inode)), inode, count, MAX_DIO_SIZE, file_offset, file_offset, count >> PAGE_SHIFT, MAX_DIO_SIZE >> PAGE_SHIFT); @@ -547,7 +547,7 @@ out: } static int ll_write_end(struct file *file, struct address_space *mapping, - loff_t pos, unsigned len, unsigned copied, + loff_t pos, unsigned int len, unsigned int copied, struct page *vmpage, void *fsdata) { struct ll_cl_context *lcc = fsdata; diff --git a/drivers/staging/lustre/lustre/llite/statahead.c b/drivers/staging/lustre/lustre/llite/statahead.c index fb7c315b33cb..9bbca018a5fe 100644 --- a/drivers/staging/lustre/lustre/llite/statahead.c +++ b/drivers/staging/lustre/lustre/llite/statahead.c @@ -528,7 +528,7 @@ static void ll_agl_trigger(struct inode *inode, struct ll_statahead_info *sai) } CDEBUG(D_READA, "Handling (init) async glimpse: inode = " - DFID", idx = %llu\n", PFID(&lli->lli_fid), index); + DFID ", idx = %llu\n", PFID(&lli->lli_fid), index); cl_agl(inode); lli->lli_agl_index = 0; @@ -536,7 +536,7 @@ static void ll_agl_trigger(struct inode *inode, struct ll_statahead_info *sai) up_write(&lli->lli_glimpse_sem); CDEBUG(D_READA, "Handled (init) async glimpse: inode= " - DFID", idx = %llu, rc = %d\n", + DFID ", idx = %llu, rc = %d\n", PFID(&lli->lli_fid), index, rc); iput(inode); @@ -1008,7 +1008,7 @@ static int ll_statahead_thread(void *arg) sai->sai_in_readpage = 0; if (IS_ERR(page)) { rc = PTR_ERR(page); - CDEBUG(D_READA, "error reading dir "DFID" at %llu/%llu: opendir_pid = %u: rc = %d\n", + CDEBUG(D_READA, "error reading dir " DFID " at %llu/%llu: opendir_pid = %u: rc = %d\n", PFID(ll_inode2fid(dir)), pos, sai->sai_index, lli->lli_opendir_pid, rc); break; @@ -1105,7 +1105,7 @@ static int ll_statahead_thread(void *arg) if (sa_low_hit(sai)) { rc = -EFAULT; atomic_inc(&sbi->ll_sa_wrong); - CDEBUG(D_READA, "Statahead for dir "DFID" hit ratio too low: hit/miss %llu/%llu, sent/replied %llu/%llu, stopping statahead thread: pid %d\n", + CDEBUG(D_READA, "Statahead for dir " DFID " hit ratio too low: hit/miss %llu/%llu, sent/replied %llu/%llu, stopping statahead thread: pid %d\n", PFID(&lli->lli_fid), sai->sai_hit, sai->sai_miss, sai->sai_sent, sai->sai_replied, current_pid()); @@ -1211,7 +1211,7 @@ void ll_deauthorize_statahead(struct inode *dir, void *key) LASSERT(lli->lli_opendir_key == key); LASSERT(lli->lli_opendir_pid); - CDEBUG(D_READA, "deauthorize statahead for "DFID"\n", + CDEBUG(D_READA, "deauthorize statahead for " DFID "\n", PFID(&lli->lli_fid)); spin_lock(&lli->lli_sa_lock); @@ -1274,7 +1274,7 @@ static int is_first_dirent(struct inode *dir, struct dentry *dentry) struct ll_inode_info *lli = ll_i2info(dir); rc = PTR_ERR(page); - CERROR("%s: error reading dir "DFID" at %llu: opendir_pid = %u : rc = %d\n", + CERROR("%s: error reading dir " DFID " at %llu: opendir_pid = %u : rc = %d\n", ll_get_fsname(dir->i_sb, NULL, 0), PFID(ll_inode2fid(dir)), pos, lli->lli_opendir_pid, rc); @@ -1471,7 +1471,7 @@ static int revalidate_statahead_dentry(struct inode *dir, } else if ((*dentryp)->d_inode != inode) { /* revalidate, but inode is recreated */ CDEBUG(D_READA, - "%s: stale dentry %pd inode "DFID", statahead inode "DFID"\n", + "%s: stale dentry %pd inode " DFID ", statahead inode " DFID "\n", ll_get_fsname((*dentryp)->d_inode->i_sb, NULL, 0), *dentryp, diff --git a/drivers/staging/lustre/lustre/llite/symlink.c b/drivers/staging/lustre/lustre/llite/symlink.c index 60aac42e5344..3cd33483afaf 100644 --- a/drivers/staging/lustre/lustre/llite/symlink.c +++ b/drivers/staging/lustre/lustre/llite/symlink.c @@ -72,7 +72,7 @@ static int ll_readlink_internal(struct inode *inode, ll_finish_md_op_data(op_data); if (rc) { if (rc != -ENOENT) - CERROR("%s: inode "DFID": rc = %d\n", + CERROR("%s: inode " DFID ": rc = %d\n", ll_get_fsname(inode->i_sb, NULL, 0), PFID(ll_inode2fid(inode)), rc); goto failed; @@ -87,7 +87,7 @@ static int ll_readlink_internal(struct inode *inode, LASSERT(symlen != 0); if (body->mbo_eadatasize != symlen) { - CERROR("%s: inode "DFID": symlink length %d not expected %d\n", + CERROR("%s: inode " DFID ": symlink length %d not expected %d\n", ll_get_fsname(inode->i_sb, NULL, 0), PFID(ll_inode2fid(inode)), body->mbo_eadatasize - 1, symlen - 1); diff --git a/drivers/staging/lustre/lustre/llite/vvp_dev.c b/drivers/staging/lustre/lustre/llite/vvp_dev.c index 6cb2db28eb60..8e45672b4617 100644 --- a/drivers/staging/lustre/lustre/llite/vvp_dev.c +++ b/drivers/staging/lustre/lustre/llite/vvp_dev.c @@ -381,11 +381,11 @@ int cl_sb_fini(struct super_block *sb) #define PGC_DEPTH_SHIFT (32) struct vvp_pgcache_id { - unsigned vpi_bucket; - unsigned vpi_depth; + unsigned int vpi_bucket; + unsigned int vpi_depth; uint32_t vpi_index; - unsigned vpi_curdep; + unsigned int vpi_curdep; struct lu_object_header *vpi_obj; }; diff --git a/drivers/staging/lustre/lustre/llite/vvp_io.c b/drivers/staging/lustre/lustre/llite/vvp_io.c index aa31bc0a58a6..c5ba265ef6ad 100644 --- a/drivers/staging/lustre/lustre/llite/vvp_io.c +++ b/drivers/staging/lustre/lustre/llite/vvp_io.c @@ -325,7 +325,7 @@ static void vvp_io_fini(const struct lu_env *env, const struct cl_io_slice *ios) io->ci_need_restart = vio->vui_layout_gen != gen; if (io->ci_need_restart) { CDEBUG(D_VFSTRACE, - DFID" layout changed from %d to %d.\n", + DFID " layout changed from %d to %d.\n", PFID(lu_object_fid(&obj->co_lu)), vio->vui_layout_gen, gen); /* today successful restore is the only possible case */ diff --git a/drivers/staging/lustre/lustre/llite/vvp_object.c b/drivers/staging/lustre/lustre/llite/vvp_object.c index 8e18cf86cefc..9bfd72e514d1 100644 --- a/drivers/staging/lustre/lustre/llite/vvp_object.c +++ b/drivers/staging/lustre/lustre/llite/vvp_object.c @@ -70,7 +70,7 @@ static int vvp_object_print(const struct lu_env *env, void *cookie, atomic_read(&obj->vob_mmap_cnt), inode); if (inode) { lli = ll_i2info(inode); - (*p)(env, cookie, "%lu/%u %o %u %d %p "DFID, + (*p)(env, cookie, "%lu/%u %o %u %d %p " DFID, inode->i_ino, inode->i_generation, inode->i_mode, inode->i_nlink, atomic_read(&inode->i_count), lli->lli_clob, PFID(&lli->lli_fid)); diff --git a/drivers/staging/lustre/lustre/llite/xattr.c b/drivers/staging/lustre/lustre/llite/xattr.c index 6187bffec8c4..bd30abdecfb9 100644 --- a/drivers/staging/lustre/lustre/llite/xattr.c +++ b/drivers/staging/lustre/lustre/llite/xattr.c @@ -195,7 +195,7 @@ static int ll_xattr_set(const struct xattr_handler *handler, LASSERT(inode); LASSERT(name); - CDEBUG(D_VFSTRACE, "VFS Op:inode="DFID"(%p), xattr %s\n", + CDEBUG(D_VFSTRACE, "VFS Op:inode=" DFID "(%p), xattr %s\n", PFID(ll_inode2fid(inode)), inode, name); if (!strcmp(name, "lov")) { @@ -370,7 +370,7 @@ static int ll_xattr_get_common(const struct xattr_handler *handler, #endif int rc; - CDEBUG(D_VFSTRACE, "VFS Op:inode="DFID"(%p)\n", + CDEBUG(D_VFSTRACE, "VFS Op:inode=" DFID "(%p)\n", PFID(ll_inode2fid(inode)), inode); ll_stats_ops_tally(ll_i2sbi(inode), LPROC_LL_GETXATTR, 1); @@ -523,7 +523,7 @@ ssize_t ll_listxattr(struct dentry *dentry, char *buffer, size_t size) LASSERT(inode); - CDEBUG(D_VFSTRACE, "VFS Op:inode="DFID"(%p)\n", + CDEBUG(D_VFSTRACE, "VFS Op:inode=" DFID "(%p)\n", PFID(ll_inode2fid(inode)), inode); ll_stats_ops_tally(ll_i2sbi(inode), LPROC_LL_LISTXATTR, 1); diff --git a/drivers/staging/lustre/lustre/llite/xattr_cache.c b/drivers/staging/lustre/lustre/llite/xattr_cache.c index 38f75f6aa887..82cf4211cc0f 100644 --- a/drivers/staging/lustre/lustre/llite/xattr_cache.c +++ b/drivers/staging/lustre/lustre/llite/xattr_cache.c @@ -311,7 +311,7 @@ static int ll_xattr_find_get_lock(struct inode *inode, if (rc < 0) { CDEBUG(D_CACHE, - "md_intent_lock failed with %d for fid "DFID"\n", + "md_intent_lock failed with %d for fid " DFID "\n", rc, PFID(ll_inode2fid(inode))); mutex_unlock(&lli->lli_xattrs_enq_lock); return rc; @@ -365,7 +365,7 @@ static int ll_xattr_cache_refill(struct inode *inode, struct lookup_intent *oit) } if (oit->it_status < 0) { - CDEBUG(D_CACHE, "getxattr intent returned %d for fid "DFID"\n", + CDEBUG(D_CACHE, "getxattr intent returned %d for fid " DFID "\n", oit->it_status, PFID(ll_inode2fid(inode))); rc = oit->it_status; /* xattr data is so large that we don't want to cache it */ diff --git a/drivers/staging/lustre/lustre/lmv/lmv_fld.c b/drivers/staging/lustre/lustre/lmv/lmv_fld.c index a5265f9b5797..6f8070fb3226 100644 --- a/drivers/staging/lustre/lustre/lmv/lmv_fld.c +++ b/drivers/staging/lustre/lustre/lmv/lmv_fld.c @@ -70,7 +70,7 @@ int lmv_fld_lookup(struct lmv_obd *lmv, const struct lu_fid *fid, u32 *mds) return rc; } - CDEBUG(D_INODE, "FLD lookup got mds #%x for fid="DFID"\n", + CDEBUG(D_INODE, "FLD lookup got mds #%x for fid=" DFID "\n", *mds, PFID(fid)); if (*mds >= lmv->desc.ld_tgt_count) { diff --git a/drivers/staging/lustre/lustre/lmv/lmv_intent.c b/drivers/staging/lustre/lustre/lmv/lmv_intent.c index aa42066678e0..f49db6c23217 100644 --- a/drivers/staging/lustre/lustre/lmv/lmv_intent.c +++ b/drivers/staging/lustre/lustre/lmv/lmv_intent.c @@ -213,7 +213,7 @@ int lmv_revalidate_slaves(struct obd_export *exp, lockh = (struct lustre_handle *)&it.it_lock_handle; if (rc > 0 && !req) { /* slave inode is still valid */ - CDEBUG(D_INODE, "slave "DFID" is still valid.\n", + CDEBUG(D_INODE, "slave " DFID " is still valid.\n", PFID(&fid)); rc = 0; } else { @@ -435,7 +435,7 @@ static int lmv_intent_lookup(struct obd_export *exp, if (IS_ERR(tgt)) return PTR_ERR(tgt); - CDEBUG(D_INODE, "Try other stripes " DFID"\n", + CDEBUG(D_INODE, "Try other stripes " DFID "\n", PFID(&oinfo->lmo_fid)); op_data->op_fid1 = oinfo->lmo_fid; @@ -479,7 +479,7 @@ int lmv_intent_lock(struct obd_export *exp, struct md_op_data *op_data, LASSERT(fid_is_sane(&op_data->op_fid1)); - CDEBUG(D_INODE, "INTENT LOCK '%s' for "DFID" '%*s' on "DFID"\n", + CDEBUG(D_INODE, "INTENT LOCK '%s' for " DFID " '%*s' on " DFID "\n", LL_IT2STR(it), PFID(&op_data->op_fid2), (int)op_data->op_namelen, op_data->op_name, PFID(&op_data->op_fid1)); diff --git a/drivers/staging/lustre/lustre/lmv/lmv_obd.c b/drivers/staging/lustre/lustre/lmv/lmv_obd.c index 732595125d8a..64fcaef0bacd 100644 --- a/drivers/staging/lustre/lustre/lmv/lmv_obd.c +++ b/drivers/staging/lustre/lustre/lmv/lmv_obd.c @@ -75,7 +75,7 @@ static void lmv_activate_target(struct lmv_obd *lmv, static int lmv_set_mdc_active(struct lmv_obd *lmv, const struct obd_uuid *uuid, int activate) { - struct lmv_tgt_desc *uninitialized_var(tgt); + struct lmv_tgt_desc *tgt = NULL; struct obd_device *obd; u32 i; int rc = 0; @@ -673,7 +673,7 @@ repeat_fid2path: *ptr = '/'; } - CDEBUG(D_INFO, "%s: get path %s "DFID" rec: %llu ln: %u\n", + CDEBUG(D_INFO, "%s: get path %s " DFID " rec: %llu ln: %u\n", tgt->ltd_exp->exp_obd->obd_name, gf->gf_path, PFID(&gf->gf_fid), gf->gf_recno, gf->gf_linkno); @@ -693,7 +693,7 @@ repeat_fid2path: } if (!fid_is_sane(&gf->gf_fid)) { - CERROR("%s: invalid FID "DFID": rc = %d\n", + CERROR("%s: invalid FID " DFID ": rc = %d\n", tgt->ltd_exp->exp_obd->obd_name, PFID(&gf->gf_fid), -EINVAL); rc = -EINVAL; @@ -1508,7 +1508,7 @@ static int lmv_null_inode(struct obd_export *exp, const struct lu_fid *fid) if (rc) return rc; - CDEBUG(D_INODE, "CBDATA for "DFID"\n", PFID(fid)); + CDEBUG(D_INODE, "CBDATA for " DFID "\n", PFID(fid)); /* * With DNE every object can have two locks in different namespaces: @@ -1540,7 +1540,7 @@ static int lmv_close(struct obd_export *exp, struct md_op_data *op_data, if (IS_ERR(tgt)) return PTR_ERR(tgt); - CDEBUG(D_INODE, "CLOSE "DFID"\n", PFID(&op_data->op_fid1)); + CDEBUG(D_INODE, "CLOSE " DFID "\n", PFID(&op_data->op_fid1)); return md_close(tgt->ltd_exp, op_data, mod, request); } @@ -1672,7 +1672,7 @@ static int lmv_create(struct obd_export *exp, struct md_op_data *op_data, if (IS_ERR(tgt)) return PTR_ERR(tgt); - CDEBUG(D_INODE, "CREATE name '%.*s' on "DFID" -> mds #%x\n", + CDEBUG(D_INODE, "CREATE name '%.*s' on " DFID " -> mds #%x\n", (int)op_data->op_namelen, op_data->op_name, PFID(&op_data->op_fid1), op_data->op_mds); @@ -1694,7 +1694,7 @@ static int lmv_create(struct obd_export *exp, struct md_op_data *op_data, CDEBUG(D_CONFIG, "Server doesn't support striped dirs\n"); } - CDEBUG(D_INODE, "CREATE obj "DFID" -> mds #%x\n", + CDEBUG(D_INODE, "CREATE obj " DFID " -> mds #%x\n", PFID(&op_data->op_fid1), op_data->op_mds); op_data->op_flags |= MF_MDC_CANCEL_FID1; @@ -1704,7 +1704,7 @@ static int lmv_create(struct obd_export *exp, struct md_op_data *op_data, if (rc == 0) { if (!*request) return rc; - CDEBUG(D_INODE, "Created - "DFID"\n", PFID(&op_data->op_fid2)); + CDEBUG(D_INODE, "Created - " DFID "\n", PFID(&op_data->op_fid2)); } return rc; } @@ -1724,7 +1724,7 @@ lmv_enqueue(struct obd_export *exp, struct ldlm_enqueue_info *einfo, if (rc) return rc; - CDEBUG(D_INODE, "ENQUEUE '%s' on "DFID"\n", + CDEBUG(D_INODE, "ENQUEUE '%s' on " DFID "\n", LL_IT2STR(it), PFID(&op_data->op_fid1)); tgt = lmv_locate_mds(lmv, op_data, &op_data->op_fid1); @@ -1769,7 +1769,7 @@ lmv_getattr_name(struct obd_export *exp, struct md_op_data *op_data, if (body->mbo_valid & OBD_MD_MDS) { struct lu_fid rid = body->mbo_fid1; - CDEBUG(D_INODE, "Request attrs for "DFID"\n", + CDEBUG(D_INODE, "Request attrs for " DFID "\n", PFID(&rid)); tgt = lmv_find_target(lmv, &rid); @@ -1818,13 +1818,13 @@ static int lmv_early_cancel(struct obd_export *exp, struct lmv_tgt_desc *tgt, } if (tgt->ltd_idx != op_tgt) { - CDEBUG(D_INODE, "EARLY_CANCEL on "DFID"\n", PFID(fid)); + CDEBUG(D_INODE, "EARLY_CANCEL on " DFID "\n", PFID(fid)); policy.l_inodebits.bits = bits; rc = md_cancel_unused(tgt->ltd_exp, fid, &policy, mode, LCF_ASYNC, NULL); } else { CDEBUG(D_INODE, - "EARLY_CANCEL skip operation target %d on "DFID"\n", + "EARLY_CANCEL skip operation target %d on " DFID "\n", op_tgt, PFID(fid)); op_data->op_flags |= flag; rc = 0; @@ -1851,7 +1851,7 @@ static int lmv_link(struct obd_export *exp, struct md_op_data *op_data, LASSERT(op_data->op_namelen != 0); - CDEBUG(D_INODE, "LINK "DFID":%*s to "DFID"\n", + CDEBUG(D_INODE, "LINK " DFID ":%*s to " DFID "\n", PFID(&op_data->op_fid2), (int)op_data->op_namelen, op_data->op_name, PFID(&op_data->op_fid1)); @@ -1901,7 +1901,7 @@ static int lmv_rename(struct obd_export *exp, struct md_op_data *op_data, LASSERT(oldlen != 0); - CDEBUG(D_INODE, "RENAME %.*s in "DFID":%d to %.*s in "DFID":%d\n", + CDEBUG(D_INODE, "RENAME %.*s in " DFID ":%d to %.*s in " DFID ":%d\n", (int)oldlen, old, PFID(&op_data->op_fid1), op_data->op_mea1 ? op_data->op_mea1->lsm_md_stripe_count : 0, (int)newlen, new, PFID(&op_data->op_fid2), @@ -1916,7 +1916,7 @@ static int lmv_rename(struct obd_export *exp, struct md_op_data *op_data, op_data->op_cap = cfs_curproc_cap_pack(); if (op_data->op_cli_flags & CLI_MIGRATE) { - LASSERTF(fid_is_sane(&op_data->op_fid3), "invalid FID "DFID"\n", + LASSERTF(fid_is_sane(&op_data->op_fid3), "invalid FID " DFID "\n", PFID(&op_data->op_fid3)); if (op_data->op_mea1) { @@ -2069,7 +2069,7 @@ static int lmv_setattr(struct obd_export *exp, struct md_op_data *op_data, if (rc) return rc; - CDEBUG(D_INODE, "SETATTR for "DFID", valid 0x%x\n", + CDEBUG(D_INODE, "SETATTR for " DFID ", valid 0x%x\n", PFID(&op_data->op_fid1), op_data->op_attr.ia_valid); op_data->op_flags |= MF_MDC_CANCEL_FID1; @@ -2274,6 +2274,7 @@ static int lmv_read_striped_page(struct obd_export *exp, struct lu_fid master_fid = op_data->op_fid1; struct obd_device *obd = exp->exp_obd; __u64 hash_offset = offset; + __u32 ldp_flags; struct page *min_ent_page = NULL; struct page *ent_page = NULL; struct lu_dirent *min_ent = NULL; @@ -2301,7 +2302,7 @@ static int lmv_read_striped_page(struct obd_export *exp, dp = kmap(ent_page); memset(dp, 0, sizeof(*dp)); dp->ldp_hash_start = cpu_to_le64(offset); - dp->ldp_flags |= LDF_COLLIDE; + ldp_flags = LDF_COLLIDE; area = dp + 1; left_bytes = PAGE_SIZE - sizeof(*dp); @@ -2379,8 +2380,8 @@ out: ent_page = NULL; } else { if (ent == area) - dp->ldp_flags |= LDF_EMPTY; - dp->ldp_flags = cpu_to_le32(dp->ldp_flags); + ldp_flags |= LDF_EMPTY; + dp->ldp_flags |= cpu_to_le32(ldp_flags); dp->ldp_hash_end = cpu_to_le64(hash_offset); } @@ -2413,9 +2414,8 @@ static int lmv_read_page(struct obd_export *exp, struct md_op_data *op_data, if (rc) return rc; - if (unlikely(lsm)) { + if (unlikely(lsm)) return lmv_read_striped_page(exp, op_data, cb_op, offset, ppage); - } tgt = lmv_find_target(lmv, &op_data->op_fid1); if (IS_ERR(tgt)) @@ -2577,7 +2577,7 @@ try_next_stripe: if (likely(!(body->mbo_valid & OBD_MD_MDS))) return rc; - CDEBUG(D_INODE, "%s: try unlink to another MDT for "DFID"\n", + CDEBUG(D_INODE, "%s: try unlink to another MDT for " DFID "\n", exp->exp_obd->obd_name, PFID(&body->mbo_fid1)); /* This is a remote object, try remote MDT, Note: it may @@ -2781,7 +2781,7 @@ static int lmv_unpack_md_v1(struct obd_export *exp, struct lmv_stripe_md *lsm, &lsm->lsm_md_oinfo[i].lmo_mds); if (rc) return rc; - CDEBUG(D_INFO, "unpack fid #%d "DFID"\n", i, + CDEBUG(D_INFO, "unpack fid #%d " DFID "\n", i, PFID(&lsm->lsm_md_oinfo[i].lmo_fid)); } @@ -2925,7 +2925,7 @@ static enum ldlm_mode lmv_lock_match(struct obd_export *exp, __u64 flags, int tgt; u32 i; - CDEBUG(D_INODE, "Lock match for "DFID"\n", PFID(fid)); + CDEBUG(D_INODE, "Lock match for " DFID "\n", PFID(fid)); /* * With DNE every object can have two locks in different namespaces: @@ -2937,7 +2937,7 @@ static enum ldlm_mode lmv_lock_match(struct obd_export *exp, __u64 flags, i < lmv->desc.ld_tgt_count; i++, tgt = (tgt + 1) % lmv->desc.ld_tgt_count) { if (tgt < 0) { - CDEBUG(D_HA, "%s: "DFID" is inaccessible: rc = %d\n", + CDEBUG(D_HA, "%s: " DFID " is inaccessible: rc = %d\n", obd->obd_name, PFID(fid), tgt); tgt = 0; } @@ -3107,9 +3107,8 @@ static int lmv_quotactl(struct obd_device *unused, struct obd_export *exp, return -EIO; } - if (oqctl->qc_cmd != Q_GETOQUOTA) { + if (oqctl->qc_cmd != Q_GETOQUOTA) return obd_quotactl(tgt->ltd_exp, oqctl); - } for (i = 0; i < lmv->desc.ld_tgt_count; i++) { int err; @@ -3149,7 +3148,7 @@ static int lmv_merge_attr(struct obd_export *exp, for (i = 0; i < lsm->lsm_md_stripe_count; i++) { struct inode *inode = lsm->lsm_md_oinfo[i].lmo_root; - CDEBUG(D_INFO, ""DFID" size %llu, blocks %llu nlink %u, atime %lu ctime %lu, mtime %lu.\n", + CDEBUG(D_INFO, "" DFID " size %llu, blocks %llu nlink %u, atime %lu ctime %lu, mtime %lu.\n", PFID(&lsm->lsm_md_oinfo[i].lmo_fid), i_size_read(inode), (unsigned long long)inode->i_blocks, inode->i_nlink, LTIME_S(inode->i_atime), diff --git a/drivers/staging/lustre/lustre/lov/lov_io.c b/drivers/staging/lustre/lustre/lov/lov_io.c index df77b2586612..babf39adef85 100644 --- a/drivers/staging/lustre/lustre/lov/lov_io.c +++ b/drivers/staging/lustre/lustre/lov/lov_io.c @@ -1021,7 +1021,7 @@ int lov_io_init_empty(const struct lu_env *env, struct cl_object *obj, break; case CIT_FAULT: result = -EFAULT; - CERROR("Page fault on a file without stripes: "DFID"\n", + CERROR("Page fault on a file without stripes: " DFID "\n", PFID(lu_object_fid(&obj->co_lu))); break; } diff --git a/drivers/staging/lustre/lustre/lov/lov_merge.c b/drivers/staging/lustre/lustre/lov/lov_merge.c index 391dfd207177..034b4fcb38f5 100644 --- a/drivers/staging/lustre/lustre/lov/lov_merge.c +++ b/drivers/staging/lustre/lustre/lov/lov_merge.c @@ -57,7 +57,7 @@ int lov_merge_lvb_kms(struct lov_stripe_md *lsm, assert_spin_locked(&lsm->lsm_lock); LASSERT(lsm->lsm_lock_owner == current_pid()); - CDEBUG(D_INODE, "MDT ID "DOSTID" initial value: s=%llu m=%llu a=%llu c=%llu b=%llu\n", + CDEBUG(D_INODE, "MDT ID " DOSTID " initial value: s=%llu m=%llu a=%llu c=%llu b=%llu\n", POSTID(&lsm->lsm_oi), lvb->lvb_size, lvb->lvb_mtime, lvb->lvb_atime, lvb->lvb_ctime, lvb->lvb_blocks); for (i = 0; i < lsm->lsm_stripe_count; i++) { @@ -89,7 +89,7 @@ int lov_merge_lvb_kms(struct lov_stripe_md *lsm, if (loi->loi_lvb.lvb_ctime > current_ctime) current_ctime = loi->loi_lvb.lvb_ctime; - CDEBUG(D_INODE, "MDT ID "DOSTID" on OST[%u]: s=%llu m=%llu a=%llu c=%llu b=%llu\n", + CDEBUG(D_INODE, "MDT ID " DOSTID " on OST[%u]: s=%llu m=%llu a=%llu c=%llu b=%llu\n", POSTID(&lsm->lsm_oi), loi->loi_ost_idx, loi->loi_lvb.lvb_size, loi->loi_lvb.lvb_mtime, loi->loi_lvb.lvb_atime, loi->loi_lvb.lvb_ctime, diff --git a/drivers/staging/lustre/lustre/lov/lov_object.c b/drivers/staging/lustre/lustre/lov/lov_object.c index eddabbe31e5c..14f38268d414 100644 --- a/drivers/staging/lustre/lustre/lov/lov_object.c +++ b/drivers/staging/lustre/lustre/lov/lov_object.c @@ -153,8 +153,7 @@ static int lov_init_sub(const struct lu_env *env, struct lov_object *lov, subhdr = cl_object_header(stripe); oinfo = lov->lo_lsm->lsm_oinfo[idx]; - CDEBUG(D_INODE, DFID"@%p[%d] -> "DFID"@%p: ostid: "DOSTID - " idx: %d gen: %d\n", + CDEBUG(D_INODE, DFID "@%p[%d] -> " DFID "@%p: ostid: " DOSTID " idx: %d gen: %d\n", PFID(&subhdr->coh_lu.loh_fid), subhdr, idx, PFID(&hdr->coh_lu.loh_fid), hdr, POSTID(&oinfo->loi_oi), oinfo->loi_ost_idx, oinfo->loi_ost_gen); @@ -757,7 +756,7 @@ static int lov_layout_change(const struct lu_env *unused, LASSERT(0 <= llt && llt < ARRAY_SIZE(lov_dispatch)); - CDEBUG(D_INODE, DFID" from %s to %s\n", + CDEBUG(D_INODE, DFID " from %s to %s\n", PFID(lu_object_fid(lov2lu(lov))), llt2str(lov->lo_type), llt2str(llt)); @@ -904,7 +903,7 @@ static int lov_conf_set(const struct lu_env *env, struct cl_object *obj, out: lov_conf_unlock(lov); lov_lsm_put(lsm); - CDEBUG(D_INODE, DFID" lo_layout_invalid=%d\n", + CDEBUG(D_INODE, DFID " lo_layout_invalid=%d\n", PFID(lu_object_fid(lov2lu(lov))), lov->lo_layout_invalid); return result; } diff --git a/drivers/staging/lustre/lustre/lov/lov_pack.c b/drivers/staging/lustre/lustre/lov/lov_pack.c index e6727cefde05..638b7646ca2c 100644 --- a/drivers/staging/lustre/lustre/lov/lov_pack.c +++ b/drivers/staging/lustre/lustre/lov/lov_pack.c @@ -56,7 +56,7 @@ void lov_dump_lmm_common(int level, void *lmmp) struct ost_id oi; lmm_oi_le_to_cpu(&oi, &lmm->lmm_oi); - CDEBUG(level, "objid "DOSTID", magic 0x%08x, pattern %#x\n", + CDEBUG(level, "objid " DOSTID ", magic 0x%08x, pattern %#x\n", POSTID(&oi), le32_to_cpu(lmm->lmm_magic), le32_to_cpu(lmm->lmm_pattern)); CDEBUG(level, "stripe_size %u, stripe_count %u, layout_gen %u\n", @@ -80,7 +80,7 @@ static void lov_dump_lmm_objects(int level, struct lov_ost_data *lod, struct ost_id oi; ostid_le_to_cpu(&lod->l_ost_oi, &oi); - CDEBUG(level, "stripe %u idx %u subobj "DOSTID"\n", i, + CDEBUG(level, "stripe %u idx %u subobj " DOSTID "\n", i, le32_to_cpu(lod->l_ost_idx), POSTID(&oi)); } } @@ -95,7 +95,7 @@ void lov_dump_lmm_v1(int level, struct lov_mds_md_v1 *lmm) void lov_dump_lmm_v3(int level, struct lov_mds_md_v3 *lmm) { lov_dump_lmm_common(level, lmm); - CDEBUG(level, "pool_name "LOV_POOLNAMEF"\n", lmm->lmm_pool_name); + CDEBUG(level, "pool_name " LOV_POOLNAMEF "\n", lmm->lmm_pool_name); lov_dump_lmm_objects(level, lmm->lmm_objects, le16_to_cpu(lmm->lmm_stripe_count)); } diff --git a/drivers/staging/lustre/lustre/lov/lov_pool.c b/drivers/staging/lustre/lustre/lov/lov_pool.c index 7daa8671fdc3..39daa17e0736 100644 --- a/drivers/staging/lustre/lustre/lov/lov_pool.c +++ b/drivers/staging/lustre/lustre/lov/lov_pool.c @@ -286,7 +286,7 @@ static int pool_proc_open(struct inode *inode, struct file *file) return rc; } -static struct file_operations pool_proc_operations = { +static const struct file_operations pool_proc_operations = { .open = pool_proc_open, .read = seq_read, .llseek = seq_lseek, @@ -429,7 +429,7 @@ int lov_pool_new(struct obd_device *obd, char *poolname) poolname, new_pool, &pool_proc_operations); if (IS_ERR_OR_NULL(new_pool->pool_debugfs_entry)) { - CWARN("Cannot add debugfs pool entry "LOV_POOLNAMEF"\n", + CWARN("Cannot add debugfs pool entry " LOV_POOLNAMEF "\n", poolname); new_pool->pool_debugfs_entry = NULL; lov_pool_putref(new_pool); @@ -450,7 +450,7 @@ int lov_pool_new(struct obd_device *obd, char *poolname) goto out_err; } - CDEBUG(D_CONFIG, LOV_POOLNAMEF" is pool #%d\n", + CDEBUG(D_CONFIG, LOV_POOLNAMEF " is pool #%d\n", poolname, lov->lov_pool_count); return 0; @@ -531,7 +531,7 @@ int lov_pool_add(struct obd_device *obd, char *poolname, char *ostname) if (rc) goto out; - CDEBUG(D_CONFIG, "Added %s to "LOV_POOLNAMEF" as member %d\n", + CDEBUG(D_CONFIG, "Added %s to " LOV_POOLNAMEF " as member %d\n", ostname, poolname, pool_tgt_count(pool)); out: @@ -575,7 +575,7 @@ int lov_pool_remove(struct obd_device *obd, char *poolname, char *ostname) lov_ost_pool_remove(&pool->pool_obds, lov_idx); - CDEBUG(D_CONFIG, "%s removed from "LOV_POOLNAMEF"\n", ostname, + CDEBUG(D_CONFIG, "%s removed from " LOV_POOLNAMEF "\n", ostname, poolname); out: diff --git a/drivers/staging/lustre/lustre/mdc/mdc_locks.c b/drivers/staging/lustre/lustre/mdc/mdc_locks.c index 392b0e38a91e..3eb66cea65db 100644 --- a/drivers/staging/lustre/lustre/mdc/mdc_locks.c +++ b/drivers/staging/lustre/lustre/mdc/mdc_locks.c @@ -830,7 +830,7 @@ resend: ptlrpc_req_finished(req); resends++; - CDEBUG(D_HA, "%s: resend:%d op:%d "DFID"/"DFID"\n", + CDEBUG(D_HA, "%s: resend:%d op:%d " DFID "/" DFID "\n", obddev->obd_name, resends, it->it_op, PFID(&op_data->op_fid1), PFID(&op_data->op_fid2)); @@ -911,13 +911,13 @@ static int mdc_finish_intent_lock(struct obd_export *exp, OBD_FAIL_TIMEOUT(OBD_FAIL_MDC_ENQUEUE_PAUSE, obd_timeout); } - if (it->it_op & IT_CREAT) { + if (it->it_op & IT_CREAT) /* XXX this belongs in ll_create_it */ - } else if (it->it_op == IT_OPEN) { + ; + else if (it->it_op == IT_OPEN) LASSERT(!it_disposition(it, DISP_OPEN_CREATE)); - } else { + else LASSERT(it->it_op & (IT_GETATTR | IT_LOOKUP | IT_LAYOUT)); - } /* If we already have a matching lock, then cancel the new * one. We have to set the data here instead of in @@ -933,7 +933,7 @@ static int mdc_finish_intent_lock(struct obd_export *exp, LASSERTF(fid_res_name_eq(&mdt_body->mbo_fid1, &lock->l_resource->lr_name), - "Lock res_id: "DLDLMRES", fid: "DFID"\n", + "Lock res_id: " DLDLMRES ", fid: " DFID "\n", PLDLMRES(lock->l_resource), PFID(&mdt_body->mbo_fid1)); LDLM_LOCK_PUT(lock); @@ -1063,7 +1063,7 @@ int mdc_intent_lock(struct obd_export *exp, struct md_op_data *op_data, LASSERT(it); - CDEBUG(D_DLMTRACE, "(name: %.*s,"DFID") in obj "DFID + CDEBUG(D_DLMTRACE, "(name: %.*s," DFID ") in obj " DFID ", intent: %s flags %#Lo\n", (int)op_data->op_namelen, op_data->op_name, PFID(&op_data->op_fid2), PFID(&op_data->op_fid1), ldlm_it2str(it->it_op), diff --git a/drivers/staging/lustre/lustre/mdc/mdc_reint.c b/drivers/staging/lustre/lustre/mdc/mdc_reint.c index 07b168490f09..2287bd46d527 100644 --- a/drivers/staging/lustre/lustre/mdc/mdc_reint.c +++ b/drivers/staging/lustre/lustre/mdc/mdc_reint.c @@ -227,7 +227,7 @@ rebuild: ptlrpc_req_finished(req); resends++; - CDEBUG(D_HA, "%s: resend:%d create on "DFID"/"DFID"\n", + CDEBUG(D_HA, "%s: resend:%d create on " DFID "/" DFID "\n", exp->exp_obd->obd_name, resends, PFID(&op_data->op_fid1), PFID(&op_data->op_fid2)); diff --git a/drivers/staging/lustre/lustre/mdc/mdc_request.c b/drivers/staging/lustre/lustre/mdc/mdc_request.c index 6bc2fb858680..1a3fa1bb7f25 100644 --- a/drivers/staging/lustre/lustre/mdc/mdc_request.c +++ b/drivers/staging/lustre/lustre/mdc/mdc_request.c @@ -105,7 +105,7 @@ static int mdc_getstatus(struct obd_export *exp, struct lu_fid *rootfid) *rootfid = body->mbo_fid1; CDEBUG(D_NET, - "root fid="DFID", last_committed=%llu\n", + "root fid=" DFID ", last_committed=%llu\n", PFID(rootfid), lustre_msg_get_last_committed(req->rq_repmsg)); out: @@ -713,7 +713,7 @@ static int mdc_close(struct obd_export *exp, struct md_op_data *op_data, /* allocate a FID for volatile file */ rc = mdc_fid_alloc(NULL, exp, &op_data->op_fid2, op_data); if (rc < 0) { - CERROR("%s: "DFID" failed to allocate FID: %d\n", + CERROR("%s: " DFID " failed to allocate FID: %d\n", obd->obd_name, PFID(&op_data->op_fid1), rc); /* save the errcode and proceed to close */ saved_rc = rc; @@ -753,7 +753,7 @@ static int mdc_close(struct obd_export *exp, struct md_op_data *op_data, /* * TODO: repeat close after errors */ - CWARN("%s: close of FID "DFID" failed, file reference will be dropped when this client unmounts or is evicted\n", + CWARN("%s: close of FID " DFID " failed, file reference will be dropped when this client unmounts or is evicted\n", obd->obd_name, PFID(&op_data->op_fid1)); rc = -ENOMEM; goto out; @@ -1254,7 +1254,7 @@ static int mdc_read_page(struct obd_export *exp, struct md_op_data *op_data, ptlrpc_req_finished(enq_req); if (rc < 0) { - CERROR("%s: "DFID" lock enqueue fails: rc = %d\n", + CERROR("%s: " DFID " lock enqueue fails: rc = %d\n", exp->exp_obd->obd_name, PFID(&op_data->op_fid1), rc); return rc; } @@ -1298,7 +1298,7 @@ static int mdc_read_page(struct obd_export *exp, struct md_op_data *op_data, rp_param.rp_hash64), mdc_read_page_remote, &rp_param); if (IS_ERR(page)) { - CERROR("%s: read cache page: "DFID" at %llu: rc %ld\n", + CERROR("%s: read cache page: " DFID " at %llu: rc %ld\n", exp->exp_obd->obd_name, PFID(&op_data->op_fid1), rp_param.rp_off, PTR_ERR(page)); rc = PTR_ERR(page); @@ -1308,7 +1308,7 @@ static int mdc_read_page(struct obd_export *exp, struct md_op_data *op_data, wait_on_page_locked(page); (void)kmap(page); if (!PageUptodate(page)) { - CERROR("%s: page not updated: "DFID" at %llu: rc %d\n", + CERROR("%s: page not updated: " DFID " at %llu: rc %d\n", exp->exp_obd->obd_name, PFID(&op_data->op_fid1), rp_param.rp_off, -5); goto fail; @@ -1316,7 +1316,7 @@ static int mdc_read_page(struct obd_export *exp, struct md_op_data *op_data, if (!PageChecked(page)) SetPageChecked(page); if (PageError(page)) { - CERROR("%s: page error: "DFID" at %llu: rc %d\n", + CERROR("%s: page error: " DFID " at %llu: rc %d\n", exp->exp_obd->obd_name, PFID(&op_data->op_fid1), rp_param.rp_off, -5); goto fail; @@ -1436,7 +1436,7 @@ static int mdc_ioc_fid2path(struct obd_export *exp, struct getinfo_fid2path *gf) memcpy(key, KEY_FID2PATH, sizeof(KEY_FID2PATH)); memcpy(key + cfs_size_round(sizeof(KEY_FID2PATH)), gf, sizeof(*gf)); - CDEBUG(D_IOCTL, "path get "DFID" from %llu #%d\n", + CDEBUG(D_IOCTL, "path get " DFID " from %llu #%d\n", PFID(&gf->gf_fid), gf->gf_recno, gf->gf_linkno); if (!fid_is_sane(&gf->gf_fid)) { diff --git a/drivers/staging/lustre/lustre/mgc/mgc_request.c b/drivers/staging/lustre/lustre/mgc/mgc_request.c index 6a76605b3c3d..eee0b667a33c 100644 --- a/drivers/staging/lustre/lustre/mgc/mgc_request.c +++ b/drivers/staging/lustre/lustre/mgc/mgc_request.c @@ -800,7 +800,7 @@ static int mgc_blocking_ast(struct ldlm_lock *lock, struct ldlm_lock_desc *desc, /* We've given up the lock, prepare ourselves to update. */ LDLM_DEBUG(lock, "MGC cancel CB"); - CDEBUG(D_MGC, "Lock res "DLDLMRES" (%.8s)\n", + CDEBUG(D_MGC, "Lock res " DLDLMRES " (%.8s)\n", PLDLMRES(lock->l_resource), (char *)&lock->l_resource->lr_name.name[0]); diff --git a/drivers/staging/lustre/lustre/obdclass/cl_lock.c b/drivers/staging/lustre/lustre/obdclass/cl_lock.c index 9d7b5939b0fd..a343e3ab2257 100644 --- a/drivers/staging/lustre/lustre/obdclass/cl_lock.c +++ b/drivers/staging/lustre/lustre/obdclass/cl_lock.c @@ -246,7 +246,7 @@ void cl_lock_descr_print(const struct lu_env *env, void *cookie, const struct lu_fid *fid; fid = lu_object_fid(&descr->cld_obj->co_lu); - (*printer)(env, cookie, DDESCR"@"DFID, PDESCR(descr), PFID(fid)); + (*printer)(env, cookie, DDESCR "@" DFID, PDESCR(descr), PFID(fid)); } EXPORT_SYMBOL(cl_lock_descr_print); diff --git a/drivers/staging/lustre/lustre/obdclass/cl_page.c b/drivers/staging/lustre/lustre/obdclass/cl_page.c index 71fcc4cc9e72..6b8c41b6f379 100644 --- a/drivers/staging/lustre/lustre/obdclass/cl_page.c +++ b/drivers/staging/lustre/lustre/obdclass/cl_page.c @@ -193,7 +193,7 @@ struct cl_page *cl_page_find(const struct lu_env *env, hdr = cl_object_header(o); - CDEBUG(D_PAGE, "%lu@"DFID" %p %lx %d\n", + CDEBUG(D_PAGE, "%lu@" DFID " %p %lx %d\n", idx, PFID(&hdr->coh_lu.loh_fid), vmpage, vmpage->private, type); /* fast path. */ if (type == CPT_CACHEABLE) { diff --git a/drivers/staging/lustre/lustre/obdclass/llog_cat.c b/drivers/staging/lustre/lustre/obdclass/llog_cat.c index ce8e2f6f002a..8f1533c127a8 100644 --- a/drivers/staging/lustre/lustre/obdclass/llog_cat.c +++ b/drivers/staging/lustre/lustre/obdclass/llog_cat.c @@ -78,7 +78,7 @@ static int llog_cat_id2handle(const struct lu_env *env, if (ostid_id(&cgl->lgl_oi) == ostid_id(&logid->lgl_oi) && ostid_seq(&cgl->lgl_oi) == ostid_seq(&logid->lgl_oi)) { if (cgl->lgl_ogen != logid->lgl_ogen) { - CERROR("%s: log "DOSTID" generation %x != %x\n", + CERROR("%s: log " DOSTID " generation %x != %x\n", loghandle->lgh_ctxt->loc_obd->obd_name, POSTID(&logid->lgl_oi), cgl->lgl_ogen, logid->lgl_ogen); @@ -95,7 +95,7 @@ static int llog_cat_id2handle(const struct lu_env *env, rc = llog_open(env, cathandle->lgh_ctxt, &loghandle, logid, NULL, LLOG_OPEN_EXISTS); if (rc < 0) { - CERROR("%s: error opening log id "DOSTID":%x: rc = %d\n", + CERROR("%s: error opening log id " DOSTID ":%x: rc = %d\n", cathandle->lgh_ctxt->loc_obd->obd_name, POSTID(&logid->lgl_oi), logid->lgl_ogen, rc); return rc; @@ -152,13 +152,13 @@ static int llog_cat_process_cb(const struct lu_env *env, CERROR("invalid record in catalog\n"); return -EINVAL; } - CDEBUG(D_HA, "processing log "DOSTID":%x at index %u of catalog " - DOSTID"\n", POSTID(&lir->lid_id.lgl_oi), lir->lid_id.lgl_ogen, + CDEBUG(D_HA, "processing log " DOSTID ":%x at index %u of catalog " + DOSTID "\n", POSTID(&lir->lid_id.lgl_oi), lir->lid_id.lgl_ogen, rec->lrh_index, POSTID(&cat_llh->lgh_id.lgl_oi)); rc = llog_cat_id2handle(env, cat_llh, &llh, &lir->lid_id); if (rc) { - CERROR("%s: cannot find handle for llog "DOSTID": %d\n", + CERROR("%s: cannot find handle for llog " DOSTID ": %d\n", cat_llh->lgh_ctxt->loc_obd->obd_name, POSTID(&lir->lid_id.lgl_oi), rc); return rc; @@ -204,7 +204,7 @@ static int llog_cat_process_or_fork(const struct lu_env *env, if (llh->llh_cat_idx > cat_llh->lgh_last_idx) { struct llog_process_cat_data cd; - CWARN("catlog "DOSTID" crosses index zero\n", + CWARN("catlog " DOSTID " crosses index zero\n", POSTID(&cat_llh->lgh_id.lgl_oi)); cd.lpcd_first_idx = llh->llh_cat_idx; diff --git a/drivers/staging/lustre/lustre/obdclass/llog_swab.c b/drivers/staging/lustre/lustre/obdclass/llog_swab.c index 723c212c6747..016046d26010 100644 --- a/drivers/staging/lustre/lustre/obdclass/llog_swab.c +++ b/drivers/staging/lustre/lustre/obdclass/llog_swab.c @@ -44,7 +44,7 @@ static void print_llogd_body(struct llogd_body *d) { CDEBUG(D_OTHER, "llogd body: %p\n", d); - CDEBUG(D_OTHER, "\tlgd_logid.lgl_oi: "DOSTID"\n", + CDEBUG(D_OTHER, "\tlgd_logid.lgl_oi: " DOSTID "\n", POSTID(&d->lgd_logid.lgl_oi)); CDEBUG(D_OTHER, "\tlgd_logid.lgl_ogen: %#x\n", d->lgd_logid.lgl_ogen); CDEBUG(D_OTHER, "\tlgd_ctxt_idx: %#x\n", d->lgd_ctxt_idx); diff --git a/drivers/staging/lustre/lustre/obdclass/lprocfs_status.c b/drivers/staging/lustre/lustre/obdclass/lprocfs_status.c index 1ec6e3767d81..bc19f19d38d9 100644 --- a/drivers/staging/lustre/lustre/obdclass/lprocfs_status.c +++ b/drivers/staging/lustre/lustre/obdclass/lprocfs_status.c @@ -301,7 +301,7 @@ EXPORT_SYMBOL(lprocfs_seq_release); struct dentry *ldebugfs_add_simple(struct dentry *root, char *name, void *data, - struct file_operations *fops) + const struct file_operations *fops) { struct dentry *entry; umode_t mode = 0; @@ -389,40 +389,6 @@ out: EXPORT_SYMBOL_GPL(ldebugfs_register); /* Generic callbacks */ -int lprocfs_rd_uint(struct seq_file *m, void *data) -{ - seq_printf(m, "%u\n", *(unsigned int *)data); - return 0; -} -EXPORT_SYMBOL(lprocfs_rd_uint); - -int lprocfs_wr_uint(struct file *file, const char __user *buffer, - unsigned long count, void *data) -{ - unsigned *p = data; - char dummy[MAX_STRING_SIZE + 1], *end; - unsigned long tmp; - - if (count >= sizeof(dummy)) - return -EINVAL; - - if (count == 0) - return 0; - - if (copy_from_user(dummy, buffer, count)) - return -EFAULT; - - dummy[count] = '\0'; - - tmp = simple_strtoul(dummy, &end, 0); - if (dummy == end) - return -EINVAL; - - *p = (unsigned int)tmp; - return count; -} -EXPORT_SYMBOL(lprocfs_wr_uint); - static ssize_t uuid_show(struct kobject *kobj, struct attribute *attr, char *buf) { @@ -736,7 +702,7 @@ static int obd_import_flags2str(struct obd_import *imp, struct seq_file *m) bool first = true; if (imp->imp_obd->obd_no_recov) { - seq_printf(m, "no_recov"); + seq_puts(m, "no_recov"); first = false; } @@ -802,15 +768,15 @@ int lprocfs_rd_import(struct seq_file *m, void *data) imp->imp_connect_data.ocd_instance); obd_connect_seq_flags2str(m, imp->imp_connect_data.ocd_connect_flags, ", "); - seq_printf(m, " ]\n"); + seq_puts(m, " ]\n"); obd_connect_data_seqprint(m, ocd); - seq_printf(m, " import_flags: [ "); + seq_puts(m, " import_flags: [ "); obd_import_flags2str(imp, m); - seq_printf(m, - " ]\n" - " connection:\n" - " failover_nids: [ "); + seq_puts(m, + " ]\n" + " connection:\n" + " failover_nids: [ "); spin_lock(&imp->imp_lock); j = 0; list_for_each_entry(conn, &imp->imp_conn_list, oic_item) { @@ -943,7 +909,7 @@ int lprocfs_rd_state(struct seq_file *m, void *data) seq_printf(m, "current_state: %s\n", ptlrpc_import_state_name(imp->imp_state)); - seq_printf(m, "state_history:\n"); + seq_puts(m, "state_history:\n"); k = imp->imp_state_hist_idx; for (j = 0; j < IMP_STATE_HIST_LEN; j++) { struct import_state_hist *ish = @@ -965,7 +931,7 @@ int lprocfs_at_hist_helper(struct seq_file *m, struct adaptive_timeout *at) for (i = 0; i < AT_BINS; i++) seq_printf(m, "%3u ", at->at_hist[i]); - seq_printf(m, "\n"); + seq_puts(m, "\n"); return 0; } EXPORT_SYMBOL(lprocfs_at_hist_helper); @@ -1033,7 +999,7 @@ int lprocfs_rd_connect_flags(struct seq_file *m, void *data) flags = obd->u.cli.cl_import->imp_connect_data.ocd_connect_flags; seq_printf(m, "flags=%#llx\n", flags); obd_connect_seq_flags2str(m, flags, "\n"); - seq_printf(m, "\n"); + seq_puts(m, "\n"); up_read(&obd->u.cli.cl_sem); return 0; } diff --git a/drivers/staging/lustre/lustre/obdclass/lu_object.c b/drivers/staging/lustre/lustre/obdclass/lu_object.c index 76ae600ae2c8..bb9d514525ce 100644 --- a/drivers/staging/lustre/lustre/obdclass/lu_object.c +++ b/drivers/staging/lustre/lustre/obdclass/lu_object.c @@ -512,7 +512,7 @@ void lu_object_header_print(const struct lu_env *env, void *cookie, lu_printer_t printer, const struct lu_object_header *hdr) { - (*printer)(env, cookie, "header@%p[%#lx, %d, "DFID"%s%s%s]", + (*printer)(env, cookie, "header@%p[%#lx, %d, " DFID "%s%s%s]", hdr, hdr->loh_flags, atomic_read(&hdr->loh_ref), PFID(&hdr->loh_fid), hlist_unhashed(&hdr->loh_hash) ? "" : " hash", @@ -918,9 +918,8 @@ static unsigned long lu_htable_order(struct lu_device *top) cache_size = cache_size / 100 * lu_cache_percent * (PAGE_SIZE / 1024); - for (bits = 1; (1 << bits) < cache_size; ++bits) { + for (bits = 1; (1 << bits) < cache_size; ++bits) ; - } return clamp_t(typeof(bits), bits, LU_SITE_BITS_MIN, bits_max); } diff --git a/drivers/staging/lustre/lustre/obdecho/echo_client.c b/drivers/staging/lustre/lustre/obdecho/echo_client.c index 77b4c5504689..1c4a8fe87dd8 100644 --- a/drivers/staging/lustre/lustre/obdecho/echo_client.c +++ b/drivers/staging/lustre/lustre/obdecho/echo_client.c @@ -277,7 +277,7 @@ static int echo_page_print(const struct lu_env *env, { struct echo_page *ep = cl2echo_page(slice); - (*printer)(env, cookie, LUSTRE_ECHO_CLIENT_NAME"-page@%p %d vm@%p\n", + (*printer)(env, cookie, LUSTRE_ECHO_CLIENT_NAME "-page@%p %d vm@%p\n", ep, mutex_is_locked(&ep->ep_lock), slice->cpl_page->cp_vmpage); return 0; @@ -1121,7 +1121,7 @@ static int echo_create_object(const struct lu_env *env, struct echo_device *ed, } cl_echo_object_put(eco); - CDEBUG(D_INFO, "oa oid "DOSTID"\n", POSTID(&oa->o_oi)); + CDEBUG(D_INFO, "oa oid " DOSTID "\n", POSTID(&oa->o_oi)); failed: if (created && rc) @@ -1646,9 +1646,8 @@ static int echo_client_connect(const struct lu_env *env, struct lustre_handle conn = { 0 }; rc = class_connect(&conn, src, cluuid); - if (rc == 0) { + if (rc == 0) *exp = class_conn2export(&conn); - } return rc; } diff --git a/drivers/staging/lustre/lustre/osc/osc_cache.c b/drivers/staging/lustre/lustre/osc/osc_cache.c index c5ccf568313a..d8a95f8fe1ff 100644 --- a/drivers/staging/lustre/lustre/osc/osc_cache.c +++ b/drivers/staging/lustre/lustre/osc/osc_cache.c @@ -472,7 +472,7 @@ static void osc_extent_insert(struct osc_object *obj, struct osc_extent *ext) else if (ext->oe_start > tmp->oe_end) n = &(*n)->rb_right; else - EASSERTF(0, tmp, EXTSTR"\n", EXTPARA(ext)); + EASSERTF(0, tmp, EXTSTR "\n", EXTPARA(ext)); } rb_link_node(&ext->oe_node, parent, n); rb_insert_color(&ext->oe_node, &obj->oo_root); @@ -690,7 +690,7 @@ static struct osc_extent *osc_extent_find(const struct lu_env *env, /* grants has been allocated by caller */ LASSERTF(*grants >= chunksize + cli->cl_extent_tax, "%u/%u/%u.\n", *grants, chunksize, cli->cl_extent_tax); - LASSERTF((max_end - cur->oe_start) < max_pages, EXTSTR"\n", + LASSERTF((max_end - cur->oe_start) < max_pages, EXTSTR "\n", EXTPARA(cur)); restart: @@ -709,7 +709,7 @@ restart: /* if covering by different locks, no chance to match */ if (olck->ols_dlmlock != ext->oe_dlmlock) { EASSERTF(!overlapped(ext, cur), ext, - EXTSTR"\n", EXTPARA(cur)); + EXTSTR "\n", EXTPARA(cur)); ext = next_extent(ext); continue; @@ -732,7 +732,7 @@ restart: */ EASSERTF((ext->oe_start <= cur->oe_start && ext->oe_end >= cur->oe_end), - ext, EXTSTR"\n", EXTPARA(cur)); + ext, EXTSTR "\n", EXTPARA(cur)); if (ext->oe_state > OES_CACHE || ext->oe_fsync_wait) { /* for simplicity, we wait for this extent to @@ -1406,9 +1406,8 @@ static void osc_release_write_grant(struct client_obd *cli, struct brw_page *pga) { assert_spin_locked(&cli->cl_loi_list_lock); - if (!(pga->flag & OBD_BRW_FROM_GRANT)) { + if (!(pga->flag & OBD_BRW_FROM_GRANT)) return; - } pga->flag &= ~OBD_BRW_FROM_GRANT; atomic_long_dec(&obd_dirty_pages); @@ -1890,10 +1889,10 @@ struct extent_rpc_data { unsigned int erd_max_chunks; }; -static inline unsigned osc_extent_chunks(const struct osc_extent *ext) +static inline unsigned int osc_extent_chunks(const struct osc_extent *ext) { struct client_obd *cli = osc_cli(ext->oe_obj); - unsigned ppc_bits = cli->cl_chunkbits - PAGE_SHIFT; + unsigned int ppc_bits = cli->cl_chunkbits - PAGE_SHIFT; return (ext->oe_end >> ppc_bits) - (ext->oe_start >> ppc_bits) + 1; } @@ -1951,7 +1950,7 @@ static int try_to_add_extent_for_io(struct client_obd *cli, return 1; } -static inline unsigned osc_max_write_chunks(const struct client_obd *cli) +static inline unsigned int osc_max_write_chunks(const struct client_obd *cli) { /* * LU-8135: diff --git a/drivers/staging/lustre/lustre/osc/osc_internal.h b/drivers/staging/lustre/lustre/osc/osc_internal.h index 845e795d8795..13a40f6423ff 100644 --- a/drivers/staging/lustre/lustre/osc/osc_internal.h +++ b/drivers/staging/lustre/lustre/osc/osc_internal.h @@ -62,7 +62,7 @@ struct osc_async_page { struct list_head oap_rpc_item; u64 oap_obj_off; - unsigned oap_page_off; + unsigned int oap_page_off; enum async_flags oap_async_flags; struct brw_page oap_brw_page; diff --git a/drivers/staging/lustre/lustre/osc/osc_request.c b/drivers/staging/lustre/lustre/osc/osc_request.c index d8aa3fb468c7..922d0cbe83dc 100644 --- a/drivers/staging/lustre/lustre/osc/osc_request.c +++ b/drivers/staging/lustre/lustre/osc/osc_request.c @@ -1227,8 +1227,7 @@ static int check_write_checksum(struct obdo *oa, msg = "changed in transit AND doesn't match the original - likely false positive due to mmap IO (bug 11742)" ; - LCONSOLE_ERROR_MSG(0x132, "BAD WRITE CHECKSUM: %s: from %s inode "DFID - " object "DOSTID" extent [%llu-%llu]\n", + LCONSOLE_ERROR_MSG(0x132, "BAD WRITE CHECKSUM: %s: from %s inode " DFID " object " DOSTID " extent [%llu-%llu]\n", msg, libcfs_nid2str(peer->nid), oa->o_valid & OBD_MD_FLFID ? oa->o_parent_seq : (__u64)0, oa->o_valid & OBD_MD_FLFID ? oa->o_parent_oid : 0, diff --git a/drivers/staging/lustre/lustre/ptlrpc/client.c b/drivers/staging/lustre/lustre/ptlrpc/client.c index 6466974a43e7..1c7779215eed 100644 --- a/drivers/staging/lustre/lustre/ptlrpc/client.c +++ b/drivers/staging/lustre/lustre/ptlrpc/client.c @@ -367,8 +367,8 @@ void ptlrpc_at_adj_net_latency(struct ptlrpc_request *req, */ CDEBUG((lustre_msg_get_flags(req->rq_reqmsg) & MSG_RESENT) ? D_ADAPTTO : D_WARNING, - "Reported service time %u > total measured time " - CFS_DURATION_T"\n", service_time, + "Reported service time %u > total measured time " CFS_DURATION_T "\n", + service_time, (long)(now - req->rq_sent)); return; } diff --git a/drivers/staging/lustre/lustre/ptlrpc/import.c b/drivers/staging/lustre/lustre/ptlrpc/import.c index 93e172fe9ce4..52cb1f0c9c94 100644 --- a/drivers/staging/lustre/lustre/ptlrpc/import.c +++ b/drivers/staging/lustre/lustre/ptlrpc/import.c @@ -1182,17 +1182,15 @@ static int ptlrpc_connect_interpret(const struct lu_env *env, } /* Sanity checks for a reconnected import. */ - if (!(imp->imp_replayable) != !(msg_flags & MSG_CONNECT_REPLAYABLE)) { + if (!(imp->imp_replayable) != !(msg_flags & MSG_CONNECT_REPLAYABLE)) CERROR("imp_replayable flag does not match server after reconnect. We should LBUG right here.\n"); - } if (lustre_msg_get_last_committed(request->rq_repmsg) > 0 && lustre_msg_get_last_committed(request->rq_repmsg) < - aa->pcaa_peer_committed) { + aa->pcaa_peer_committed) CERROR("%s went back in time (transno %lld was previously committed, server now claims %lld)! See https://bugzilla.lustre.org/show_bug.cgi?id=9646\n", obd2cli_tgt(imp->imp_obd), aa->pcaa_peer_committed, lustre_msg_get_last_committed(request->rq_repmsg)); - } finish: ptlrpc_prepare_replay(imp); @@ -1437,20 +1435,17 @@ int ptlrpc_import_recovery_state_machine(struct obd_import *imp) rc = 0; } - if (imp->imp_state == LUSTRE_IMP_REPLAY_LOCKS) { + if (imp->imp_state == LUSTRE_IMP_REPLAY_LOCKS) if (atomic_read(&imp->imp_replay_inflight) == 0) { IMPORT_SET_STATE(imp, LUSTRE_IMP_REPLAY_WAIT); rc = signal_completed_replay(imp); if (rc) goto out; } - } - if (imp->imp_state == LUSTRE_IMP_REPLAY_WAIT) { - if (atomic_read(&imp->imp_replay_inflight) == 0) { + if (imp->imp_state == LUSTRE_IMP_REPLAY_WAIT) + if (atomic_read(&imp->imp_replay_inflight) == 0) IMPORT_SET_STATE(imp, LUSTRE_IMP_RECOVER); - } - } if (imp->imp_state == LUSTRE_IMP_RECOVER) { CDEBUG(D_HA, "reconnected to %s@%s\n", diff --git a/drivers/staging/lustre/lustre/ptlrpc/layout.c b/drivers/staging/lustre/lustre/ptlrpc/layout.c index 8177e1a31ca9..5810bbab6585 100644 --- a/drivers/staging/lustre/lustre/ptlrpc/layout.c +++ b/drivers/staging/lustre/lustre/ptlrpc/layout.c @@ -1761,7 +1761,7 @@ static u32 __req_capsule_offset(const struct req_capsule *pill, field->rmf_name, offset, loc); offset--; - LASSERT(0 <= offset && offset < REQ_MAX_FIELD_NR); + LASSERT(offset < REQ_MAX_FIELD_NR); return offset; } diff --git a/drivers/staging/lustre/lustre/ptlrpc/pack_generic.c b/drivers/staging/lustre/lustre/ptlrpc/pack_generic.c index 9456a1825918..55e8696e7d86 100644 --- a/drivers/staging/lustre/lustre/ptlrpc/pack_generic.c +++ b/drivers/staging/lustre/lustre/ptlrpc/pack_generic.c @@ -2089,7 +2089,7 @@ static void dump_obdo(struct obdo *oa) CDEBUG(D_RPCTRACE, "obdo: o_valid = %08x\n", valid); if (valid & OBD_MD_FLID) - CDEBUG(D_RPCTRACE, "obdo: id = "DOSTID"\n", POSTID(&oa->o_oi)); + CDEBUG(D_RPCTRACE, "obdo: id = " DOSTID "\n", POSTID(&oa->o_oi)); if (valid & OBD_MD_FLFID) CDEBUG(D_RPCTRACE, "obdo: o_parent_seq = %#llx\n", oa->o_parent_seq); diff --git a/drivers/staging/lustre/lustre/ptlrpc/ptlrpc_internal.h b/drivers/staging/lustre/lustre/ptlrpc/ptlrpc_internal.h index d2707a323c47..c38e166f1502 100644 --- a/drivers/staging/lustre/lustre/ptlrpc/ptlrpc_internal.h +++ b/drivers/staging/lustre/lustre/ptlrpc/ptlrpc_internal.h @@ -68,7 +68,7 @@ void ptlrpc_init_xid(void); void ptlrpc_set_add_new_req(struct ptlrpcd_ctl *pc, struct ptlrpc_request *req); int ptlrpc_expired_set(void *data); -int ptlrpc_set_next_timeout(struct ptlrpc_request_set *); +int ptlrpc_set_next_timeout(struct ptlrpc_request_set *set); void ptlrpc_resend_req(struct ptlrpc_request *request); void ptlrpc_set_bulk_mbits(struct ptlrpc_request *req); void ptlrpc_assign_next_xid_nolock(struct ptlrpc_request *req); @@ -79,7 +79,7 @@ void ptlrpc_add_unreplied(struct ptlrpc_request *req); int ptlrpc_init_portals(void); void ptlrpc_exit_portals(void); -void ptlrpc_request_handle_notconn(struct ptlrpc_request *); +void ptlrpc_request_handle_notconn(struct ptlrpc_request *req); void lustre_assert_wire_constants(void); int ptlrpc_import_in_recovery(struct obd_import *imp); int ptlrpc_set_import_discon(struct obd_import *imp, __u32 conn_cnt); diff --git a/drivers/staging/lustre/lustre/ptlrpc/service.c b/drivers/staging/lustre/lustre/ptlrpc/service.c index b8091c118302..759aa6c16e28 100644 --- a/drivers/staging/lustre/lustre/ptlrpc/service.c +++ b/drivers/staging/lustre/lustre/ptlrpc/service.c @@ -1565,7 +1565,7 @@ ptlrpc_server_handle_req_in(struct ptlrpc_service_part *svcpt, /* req_in handling should/must be fast */ if (ktime_get_real_seconds() - req->rq_arrival_time.tv_sec > 5) - DEBUG_REQ(D_WARNING, req, "Slow req_in handling "CFS_DURATION_T"s", + DEBUG_REQ(D_WARNING, req, "Slow req_in handling " CFS_DURATION_T "s", (long)(ktime_get_real_seconds() - req->rq_arrival_time.tv_sec)); diff --git a/drivers/staging/most/aim-network/networking.c b/drivers/staging/most/aim-network/networking.c index ce1764cba5f0..4c259c20048f 100644 --- a/drivers/staging/most/aim-network/networking.c +++ b/drivers/staging/most/aim-network/networking.c @@ -22,7 +22,6 @@ #include <linux/wait.h> #include <linux/kobject.h> #include "mostcore.h" -#include "networking.h" #define MEP_HDR_LEN 8 #define MDP_HDR_LEN 16 @@ -65,17 +64,16 @@ struct net_dev_channel { struct net_dev_context { struct most_interface *iface; - bool channels_opened; bool is_mamac; struct net_device *dev; struct net_dev_channel rx; struct net_dev_channel tx; - struct completion mac_compl; struct list_head list; }; static struct list_head net_devices = LIST_HEAD_INIT(net_devices); -static struct spinlock list_lock; +static struct mutex probe_disc_mt; /* ch->linked = true, most_nd_open */ +static struct spinlock list_lock; /* list_head, ch->linked = false, dev_hold */ static struct most_aim aim; static int skb_to_mamac(const struct sk_buff *skb, struct mbo *mbo) @@ -157,14 +155,12 @@ static int skb_to_mep(const struct sk_buff *skb, struct mbo *mbo) static int most_nd_set_mac_address(struct net_device *dev, void *p) { - struct net_dev_context *nd = dev->ml_priv; + struct net_dev_context *nd = netdev_priv(dev); int err = eth_mac_addr(dev, p); if (err) return err; - BUG_ON(nd->dev != dev); - nd->is_mamac = (dev->dev_addr[0] == 0 && dev->dev_addr[1] == 0 && dev->dev_addr[2] == 0 && dev->dev_addr[3] == 0); @@ -178,71 +174,52 @@ static int most_nd_set_mac_address(struct net_device *dev, void *p) return 0; } +static void on_netinfo(struct most_interface *iface, + unsigned char link_stat, unsigned char *mac_addr); + static int most_nd_open(struct net_device *dev) { - struct net_dev_context *nd = dev->ml_priv; - long ret; - - netdev_info(dev, "open net device\n"); - - BUG_ON(nd->dev != dev); + struct net_dev_context *nd = netdev_priv(dev); + int ret = 0; - if (nd->channels_opened) - return -EFAULT; - - BUG_ON(!nd->tx.linked || !nd->rx.linked); + mutex_lock(&probe_disc_mt); if (most_start_channel(nd->iface, nd->rx.ch_id, &aim)) { netdev_err(dev, "most_start_channel() failed\n"); - return -EBUSY; + ret = -EBUSY; + goto unlock; } if (most_start_channel(nd->iface, nd->tx.ch_id, &aim)) { netdev_err(dev, "most_start_channel() failed\n"); most_stop_channel(nd->iface, nd->rx.ch_id, &aim); - return -EBUSY; + ret = -EBUSY; + goto unlock; } - if (!is_valid_ether_addr(dev->dev_addr)) { - nd->iface->request_netinfo(nd->iface, nd->tx.ch_id); - ret = wait_for_completion_interruptible_timeout( - &nd->mac_compl, msecs_to_jiffies(5000)); - if (!ret) { - netdev_err(dev, "mac timeout\n"); - ret = -EBUSY; - goto err; - } - - if (ret < 0) { - netdev_warn(dev, "mac waiting interrupted\n"); - goto err; - } - } - - nd->channels_opened = true; + netif_carrier_off(dev); + if (is_valid_ether_addr(dev->dev_addr)) + netif_dormant_off(dev); + else + netif_dormant_on(dev); netif_wake_queue(dev); - return 0; + if (nd->iface->request_netinfo) + nd->iface->request_netinfo(nd->iface, nd->tx.ch_id, on_netinfo); -err: - most_stop_channel(nd->iface, nd->tx.ch_id, &aim); - most_stop_channel(nd->iface, nd->rx.ch_id, &aim); +unlock: + mutex_unlock(&probe_disc_mt); return ret; } static int most_nd_stop(struct net_device *dev) { - struct net_dev_context *nd = dev->ml_priv; - - netdev_info(dev, "stop net device\n"); + struct net_dev_context *nd = netdev_priv(dev); - BUG_ON(nd->dev != dev); netif_stop_queue(dev); - - if (nd->channels_opened) { - most_stop_channel(nd->iface, nd->rx.ch_id, &aim); - most_stop_channel(nd->iface, nd->tx.ch_id, &aim); - nd->channels_opened = false; - } + if (nd->iface->request_netinfo) + nd->iface->request_netinfo(nd->iface, nd->tx.ch_id, NULL); + most_stop_channel(nd->iface, nd->rx.ch_id, &aim); + most_stop_channel(nd->iface, nd->tx.ch_id, &aim); return 0; } @@ -250,12 +227,10 @@ static int most_nd_stop(struct net_device *dev) static netdev_tx_t most_nd_start_xmit(struct sk_buff *skb, struct net_device *dev) { - struct net_dev_context *nd = dev->ml_priv; + struct net_dev_context *nd = netdev_priv(dev); struct mbo *mbo; int ret; - BUG_ON(nd->dev != dev); - mbo = most_get_mbo(nd->iface, nd->tx.ch_id, &aim); if (!mbo) { @@ -296,33 +271,29 @@ static void most_nd_setup(struct net_device *dev) dev->netdev_ops = &most_nd_ops; } -static void most_net_rm_netdev_safe(struct net_dev_context *nd) +static struct net_dev_context *get_net_dev(struct most_interface *iface) { - if (!nd->dev) - return; - - pr_info("remove net device %p\n", nd->dev); + struct net_dev_context *nd; - unregister_netdev(nd->dev); - free_netdev(nd->dev); - nd->dev = NULL; + list_for_each_entry(nd, &net_devices, list) + if (nd->iface == iface) + return nd; + return NULL; } -static struct net_dev_context *get_net_dev_context( - struct most_interface *iface) +static struct net_dev_context *get_net_dev_hold(struct most_interface *iface) { - struct net_dev_context *nd, *tmp; + struct net_dev_context *nd; unsigned long flags; spin_lock_irqsave(&list_lock, flags); - list_for_each_entry_safe(nd, tmp, &net_devices, list) { - if (nd->iface == iface) { - spin_unlock_irqrestore(&list_lock, flags); - return nd; - } - } + nd = get_net_dev(iface); + if (nd && nd->rx.linked && nd->tx.linked) + dev_hold(nd->dev); + else + nd = NULL; spin_unlock_irqrestore(&list_lock, flags); - return NULL; + return nd; } static int aim_probe_channel(struct most_interface *iface, int channel_idx, @@ -331,7 +302,9 @@ static int aim_probe_channel(struct most_interface *iface, int channel_idx, { struct net_dev_context *nd; struct net_dev_channel *ch; + struct net_device *dev; unsigned long flags; + int ret = 0; if (!iface) return -EINVAL; @@ -339,54 +312,45 @@ static int aim_probe_channel(struct most_interface *iface, int channel_idx, if (ccfg->data_type != MOST_CH_ASYNC) return -EINVAL; - nd = get_net_dev_context(iface); - + mutex_lock(&probe_disc_mt); + nd = get_net_dev(iface); if (!nd) { - nd = kzalloc(sizeof(*nd), GFP_KERNEL); - if (!nd) - return -ENOMEM; + dev = alloc_netdev(sizeof(struct net_dev_context), "meth%d", + NET_NAME_UNKNOWN, most_nd_setup); + if (!dev) { + ret = -ENOMEM; + goto unlock; + } - init_completion(&nd->mac_compl); + nd = netdev_priv(dev); nd->iface = iface; + nd->dev = dev; spin_lock_irqsave(&list_lock, flags); list_add(&nd->list, &net_devices); spin_unlock_irqrestore(&list_lock, flags); - } - ch = ccfg->direction == MOST_CH_TX ? &nd->tx : &nd->rx; - if (ch->linked) { - pr_err("only one channel per instance & direction allowed\n"); - return -EINVAL; - } - - if (nd->tx.linked || nd->rx.linked) { - struct net_device *dev = - alloc_netdev(0, "meth%d", NET_NAME_UNKNOWN, - most_nd_setup); - - if (!dev) { - pr_err("no memory for net_device\n"); - return -ENOMEM; + ch = ccfg->direction == MOST_CH_TX ? &nd->tx : &nd->rx; + } else { + ch = ccfg->direction == MOST_CH_TX ? &nd->tx : &nd->rx; + if (ch->linked) { + pr_err("direction is allocated\n"); + ret = -EINVAL; + goto unlock; } - nd->dev = dev; - ch->ch_id = channel_idx; - ch->linked = true; - - dev->ml_priv = nd; - if (register_netdev(dev)) { - pr_err("registering net device failed\n"); - ch->linked = false; - free_netdev(dev); - return -EINVAL; + if (register_netdev(nd->dev)) { + pr_err("register_netdev() failed\n"); + ret = -EINVAL; + goto unlock; } } - ch->ch_id = channel_idx; ch->linked = true; - return 0; +unlock: + mutex_unlock(&probe_disc_mt); + return ret; } static int aim_disconnect_channel(struct most_interface *iface, @@ -395,34 +359,45 @@ static int aim_disconnect_channel(struct most_interface *iface, struct net_dev_context *nd; struct net_dev_channel *ch; unsigned long flags; + int ret = 0; - nd = get_net_dev_context(iface); - if (!nd) - return -EINVAL; + mutex_lock(&probe_disc_mt); + nd = get_net_dev(iface); + if (!nd) { + ret = -EINVAL; + goto unlock; + } - if (nd->rx.linked && channel_idx == nd->rx.ch_id) + if (nd->rx.linked && channel_idx == nd->rx.ch_id) { ch = &nd->rx; - else if (nd->tx.linked && channel_idx == nd->tx.ch_id) + } else if (nd->tx.linked && channel_idx == nd->tx.ch_id) { ch = &nd->tx; - else - return -EINVAL; - - ch->linked = false; + } else { + ret = -EINVAL; + goto unlock; + } - /* - * do not call most_stop_channel() here, because channels are - * going to be closed in ndo_stop() after unregister_netdev() - */ - most_net_rm_netdev_safe(nd); + if (nd->rx.linked && nd->tx.linked) { + spin_lock_irqsave(&list_lock, flags); + ch->linked = false; + spin_unlock_irqrestore(&list_lock, flags); - if (!nd->rx.linked && !nd->tx.linked) { + /* + * do not call most_stop_channel() here, because channels are + * going to be closed in ndo_stop() after unregister_netdev() + */ + unregister_netdev(nd->dev); + } else { spin_lock_irqsave(&list_lock, flags); list_del(&nd->list); spin_unlock_irqrestore(&list_lock, flags); - kfree(nd); + + free_netdev(nd->dev); } - return 0; +unlock: + mutex_unlock(&probe_disc_mt); + return ret; } static int aim_resume_tx_channel(struct most_interface *iface, @@ -430,14 +405,17 @@ static int aim_resume_tx_channel(struct most_interface *iface, { struct net_dev_context *nd; - nd = get_net_dev_context(iface); - if (!nd || !nd->channels_opened || nd->tx.ch_id != channel_idx) + nd = get_net_dev_hold(iface); + if (!nd) return 0; - if (!nd->dev) - return 0; + if (nd->tx.ch_id != channel_idx) + goto put_nd; netif_wake_queue(nd->dev); + +put_nd: + dev_put(nd->dev); return 0; } @@ -450,25 +428,31 @@ static int aim_rx_data(struct mbo *mbo) struct sk_buff *skb; struct net_device *dev; unsigned int skb_len; + int ret = 0; - nd = get_net_dev_context(mbo->ifp); - if (!nd || !nd->channels_opened || nd->rx.ch_id != mbo->hdm_channel_id) + nd = get_net_dev_hold(mbo->ifp); + if (!nd) return -EIO; - dev = nd->dev; - if (!dev) { - pr_err_once("drop packet: missing net_device\n"); - return -EIO; + if (nd->rx.ch_id != mbo->hdm_channel_id) { + ret = -EIO; + goto put_nd; } + dev = nd->dev; + if (nd->is_mamac) { - if (!PMS_IS_MAMAC(buf, len)) - return -EIO; + if (!PMS_IS_MAMAC(buf, len)) { + ret = -EIO; + goto put_nd; + } skb = dev_alloc_skb(len - MDP_HDR_LEN + 2 * ETH_ALEN + 2); } else { - if (!PMS_IS_MEP(buf, len)) - return -EIO; + if (!PMS_IS_MEP(buf, len)) { + ret = -EIO; + goto put_nd; + } skb = dev_alloc_skb(len - MEP_HDR_LEN); } @@ -511,7 +495,10 @@ static int aim_rx_data(struct mbo *mbo) out: most_put_mbo(mbo); - return 0; + +put_nd: + dev_put(nd->dev); + return ret; } static struct most_aim aim = { @@ -524,68 +511,54 @@ static struct most_aim aim = { static int __init most_net_init(void) { - pr_info("most_net_init()\n"); spin_lock_init(&list_lock); + mutex_init(&probe_disc_mt); return most_register_aim(&aim); } static void __exit most_net_exit(void) { - struct net_dev_context *nd, *tmp; - unsigned long flags; - - spin_lock_irqsave(&list_lock, flags); - list_for_each_entry_safe(nd, tmp, &net_devices, list) { - list_del(&nd->list); - spin_unlock_irqrestore(&list_lock, flags); - /* - * do not call most_stop_channel() here, because channels are - * going to be closed in ndo_stop() after unregister_netdev() - */ - most_net_rm_netdev_safe(nd); - kfree(nd); - spin_lock_irqsave(&list_lock, flags); - } - spin_unlock_irqrestore(&list_lock, flags); - most_deregister_aim(&aim); - pr_info("most_net_exit()\n"); } /** - * most_deliver_netinfo - callback for HDM to be informed about HW's MAC + * on_netinfo - callback for HDM to be informed about HW's MAC * @param iface - most interface instance * @param link_stat - link status * @param mac_addr - MAC address */ -void most_deliver_netinfo(struct most_interface *iface, - unsigned char link_stat, unsigned char *mac_addr) +static void on_netinfo(struct most_interface *iface, + unsigned char link_stat, unsigned char *mac_addr) { struct net_dev_context *nd; struct net_device *dev; const u8 *m = mac_addr; - nd = get_net_dev_context(iface); + nd = get_net_dev_hold(iface); if (!nd) return; dev = nd->dev; - if (!dev) - return; + + if (link_stat) + netif_carrier_on(dev); + else + netif_carrier_off(dev); if (m && is_valid_ether_addr(m)) { if (!is_valid_ether_addr(dev->dev_addr)) { netdev_info(dev, "set mac %02x-%02x-%02x-%02x-%02x-%02x\n", m[0], m[1], m[2], m[3], m[4], m[5]); ether_addr_copy(dev->dev_addr, m); - complete(&nd->mac_compl); + netif_dormant_off(dev); } else if (!ether_addr_equal(dev->dev_addr, m)) { netdev_warn(dev, "reject mac %02x-%02x-%02x-%02x-%02x-%02x\n", m[0], m[1], m[2], m[3], m[4], m[5]); } } + + dev_put(nd->dev); } -EXPORT_SYMBOL(most_deliver_netinfo); module_init(most_net_init); module_exit(most_net_exit); diff --git a/drivers/staging/most/aim-network/networking.h b/drivers/staging/most/aim-network/networking.h deleted file mode 100644 index 6f346d410525..000000000000 --- a/drivers/staging/most/aim-network/networking.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Networking AIM - Networking Application Interface Module for MostCore - * - * Copyright (C) 2015, Microchip Technology Germany II GmbH & Co. KG - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * This file is licensed under GPLv2. - */ -#ifndef _NETWORKING_H_ -#define _NETWORKING_H_ - -#include "mostcore.h" - -void most_deliver_netinfo(struct most_interface *iface, - unsigned char link_stat, unsigned char *mac_addr); - -#endif diff --git a/drivers/staging/most/hdm-dim2/Kconfig b/drivers/staging/most/hdm-dim2/Kconfig index 28a0e1791600..663bfebff674 100644 --- a/drivers/staging/most/hdm-dim2/Kconfig +++ b/drivers/staging/most/hdm-dim2/Kconfig @@ -4,7 +4,6 @@ config HDM_DIM2 tristate "DIM2 HDM" - depends on AIM_NETWORK depends on HAS_IOMEM ---help--- diff --git a/drivers/staging/most/hdm-dim2/dim2_hal.c b/drivers/staging/most/hdm-dim2/dim2_hal.c index d604ec09df28..91484643d289 100644 --- a/drivers/staging/most/hdm-dim2/dim2_hal.c +++ b/drivers/staging/most/hdm-dim2/dim2_hal.c @@ -217,12 +217,15 @@ static inline void dim2_clear_ctr(u32 ctr_addr) } static void dim2_configure_cat(u8 cat_base, u8 ch_addr, u8 ch_type, - bool read_not_write, bool sync_mfe) + bool read_not_write) { + bool isoc_fce = ch_type == CAT_CT_VAL_ISOC; + bool sync_mfe = ch_type == CAT_CT_VAL_SYNC; u16 const cat = (read_not_write << CAT_RNW_BIT) | (ch_type << CAT_CT_SHIFT) | (ch_addr << CAT_CL_SHIFT) | + (isoc_fce << CAT_FCE_BIT) | (sync_mfe << CAT_MFE_BIT) | (false << CAT_MT_BIT) | (true << CAT_CE_BIT); @@ -350,13 +353,13 @@ static void dim2_clear_ctram(void) static void dim2_configure_channel( u8 ch_addr, u8 type, u8 is_tx, u16 dbr_address, u16 hw_buffer_size, - u16 packet_length, bool sync_mfe) + u16 packet_length) { dim2_configure_cdt(ch_addr, dbr_address, hw_buffer_size, packet_length); - dim2_configure_cat(MLB_CAT, ch_addr, type, is_tx ? 1 : 0, sync_mfe); + dim2_configure_cat(MLB_CAT, ch_addr, type, is_tx ? 1 : 0); dim2_configure_adt(ch_addr); - dim2_configure_cat(AHB_CAT, ch_addr, type, is_tx ? 0 : 1, sync_mfe); + dim2_configure_cat(AHB_CAT, ch_addr, type, is_tx ? 0 : 1); /* unmask interrupt for used channel, enable mlb_sys_int[0] interrupt */ dimcb_io_write(&g.dim2->ACMR0, @@ -771,7 +774,7 @@ static u8 init_ctrl_async(struct dim_channel *ch, u8 type, u8 is_tx, channel_init(ch, ch_address / 2); dim2_configure_channel(ch->addr, type, is_tx, - ch->dbr_addr, ch->dbr_size, 0, false); + ch->dbr_addr, ch->dbr_size, 0); return DIM_NO_ERROR; } @@ -857,7 +860,7 @@ u8 dim_init_isoc(struct dim_channel *ch, u8 is_tx, u16 ch_address, isoc_init(ch, ch_address / 2, packet_length); dim2_configure_channel(ch->addr, CAT_CT_VAL_ISOC, is_tx, ch->dbr_addr, - ch->dbr_size, packet_length, false); + ch->dbr_size, packet_length); return DIM_NO_ERROR; } @@ -885,7 +888,7 @@ u8 dim_init_sync(struct dim_channel *ch, u8 is_tx, u16 ch_address, dim2_clear_dbr(ch->dbr_addr, ch->dbr_size); dim2_configure_channel(ch->addr, CAT_CT_VAL_SYNC, is_tx, - ch->dbr_addr, ch->dbr_size, 0, true); + ch->dbr_addr, ch->dbr_size, 0); return DIM_NO_ERROR; } diff --git a/drivers/staging/most/hdm-dim2/dim2_hdm.c b/drivers/staging/most/hdm-dim2/dim2_hdm.c index 902824e728ea..4607d03c577b 100644 --- a/drivers/staging/most/hdm-dim2/dim2_hdm.c +++ b/drivers/staging/most/hdm-dim2/dim2_hdm.c @@ -26,7 +26,6 @@ #include <linux/kthread.h> #include <mostcore.h> -#include <networking.h> #include "dim2_hal.h" #include "dim2_hdm.h" #include "dim2_errors.h" @@ -107,6 +106,8 @@ struct dim2_hdm { unsigned char link_state; int atx_idx; struct medialb_bus bus; + void (*on_netinfo)(struct most_interface *, + unsigned char, unsigned char *); }; #define iface_to_hdm(iface) container_of(iface, struct dim2_hdm, most_iface) @@ -287,8 +288,11 @@ static int deliver_netinfo_thread(void *data) if (dev->deliver_netinfo) { dev->deliver_netinfo--; - most_deliver_netinfo(&dev->most_iface, dev->link_state, - dev->mac_addrs); + if (dev->on_netinfo) { + dev->on_netinfo(&dev->most_iface, + dev->link_state, + dev->mac_addrs); + } } } @@ -654,12 +658,18 @@ static int enqueue(struct most_interface *most_iface, int ch_idx, * Send a command to INIC which triggers retrieving of network info by means of * "Message exchange over MDP/MEP". Return 0 on success, negative on failure. */ -static void request_netinfo(struct most_interface *most_iface, int ch_idx) +static void request_netinfo(struct most_interface *most_iface, int ch_idx, + void (*on_netinfo)(struct most_interface *, + unsigned char, unsigned char *)) { struct dim2_hdm *dev = iface_to_hdm(most_iface); struct mbo *mbo; u8 *data; + dev->on_netinfo = on_netinfo; + if (!on_netinfo) + return; + if (dev->atx_idx < 0) { pr_err("Async Tx Not initialized\n"); return; diff --git a/drivers/staging/most/hdm-dim2/dim2_reg.h b/drivers/staging/most/hdm-dim2/dim2_reg.h index 01fe499411ff..f7d9fbcd29f2 100644 --- a/drivers/staging/most/hdm-dim2/dim2_reg.h +++ b/drivers/staging/most/hdm-dim2/dim2_reg.h @@ -141,6 +141,7 @@ enum { ADT1_CTRL_ASYNC_BD_MASK = DIM2_MASK(11), ADT1_ISOC_SYNC_BD_MASK = DIM2_MASK(13), + CAT_FCE_BIT = 14, CAT_MFE_BIT = 14, CAT_MT_BIT = 13, diff --git a/drivers/staging/most/hdm-i2c/hdm_i2c.c b/drivers/staging/most/hdm-i2c/hdm_i2c.c index 1d5b22927bcd..2b4de404e46a 100644 --- a/drivers/staging/most/hdm-i2c/hdm_i2c.c +++ b/drivers/staging/most/hdm-i2c/hdm_i2c.c @@ -185,12 +185,6 @@ static int poison_channel(struct most_interface *most_iface, return 0; } -static void request_netinfo(struct most_interface *most_iface, - int ch_idx) -{ - pr_info("request_netinfo()\n"); -} - static void do_rx_work(struct hdm_i2c *dev) { struct mbo *mbo; @@ -343,7 +337,6 @@ static int i2c_probe(struct i2c_client *client, const struct i2c_device_id *id) dev->most_iface.configure = configure_channel; dev->most_iface.enqueue = enqueue; dev->most_iface.poison_channel = poison_channel; - dev->most_iface.request_netinfo = request_netinfo; INIT_LIST_HEAD(&dev->rx.list); mutex_init(&dev->rx.list_mutex); diff --git a/drivers/staging/most/hdm-usb/Kconfig b/drivers/staging/most/hdm-usb/Kconfig index ec1546312ee6..487f1f34776c 100644 --- a/drivers/staging/most/hdm-usb/Kconfig +++ b/drivers/staging/most/hdm-usb/Kconfig @@ -5,7 +5,7 @@ config HDM_USB tristate "USB HDM" depends on USB && NET - select AIM_NETWORK + ---help--- Say Y here if you want to connect via USB to network tranceiver. This device driver depends on the networking AIM. diff --git a/drivers/staging/most/hdm-usb/hdm_usb.c b/drivers/staging/most/hdm-usb/hdm_usb.c index a95b5910d9fc..d0f68cb3c173 100644 --- a/drivers/staging/most/hdm-usb/hdm_usb.c +++ b/drivers/staging/most/hdm-usb/hdm_usb.c @@ -30,7 +30,6 @@ #include <linux/etherdevice.h> #include <linux/uaccess.h> #include "mostcore.h" -#include "networking.h" #define USB_MTU 512 #define NO_ISOCHRONOUS_URB 0 @@ -126,6 +125,8 @@ struct most_dev { struct mutex io_mutex; struct timer_list link_stat_timer; struct work_struct poll_work_obj; + void (*on_netinfo)(struct most_interface *, unsigned char, + unsigned char *); }; #define to_mdev(d) container_of(d, struct most_dev, iface) @@ -719,12 +720,19 @@ exit: * polls for the NI state of the INIC every 2 seconds. * */ -static void hdm_request_netinfo(struct most_interface *iface, int channel) +static void hdm_request_netinfo(struct most_interface *iface, int channel, + void (*on_netinfo)(struct most_interface *, + unsigned char, + unsigned char *)) { struct most_dev *mdev; BUG_ON(!iface); mdev = to_mdev(iface); + mdev->on_netinfo = on_netinfo; + if (!on_netinfo) + return; + mdev->link_stat_timer.expires = jiffies + HZ; mod_timer(&mdev->link_stat_timer, mdev->link_stat_timer.expires); } @@ -786,7 +794,8 @@ static void wq_netinfo(struct work_struct *wq_obj) hw_addr[4] = lo >> 8; hw_addr[5] = lo; - most_deliver_netinfo(&mdev->iface, link, hw_addr); + if (mdev->on_netinfo) + mdev->on_netinfo(&mdev->iface, link, hw_addr); } /** diff --git a/drivers/staging/most/mostcore/mostcore.h b/drivers/staging/most/mostcore/mostcore.h index 5f8339bd046f..915e5159d1eb 100644 --- a/drivers/staging/most/mostcore/mostcore.h +++ b/drivers/staging/most/mostcore/mostcore.h @@ -233,6 +233,8 @@ struct mbo { * The callback returns a negative value on error, otherwise 0. * @request_netinfo: triggers retrieving of network info from the HDM by * means of "Message exchange over MDP/MEP" + * The call of the function request_netinfo with the parameter on_netinfo as + * NULL prohibits use of the previously obtained function pointer. * @priv Private field used by mostcore to store context information. */ struct most_interface { @@ -246,7 +248,10 @@ struct most_interface { int (*enqueue)(struct most_interface *iface, int channel_idx, struct mbo *mbo); int (*poison_channel)(struct most_interface *iface, int channel_idx); - void (*request_netinfo)(struct most_interface *iface, int channel_idx); + void (*request_netinfo)(struct most_interface *iface, int channel_idx, + void (*on_netinfo)(struct most_interface *iface, + unsigned char link_stat, + unsigned char *mac_addr)); void *priv; }; diff --git a/drivers/staging/octeon-usb/octeon-hcd.c b/drivers/staging/octeon-usb/octeon-hcd.c index 9a7858a300fd..068aece25d37 100644 --- a/drivers/staging/octeon-usb/octeon-hcd.c +++ b/drivers/staging/octeon-usb/octeon-hcd.c @@ -3659,14 +3659,14 @@ static int octeon_usb_probe(struct platform_device *pdev) status = cvmx_usb_initialize(dev, usb); if (status) { dev_dbg(dev, "USB initialization failed with %d\n", status); - kfree(hcd); + usb_put_hcd(hcd); return -1; } status = usb_add_hcd(hcd, irq, 0); if (status) { dev_dbg(dev, "USB add HCD failed with %d\n", status); - kfree(hcd); + usb_put_hcd(hcd); return -1; } device_wakeup_enable(hcd->self.controller); @@ -3691,7 +3691,7 @@ static int octeon_usb_remove(struct platform_device *pdev) if (status) dev_dbg(dev, "USB shutdown failed with %d\n", status); - kfree(hcd); + usb_put_hcd(hcd); return 0; } diff --git a/drivers/staging/octeon/ethernet-util.h b/drivers/staging/octeon/ethernet-util.h index 617da8037a4d..cb5540dc0e9d 100644 --- a/drivers/staging/octeon/ethernet-util.h +++ b/drivers/staging/octeon/ethernet-util.h @@ -39,7 +39,7 @@ static inline int INTERFACE(int ipd_port) interface = cvmx_helper_get_interface_num(ipd_port); if (interface >= 0) return interface; - panic("Illegal ipd_port %d passed to INTERFACE\n", ipd_port); + panic("Illegal ipd_port %d passed to %s\n", ipd_port, __func__); } /** diff --git a/drivers/staging/rtl8188eu/core/rtw_ap.c b/drivers/staging/rtl8188eu/core/rtw_ap.c index 519b4d3584a2..647a922d79d1 100644 --- a/drivers/staging/rtl8188eu/core/rtw_ap.c +++ b/drivers/staging/rtl8188eu/core/rtw_ap.c @@ -735,9 +735,11 @@ static void start_bss_network(struct adapter *padapter, u8 *pbuf) cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; - /* check if there is wps ie, */ - /* if there is wpsie in beacon, the hostapd will update beacon twice when stating hostapd, */ - /* and at first time the security ie (RSN/WPA IE) will not include in beacon. */ + /* check if there is wps ie, + * if there is wpsie in beacon, the hostapd will update + * beacon twice when stating hostapd, and at first time the + * security ie (RSN/WPA IE) will not include in beacon. + */ if (!rtw_get_wps_ie(pnetwork->IEs + _FIXED_IE_LENGTH_, pnetwork->IELength - _FIXED_IE_LENGTH_, NULL, NULL)) pmlmeext->bstart_bss = true; @@ -751,8 +753,11 @@ static void start_bss_network(struct adapter *padapter, u8 *pbuf) update_hw_ht_param(padapter); } - if (pmlmepriv->cur_network.join_res != true) { /* setting only at first time */ - /* WEP Key will be set before this function, do not clear CAM. */ + /* setting only at first time */ + if (!(pmlmepriv->cur_network.join_res)) { + /* WEP Key will be set before this function, do not + * clear CAM. + */ if ((psecuritypriv->dot11PrivacyAlgrthm != _WEP40_) && (psecuritypriv->dot11PrivacyAlgrthm != _WEP104_)) flush_all_cam_entry(padapter); /* clear CAM */ @@ -809,7 +814,9 @@ static void start_bss_network(struct adapter *padapter, u8 *pbuf) } } } - /* TODO: need to judge the phy parameters on concurrent mode for single phy */ + /* TODO: need to judge the phy parameters on concurrent + * mode for single phy + */ set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode); DBG_88E("CH =%d, BW =%d, offset =%d\n", cur_channel, cur_bwmode, cur_ch_offset); @@ -991,7 +998,7 @@ int rtw_check_beacon_data(struct adapter *padapter, u8 *pbuf, int len) } break; } - if ((p == NULL) || (ie_len == 0)) + if ((!p) || (ie_len == 0)) break; } @@ -1005,9 +1012,12 @@ int rtw_check_beacon_data(struct adapter *padapter, u8 *pbuf, int len) if ((p) && !memcmp(p + 2, WMM_PARA_IE, 6)) { pmlmepriv->qospriv.qos_option = 1; - *(p + 8) |= BIT(7);/* QoS Info, support U-APSD */ + /* QoS Info, support U-APSD */ + *(p + 8) |= BIT(7); - /* disable all ACM bits since the WMM admission control is not supported */ + /* disable all ACM bits since the WMM + * admission control is not supported + */ *(p + 10) &= ~BIT(4); /* BE */ *(p + 14) &= ~BIT(4); /* BK */ *(p + 18) &= ~BIT(4); /* VI */ @@ -1015,7 +1025,7 @@ int rtw_check_beacon_data(struct adapter *padapter, u8 *pbuf, int len) break; } - if ((p == NULL) || (ie_len == 0)) + if ((!p) || (ie_len == 0)) break; } } @@ -1097,7 +1107,7 @@ int rtw_check_beacon_data(struct adapter *padapter, u8 *pbuf, int len) psta = rtw_get_stainfo(&padapter->stapriv, pbss_network->MacAddress); if (!psta) { psta = rtw_alloc_stainfo(&padapter->stapriv, pbss_network->MacAddress); - if (psta == NULL) + if (!psta) return _FAIL; } @@ -1268,12 +1278,12 @@ static void update_bcn_wps_ie(struct adapter *padapter) DBG_88E("%s\n", __func__); pwps_ie_src = pmlmepriv->wps_beacon_ie; - if (pwps_ie_src == NULL) + if (!pwps_ie_src) return; pwps_ie = rtw_get_wps_ie(ie+_FIXED_IE_LENGTH_, ielen-_FIXED_IE_LENGTH_, NULL, &wps_ielen); - if (pwps_ie == NULL || wps_ielen == 0) + if (!pwps_ie || wps_ielen == 0) return; wps_offset = (uint)(pwps_ie-ie); @@ -1834,7 +1844,9 @@ void stop_ap_mode(struct adapter *padapter) pmlmepriv->update_bcn = false; pmlmeext->bstart_bss = false; - /* reset and init security priv , this can refine with rtw_reset_securitypriv */ + /* reset and init security priv , this can refine with + * rtw_reset_securitypriv + */ memset((unsigned char *)&padapter->securitypriv, 0, sizeof(struct security_priv)); padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen; padapter->securitypriv.ndisencryptstatus = Ndis802_11WEPDisabled; diff --git a/drivers/staging/rtl8188eu/core/rtw_cmd.c b/drivers/staging/rtl8188eu/core/rtw_cmd.c index 9754322b506e..002d09159896 100644 --- a/drivers/staging/rtl8188eu/core/rtw_cmd.c +++ b/drivers/staging/rtl8188eu/core/rtw_cmd.c @@ -21,35 +21,33 @@ #include <rtw_mlme_ext.h> /* -Caller and the rtw_cmd_thread can protect cmd_q by spin_lock. -No irqsave is necessary. -*/ + * Caller and the rtw_cmd_thread can protect cmd_q by spin_lock. + * No irqsave is necessary. + */ int rtw_init_cmd_priv(struct cmd_priv *pcmdpriv) { init_completion(&pcmdpriv->cmd_queue_comp); init_completion(&pcmdpriv->terminate_cmdthread_comp); - _rtw_init_queue(&(pcmdpriv->cmd_queue)); + _rtw_init_queue(&pcmdpriv->cmd_queue); return _SUCCESS; } /* -Calling Context: - -rtw_enqueue_cmd can only be called between kernel thread, -since only spin_lock is used. - -ISR/Call-Back functions can't call this sub-function. - -*/ + * Calling Context: + * + * rtw_enqueue_cmd can only be called between kernel thread, + * since only spin_lock is used. + * + * ISR/Call-Back functions can't call this sub-function. + */ static int _rtw_enqueue_cmd(struct __queue *queue, struct cmd_obj *obj) { unsigned long irqL; - - if (obj == NULL) + if (!obj) goto exit; spin_lock_irqsave(&queue->lock, irqL); @@ -60,7 +58,6 @@ static int _rtw_enqueue_cmd(struct __queue *queue, struct cmd_obj *obj) exit: - return _SUCCESS; } @@ -107,8 +104,7 @@ u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj) int res = _FAIL; struct adapter *padapter = pcmdpriv->padapter; - - if (cmd_obj == NULL) + if (!cmd_obj) goto exit; cmd_obj->padapter = padapter; @@ -126,19 +122,17 @@ u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj) exit: - return res; } void rtw_free_cmd_obj(struct cmd_obj *pcmd) { - if ((pcmd->cmdcode != _JoinBss_CMD_) && (pcmd->cmdcode != _CreateBss_CMD_)) { /* free parmbuf in cmd_obj */ kfree(pcmd->parmbuf); } - if (pcmd->rsp != NULL) { + if (!pcmd->rsp) { if (pcmd->rspsz != 0) { /* free rsp in cmd_obj */ kfree(pcmd->rsp); @@ -147,7 +141,6 @@ void rtw_free_cmd_obj(struct cmd_obj *pcmd) /* free cmd_obj */ kfree(pcmd); - } int rtw_cmd_thread(void *context) @@ -157,14 +150,15 @@ int rtw_cmd_thread(void *context) u8 (*cmd_hdl)(struct adapter *padapter, u8 *pbuf); void (*pcmd_callback)(struct adapter *dev, struct cmd_obj *pcmd); struct adapter *padapter = context; - struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; allow_signal(SIGTERM); pcmdpriv->cmdthd_running = true; complete(&pcmdpriv->terminate_cmdthread_comp); - RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("start r871x rtw_cmd_thread !!!!\n")); + RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, + ("start r871x %s !!!!\n", __func__)); while (1) { if (wait_for_completion_interruptible(&pcmdpriv->cmd_queue_comp)) @@ -208,7 +202,7 @@ _next: /* call callback function for post-processed */ if (pcmd->cmdcode < ARRAY_SIZE(rtw_cmd_callback)) { pcmd_callback = rtw_cmd_callback[pcmd->cmdcode].callback; - if (pcmd_callback == NULL) { + if (!pcmd_callback) { RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("mlme_cmd_hdl(): pcmd_callback = 0x%p, cmdcode = 0x%x\n", pcmd_callback, pcmd->cmdcode)); rtw_free_cmd_obj(pcmd); } else { @@ -236,15 +230,15 @@ _next: complete(&pcmdpriv->terminate_cmdthread_comp); - complete_and_exit(NULL, 0); } /* -rtw_sitesurvey_cmd(~) - ### NOTE:#### (!!!!) - MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock -*/ + * rtw_sitesurvey_cmd(~) + * ### NOTE:#### (!!!!) + * MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE + * LOCKED pmlmepriv->lock + */ u8 rtw_sitesurvey_cmd(struct adapter *padapter, struct ndis_802_11_ssid *ssid, int ssid_num, struct rtw_ieee80211_channel *ch, int ch_num) { @@ -315,13 +309,11 @@ u8 rtw_sitesurvey_cmd(struct adapter *padapter, struct ndis_802_11_ssid *ssid, _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY); } - return res; } void rtw_readtssi_cmdrsp_callback(struct adapter *padapter, struct cmd_obj *pcmd) { - kfree(pcmd->parmbuf); kfree(pcmd); } @@ -334,7 +326,6 @@ u8 rtw_createbss_cmd(struct adapter *padapter) struct wlan_bssid_ex *pdev_network = &padapter->registrypriv.dev_network; u8 res = _SUCCESS; - LedControl8188eu(padapter, LED_CTL_START_TO_LINK); if (pmlmepriv->assoc_ssid.SsidLength == 0) @@ -358,7 +349,6 @@ u8 rtw_createbss_cmd(struct adapter *padapter) res = rtw_enqueue_cmd(pcmdpriv, pcmd); exit: - return res; } @@ -376,8 +366,7 @@ u8 rtw_joinbss_cmd(struct adapter *padapter, struct wlan_network *pnetwork) struct ht_priv *phtpriv = &pmlmepriv->htpriv; enum ndis_802_11_network_infra ndis_network_mode = pnetwork->network.InfrastructureMode; struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; LedControl8188eu(padapter, LED_CTL_START_TO_LINK); @@ -394,9 +383,8 @@ u8 rtw_joinbss_cmd(struct adapter *padapter, struct wlan_network *pnetwork) /* for IEs is fix buf size */ t_len = sizeof(struct wlan_bssid_ex); - /* for hidden ap to set fw_state here */ - if (!check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE)) { + if (!check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE)) { switch (ndis_network_mode) { case Ndis802_11IBSS: set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); @@ -412,12 +400,13 @@ u8 rtw_joinbss_cmd(struct adapter *padapter, struct wlan_network *pnetwork) } psecnetwork = (struct wlan_bssid_ex *)&psecuritypriv->sec_bss; - if (psecnetwork == NULL) { + if (!psecnetwork) { kfree(pcmd); res = _FAIL; - RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("rtw_joinbss_cmd :psecnetwork == NULL!!!\n")); + RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, + ("%s :psecnetwork == NULL!!!\n", __func__)); goto exit; } @@ -444,7 +433,6 @@ u8 rtw_joinbss_cmd(struct adapter *padapter, struct wlan_network *pnetwork) psecnetwork->IELength = rtw_restruct_sec_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], pnetwork->network.IELength); - pqospriv->qos_option = 0; if (pregistrypriv->wmm_enable) { @@ -498,7 +486,6 @@ u8 rtw_joinbss_cmd(struct adapter *padapter, struct wlan_network *pnetwork) exit: - return res; } @@ -509,8 +496,7 @@ u8 rtw_disassoc_cmd(struct adapter *padapter, u32 deauth_timeout_ms, bool enqueu struct cmd_priv *cmdpriv = &padapter->cmdpriv; u8 res = _SUCCESS; - - RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_disassoc_cmd\n")); + RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+%s\n", __func__)); /* prepare cmd parameter */ param = kzalloc(sizeof(*param), GFP_KERNEL); @@ -539,7 +525,6 @@ u8 rtw_disassoc_cmd(struct adapter *padapter, u32 deauth_timeout_ms, bool enqueu exit: - return res; } @@ -617,7 +602,6 @@ u8 rtw_clearstakey_cmd(struct adapter *padapter, u8 *psta, u8 entry, u8 enqueue) struct sta_info *sta = (struct sta_info *)psta; u8 res = _SUCCESS; - if (!enqueue) { clear_cam_entry(padapter, entry); } else { @@ -656,7 +640,6 @@ u8 rtw_clearstakey_cmd(struct adapter *padapter, u8 *psta, u8 entry, u8 enqueue) } exit: - return res; } @@ -667,7 +650,6 @@ u8 rtw_addbareq_cmd(struct adapter *padapter, u8 tid, u8 *addr) struct addBaReq_parm *paddbareq_parm; u8 res = _SUCCESS; - ph2c = kzalloc(sizeof(struct cmd_obj), GFP_ATOMIC); if (!ph2c) { res = _FAIL; @@ -693,7 +675,6 @@ u8 rtw_addbareq_cmd(struct adapter *padapter, u8 tid, u8 *addr) exit: - return res; } @@ -704,7 +685,6 @@ u8 rtw_dynamic_chk_wk_cmd(struct adapter *padapter) struct cmd_priv *pcmdpriv = &padapter->cmdpriv; u8 res = _SUCCESS; - ph2c = kzalloc(sizeof(struct cmd_obj), GFP_ATOMIC); if (!ph2c) { res = _FAIL; @@ -724,7 +704,6 @@ u8 rtw_dynamic_chk_wk_cmd(struct adapter *padapter) init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, _Set_Drv_Extra_CMD_); - /* rtw_enqueue_cmd(pcmdpriv, ph2c); */ res = rtw_enqueue_cmd(pcmdpriv, ph2c); exit: @@ -739,8 +718,7 @@ u8 rtw_set_chplan_cmd(struct adapter *padapter, u8 chplan, u8 enqueue) u8 res = _SUCCESS; - - RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_set_chplan_cmd\n")); + RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+%s\n", __func__)); /* check input parameter */ if (!rtw_is_channel_plan_valid(chplan)) { @@ -781,7 +759,6 @@ u8 rtw_set_chplan_cmd(struct adapter *padapter, u8 chplan, u8 enqueue) exit: - return res; } @@ -790,7 +767,7 @@ static void traffic_status_watchdog(struct adapter *padapter) u8 bEnterPS; u8 bBusyTraffic = false, bTxBusyTraffic = false, bRxBusyTraffic = false; u8 bHigherBusyTraffic = false, bHigherBusyRxTraffic = false, bHigherBusyTxTraffic = false; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; /* */ /* Determine if our traffic is busy now */ @@ -849,7 +826,7 @@ static void dynamic_chk_wk_hdl(struct adapter *padapter, u8 *pbuf, int sz) struct mlme_priv *pmlmepriv; padapter = (struct adapter *)pbuf; - pmlmepriv = &(padapter->mlmepriv); + pmlmepriv = &padapter->mlmepriv; #ifdef CONFIG_88EU_AP_MODE if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == true) @@ -865,10 +842,9 @@ static void dynamic_chk_wk_hdl(struct adapter *padapter, u8 *pbuf, int sz) static void lps_ctrl_wk_hdl(struct adapter *padapter, u8 lps_ctrl_type) { struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; - struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; u8 mstatus; - if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == true) || (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == true)) return; @@ -905,7 +881,6 @@ static void lps_ctrl_wk_hdl(struct adapter *padapter, u8 lps_ctrl_type) default: break; } - } u8 rtw_lps_ctrl_wk_cmd(struct adapter *padapter, u8 lps_ctrl_type, u8 enqueue) @@ -943,7 +918,6 @@ u8 rtw_lps_ctrl_wk_cmd(struct adapter *padapter, u8 lps_ctrl_type, u8 enqueue) exit: - return res; } @@ -980,7 +954,6 @@ u8 rtw_rpt_timer_cfg_cmd(struct adapter *padapter, u16 min_time) res = rtw_enqueue_cmd(pcmdpriv, ph2c); exit: - return res; } @@ -1026,7 +999,6 @@ u8 rtw_antenna_select_cmd(struct adapter *padapter, u8 antenna, u8 enqueue) } exit: - return res; } @@ -1169,7 +1141,6 @@ void rtw_survey_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd) { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - if (pcmd->res == H2C_DROPPED) { /* TODO: cancel timer and do timeout handler directly... */ /* need to make timeout handlerOS independent */ @@ -1183,13 +1154,12 @@ void rtw_survey_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd) /* free cmd */ rtw_free_cmd_obj(pcmd); - } + void rtw_disassoc_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd) { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - if (pcmd->res != H2C_SUCCESS) { spin_lock_bh(&pmlmepriv->lock); set_fwstate(pmlmepriv, _FW_LINKED); @@ -1207,7 +1177,6 @@ void rtw_joinbss_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd) { struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - if (pcmd->res == H2C_DROPPED) { /* TODO: cancel timer and do timeout handler directly... */ /* need to make timeout handlerOS independent */ @@ -1220,7 +1189,6 @@ void rtw_joinbss_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd) } rtw_free_cmd_obj(pcmd); - } void rtw_createbss_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd) @@ -1229,11 +1197,11 @@ void rtw_createbss_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd) struct wlan_network *pwlan = NULL; struct mlme_priv *pmlmepriv = &padapter->mlmepriv; struct wlan_bssid_ex *pnetwork = (struct wlan_bssid_ex *)pcmd->parmbuf; - struct wlan_network *tgt_network = &(pmlmepriv->cur_network); - + struct wlan_network *tgt_network = &pmlmepriv->cur_network; if (pcmd->res != H2C_SUCCESS) { - RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("\n ********Error: rtw_createbss_cmd_callback Fail ************\n\n.")); + RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, + ("\n **** Error: %s Fail ****\n\n.", __func__)); mod_timer(&pmlmepriv->assoc_timer, jiffies + msecs_to_jiffies(1)); } @@ -1246,7 +1214,7 @@ void rtw_createbss_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd) psta = rtw_get_stainfo(&padapter->stapriv, pnetwork->MacAddress); if (!psta) { psta = rtw_alloc_stainfo(&padapter->stapriv, pnetwork->MacAddress); - if (psta == NULL) { + if (!psta) { RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("\nCan't alloc sta_info when createbss_cmd_callback\n")); goto createbss_cmd_fail; } @@ -1255,28 +1223,31 @@ void rtw_createbss_cmd_callback(struct adapter *padapter, struct cmd_obj *pcmd) rtw_indicate_connect(padapter); } else { pwlan = _rtw_alloc_network(pmlmepriv); - spin_lock_bh(&(pmlmepriv->scanned_queue.lock)); - if (pwlan == NULL) { + spin_lock_bh(&pmlmepriv->scanned_queue.lock); + if (!pwlan) { pwlan = rtw_get_oldest_wlan_network(&pmlmepriv->scanned_queue); - if (pwlan == NULL) { + if (!pwlan) { RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("\n Error: can't get pwlan in rtw_joinbss_event_callback\n")); spin_unlock_bh(&pmlmepriv->scanned_queue.lock); goto createbss_cmd_fail; } pwlan->last_scanned = jiffies; } else { - list_add_tail(&(pwlan->list), &pmlmepriv->scanned_queue.queue); + list_add_tail(&pwlan->list, + &pmlmepriv->scanned_queue.queue); } pnetwork->Length = get_wlan_bssid_ex_sz(pnetwork); - memcpy(&(pwlan->network), pnetwork, pnetwork->Length); + memcpy(&pwlan->network, pnetwork, pnetwork->Length); memcpy(&tgt_network->network, pnetwork, (get_wlan_bssid_ex_sz(pnetwork))); _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); spin_unlock_bh(&pmlmepriv->scanned_queue.lock); - /* we will set _FW_LINKED when there is one more sat to join us (rtw_stassoc_event_callback) */ + /* we will set _FW_LINKED when there is one more sat to + * join us (rtw_stassoc_event_callback) + */ } createbss_cmd_fail: @@ -1284,7 +1255,6 @@ createbss_cmd_fail: spin_unlock_bh(&pmlmepriv->lock); rtw_free_cmd_obj(pcmd); - } void rtw_setstaKey_cmdrsp_callback(struct adapter *padapter, struct cmd_obj *pcmd) @@ -1293,8 +1263,7 @@ void rtw_setstaKey_cmdrsp_callback(struct adapter *padapter, struct cmd_obj *pc struct set_stakey_rsp *psetstakey_rsp = (struct set_stakey_rsp *)(pcmd->rsp); struct sta_info *psta = rtw_get_stainfo(pstapriv, psetstakey_rsp->addr); - - if (psta == NULL) { + if (!psta) { RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("\nERROR: %s => can't get sta_info\n\n", __func__)); goto exit; } @@ -1310,8 +1279,7 @@ void rtw_setassocsta_cmdrsp_callback(struct adapter *padapter, struct cmd_obj * struct set_assocsta_rsp *passocsta_rsp = (struct set_assocsta_rsp *)(pcmd->rsp); struct sta_info *psta = rtw_get_stainfo(pstapriv, passocsta_parm->addr); - - if (psta == NULL) { + if (!psta) { RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("\nERROR: %s => can't get sta_info\n\n", __func__)); goto exit; } @@ -1326,5 +1294,4 @@ void rtw_setassocsta_cmdrsp_callback(struct adapter *padapter, struct cmd_obj * exit: rtw_free_cmd_obj(pcmd); - } diff --git a/drivers/staging/rtl8188eu/core/rtw_ieee80211.c b/drivers/staging/rtl8188eu/core/rtw_ieee80211.c index d1dafe0f20c6..bb867a987c2b 100644 --- a/drivers/staging/rtl8188eu/core/rtw_ieee80211.c +++ b/drivers/staging/rtl8188eu/core/rtw_ieee80211.c @@ -955,50 +955,6 @@ void rtw_macaddr_cfg(u8 *mac_addr) DBG_88E("rtw_macaddr_cfg MAC Address = %pM\n", (mac_addr)); } -/* Baron adds to avoid FreeBSD warning */ -int ieee80211_is_empty_essid(const char *essid, int essid_len) -{ - /* Single white space is for Linksys APs */ - if (essid_len == 1 && essid[0] == ' ') - return 1; - - /* Otherwise, if the entire essid is 0, we assume it is hidden */ - while (essid_len) { - essid_len--; - if (essid[essid_len] != '\0') - return 0; - } - - return 1; -} - -int ieee80211_get_hdrlen(u16 fc) -{ - int hdrlen = 24; - - switch (WLAN_FC_GET_TYPE(fc)) { - case RTW_IEEE80211_FTYPE_DATA: - if (fc & RTW_IEEE80211_STYPE_QOS_DATA) - hdrlen += 2; - if ((fc & RTW_IEEE80211_FCTL_FROMDS) && (fc & RTW_IEEE80211_FCTL_TODS)) - hdrlen += 6; /* Addr4 */ - break; - case RTW_IEEE80211_FTYPE_CTL: - switch (WLAN_FC_GET_STYPE(fc)) { - case RTW_IEEE80211_STYPE_CTS: - case RTW_IEEE80211_STYPE_ACK: - hdrlen = 10; - break; - default: - hdrlen = 16; - break; - } - break; - } - - return hdrlen; -} - static int rtw_get_cipher_info(struct wlan_network *pnetwork) { uint wpa_ielen; diff --git a/drivers/staging/rtl8188eu/core/rtw_mlme.c b/drivers/staging/rtl8188eu/core/rtw_mlme.c index 301085a459c9..fde306087844 100644 --- a/drivers/staging/rtl8188eu/core/rtw_mlme.c +++ b/drivers/staging/rtl8188eu/core/rtw_mlme.c @@ -370,7 +370,7 @@ void update_network(struct wlan_bssid_ex *dst, struct wlan_bssid_ex *src, sq_final = padapter->recvpriv.signal_qual; /* the rssi value here is undecorated, and will be used for antenna diversity */ if (sq_smp != 101) /* from the right channel */ - rssi_final = (src->Rssi+dst->Rssi*4)/5; + rssi_final = (src->Rssi + dst->Rssi * 4) / 5; else rssi_final = rssi_ori; } else { @@ -1081,10 +1081,10 @@ void rtw_joinbss_event_prehandle(struct adapter *adapter, u8 *pbuf) RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("adhoc mode, fw_state:%x", get_fwstate(pmlmepriv))); } - /* s5. Cancle assoc_timer */ + /* s5. Cancel assoc_timer */ del_timer_sync(&pmlmepriv->assoc_timer); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("Cancle assoc_timer\n")); + RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("Cancel assoc_timer\n")); } else { RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("rtw_joinbss_event_callback err: fw_state:%x", get_fwstate(pmlmepriv))); @@ -1926,7 +1926,7 @@ unsigned int rtw_restructure_ht_ie(struct adapter *padapter, u8 *in_ie, u8 *out_ if (pqospriv->qos_option == 0) { out_len = *pout_len; - rtw_set_ie(out_ie+out_len, _VENDOR_SPECIFIC_IE_, + rtw_set_ie(out_ie + out_len, _VENDOR_SPECIFIC_IE_, _WMM_IE_Length_, WMM_IE, pout_len); pqospriv->qos_option = 1; @@ -2058,8 +2058,8 @@ void rtw_issue_addbareq_cmd(struct adapter *padapter, struct xmit_frame *pxmitfr phtpriv = &psta->htpriv; if ((phtpriv->ht_option) && (phtpriv->ampdu_enable)) { - issued = (phtpriv->agg_enable_bitmap>>priority)&0x1; - issued |= (phtpriv->candidate_tid_bitmap>>priority)&0x1; + issued = (phtpriv->agg_enable_bitmap >> priority) & 0x1; + issued |= (phtpriv->candidate_tid_bitmap >> priority) & 0x1; if (issued == 0) { DBG_88E("rtw_issue_addbareq_cmd, p=%d\n", priority); diff --git a/drivers/staging/rtl8188eu/core/rtw_recv.c b/drivers/staging/rtl8188eu/core/rtw_recv.c index c6c4404e717b..2c37bb548c0f 100644 --- a/drivers/staging/rtl8188eu/core/rtw_recv.c +++ b/drivers/staging/rtl8188eu/core/rtw_recv.c @@ -259,12 +259,10 @@ static int recvframe_chkmic(struct adapter *adapter, } /* icv_len included the mic code */ - datalen = precvframe->pkt->len-prxattrib->hdrlen - - prxattrib->iv_len-prxattrib->icv_len-8; + datalen = precvframe->pkt->len-prxattrib->hdrlen - 8; pframe = precvframe->pkt->data; - payload = pframe+prxattrib->hdrlen+prxattrib->iv_len; + payload = pframe+prxattrib->hdrlen; - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("\n prxattrib->iv_len=%d prxattrib->icv_len=%d\n", prxattrib->iv_len, prxattrib->icv_len)); rtw_seccalctkipmic(mickey, pframe, payload, datalen, &miccode[0], (unsigned char)prxattrib->priority); /* care the length of the data */ @@ -409,9 +407,15 @@ static struct recv_frame *decryptor(struct adapter *padapter, default: break; } + if (res != _FAIL) { + memmove(precv_frame->pkt->data + precv_frame->attrib.iv_len, precv_frame->pkt->data, precv_frame->attrib.hdrlen); + skb_pull(precv_frame->pkt, precv_frame->attrib.iv_len); + skb_trim(precv_frame->pkt, precv_frame->pkt->len - precv_frame->attrib.icv_len); + } } else if (prxattrib->bdecrypted == 1 && prxattrib->encrypt > 0 && - (psecuritypriv->busetkipkey == 1 || prxattrib->encrypt != _TKIP_)) - psecuritypriv->hw_decrypted = true; + (psecuritypriv->busetkipkey == 1 || prxattrib->encrypt != _TKIP_)) { + psecuritypriv->hw_decrypted = true; + } if (res == _FAIL) { rtw_free_recvframe(return_packet, &padapter->recvpriv.free_recv_queue); @@ -452,7 +456,7 @@ static struct recv_frame *portctrl(struct adapter *adapter, if (auth_alg == 2) { /* get ether_type */ - ptr = ptr + pfhdr->attrib.hdrlen + LLC_HEADER_SIZE + pfhdr->attrib.iv_len; + ptr = ptr + pfhdr->attrib.hdrlen + LLC_HEADER_SIZE; memcpy(&be_tmp, ptr, 2); ether_type = ntohs(be_tmp); @@ -1134,6 +1138,8 @@ static int validate_recv_data_frame(struct adapter *adapter, } if (pattrib->privacy) { + struct sk_buff *skb = precv_frame->pkt; + RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("validate_recv_data_frame:pattrib->privacy=%x\n", pattrib->privacy)); RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("\n ^^^^^^^^^^^IS_MCAST(pattrib->ra(0x%02x))=%d^^^^^^^^^^^^^^^6\n", pattrib->ra[0], IS_MCAST(pattrib->ra))); @@ -1142,6 +1148,13 @@ static int validate_recv_data_frame(struct adapter *adapter, RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("\n pattrib->encrypt=%d\n", pattrib->encrypt)); SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt); + + if (pattrib->bdecrypted == 1 && pattrib->encrypt > 0) { + memmove(skb->data + pattrib->iv_len, + skb->data, pattrib->hdrlen); + skb_pull(skb, pattrib->iv_len); + skb_trim(skb, skb->len - pattrib->icv_len); + } } else { pattrib->encrypt = 0; pattrib->iv_len = 0; @@ -1261,6 +1274,7 @@ static int validate_recv_frame(struct adapter *adapter, * Hence forward the frame to the monitor anyway to preserve the order * in which frames were received. */ + rtl88eu_mon_recv_hook(adapter->pmondev, precv_frame); exit: @@ -1282,11 +1296,8 @@ static int wlanhdr_to_ethhdr(struct recv_frame *precvframe) u8 *ptr = precvframe->pkt->data; struct rx_pkt_attrib *pattrib = &precvframe->attrib; - if (pattrib->encrypt) - skb_trim(precvframe->pkt, precvframe->pkt->len - pattrib->icv_len); - - psnap = (struct ieee80211_snap_hdr *)(ptr+pattrib->hdrlen + pattrib->iv_len); - psnap_type = ptr+pattrib->hdrlen + pattrib->iv_len+SNAP_SIZE; + psnap = (struct ieee80211_snap_hdr *)(ptr+pattrib->hdrlen); + psnap_type = ptr+pattrib->hdrlen + SNAP_SIZE; /* convert hdr + possible LLC headers into Ethernet header */ if ((!memcmp(psnap, rtw_rfc1042_header, SNAP_SIZE) && (!memcmp(psnap_type, SNAP_ETH_TYPE_IPX, 2) == false) && @@ -1299,12 +1310,9 @@ static int wlanhdr_to_ethhdr(struct recv_frame *precvframe) bsnaphdr = false; } - rmv_len = pattrib->hdrlen + pattrib->iv_len + (bsnaphdr ? SNAP_SIZE : 0); + rmv_len = pattrib->hdrlen + (bsnaphdr ? SNAP_SIZE : 0); len = precvframe->pkt->len - rmv_len; - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, - ("\n===pattrib->hdrlen: %x, pattrib->iv_len:%x===\n\n", pattrib->hdrlen, pattrib->iv_len)); - memcpy(&be_tmp, ptr+rmv_len, 2); eth_type = ntohs(be_tmp); /* pattrib->ether_type */ pattrib->eth_type = eth_type; @@ -1329,7 +1337,6 @@ static struct recv_frame *recvframe_defrag(struct adapter *adapter, struct __queue *defrag_q) { struct list_head *plist, *phead; - u8 wlanhdr_offset; u8 curfragnum; struct recv_frame *pfhdr, *pnfhdr; struct recv_frame *prframe, *pnextrframe; @@ -1378,12 +1385,7 @@ static struct recv_frame *recvframe_defrag(struct adapter *adapter, /* copy the 2nd~n fragment frame's payload to the first fragment */ /* get the 2nd~last fragment frame's payload */ - wlanhdr_offset = pnfhdr->attrib.hdrlen + pnfhdr->attrib.iv_len; - - skb_pull(pnextrframe->pkt, wlanhdr_offset); - - /* append to first fragment frame's tail (if privacy frame, pull the ICV) */ - skb_trim(prframe->pkt, prframe->pkt->len - pfhdr->attrib.icv_len); + skb_pull(pnextrframe->pkt, pnfhdr->attrib.hdrlen); /* memcpy */ memcpy(skb_tail_pointer(pfhdr->pkt), pnfhdr->pkt->data, @@ -1391,7 +1393,7 @@ static struct recv_frame *recvframe_defrag(struct adapter *adapter, skb_put(prframe->pkt, pnfhdr->pkt->len); - pfhdr->attrib.icv_len = pnfhdr->attrib.icv_len; + pfhdr->attrib.icv_len = 0; plist = plist->next; } @@ -1518,11 +1520,6 @@ static int amsdu_to_msdu(struct adapter *padapter, struct recv_frame *prframe) nr_subframes = 0; pattrib = &prframe->attrib; - skb_pull(prframe->pkt, prframe->attrib.hdrlen); - - if (prframe->attrib.iv_len > 0) - skb_pull(prframe->pkt, prframe->attrib.iv_len); - a_len = prframe->pkt->len; pdata = prframe->pkt->data; @@ -1892,24 +1889,6 @@ static int process_recv_indicatepkts(struct adapter *padapter, return retval; } -static int recv_func_prehandle(struct adapter *padapter, - struct recv_frame *rframe) -{ - int ret = _SUCCESS; - struct __queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; - - /* check the frame crtl field and decache */ - ret = validate_recv_frame(padapter, rframe); - if (ret != _SUCCESS) { - RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("recv_func: validate_recv_frame fail! drop pkt\n")); - rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */ - goto exit; - } - -exit: - return ret; -} - static int recv_func_posthandle(struct adapter *padapter, struct recv_frame *prframe) { @@ -1962,6 +1941,7 @@ static int recv_func(struct adapter *padapter, struct recv_frame *rframe) struct rx_pkt_attrib *prxattrib = &rframe->attrib; struct security_priv *psecuritypriv = &padapter->securitypriv; struct mlme_priv *mlmepriv = &padapter->mlmepriv; + struct __queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; /* check if need to handle uc_swdec_pending_queue*/ if (check_fwstate(mlmepriv, WIFI_STATION_STATE) && psecuritypriv->busetkipkey) { @@ -1973,9 +1953,12 @@ static int recv_func(struct adapter *padapter, struct recv_frame *rframe) } } - ret = recv_func_prehandle(padapter, rframe); - - if (ret == _SUCCESS) { + /* check the frame crtl field and decache */ + ret = validate_recv_frame(padapter, rframe); + if (ret != _SUCCESS) { + RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("recv_func: validate_recv_frame fail! drop pkt\n")); + rtw_free_recvframe(rframe, pfree_recv_queue);/* free this recv_frame */ + } else { /* check if need to enqueue into uc_swdec_pending_queue*/ if (check_fwstate(mlmepriv, WIFI_STATION_STATE) && !IS_MCAST(prxattrib->ra) && prxattrib->encrypt > 0 && diff --git a/drivers/staging/rtl8188eu/core/rtw_sta_mgt.c b/drivers/staging/rtl8188eu/core/rtw_sta_mgt.c index 2ecfb117bf3f..22cf362b8528 100644 --- a/drivers/staging/rtl8188eu/core/rtw_sta_mgt.c +++ b/drivers/staging/rtl8188eu/core/rtw_sta_mgt.c @@ -61,7 +61,6 @@ static void _rtw_init_stainfo(struct sta_info *psta) psta->keep_alive_trycnt = 0; #endif /* CONFIG_88EU_AP_MODE */ - } u32 _rtw_init_sta_priv(struct sta_priv *pstapriv) @@ -69,7 +68,6 @@ u32 _rtw_init_sta_priv(struct sta_priv *pstapriv) struct sta_info *psta; s32 i; - pstapriv->pallocated_stainfo_buf = vzalloc(sizeof(struct sta_info) * NUM_STA + 4); if (!pstapriv->pallocated_stainfo_buf) @@ -116,7 +114,6 @@ u32 _rtw_init_sta_priv(struct sta_priv *pstapriv) pstapriv->max_num_sta = NUM_STA; #endif - return _SUCCESS; } @@ -263,7 +260,6 @@ u32 rtw_free_stainfo(struct adapter *padapter, struct sta_info *psta) struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct sta_priv *pstapriv = &padapter->stapriv; - if (!psta) goto exit; @@ -381,7 +377,6 @@ u32 rtw_free_stainfo(struct adapter *padapter, struct sta_info *psta) exit: - return _SUCCESS; } @@ -394,7 +389,6 @@ void rtw_free_all_stainfo(struct adapter *padapter) struct sta_priv *pstapriv = &padapter->stapriv; struct sta_info *pbcmc_stainfo = rtw_get_bcmc_stainfo(padapter); - if (pstapriv->asoc_sta_count == 1) return; @@ -425,7 +419,6 @@ struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) u8 *addr; u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - if (!hwaddr) return NULL; @@ -463,7 +456,6 @@ u32 rtw_init_bcmc_stainfo(struct adapter *padapter) unsigned char bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; struct sta_priv *pstapriv = &padapter->stapriv; - psta = rtw_alloc_stainfo(pstapriv, bcast_addr); if (!psta) { diff --git a/drivers/staging/rtl8188eu/hal/phy.c b/drivers/staging/rtl8188eu/hal/phy.c index 054f5996f60d..3039bbe44a25 100644 --- a/drivers/staging/rtl8188eu/hal/phy.c +++ b/drivers/staging/rtl8188eu/hal/phy.c @@ -1091,7 +1091,7 @@ static void phy_iq_calibrate(struct adapter *adapt, s32 result[][8], } } - if (0x00 == path_a_ok) { + if (path_a_ok == 0x00) { ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n")); } @@ -1122,7 +1122,7 @@ static void phy_iq_calibrate(struct adapter *adapt, s32 result[][8], } } - if (0x00 == path_b_ok) { + if (path_b_ok == 0x00) { ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); } diff --git a/drivers/staging/rtl8188eu/hal/rtl8188e_rxdesc.c b/drivers/staging/rtl8188eu/hal/rtl8188e_rxdesc.c index d9fa290c5f78..9f51f54f866a 100644 --- a/drivers/staging/rtl8188eu/hal/rtl8188e_rxdesc.c +++ b/drivers/staging/rtl8188eu/hal/rtl8188e_rxdesc.c @@ -58,7 +58,7 @@ static void process_link_qual(struct adapter *padapter, } void rtl8188e_process_phy_info(struct adapter *padapter, - struct recv_frame *precvframe) + struct recv_frame *precvframe) { /* Check RSSI */ process_rssi(padapter, precvframe); diff --git a/drivers/staging/rtl8188eu/include/ieee80211.h b/drivers/staging/rtl8188eu/include/ieee80211.h index 22ab0c43e376..284db7d00f50 100644 --- a/drivers/staging/rtl8188eu/include/ieee80211.h +++ b/drivers/staging/rtl8188eu/include/ieee80211.h @@ -306,68 +306,6 @@ enum eap_type { #define MIN_FRAG_THRESHOLD 256U #define MAX_FRAG_THRESHOLD 2346U -/* Frame control field constants */ -#define RTW_IEEE80211_FCTL_VERS 0x0003 -#define RTW_IEEE80211_FCTL_FTYPE 0x000c -#define RTW_IEEE80211_FCTL_STYPE 0x00f0 -#define RTW_IEEE80211_FCTL_TODS 0x0100 -#define RTW_IEEE80211_FCTL_FROMDS 0x0200 -#define RTW_IEEE80211_FCTL_MOREFRAGS 0x0400 -#define RTW_IEEE80211_FCTL_RETRY 0x0800 -#define RTW_IEEE80211_FCTL_PM 0x1000 -#define RTW_IEEE80211_FCTL_MOREDATA 0x2000 -#define RTW_IEEE80211_FCTL_PROTECTED 0x4000 -#define RTW_IEEE80211_FCTL_ORDER 0x8000 -#define RTW_IEEE80211_FCTL_CTL_EXT 0x0f00 - -#define RTW_IEEE80211_FTYPE_MGMT 0x0000 -#define RTW_IEEE80211_FTYPE_CTL 0x0004 -#define RTW_IEEE80211_FTYPE_DATA 0x0008 -#define RTW_IEEE80211_FTYPE_EXT 0x000c - -/* management */ -#define RTW_IEEE80211_STYPE_ASSOC_REQ 0x0000 -#define RTW_IEEE80211_STYPE_ASSOC_RESP 0x0010 -#define RTW_IEEE80211_STYPE_REASSOC_REQ 0x0020 -#define RTW_IEEE80211_STYPE_REASSOC_RESP 0x0030 -#define RTW_IEEE80211_STYPE_PROBE_REQ 0x0040 -#define RTW_IEEE80211_STYPE_PROBE_RESP 0x0050 -#define RTW_IEEE80211_STYPE_BEACON 0x0080 -#define RTW_IEEE80211_STYPE_ATIM 0x0090 -#define RTW_IEEE80211_STYPE_DISASSOC 0x00A0 -#define RTW_IEEE80211_STYPE_AUTH 0x00B0 -#define RTW_IEEE80211_STYPE_DEAUTH 0x00C0 -#define RTW_IEEE80211_STYPE_ACTION 0x00D0 - -/* control */ -#define RTW_IEEE80211_STYPE_CTL_EXT 0x0060 -#define RTW_IEEE80211_STYPE_BACK_REQ 0x0080 -#define RTW_IEEE80211_STYPE_BACK 0x0090 -#define RTW_IEEE80211_STYPE_PSPOLL 0x00A0 -#define RTW_IEEE80211_STYPE_RTS 0x00B0 -#define RTW_IEEE80211_STYPE_CTS 0x00C0 -#define RTW_IEEE80211_STYPE_ACK 0x00D0 -#define RTW_IEEE80211_STYPE_CFEND 0x00E0 -#define RTW_IEEE80211_STYPE_CFENDACK 0x00F0 - -/* data */ -#define RTW_IEEE80211_STYPE_DATA 0x0000 -#define RTW_IEEE80211_STYPE_DATA_CFACK 0x0010 -#define RTW_IEEE80211_STYPE_DATA_CFPOLL 0x0020 -#define RTW_IEEE80211_STYPE_DATA_CFACKPOLL 0x0030 -#define RTW_IEEE80211_STYPE_NULLFUNC 0x0040 -#define RTW_IEEE80211_STYPE_CFACK 0x0050 -#define RTW_IEEE80211_STYPE_CFPOLL 0x0060 -#define RTW_IEEE80211_STYPE_CFACKPOLL 0x0070 -#define RTW_IEEE80211_STYPE_QOS_DATA 0x0080 -#define RTW_IEEE80211_STYPE_QOS_DATA_CFACK 0x0090 -#define RTW_IEEE80211_STYPE_QOS_DATA_CFPOLL 0x00A0 -#define RTW_IEEE80211_STYPE_QOS_DATA_CFACKPOLL 0x00B0 -#define RTW_IEEE80211_STYPE_QOS_NULLFUNC 0x00C0 -#define RTW_IEEE80211_STYPE_QOS_CFACK 0x00D0 -#define RTW_IEEE80211_STYPE_QOS_CFPOLL 0x00E0 -#define RTW_IEEE80211_STYPE_QOS_CFACKPOLL 0x00F0 - /* sequence control field */ #define RTW_IEEE80211_SCTL_FRAG 0x000F #define RTW_IEEE80211_SCTL_SEQ 0xFFF0 @@ -408,9 +346,6 @@ struct ieee80211_snap_hdr { #define SNAP_SIZE sizeof(struct ieee80211_snap_hdr) -#define WLAN_FC_GET_TYPE(fc) ((fc) & RTW_IEEE80211_FCTL_FTYPE) -#define WLAN_FC_GET_STYPE(fc) ((fc) & RTW_IEEE80211_FCTL_STYPE) - #define WLAN_QC_GET_TID(qc) ((qc) & 0x0f) #define WLAN_GET_SEQ_FRAG(seq) ((seq) & RTW_IEEE80211_SCTL_FRAG) @@ -423,14 +358,6 @@ struct ieee80211_snap_hdr { #define IEEE80211_DATA_HDR3_LEN 24 #define IEEE80211_DATA_HDR4_LEN 30 - -#define IEEE80211_STATMASK_SIGNAL (1<<0) -#define IEEE80211_STATMASK_RSSI (1<<1) -#define IEEE80211_STATMASK_NOISE (1<<2) -#define IEEE80211_STATMASK_RATE (1<<3) -#define IEEE80211_STATMASK_WEMASK 0x7 - - #define IEEE80211_CCK_MODULATION (1<<0) #define IEEE80211_OFDM_MODULATION (1<<1) @@ -488,9 +415,6 @@ struct ieee80211_snap_hdr { IEEE80211_OFDM_RATE_36MB_MASK | \ IEEE80211_OFDM_RATE_48MB_MASK | \ IEEE80211_OFDM_RATE_54MB_MASK) -#define IEEE80211_DEFAULT_RATES_MASK \ - (IEEE80211_OFDM_DEFAULT_RATES_MASK | \ - IEEE80211_CCK_DEFAULT_RATES_MASK) #define IEEE80211_NUM_OFDM_RATES 8 #define IEEE80211_NUM_CCK_RATES 4 @@ -521,25 +445,6 @@ struct ieee80211_snap_hdr { #define WEP_KEYS 4 #define WEP_KEY_LEN 13 -#define BEACON_PROBE_SSID_ID_POSITION 12 - -/* Management Frame Information Element Types */ -#define MFIE_TYPE_SSID 0 -#define MFIE_TYPE_RATES 1 -#define MFIE_TYPE_FH_SET 2 -#define MFIE_TYPE_DS_SET 3 -#define MFIE_TYPE_CF_SET 4 -#define MFIE_TYPE_TIM 5 -#define MFIE_TYPE_IBSS_SET 6 -#define MFIE_TYPE_CHALLENGE 16 -#define MFIE_TYPE_ERP 42 -#define MFIE_TYPE_RSN 48 -#define MFIE_TYPE_RATES_EX 50 -#define MFIE_TYPE_GENERIC 221 - -#define IEEE80211_DEFAULT_TX_ESSID "Penguin" -#define IEEE80211_DEFAULT_BASIC_RATE 10 - /* SWEEP TABLE ENTRIES NUMBER*/ #define MAX_SWEEP_TAB_ENTRIES 42 #define MAX_SWEEP_TAB_ENTRIES_PER_PACKET 7 @@ -566,14 +471,6 @@ struct ieee80211_snap_hdr { #define NETWORK_HAS_OFDM (1<<1) #define NETWORK_HAS_CCK (1<<2) -#define IEEE80211_DTIM_MBCAST 4 -#define IEEE80211_DTIM_UCAST 2 -#define IEEE80211_DTIM_VALID 1 -#define IEEE80211_DTIM_INVALID 0 - -#define IEEE80211_PS_DISABLED 0 -#define IEEE80211_PS_UNICAST IEEE80211_DTIM_UCAST -#define IEEE80211_PS_MBCAST IEEE80211_DTIM_MBCAST #define IW_ESSID_MAX_SIZE 32 /* join_res: @@ -644,10 +541,6 @@ static inline int is_broadcast_mac_addr(const u8 *addr) #define IEEE_G (1<<2) #define IEEE_MODE_MASK (IEEE_A|IEEE_B|IEEE_G) -/* Baron move to ieee80211.c */ -int ieee80211_is_empty_essid(const char *essid, int essid_len); -int ieee80211_get_hdrlen(u16 fc); - /* Action category code */ enum rtw_ieee80211_category { RTW_WLAN_CATEGORY_SPECTRUM_MGMT = 0, diff --git a/drivers/staging/rtl8188eu/os_dep/mon.c b/drivers/staging/rtl8188eu/os_dep/mon.c index 859d0d6051cd..7326d9b0fa7f 100644 --- a/drivers/staging/rtl8188eu/os_dep/mon.c +++ b/drivers/staging/rtl8188eu/os_dep/mon.c @@ -66,6 +66,34 @@ static void mon_recv_decrypted(struct net_device *dev, const u8 *data, netif_rx(skb); } +static void mon_recv_decrypted_recv(struct net_device *dev, const u8 *data, + int data_len) +{ + struct sk_buff *skb; + struct ieee80211_hdr *hdr; + int hdr_len; + + skb = netdev_alloc_skb(dev, data_len); + if (!skb) + return; + memcpy(skb_put(skb, data_len), data, data_len); + + /* + * Frame data is not encrypted. Strip off protection so + * userspace doesn't think that it is. + */ + + hdr = (struct ieee80211_hdr *)skb->data; + hdr_len = ieee80211_hdrlen(hdr->frame_control); + + if (ieee80211_has_protected(hdr->frame_control)) + hdr->frame_control &= ~cpu_to_le16(IEEE80211_FCTL_PROTECTED); + + skb->ip_summed = CHECKSUM_UNNECESSARY; + skb->protocol = eth_type_trans(skb, dev); + netif_rx(skb); +} + static void mon_recv_encrypted(struct net_device *dev, const u8 *data, int data_len) { @@ -82,7 +110,6 @@ static void mon_recv_encrypted(struct net_device *dev, const u8 *data, void rtl88eu_mon_recv_hook(struct net_device *dev, struct recv_frame *frame) { struct rx_pkt_attrib *attr; - int iv_len, icv_len; int data_len; u8 *data; @@ -95,11 +122,8 @@ void rtl88eu_mon_recv_hook(struct net_device *dev, struct recv_frame *frame) data = frame->pkt->data; data_len = frame->pkt->len; - /* Broadcast and multicast frames don't have attr->{iv,icv}_len set */ - SET_ICE_IV_LEN(iv_len, icv_len, attr->encrypt); - if (attr->bdecrypted) - mon_recv_decrypted(dev, data, data_len, iv_len, icv_len); + mon_recv_decrypted_recv(dev, data, data_len); else mon_recv_encrypted(dev, data, data_len); } diff --git a/drivers/staging/rtl8192e/dot11d.h b/drivers/staging/rtl8192e/dot11d.h index 623075cf0c05..7fa3c4d963c4 100644 --- a/drivers/staging/rtl8192e/dot11d.h +++ b/drivers/staging/rtl8192e/dot11d.h @@ -30,8 +30,8 @@ enum dot11d_state { }; /** - * struct rt_dot11d_info * @CountryIeLen: value greater than 0 if @CountryIeBuf contains - * valid country information element. + * struct rt_dot11d_info * @CountryIeLen: value greater than 0 if + * @CountryIeBuf contains valid country information element. * @channel_map: holds channel values * 0 - invalid, * 1 - valid (active scan), diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_core.c b/drivers/staging/rtl8192e/rtl8192e/rtl_core.c index a4d1bac4a844..aca52654825b 100644 --- a/drivers/staging/rtl8192e/rtl8192e/rtl_core.c +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_core.c @@ -2275,131 +2275,6 @@ static int _rtl92e_set_mac_adr(struct net_device *dev, void *mac) return 0; } -/* based on ipw2200 driver */ -static int _rtl92e_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) -{ - struct r8192_priv *priv = rtllib_priv(dev); - struct iwreq *wrq = (struct iwreq *)rq; - int ret = -1; - struct rtllib_device *ieee = priv->rtllib; - u32 key[4]; - const u8 broadcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - struct iw_point *p = &wrq->u.data; - struct ieee_param *ipw = NULL; - - mutex_lock(&priv->wx_mutex); - - switch (cmd) { - case RTL_IOCTL_WPA_SUPPLICANT: - if (p->length < sizeof(struct ieee_param) || !p->pointer) { - ret = -EINVAL; - goto out; - } - - ipw = memdup_user(p->pointer, p->length); - if (IS_ERR(ipw)) { - ret = PTR_ERR(ipw); - goto out; - } - - if (ipw->cmd == IEEE_CMD_SET_ENCRYPTION) { - if (ipw->u.crypt.set_tx) { - if (strcmp(ipw->u.crypt.alg, "CCMP") == 0) - ieee->pairwise_key_type = KEY_TYPE_CCMP; - else if (strcmp(ipw->u.crypt.alg, "TKIP") == 0) - ieee->pairwise_key_type = KEY_TYPE_TKIP; - else if (strcmp(ipw->u.crypt.alg, "WEP") == 0) { - if (ipw->u.crypt.key_len == 13) - ieee->pairwise_key_type = - KEY_TYPE_WEP104; - else if (ipw->u.crypt.key_len == 5) - ieee->pairwise_key_type = - KEY_TYPE_WEP40; - } else { - ieee->pairwise_key_type = KEY_TYPE_NA; - } - - if (ieee->pairwise_key_type) { - if (is_zero_ether_addr(ieee->ap_mac_addr)) - ieee->iw_mode = IW_MODE_ADHOC; - memcpy((u8 *)key, ipw->u.crypt.key, 16); - rtl92e_enable_hw_security_config(dev); - rtl92e_set_swcam(dev, 4, - ipw->u.crypt.idx, - ieee->pairwise_key_type, - (u8 *)ieee->ap_mac_addr, - 0, key, 0); - rtl92e_set_key(dev, 4, ipw->u.crypt.idx, - ieee->pairwise_key_type, - (u8 *)ieee->ap_mac_addr, - 0, key); - if (ieee->iw_mode == IW_MODE_ADHOC) { - rtl92e_set_swcam(dev, - ipw->u.crypt.idx, - ipw->u.crypt.idx, - ieee->pairwise_key_type, - (u8 *)ieee->ap_mac_addr, - 0, key, 0); - rtl92e_set_key(dev, - ipw->u.crypt.idx, - ipw->u.crypt.idx, - ieee->pairwise_key_type, - (u8 *)ieee->ap_mac_addr, - 0, key); - } - } - if ((ieee->pairwise_key_type == - KEY_TYPE_CCMP) && - ieee->pHTInfo->bCurrentHTSupport) { - rtl92e_writeb(dev, 0x173, 1); - } - - } else { - memcpy((u8 *)key, ipw->u.crypt.key, 16); - if (strcmp(ipw->u.crypt.alg, "CCMP") == 0) - ieee->group_key_type = KEY_TYPE_CCMP; - else if (strcmp(ipw->u.crypt.alg, "TKIP") == 0) - ieee->group_key_type = KEY_TYPE_TKIP; - else if (strcmp(ipw->u.crypt.alg, "WEP") == 0) { - if (ipw->u.crypt.key_len == 13) - ieee->group_key_type = - KEY_TYPE_WEP104; - else if (ipw->u.crypt.key_len == 5) - ieee->group_key_type = - KEY_TYPE_WEP40; - } else - ieee->group_key_type = KEY_TYPE_NA; - - if (ieee->group_key_type) { - rtl92e_set_swcam(dev, ipw->u.crypt.idx, - ipw->u.crypt.idx, - ieee->group_key_type, - broadcast_addr, 0, key, - 0); - rtl92e_set_key(dev, ipw->u.crypt.idx, - ipw->u.crypt.idx, - ieee->group_key_type, - broadcast_addr, 0, key); - } - } - } - - ret = rtllib_wpa_supplicant_ioctl(priv->rtllib, &wrq->u.data, - 0); - kfree(ipw); - break; - default: - ret = -EOPNOTSUPP; - break; - } - -out: - mutex_unlock(&priv->wx_mutex); - - return ret; -} - - static irqreturn_t _rtl92e_irq(int irq, void *netdev) { struct net_device *dev = netdev; @@ -2542,7 +2417,6 @@ static const struct net_device_ops rtl8192_netdev_ops = { .ndo_open = _rtl92e_open, .ndo_stop = _rtl92e_close, .ndo_tx_timeout = _rtl92e_tx_timeout, - .ndo_do_ioctl = _rtl92e_ioctl, .ndo_set_rx_mode = _rtl92e_set_multicast, .ndo_set_mac_address = _rtl92e_set_mac_adr, .ndo_validate_addr = eth_validate_addr, diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_core.h b/drivers/staging/rtl8192e/rtl8192e/rtl_core.h index 0335823e2766..9d3089cb6a5a 100644 --- a/drivers/staging/rtl8192e/rtl8192e/rtl_core.h +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_core.h @@ -102,8 +102,6 @@ #define PHY_RSSI_SLID_WIN_MAX 100 -#define RTL_IOCTL_WPA_SUPPLICANT (SIOCIWFIRSTPRIV + 30) - #define TxBBGainTableLength 37 #define CCKTxBBGainTableLength 23 diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c b/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c index 1a43c684f9f3..b8205ebafd72 100644 --- a/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c @@ -1693,22 +1693,6 @@ static void _rtl92e_dm_check_edca_turbo(struct net_device *dev) if (priv->rtllib->pHTInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO) goto dm_CheckEdcaTurbo_EXIT; - { - u8 *peername[11] = { - "unknown", "realtek_90", "realtek_92se", "broadcom", - "ralink", "atheros", "cisco", "marvell", "92u_softap", - "self_softap" - }; - static int wb_tmp; - - if (wb_tmp == 0) { - netdev_info(dev, - "%s():iot peer is %s, bssid: %pM\n", - __func__, peername[pHTInfo->IOTPeer], - priv->rtllib->current_network.bssid); - wb_tmp = 1; - } - } if (!priv->rtllib->bis_any_nonbepkts) { curTxOkCnt = priv->stats.txbytesunicast - lastTxOkCnt; curRxOkCnt = priv->stats.rxbytesunicast - lastRxOkCnt; diff --git a/drivers/staging/rtl8192e/rtl819x_HTProc.c b/drivers/staging/rtl8192e/rtl819x_HTProc.c index 4ae1d382ac5c..f0e11726a72a 100644 --- a/drivers/staging/rtl8192e/rtl819x_HTProc.c +++ b/drivers/staging/rtl8192e/rtl819x_HTProc.c @@ -908,8 +908,8 @@ void HTSetConnectBwMode(struct rtllib_device *ieee, pHTInfo->CurSTAExtChnlOffset = HT_EXTCHNL_OFFSET_NO_EXT; } - pr_info("%s():pHTInfo->bCurBW40MHz:%x\n", __func__, - pHTInfo->bCurBW40MHz); + netdev_dbg(ieee->dev, "%s():pHTInfo->bCurBW40MHz:%x\n", __func__, + pHTInfo->bCurBW40MHz); pHTInfo->bSwBwInProgress = true; diff --git a/drivers/staging/rtl8192e/rtllib.h b/drivers/staging/rtl8192e/rtllib.h index 827651b62791..0042a0f6cf79 100644 --- a/drivers/staging/rtl8192e/rtllib.h +++ b/drivers/staging/rtl8192e/rtllib.h @@ -335,60 +335,8 @@ enum rt_op_mode { #define MGMT_QUEUE_NUM 5 -#define IEEE_CMD_SET_WPA_PARAM 1 -#define IEEE_CMD_SET_WPA_IE 2 -#define IEEE_CMD_SET_ENCRYPTION 3 -#define IEEE_CMD_MLME 4 - -#define IEEE_PARAM_WPA_ENABLED 1 -#define IEEE_PARAM_TKIP_COUNTERMEASURES 2 -#define IEEE_PARAM_DROP_UNENCRYPTED 3 -#define IEEE_PARAM_PRIVACY_INVOKED 4 -#define IEEE_PARAM_AUTH_ALGS 5 -#define IEEE_PARAM_IEEE_802_1X 6 -#define IEEE_PARAM_WPAX_SELECT 7 - -#define IEEE_MLME_STA_DEAUTH 1 -#define IEEE_MLME_STA_DISASSOC 2 - - -#define IEEE_CRYPT_ERR_UNKNOWN_ALG 2 -#define IEEE_CRYPT_ERR_CRYPT_INIT_FAILED 4 -#define IEEE_CRYPT_ERR_KEY_SET_FAILED 5 -#define IEEE_CRYPT_ERR_CARD_CONF_FAILED 7 -#define IEEE_CRYPT_ALG_NAME_LEN 16 - #define MAX_IE_LEN 0xff -struct ieee_param { - u32 cmd; - u8 sta_addr[ETH_ALEN]; - union { - struct { - u8 name; - u32 value; - } wpa_param; - struct { - u32 len; - u8 reserved[32]; - u8 data[0]; - } wpa_ie; - struct { - int command; - int reason_code; - } mlme; - struct { - u8 alg[IEEE_CRYPT_ALG_NAME_LEN]; - u8 set_tx; - u32 err; - u8 idx; - u8 seq[8]; /* sequence counter (set: RX, get: TX) */ - u16 key_len; - u8 key[0]; - } crypt; - } u; -}; - #define msleep_interruptible_rsl msleep_interruptible /* Maximum size for the MA-UNITDATA primitive, 802.11 standard section @@ -2066,8 +2014,6 @@ void rtllib_stop_all_queues(struct rtllib_device *ieee); struct sk_buff *rtllib_get_beacon(struct rtllib_device *ieee); void rtllib_start_send_beacons(struct rtllib_device *ieee); void rtllib_stop_send_beacons(struct rtllib_device *ieee); -int rtllib_wpa_supplicant_ioctl(struct rtllib_device *ieee, - struct iw_point *p, u8 is_mesh); void notify_wx_assoc_event(struct rtllib_device *ieee); void rtllib_ps_tx_ack(struct rtllib_device *ieee, short success); diff --git a/drivers/staging/rtl8192e/rtllib_rx.c b/drivers/staging/rtl8192e/rtllib_rx.c index 43a77745e6fb..0033dc6979e7 100644 --- a/drivers/staging/rtl8192e/rtllib_rx.c +++ b/drivers/staging/rtl8192e/rtllib_rx.c @@ -1214,9 +1214,6 @@ static int rtllib_rx_decrypt(struct rtllib_device *ieee, struct sk_buff *skb, return -1; } - if (rtllib_is_eapol_frame(ieee, skb, hdrlen)) - netdev_warn(ieee->dev, "RX: IEEE802.1X EAPOL frame!\n"); - return 0; } diff --git a/drivers/staging/rtl8192e/rtllib_softmac.c b/drivers/staging/rtl8192e/rtllib_softmac.c index eeda17d6409b..64b0034c9c37 100644 --- a/drivers/staging/rtl8192e/rtllib_softmac.c +++ b/drivers/staging/rtl8192e/rtllib_softmac.c @@ -1525,7 +1525,8 @@ static void rtllib_associate_complete_wq(void *data) associate_complete_wq); struct rt_pwr_save_ctrl *pPSC = &(ieee->PowerSaveControl); - netdev_info(ieee->dev, "Associated successfully\n"); + netdev_info(ieee->dev, "Associated successfully with %pM\n", + ieee->current_network.bssid); if (!ieee->is_silent_reset) { netdev_info(ieee->dev, "normal associate\n"); notify_wx_assoc_event(ieee); @@ -2309,7 +2310,8 @@ static void rtllib_rx_auth_resp(struct rtllib_device *ieee, struct sk_buff *skb) if (errcode) { ieee->softmac_stats.rx_auth_rs_err++; netdev_info(ieee->dev, - "Authentication respose status code 0x%x", errcode); + "Authentication response status code 0x%x", + errcode); rtllib_associate_abort(ieee); return; } @@ -3076,333 +3078,6 @@ void rtllib_softmac_free(struct rtllib_device *ieee) tasklet_kill(&ieee->ps_task); } -/******************************************************** - * Start of WPA code. * - * this is stolen from the ipw2200 driver * - ********************************************************/ - - -static int rtllib_wpa_enable(struct rtllib_device *ieee, int value) -{ - /* This is called when wpa_supplicant loads and closes the driver - * interface. - */ - netdev_info(ieee->dev, "%s WPA\n", value ? "enabling" : "disabling"); - ieee->wpa_enabled = value; - eth_zero_addr(ieee->ap_mac_addr); - return 0; -} - - -static void rtllib_wpa_assoc_frame(struct rtllib_device *ieee, char *wpa_ie, - int wpa_ie_len) -{ - /* make sure WPA is enabled */ - rtllib_wpa_enable(ieee, 1); - - rtllib_disassociate(ieee); -} - - -static int rtllib_wpa_mlme(struct rtllib_device *ieee, int command, int reason) -{ - - int ret = 0; - - switch (command) { - case IEEE_MLME_STA_DEAUTH: - break; - - case IEEE_MLME_STA_DISASSOC: - rtllib_disassociate(ieee); - break; - - default: - netdev_info(ieee->dev, "Unknown MLME request: %d\n", command); - ret = -EOPNOTSUPP; - } - - return ret; -} - - -static int rtllib_wpa_set_wpa_ie(struct rtllib_device *ieee, - struct ieee_param *param, int plen) -{ - u8 *buf; - - if (param->u.wpa_ie.len > MAX_WPA_IE_LEN || - (param->u.wpa_ie.len && param->u.wpa_ie.data == NULL)) - return -EINVAL; - - if (param->u.wpa_ie.len) { - buf = kmemdup(param->u.wpa_ie.data, param->u.wpa_ie.len, - GFP_KERNEL); - if (buf == NULL) - return -ENOMEM; - - kfree(ieee->wpa_ie); - ieee->wpa_ie = buf; - ieee->wpa_ie_len = param->u.wpa_ie.len; - } else { - kfree(ieee->wpa_ie); - ieee->wpa_ie = NULL; - ieee->wpa_ie_len = 0; - } - - rtllib_wpa_assoc_frame(ieee, ieee->wpa_ie, ieee->wpa_ie_len); - return 0; -} - -#define AUTH_ALG_OPEN_SYSTEM 0x1 -#define AUTH_ALG_SHARED_KEY 0x2 -#define AUTH_ALG_LEAP 0x4 -static int rtllib_wpa_set_auth_algs(struct rtllib_device *ieee, int value) -{ - - struct rtllib_security sec = { - .flags = SEC_AUTH_MODE, - }; - - if (value & AUTH_ALG_SHARED_KEY) { - sec.auth_mode = WLAN_AUTH_SHARED_KEY; - ieee->open_wep = 0; - ieee->auth_mode = 1; - } else if (value & AUTH_ALG_OPEN_SYSTEM) { - sec.auth_mode = WLAN_AUTH_OPEN; - ieee->open_wep = 1; - ieee->auth_mode = 0; - } else if (value & AUTH_ALG_LEAP) { - sec.auth_mode = WLAN_AUTH_LEAP >> 6; - ieee->open_wep = 1; - ieee->auth_mode = 2; - } - - - if (ieee->set_security) - ieee->set_security(ieee->dev, &sec); - - return 0; -} - -static int rtllib_wpa_set_param(struct rtllib_device *ieee, u8 name, u32 value) -{ - int ret = 0; - unsigned long flags; - - switch (name) { - case IEEE_PARAM_WPA_ENABLED: - ret = rtllib_wpa_enable(ieee, value); - break; - - case IEEE_PARAM_TKIP_COUNTERMEASURES: - ieee->tkip_countermeasures = value; - break; - - case IEEE_PARAM_DROP_UNENCRYPTED: - { - /* HACK: - * - * wpa_supplicant calls set_wpa_enabled when the driver - * is loaded and unloaded, regardless of if WPA is being - * used. No other calls are made which can be used to - * determine if encryption will be used or not prior to - * association being expected. If encryption is not being - * used, drop_unencrypted is set to false, else true -- we - * can use this to determine if the CAP_PRIVACY_ON bit should - * be set. - */ - struct rtllib_security sec = { - .flags = SEC_ENABLED, - .enabled = value, - }; - ieee->drop_unencrypted = value; - /* We only change SEC_LEVEL for open mode. Others - * are set by ipw_wpa_set_encryption. - */ - if (!value) { - sec.flags |= SEC_LEVEL; - sec.level = SEC_LEVEL_0; - } else { - sec.flags |= SEC_LEVEL; - sec.level = SEC_LEVEL_1; - } - if (ieee->set_security) - ieee->set_security(ieee->dev, &sec); - break; - } - - case IEEE_PARAM_PRIVACY_INVOKED: - ieee->privacy_invoked = value; - break; - - case IEEE_PARAM_AUTH_ALGS: - ret = rtllib_wpa_set_auth_algs(ieee, value); - break; - - case IEEE_PARAM_IEEE_802_1X: - ieee->ieee802_1x = value; - break; - case IEEE_PARAM_WPAX_SELECT: - spin_lock_irqsave(&ieee->wpax_suitlist_lock, flags); - spin_unlock_irqrestore(&ieee->wpax_suitlist_lock, flags); - break; - - default: - netdev_info(ieee->dev, "Unknown WPA param: %d\n", name); - ret = -EOPNOTSUPP; - } - - return ret; -} - -/* implementation borrowed from hostap driver */ -static int rtllib_wpa_set_encryption(struct rtllib_device *ieee, - struct ieee_param *param, int param_len, - u8 is_mesh) -{ - int ret = 0; - struct lib80211_crypto_ops *ops; - struct lib80211_crypt_data **crypt; - - struct rtllib_security sec = { - .flags = 0, - }; - - param->u.crypt.err = 0; - param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; - - if (param_len != - (int) ((char *) param->u.crypt.key - (char *) param) + - param->u.crypt.key_len) { - netdev_info(ieee->dev, "Len mismatch %d, %d\n", param_len, - param->u.crypt.key_len); - return -EINVAL; - } - if (is_broadcast_ether_addr(param->sta_addr)) { - if (param->u.crypt.idx >= NUM_WEP_KEYS) - return -EINVAL; - crypt = &ieee->crypt_info.crypt[param->u.crypt.idx]; - } else { - return -EINVAL; - } - - if (strcmp(param->u.crypt.alg, "none") == 0) { - if (crypt) { - sec.enabled = 0; - sec.level = SEC_LEVEL_0; - sec.flags |= SEC_ENABLED | SEC_LEVEL; - lib80211_crypt_delayed_deinit(&ieee->crypt_info, crypt); - } - goto done; - } - sec.enabled = 1; - sec.flags |= SEC_ENABLED; - - /* IPW HW cannot build TKIP MIC, host decryption still needed. */ - if (!(ieee->host_encrypt || ieee->host_decrypt) && - strcmp(param->u.crypt.alg, "R-TKIP")) - goto skip_host_crypt; - - ops = lib80211_get_crypto_ops(param->u.crypt.alg); - if (ops == NULL && strcmp(param->u.crypt.alg, "R-WEP") == 0) { - request_module("rtllib_crypt_wep"); - ops = lib80211_get_crypto_ops(param->u.crypt.alg); - } else if (ops == NULL && strcmp(param->u.crypt.alg, "R-TKIP") == 0) { - request_module("rtllib_crypt_tkip"); - ops = lib80211_get_crypto_ops(param->u.crypt.alg); - } else if (ops == NULL && strcmp(param->u.crypt.alg, "R-CCMP") == 0) { - request_module("rtllib_crypt_ccmp"); - ops = lib80211_get_crypto_ops(param->u.crypt.alg); - } - if (ops == NULL) { - netdev_info(ieee->dev, "unknown crypto alg '%s'\n", - param->u.crypt.alg); - param->u.crypt.err = IEEE_CRYPT_ERR_UNKNOWN_ALG; - ret = -EINVAL; - goto done; - } - if (*crypt == NULL || (*crypt)->ops != ops) { - struct lib80211_crypt_data *new_crypt; - - lib80211_crypt_delayed_deinit(&ieee->crypt_info, crypt); - - new_crypt = kzalloc(sizeof(*new_crypt), GFP_KERNEL); - if (new_crypt == NULL) { - ret = -ENOMEM; - goto done; - } - new_crypt->ops = ops; - if (new_crypt->ops && try_module_get(new_crypt->ops->owner)) - new_crypt->priv = - new_crypt->ops->init(param->u.crypt.idx); - - if (new_crypt->priv == NULL) { - kfree(new_crypt); - param->u.crypt.err = IEEE_CRYPT_ERR_CRYPT_INIT_FAILED; - ret = -EINVAL; - goto done; - } - - *crypt = new_crypt; - } - - if (param->u.crypt.key_len > 0 && (*crypt)->ops->set_key && - (*crypt)->ops->set_key(param->u.crypt.key, - param->u.crypt.key_len, param->u.crypt.seq, - (*crypt)->priv) < 0) { - netdev_info(ieee->dev, "key setting failed\n"); - param->u.crypt.err = IEEE_CRYPT_ERR_KEY_SET_FAILED; - ret = -EINVAL; - goto done; - } - - skip_host_crypt: - if (param->u.crypt.set_tx) { - ieee->crypt_info.tx_keyidx = param->u.crypt.idx; - sec.active_key = param->u.crypt.idx; - sec.flags |= SEC_ACTIVE_KEY; - } else - sec.flags &= ~SEC_ACTIVE_KEY; - - memcpy(sec.keys[param->u.crypt.idx], - param->u.crypt.key, - param->u.crypt.key_len); - sec.key_sizes[param->u.crypt.idx] = param->u.crypt.key_len; - sec.flags |= (1 << param->u.crypt.idx); - - if (strcmp(param->u.crypt.alg, "R-WEP") == 0) { - sec.flags |= SEC_LEVEL; - sec.level = SEC_LEVEL_1; - } else if (strcmp(param->u.crypt.alg, "R-TKIP") == 0) { - sec.flags |= SEC_LEVEL; - sec.level = SEC_LEVEL_2; - } else if (strcmp(param->u.crypt.alg, "R-CCMP") == 0) { - sec.flags |= SEC_LEVEL; - sec.level = SEC_LEVEL_3; - } - done: - if (ieee->set_security) - ieee->set_security(ieee->dev, &sec); - - /* Do not reset port if card is in Managed mode since resetting will - * generate new IEEE 802.11 authentication which may end up in looping - * with IEEE 802.1X. If your hardware requires a reset after WEP - * configuration (for example... Prism2), implement the reset_port in - * the callbacks structures used to initialize the 802.11 stack. - */ - if (ieee->reset_on_keychange && - ieee->iw_mode != IW_MODE_INFRA && - ieee->reset_port && - ieee->reset_port(ieee->dev)) { - netdev_info(ieee->dev, "reset_port failed\n"); - param->u.crypt.err = IEEE_CRYPT_ERR_CARD_CONF_FAILED; - return -EINVAL; - } - - return ret; -} - static inline struct sk_buff * rtllib_disauth_skb(struct rtllib_network *beacon, struct rtllib_device *ieee, u16 asRsn) @@ -3501,62 +3176,6 @@ u8 rtllib_ap_sec_type(struct rtllib_device *ieee) } } -int rtllib_wpa_supplicant_ioctl(struct rtllib_device *ieee, struct iw_point *p, - u8 is_mesh) -{ - struct ieee_param *param; - int ret = 0; - - mutex_lock(&ieee->wx_mutex); - - if (p->length < sizeof(struct ieee_param) || !p->pointer) { - ret = -EINVAL; - goto out; - } - - param = memdup_user(p->pointer, p->length); - if (IS_ERR(param)) { - ret = PTR_ERR(param); - goto out; - } - - switch (param->cmd) { - case IEEE_CMD_SET_WPA_PARAM: - ret = rtllib_wpa_set_param(ieee, param->u.wpa_param.name, - param->u.wpa_param.value); - break; - - case IEEE_CMD_SET_WPA_IE: - ret = rtllib_wpa_set_wpa_ie(ieee, param, p->length); - break; - - case IEEE_CMD_SET_ENCRYPTION: - ret = rtllib_wpa_set_encryption(ieee, param, p->length, 0); - break; - - case IEEE_CMD_MLME: - ret = rtllib_wpa_mlme(ieee, param->u.mlme.command, - param->u.mlme.reason_code); - break; - - default: - netdev_info(ieee->dev, "Unknown WPA supplicant request: %d\n", - param->cmd); - ret = -EOPNOTSUPP; - break; - } - - if (ret == 0 && copy_to_user(p->pointer, param, p->length)) - ret = -EFAULT; - - kfree(param); -out: - mutex_unlock(&ieee->wx_mutex); - - return ret; -} -EXPORT_SYMBOL(rtllib_wpa_supplicant_ioctl); - static void rtllib_MgntDisconnectIBSS(struct rtllib_device *rtllib) { u8 OpMode; diff --git a/drivers/staging/rtl8192e/rtllib_wx.c b/drivers/staging/rtl8192e/rtllib_wx.c index c5c0d9676dc8..f7eba01b5d15 100644 --- a/drivers/staging/rtl8192e/rtllib_wx.c +++ b/drivers/staging/rtl8192e/rtllib_wx.c @@ -595,7 +595,7 @@ int rtllib_wx_set_encode_ext(struct rtllib_device *ieee, ret = -EINVAL; goto done; } - netdev_info(dev, "alg name:%s\n", alg); + netdev_dbg(dev, "alg name:%s\n", alg); ops = lib80211_get_crypto_ops(alg); if (ops == NULL) { diff --git a/drivers/staging/rtl8192u/ieee80211/ieee80211.h b/drivers/staging/rtl8192u/ieee80211/ieee80211.h index 899c77ed2a43..b062cad052b9 100644 --- a/drivers/staging/rtl8192u/ieee80211/ieee80211.h +++ b/drivers/staging/rtl8192u/ieee80211/ieee80211.h @@ -2187,7 +2187,7 @@ int ieee80211_encrypt_fragment(struct ieee80211_device *ieee, struct sk_buff *frag, int hdr_len); int ieee80211_xmit(struct sk_buff *skb, struct net_device *dev); -void ieee80211_txb_free(struct ieee80211_txb *); +void ieee80211_txb_free(struct ieee80211_txb *txb); /* ieee80211_rx.c */ diff --git a/drivers/staging/rtl8192u/ieee80211/ieee80211_crypt.h b/drivers/staging/rtl8192u/ieee80211/ieee80211_crypt.h index 005bf89aae65..a0aa0f5be63a 100644 --- a/drivers/staging/rtl8192u/ieee80211/ieee80211_crypt.h +++ b/drivers/staging/rtl8192u/ieee80211/ieee80211_crypt.h @@ -82,8 +82,8 @@ struct ieee80211_crypt_data { int ieee80211_register_crypto_ops(struct ieee80211_crypto_ops *ops); int ieee80211_unregister_crypto_ops(struct ieee80211_crypto_ops *ops); struct ieee80211_crypto_ops *ieee80211_get_crypto_ops(const char *name); -void ieee80211_crypt_deinit_entries(struct ieee80211_device *, int); -void ieee80211_crypt_deinit_handler(unsigned long); +void ieee80211_crypt_deinit_entries(struct ieee80211_device *ieee, int force); +void ieee80211_crypt_deinit_handler(unsigned long data); void ieee80211_crypt_delayed_deinit(struct ieee80211_device *ieee, struct ieee80211_crypt_data **crypt); diff --git a/drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_tkip.c b/drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_tkip.c index 5039172409e3..60ecfec71112 100644 --- a/drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_tkip.c +++ b/drivers/staging/rtl8192u/ieee80211/ieee80211_crypt_tkip.c @@ -171,13 +171,6 @@ static inline u16 Mk16(u8 hi, u8 lo) return lo | (((u16) hi) << 8); } - -static inline u16 Mk16_le(u16 *v) -{ - return le16_to_cpu(*v); -} - - static const u16 Sbox[256] = { 0xC6A5, 0xF884, 0xEE99, 0xF68D, 0xFF0D, 0xD6BD, 0xDEB1, 0x9154, 0x6050, 0x0203, 0xCEA9, 0x567D, 0xE719, 0xB562, 0x4DE6, 0xEC9A, @@ -264,15 +257,15 @@ static void tkip_mixing_phase2(u8 *WEPSeed, const u8 *TK, const u16 *TTAK, PPK[5] = TTAK[4] + IV16; /* Step 2 - 96-bit bijective mixing using S-box */ - PPK[0] += _S_(PPK[5] ^ Mk16_le((u16 *) &TK[0])); - PPK[1] += _S_(PPK[0] ^ Mk16_le((u16 *) &TK[2])); - PPK[2] += _S_(PPK[1] ^ Mk16_le((u16 *) &TK[4])); - PPK[3] += _S_(PPK[2] ^ Mk16_le((u16 *) &TK[6])); - PPK[4] += _S_(PPK[3] ^ Mk16_le((u16 *) &TK[8])); - PPK[5] += _S_(PPK[4] ^ Mk16_le((u16 *) &TK[10])); - - PPK[0] += RotR1(PPK[5] ^ Mk16_le((u16 *) &TK[12])); - PPK[1] += RotR1(PPK[0] ^ Mk16_le((u16 *) &TK[14])); + PPK[0] += _S_(PPK[5] ^ le16_to_cpu(*(__le16 *)(&TK[0]))); + PPK[1] += _S_(PPK[0] ^ le16_to_cpu(*(__le16 *)(&TK[2]))); + PPK[2] += _S_(PPK[1] ^ le16_to_cpu(*(__le16 *)(&TK[4]))); + PPK[3] += _S_(PPK[2] ^ le16_to_cpu(*(__le16 *)(&TK[6]))); + PPK[4] += _S_(PPK[3] ^ le16_to_cpu(*(__le16 *)(&TK[8]))); + PPK[5] += _S_(PPK[4] ^ le16_to_cpu(*(__le16 *)(&TK[10]))); + + PPK[0] += RotR1(PPK[5] ^ le16_to_cpu(*(__le16 *)(&TK[12]))); + PPK[1] += RotR1(PPK[0] ^ le16_to_cpu(*(__le16 *)(&TK[14]))); PPK[2] += RotR1(PPK[1]); PPK[3] += RotR1(PPK[2]); PPK[4] += RotR1(PPK[3]); @@ -285,7 +278,7 @@ static void tkip_mixing_phase2(u8 *WEPSeed, const u8 *TK, const u16 *TTAK, WEPSeed[0] = Hi8(IV16); WEPSeed[1] = (Hi8(IV16) | 0x20) & 0x7F; WEPSeed[2] = Lo8(IV16); - WEPSeed[3] = Lo8((PPK[5] ^ Mk16_le((u16 *) &TK[0])) >> 1); + WEPSeed[3] = Lo8((PPK[5] ^ le16_to_cpu(*(__le16 *)(&TK[0]))) >> 1); #ifdef __BIG_ENDIAN { diff --git a/drivers/staging/rtl8192u/ieee80211/ieee80211_module.c b/drivers/staging/rtl8192u/ieee80211/ieee80211_module.c index a791175b86f5..8f236b332a47 100644 --- a/drivers/staging/rtl8192u/ieee80211/ieee80211_module.c +++ b/drivers/staging/rtl8192u/ieee80211/ieee80211_module.c @@ -157,8 +157,7 @@ struct net_device *alloc_ieee80211(int sizeof_priv) ieee80211_softmac_init(ieee); ieee->pHTInfo = kzalloc(sizeof(RT_HIGH_THROUGHPUT), GFP_KERNEL); - if (ieee->pHTInfo == NULL) - { + if (ieee->pHTInfo == NULL) { IEEE80211_DEBUG(IEEE80211_DL_ERR, "can't alloc memory for HTInfo\n"); goto failed; } diff --git a/drivers/staging/rtl8192u/ieee80211/rtl819x_TSProc.c b/drivers/staging/rtl8192u/ieee80211/rtl819x_TSProc.c index b4c13fff2c65..f98bb03aa293 100644 --- a/drivers/staging/rtl8192u/ieee80211/rtl819x_TSProc.c +++ b/drivers/staging/rtl8192u/ieee80211/rtl819x_TSProc.c @@ -36,18 +36,15 @@ static void RxPktPendingTimeout(unsigned long data) spin_lock_irqsave(&(ieee->reorder_spinlock), flags); IEEE80211_DEBUG(IEEE80211_DL_REORDER,"==================>%s()\n",__func__); - if(pRxTs->RxTimeoutIndicateSeq != 0xffff) - { + if(pRxTs->RxTimeoutIndicateSeq != 0xffff) { // Indicate the pending packets sequentially according to SeqNum until meet the gap. - while(!list_empty(&pRxTs->RxPendingPktList)) - { + while(!list_empty(&pRxTs->RxPendingPktList)) { pReorderEntry = (PRX_REORDER_ENTRY)list_entry(pRxTs->RxPendingPktList.prev,RX_REORDER_ENTRY,List); if(index == 0) pRxTs->RxIndicateSeq = pReorderEntry->SeqNum; if( SN_LESS(pReorderEntry->SeqNum, pRxTs->RxIndicateSeq) || - SN_EQUAL(pReorderEntry->SeqNum, pRxTs->RxIndicateSeq) ) - { + SN_EQUAL(pReorderEntry->SeqNum, pRxTs->RxIndicateSeq) ) { list_del_init(&pReorderEntry->List); if(SN_EQUAL(pReorderEntry->SeqNum, pRxTs->RxIndicateSeq)) @@ -58,22 +55,19 @@ static void RxPktPendingTimeout(unsigned long data) index++; list_add_tail(&pReorderEntry->List, &ieee->RxReorder_Unused_List); - } - else - { + } else { bPktInBuf = true; break; } } } - if(index>0) - { + if(index>0) { // Set RxTimeoutIndicateSeq to 0xffff to indicate no pending packets in buffer now. pRxTs->RxTimeoutIndicateSeq = 0xffff; // Indicate packets - if(index > REORDER_WIN_SIZE){ + if(index > REORDER_WIN_SIZE) { IEEE80211_DEBUG(IEEE80211_DL_ERR, "RxReorderIndicatePacket(): Rx Reorder buffer full!! \n"); spin_unlock_irqrestore(&(ieee->reorder_spinlock), flags); return; @@ -81,8 +75,7 @@ static void RxPktPendingTimeout(unsigned long data) ieee80211_indicate_packets(ieee, ieee->stats_IndicateArray, index); } - if(bPktInBuf && (pRxTs->RxTimeoutIndicateSeq==0xffff)) - { + if(bPktInBuf && (pRxTs->RxTimeoutIndicateSeq==0xffff)) { pRxTs->RxTimeoutIndicateSeq = pRxTs->RxIndicateSeq; mod_timer(&pRxTs->RxPktPendingTimer, jiffies + msecs_to_jiffies(ieee->pHTInfo->RxReorderPendingTime)); @@ -147,8 +140,7 @@ void TSInitialize(struct ieee80211_device *ieee) INIT_LIST_HEAD(&ieee->Tx_TS_Pending_List); INIT_LIST_HEAD(&ieee->Tx_TS_Unused_List); - for(count = 0; count < TOTAL_TS_NUM; count++) - { + for(count = 0; count < TOTAL_TS_NUM; count++) { // pTxTS->num = count; // The timers for the operation of Traffic Stream and Block Ack. @@ -172,8 +164,7 @@ void TSInitialize(struct ieee80211_device *ieee) INIT_LIST_HEAD(&ieee->Rx_TS_Admit_List); INIT_LIST_HEAD(&ieee->Rx_TS_Pending_List); INIT_LIST_HEAD(&ieee->Rx_TS_Unused_List); - for(count = 0; count < TOTAL_TS_NUM; count++) - { + for(count = 0; count < TOTAL_TS_NUM; count++) { pRxTS->num = count; INIT_LIST_HEAD(&pRxTS->RxPendingPktList); setup_timer(&pRxTS->TsCommonInfo.SetupTimer, TsSetupTimeOut, @@ -191,15 +182,13 @@ void TSInitialize(struct ieee80211_device *ieee) // Initialize unused Rx Reorder List. INIT_LIST_HEAD(&ieee->RxReorder_Unused_List); //#ifdef TO_DO_LIST - for(count = 0; count < REORDER_ENTRY_NUM; count++) - { + for(count = 0; count < REORDER_ENTRY_NUM; count++) { list_add_tail( &pRxReorderEntry->List,&ieee->RxReorder_Unused_List); if(count == (REORDER_ENTRY_NUM-1)) break; pRxReorderEntry = &ieee->RxReorderEntry[count+1]; } //#endif - } static void AdmitTS(struct ieee80211_device *ieee, @@ -223,36 +212,25 @@ static PTS_COMMON_INFO SearchAdmitTRStream(struct ieee80211_device *ieee, bool search_dir[4] = {0}; struct list_head *psearch_list; //FIXME PTS_COMMON_INFO pRet = NULL; - if(ieee->iw_mode == IW_MODE_MASTER) //ap mode - { - if(TxRxSelect == TX_DIR) - { + if(ieee->iw_mode == IW_MODE_MASTER) { //ap mode + if(TxRxSelect == TX_DIR) { search_dir[DIR_DOWN] = true; search_dir[DIR_BI_DIR]= true; - } - else - { + } else { search_dir[DIR_UP] = true; search_dir[DIR_BI_DIR]= true; } - } - else if(ieee->iw_mode == IW_MODE_ADHOC) - { + } else if(ieee->iw_mode == IW_MODE_ADHOC) { if(TxRxSelect == TX_DIR) search_dir[DIR_UP] = true; else search_dir[DIR_DOWN] = true; - } - else - { - if(TxRxSelect == TX_DIR) - { + } else { + if(TxRxSelect == TX_DIR) { search_dir[DIR_UP] = true; search_dir[DIR_BI_DIR]= true; search_dir[DIR_DIRECT]= true; - } - else - { + } else { search_dir[DIR_DOWN] = true; search_dir[DIR_BI_DIR]= true; search_dir[DIR_DIRECT]= true; @@ -265,28 +243,24 @@ static PTS_COMMON_INFO SearchAdmitTRStream(struct ieee80211_device *ieee, psearch_list = &ieee->Rx_TS_Admit_List; //for(dir = DIR_UP; dir <= DIR_BI_DIR; dir++) - for(dir = 0; dir <= DIR_BI_DIR; dir++) - { + for(dir = 0; dir <= DIR_BI_DIR; dir++) { if (!search_dir[dir]) continue; list_for_each_entry(pRet, psearch_list, List){ // IEEE80211_DEBUG(IEEE80211_DL_TS, "ADD:%pM, TID:%d, dir:%d\n", pRet->Addr, pRet->TSpec.f.TSInfo.field.ucTSID, pRet->TSpec.f.TSInfo.field.ucDirection); if (memcmp(pRet->Addr, Addr, 6) == 0) if (pRet->TSpec.f.TSInfo.field.ucTSID == TID) - if(pRet->TSpec.f.TSInfo.field.ucDirection == dir) - { + if(pRet->TSpec.f.TSInfo.field.ucDirection == dir) { // printk("Bingo! got it\n"); break; } - } if(&pRet->List != psearch_list) break; } - if(&pRet->List != psearch_list){ + if(&pRet->List != psearch_list) return pRet ; - } else return NULL; } @@ -327,25 +301,21 @@ bool GetTs( // We do not build any TS for Broadcast or Multicast stream. // So reject these kinds of search here. // - if (is_multicast_ether_addr(Addr)) - { + if (is_multicast_ether_addr(Addr)) { IEEE80211_DEBUG(IEEE80211_DL_ERR, "get TS for Broadcast or Multicast\n"); return false; } - if (ieee->current_network.qos_data.supported == 0) + if (ieee->current_network.qos_data.supported == 0) { UP = 0; - else - { + } else { // In WMM case: we use 4 TID only - if (!IsACValid(TID)) - { + if (!IsACValid(TID)) { IEEE80211_DEBUG(IEEE80211_DL_ERR, " in %s(), TID(%d) is not valid\n", __func__, TID); return false; } - switch (TID) - { + switch (TID) { case 0: case 3: UP = 0; @@ -373,18 +343,13 @@ bool GetTs( Addr, UP, TxRxSelect); - if(*ppTS != NULL) - { + if(*ppTS != NULL) { return true; - } - else - { + } else { if (!bAddNewTs) { IEEE80211_DEBUG(IEEE80211_DL_TS, "add new TS failed(tid:%d)\n", UP); return false; - } - else - { + } else { // // Create a new Traffic stream for current Tx/Rx // This is for EDCA and WMM to add a new TS. @@ -406,16 +371,13 @@ bool GetTs( ((TxRxSelect==TX_DIR)?DIR_DOWN:DIR_UP): ((TxRxSelect==TX_DIR)?DIR_UP:DIR_DOWN); IEEE80211_DEBUG(IEEE80211_DL_TS, "to add Ts\n"); - if(!list_empty(pUnusedList)) - { + if(!list_empty(pUnusedList)) { (*ppTS) = list_entry(pUnusedList->next, TS_COMMON_INFO, List); list_del_init(&(*ppTS)->List); - if(TxRxSelect==TX_DIR) - { + if(TxRxSelect==TX_DIR) { PTX_TS_RECORD tmp = container_of(*ppTS, TX_TS_RECORD, TsCommonInfo); ResetTxTsEntry(tmp); - } - else{ + } else { PRX_TS_RECORD tmp = container_of(*ppTS, RX_TS_RECORD, TsCommonInfo); ResetRxTsEntry(tmp); } @@ -438,9 +400,7 @@ bool GetTs( // if there is DirectLink, we need to do additional operation here!! return true; - } - else - { + } else { IEEE80211_DEBUG(IEEE80211_DL_ERR, "in function %s() There is not enough TS record to be used!!", __func__); return false; } @@ -457,16 +417,14 @@ static void RemoveTsEntry(struct ieee80211_device *ieee, PTS_COMMON_INFO pTs, del_timer_sync(&pTs->InactTimer); TsInitDelBA(ieee, pTs, TxRxSelect); - if(TxRxSelect == RX_DIR) - { + if(TxRxSelect == RX_DIR) { //#ifdef TO_DO_LIST PRX_REORDER_ENTRY pRxReorderEntry; PRX_TS_RECORD pRxTS = (PRX_TS_RECORD)pTs; if(timer_pending(&pRxTS->RxPktPendingTimer)) del_timer_sync(&pRxTS->RxPktPendingTimer); - while(!list_empty(&pRxTS->RxPendingPktList)) - { + while(!list_empty(&pRxTS->RxPendingPktList)) { spin_lock_irqsave(&(ieee->reorder_spinlock), flags); //pRxReorderEntry = list_entry(&pRxTS->RxPendingPktList.prev,RX_REORDER_ENTRY,List); pRxReorderEntry = (PRX_REORDER_ENTRY)list_entry(pRxTS->RxPendingPktList.prev,RX_REORDER_ENTRY,List); @@ -474,14 +432,13 @@ static void RemoveTsEntry(struct ieee80211_device *ieee, PTS_COMMON_INFO pTs, { int i = 0; struct ieee80211_rxb *prxb = pRxReorderEntry->prxb; - if (unlikely(!prxb)) - { + if (unlikely(!prxb)) { spin_unlock_irqrestore(&(ieee->reorder_spinlock), flags); return; } - for(i =0; i < prxb->nr_subframes; i++) { + for(i =0; i < prxb->nr_subframes; i++) dev_kfree_skb(prxb->subframes[i]); - } + kfree(prxb); prxb = NULL; } @@ -490,9 +447,7 @@ static void RemoveTsEntry(struct ieee80211_device *ieee, PTS_COMMON_INFO pTs, } //#endif - } - else - { + } else { PTX_TS_RECORD pTxTS = (PTX_TS_RECORD)pTs; del_timer_sync(&pTxTS->TsAddBaTimer); } @@ -503,20 +458,16 @@ void RemovePeerTS(struct ieee80211_device *ieee, u8 *Addr) PTS_COMMON_INFO pTS, pTmpTS; printk("===========>RemovePeerTS,%pM\n", Addr); - list_for_each_entry_safe(pTS, pTmpTS, &ieee->Tx_TS_Pending_List, List) - { - if (memcmp(pTS->Addr, Addr, 6) == 0) - { + list_for_each_entry_safe(pTS, pTmpTS, &ieee->Tx_TS_Pending_List, List) { + if (memcmp(pTS->Addr, Addr, 6) == 0) { RemoveTsEntry(ieee, pTS, TX_DIR); list_del_init(&pTS->List); list_add_tail(&pTS->List, &ieee->Tx_TS_Unused_List); } } - list_for_each_entry_safe(pTS, pTmpTS, &ieee->Tx_TS_Admit_List, List) - { - if (memcmp(pTS->Addr, Addr, 6) == 0) - { + list_for_each_entry_safe(pTS, pTmpTS, &ieee->Tx_TS_Admit_List, List) { + if (memcmp(pTS->Addr, Addr, 6) == 0) { printk("====>remove Tx_TS_admin_list\n"); RemoveTsEntry(ieee, pTS, TX_DIR); list_del_init(&pTS->List); @@ -524,20 +475,16 @@ void RemovePeerTS(struct ieee80211_device *ieee, u8 *Addr) } } - list_for_each_entry_safe(pTS, pTmpTS, &ieee->Rx_TS_Pending_List, List) - { - if (memcmp(pTS->Addr, Addr, 6) == 0) - { + list_for_each_entry_safe(pTS, pTmpTS, &ieee->Rx_TS_Pending_List, List) { + if (memcmp(pTS->Addr, Addr, 6) == 0) { RemoveTsEntry(ieee, pTS, RX_DIR); list_del_init(&pTS->List); list_add_tail(&pTS->List, &ieee->Rx_TS_Unused_List); } } - list_for_each_entry_safe(pTS, pTmpTS, &ieee->Rx_TS_Admit_List, List) - { - if (memcmp(pTS->Addr, Addr, 6) == 0) - { + list_for_each_entry_safe(pTS, pTmpTS, &ieee->Rx_TS_Admit_List, List) { + if (memcmp(pTS->Addr, Addr, 6) == 0) { RemoveTsEntry(ieee, pTS, RX_DIR); list_del_init(&pTS->List); list_add_tail(&pTS->List, &ieee->Rx_TS_Unused_List); @@ -549,29 +496,25 @@ void RemoveAllTS(struct ieee80211_device *ieee) { PTS_COMMON_INFO pTS, pTmpTS; - list_for_each_entry_safe(pTS, pTmpTS, &ieee->Tx_TS_Pending_List, List) - { + list_for_each_entry_safe(pTS, pTmpTS, &ieee->Tx_TS_Pending_List, List) { RemoveTsEntry(ieee, pTS, TX_DIR); list_del_init(&pTS->List); list_add_tail(&pTS->List, &ieee->Tx_TS_Unused_List); } - list_for_each_entry_safe(pTS, pTmpTS, &ieee->Tx_TS_Admit_List, List) - { + list_for_each_entry_safe(pTS, pTmpTS, &ieee->Tx_TS_Admit_List, List) { RemoveTsEntry(ieee, pTS, TX_DIR); list_del_init(&pTS->List); list_add_tail(&pTS->List, &ieee->Tx_TS_Unused_List); } - list_for_each_entry_safe(pTS, pTmpTS, &ieee->Rx_TS_Pending_List, List) - { + list_for_each_entry_safe(pTS, pTmpTS, &ieee->Rx_TS_Pending_List, List) { RemoveTsEntry(ieee, pTS, RX_DIR); list_del_init(&pTS->List); list_add_tail(&pTS->List, &ieee->Rx_TS_Unused_List); } - list_for_each_entry_safe(pTS, pTmpTS, &ieee->Rx_TS_Admit_List, List) - { + list_for_each_entry_safe(pTS, pTmpTS, &ieee->Rx_TS_Admit_List, List) { RemoveTsEntry(ieee, pTS, RX_DIR); list_del_init(&pTS->List); list_add_tail(&pTS->List, &ieee->Rx_TS_Unused_List); @@ -580,21 +523,17 @@ void RemoveAllTS(struct ieee80211_device *ieee) void TsStartAddBaProcess(struct ieee80211_device *ieee, PTX_TS_RECORD pTxTS) { - if(!pTxTS->bAddBaReqInProgress) - { + if(!pTxTS->bAddBaReqInProgress) { pTxTS->bAddBaReqInProgress = true; - if(pTxTS->bAddBaReqDelayed) - { + if(pTxTS->bAddBaReqDelayed) { IEEE80211_DEBUG(IEEE80211_DL_BA, "TsStartAddBaProcess(): Delayed Start ADDBA after 60 sec!!\n"); mod_timer(&pTxTS->TsAddBaTimer, jiffies + msecs_to_jiffies(TS_ADDBA_DELAY)); - } - else - { + } else { IEEE80211_DEBUG(IEEE80211_DL_BA,"TsStartAddBaProcess(): Immediately Start ADDBA now!!\n"); mod_timer(&pTxTS->TsAddBaTimer, jiffies+10); //set 10 ticks } - } - else + } else { IEEE80211_DEBUG(IEEE80211_DL_ERR, "%s()==>BA timer is already added\n", __func__); + } } diff --git a/drivers/staging/rtl8192u/r8192U.h b/drivers/staging/rtl8192u/r8192U.h index e702afb5a70e..51c150a39fc2 100644 --- a/drivers/staging/rtl8192u/r8192U.h +++ b/drivers/staging/rtl8192u/r8192U.h @@ -34,7 +34,7 @@ #include <linux/proc_fs.h> #include <linux/if_arp.h> #include <linux/random.h> -#include <asm/io.h> +#include <linux/io.h> #include "ieee80211/ieee80211.h" #define RTL8192U @@ -1147,9 +1147,9 @@ int write_nic_word(struct net_device *dev, int x, u16 y); int write_nic_dword(struct net_device *dev, int x, u32 y); void force_pci_posting(struct net_device *dev); -void rtl8192_rtx_disable(struct net_device *); -void rtl8192_rx_enable(struct net_device *); -void rtl8192_tx_enable(struct net_device *); +void rtl8192_rtx_disable(struct net_device *dev); +void rtl8192_rx_enable(struct net_device *dev); +void rtl8192_tx_enable(struct net_device *dev); void rtl8192_disassociate(struct net_device *dev); void rtl8185_set_rf_pins_enable(struct net_device *dev, u32 a); diff --git a/drivers/staging/rtl8192u/r8192U_core.c b/drivers/staging/rtl8192u/r8192U_core.c index 9f370e8d84d3..779ecdbc4e17 100644 --- a/drivers/staging/rtl8192u/r8192U_core.c +++ b/drivers/staging/rtl8192u/r8192U_core.c @@ -1797,8 +1797,8 @@ static void rtl8192_link_change(struct net_device *dev) * way, but there is no chance to set this as wep will not set * group key in wext. */ - if (KEY_TYPE_WEP40 == ieee->pairwise_key_type || - KEY_TYPE_WEP104 == ieee->pairwise_key_type) + if (ieee->pairwise_key_type == KEY_TYPE_WEP40 || + ieee->pairwise_key_type == KEY_TYPE_WEP104) EnableHWSecurityConfig8192(dev); } /*update timing params*/ @@ -2071,7 +2071,7 @@ static bool GetNmodeSupportBySecCfg8192(struct net_device *dev) */ encrypt = (network->capability & WLAN_CAPABILITY_PRIVACY) || (ieee->host_encrypt && crypt && crypt->ops && - (0 == strcmp(crypt->ops->name, "WEP"))); + (strcmp(crypt->ops->name, "WEP") == 0)); /* simply judge */ if (encrypt && (wpa_ie_len == 0)) { @@ -4498,7 +4498,7 @@ static void TranslateRxSignalStuff819xUsb(struct sk_buff *skb, praddr = hdr->addr1; /* Check if the received packet is acceptable. */ - bpacket_match_bssid = (IEEE80211_FTYPE_CTL != type) && + bpacket_match_bssid = (type != IEEE80211_FTYPE_CTL) && (eqMacAddr(priv->ieee80211->current_network.bssid, (fc & IEEE80211_FCTL_TODS) ? hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS) ? hdr->addr2 : hdr->addr3)) && (!pstats->bHwError) && (!pstats->bCRC) && (!pstats->bICV); bpacket_toself = bpacket_match_bssid & @@ -5098,7 +5098,7 @@ void EnableHWSecurityConfig8192(struct net_device *dev) struct ieee80211_device *ieee = priv->ieee80211; SECR_value = SCR_TxEncEnable | SCR_RxDecEnable; - if (((KEY_TYPE_WEP40 == ieee->pairwise_key_type) || (KEY_TYPE_WEP104 == ieee->pairwise_key_type)) && (priv->ieee80211->auth_mode != 2)) { + if (((ieee->pairwise_key_type == KEY_TYPE_WEP40) || (ieee->pairwise_key_type == KEY_TYPE_WEP104)) && (priv->ieee80211->auth_mode != 2)) { SECR_value |= SCR_RxUseDK; SECR_value |= SCR_TxUseDK; } else if ((ieee->iw_mode == IW_MODE_ADHOC) && (ieee->pairwise_key_type & (KEY_TYPE_CCMP | KEY_TYPE_TKIP))) { diff --git a/drivers/staging/rtl8192u/r8192U_dm.c b/drivers/staging/rtl8192u/r8192U_dm.c index 975f707827e1..e6f8d1da65d9 100644 --- a/drivers/staging/rtl8192u/r8192U_dm.c +++ b/drivers/staging/rtl8192u/r8192U_dm.c @@ -2300,43 +2300,52 @@ static void dm_check_edca_turbo( * Restore original EDCA according to the declaration of AP. */ if (priv->bcurrent_turbo_EDCA) { + u8 u1bAIFS; + u32 u4bAcParam, op_limit, cw_max, cw_min; + + struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters; + u8 mode = priv->ieee80211->mode; + + /* For Each time updating EDCA parameter, reset EDCA turbo mode status. */ + dm_init_edca_turbo(dev); + + u1bAIFS = qos_parameters->aifs[0] * ((mode & (IEEE_G | IEEE_N_24G)) ? 9 : 20) + aSifsTime; + + op_limit = (u32)le16_to_cpu(qos_parameters->tx_op_limit[0]); + cw_max = (u32)le16_to_cpu(qos_parameters->cw_max[0]); + cw_min = (u32)le16_to_cpu(qos_parameters->cw_min[0]); + + op_limit <<= AC_PARAM_TXOP_LIMIT_OFFSET; + cw_max <<= AC_PARAM_ECW_MAX_OFFSET; + cw_min <<= AC_PARAM_ECW_MIN_OFFSET; + u1bAIFS <<= AC_PARAM_AIFS_OFFSET; + + u4bAcParam = op_limit | cw_max | cw_min | u1bAIFS; + cpu_to_le32s(&u4bAcParam); + + write_nic_dword(dev, EDCAPARA_BE, u4bAcParam); + + + /* + * Check ACM bit. + * If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13. + */ { - u8 u1bAIFS; - u32 u4bAcParam; - struct ieee80211_qos_parameters *qos_parameters = &priv->ieee80211->current_network.qos_data.parameters; - u8 mode = priv->ieee80211->mode; - - /* For Each time updating EDCA parameter, reset EDCA turbo mode status. */ - dm_init_edca_turbo(dev); - u1bAIFS = qos_parameters->aifs[0] * ((mode&(IEEE_G|IEEE_N_24G)) ? 9 : 20) + aSifsTime; - u4bAcParam = (((le16_to_cpu(qos_parameters->tx_op_limit[0])) << AC_PARAM_TXOP_LIMIT_OFFSET)| - ((le16_to_cpu(qos_parameters->cw_max[0])) << AC_PARAM_ECW_MAX_OFFSET)| - ((le16_to_cpu(qos_parameters->cw_min[0])) << AC_PARAM_ECW_MIN_OFFSET)| - ((u32)u1bAIFS << AC_PARAM_AIFS_OFFSET)); - /*write_nic_dword(dev, WDCAPARA_ADD[i], u4bAcParam);*/ - write_nic_dword(dev, EDCAPARA_BE, u4bAcParam); - - /* - * Check ACM bit. - * If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13. - */ - { - /* TODO: Modified this part and try to set acm control in only 1 IO processing!! */ - - PACI_AIFSN pAciAifsn = (PACI_AIFSN)&(qos_parameters->aifs[0]); - u8 AcmCtrl; - - read_nic_byte(dev, AcmHwCtrl, &AcmCtrl); - - if (pAciAifsn->f.ACM) { /* ACM bit is 1. */ - AcmCtrl |= AcmHw_BeqEn; - } else { /* ACM bit is 0. */ - AcmCtrl &= (~AcmHw_BeqEn); - } + /* TODO: Modified this part and try to set acm control in only 1 IO processing!! */ - RT_TRACE(COMP_QOS, "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl); - write_nic_byte(dev, AcmHwCtrl, AcmCtrl); + PACI_AIFSN pAciAifsn = (PACI_AIFSN)&(qos_parameters->aifs[0]); + u8 AcmCtrl; + + read_nic_byte(dev, AcmHwCtrl, &AcmCtrl); + + if (pAciAifsn->f.ACM) { /* ACM bit is 1. */ + AcmCtrl |= AcmHw_BeqEn; + } else { /* ACM bit is 0. */ + AcmCtrl &= (~AcmHw_BeqEn); } + + RT_TRACE(COMP_QOS, "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl); + write_nic_byte(dev, AcmHwCtrl, AcmCtrl); } priv->bcurrent_turbo_EDCA = false; } diff --git a/drivers/staging/rtl8712/ieee80211.c b/drivers/staging/rtl8712/ieee80211.c index f35121eedac6..33e82a9dd462 100644 --- a/drivers/staging/rtl8712/ieee80211.c +++ b/drivers/staging/rtl8712/ieee80211.c @@ -166,7 +166,7 @@ static uint r8712_get_rateset_len(u8 *rateset) int r8712_generate_ie(struct registry_priv *pregistrypriv) { - int sz = 0, rateLen; + int sz = 0, rate_len; struct wlan_bssid_ex *pdev_network = &pregistrypriv->dev_network; u8 *ie = pdev_network->IEs; @@ -191,15 +191,16 @@ int r8712_generate_ie(struct registry_priv *pregistrypriv) pdev_network->Ssid.Ssid, &sz); /*supported rates*/ set_supported_rate(pdev_network->rates, pregistrypriv->wireless_mode); - rateLen = r8712_get_rateset_len(pdev_network->rates); - if (rateLen > 8) { + rate_len = r8712_get_rateset_len(pdev_network->rates); + if (rate_len > 8) { ie = r8712_set_ie(ie, _SUPPORTEDRATES_IE_, 8, pdev_network->rates, &sz); - ie = r8712_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), + ie = r8712_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (pdev_network->rates + 8), &sz); - } else + } else { ie = r8712_set_ie(ie, _SUPPORTEDRATES_IE_, - rateLen, pdev_network->rates, &sz); + rate_len, pdev_network->rates, &sz); + } /*DS parameter set*/ ie = r8712_set_ie(ie, _DSSET_IE_, 1, (u8 *)&pdev_network->Configuration.DSConfig, &sz); diff --git a/drivers/staging/rtl8712/os_intfs.c b/drivers/staging/rtl8712/os_intfs.c index 8836b31b4ef8..e698f6ede449 100644 --- a/drivers/staging/rtl8712/os_intfs.c +++ b/drivers/staging/rtl8712/os_intfs.c @@ -93,7 +93,7 @@ static char *initmac; */ static int wifi_test; -module_param_string(ifname, ifname, sizeof(ifname), S_IRUGO | S_IWUSR); +module_param_string(ifname, ifname, sizeof(ifname), 0644); module_param(wifi_test, int, 0644); module_param(initmac, charp, 0644); module_param(video_mode, int, 0644); diff --git a/drivers/staging/rtl8712/wifi.h b/drivers/staging/rtl8712/wifi.h index 556367bfbe8a..0ed2f44ab4e9 100644 --- a/drivers/staging/rtl8712/wifi.h +++ b/drivers/staging/rtl8712/wifi.h @@ -170,8 +170,10 @@ enum WIFI_REG_DOMAIN { *(__le16 *)(pbuf) &= (~cpu_to_le16(_FROM_DS_)); \ }) -#define get_tofr_ds(pframe) ((GetToDs(pframe) << 1) | GetFrDs(pframe)) - +static inline unsigned char get_tofr_ds(unsigned char *pframe) +{ + return ((GetToDs(pframe) << 1) | GetFrDs(pframe)); +} #define SetMFrag(pbuf) ({ \ *(__le16 *)(pbuf) |= cpu_to_le16(_MORE_FRAG_); \ diff --git a/drivers/staging/rtl8723bs/core/rtw_mlme.c b/drivers/staging/rtl8723bs/core/rtw_mlme.c index 9e355734f0c0..d5ab12305e59 100644 --- a/drivers/staging/rtl8723bs/core/rtw_mlme.c +++ b/drivers/staging/rtl8723bs/core/rtw_mlme.c @@ -249,7 +249,7 @@ void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network * /* return the wlan_network with the matching addr - Shall be calle under atomic context... to avoid possible racing condition... + Shall be called under atomic context... to avoid possible racing condition... */ struct wlan_network *_rtw_find_network(struct __queue *scanned_queue, u8 *addr) { @@ -412,7 +412,7 @@ void rtw_free_network_queue(struct adapter *dev, u8 isfreeall) /* return the wlan_network with the matching addr - Shall be calle under atomic context... to avoid possible racing condition... + Shall be called under atomic context... to avoid possible racing condition... */ struct wlan_network *rtw_find_network(struct __queue *scanned_queue, u8 *addr) { @@ -564,7 +564,7 @@ void update_network(struct wlan_bssid_ex *dst, struct wlan_bssid_ex *src, sq_final = ((u32)(src->PhyInfo.SignalQuality)+(u32)(dst->PhyInfo.SignalQuality)*4)/5; rssi_final = (src->Rssi+dst->Rssi*4)/5; } else { - /* bss info not receving from the right channel, use the original RX signal infos */ + /* bss info not receiving from the right channel, use the original RX signal infos */ ss_final = dst->PhyInfo.SignalStrength; sq_final = dst->PhyInfo.SignalQuality; rssi_final = dst->Rssi; @@ -680,7 +680,7 @@ void rtw_update_scanned_network(struct adapter *adapter, struct wlan_bssid_ex *t pnetwork->aid = 0; pnetwork->join_res = 0; - /* bss info not receving from the right channel */ + /* bss info not receiving from the right channel */ if (pnetwork->network.PhyInfo.SignalQuality == 101) pnetwork->network.PhyInfo.SignalQuality = 0; } else { @@ -699,7 +699,7 @@ void rtw_update_scanned_network(struct adapter *adapter, struct wlan_bssid_ex *t pnetwork->last_scanned = jiffies; - /* bss info not receving from the right channel */ + /* bss info not receiving from the right channel */ if (pnetwork->network.PhyInfo.SignalQuality == 101) pnetwork->network.PhyInfo.SignalQuality = 0; @@ -715,7 +715,7 @@ void rtw_update_scanned_network(struct adapter *adapter, struct wlan_bssid_ex *t pnetwork->last_scanned = jiffies; - /* target.Reserved[0]== 1, means that scaned network is a bcn frame. */ + /* target.Reserved[0]== 1, means that scanned network is a bcn frame. */ if ((pnetwork->network.IELength > target->IELength) && (target->Reserved[0] == 1)) update_ie = false; @@ -1264,7 +1264,7 @@ static struct sta_info *rtw_joinbss_update_stainfo(struct adapter *padapter, str /* Commented by Albert 2012/07/21 */ /* When doing the WPS, the wps_ie_len won't equal to 0 */ - /* And the Wi-Fi driver shouldn't allow the data packet to be tramsmitted. */ + /* And the Wi-Fi driver shouldn't allow the data packet to be transmitted. */ if (padapter->securitypriv.wps_ie_len != 0) { psta->ieee8021x_blocked = true; padapter->securitypriv.wps_ie_len = 0; @@ -1272,7 +1272,7 @@ static struct sta_info *rtw_joinbss_update_stainfo(struct adapter *padapter, str /* for A-MPDU Rx reordering buffer control for bmc_sta & sta_info */ - /* if A-MPDU Rx is enabled, reseting rx_ordering_ctrl wstart_b(indicate_seq) to default value = 0xffff */ + /* if A-MPDU Rx is enabled, resetting rx_ordering_ctrl wstart_b(indicate_seq) to default value = 0xffff */ /* todo: check if AP can send A-MPDU packets */ for (i = 0; i < 16 ; i++) { /* preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; */ @@ -1374,7 +1374,7 @@ static void rtw_joinbss_update_network(struct adapter *padapter, struct wlan_net rtw_update_ht_cap(padapter, cur_network->network.IEs, cur_network->network.IELength, (u8) cur_network->network.Configuration.DSConfig); } -/* Notes: the fucntion could be > passive_level (the same context as Rx tasklet) */ +/* Notes: the function could be > passive_level (the same context as Rx tasklet) */ /* pnetwork : returns from rtw_joinbss_event_callback */ /* ptarget_wlan: found from scanned_queue */ /* if join_res > 0, for (fw_state ==WIFI_STATION_STATE), we check if "ptarget_sta" & "ptarget_wlan" exist. */ @@ -1482,10 +1482,10 @@ void rtw_joinbss_event_prehandle(struct adapter *adapter, u8 *pbuf) } - /* s5. Cancle assoc_timer */ + /* s5. Cancel assoc_timer */ _cancel_timer(&pmlmepriv->assoc_timer, &timer_cancelled); - RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("Cancle assoc_timer\n")); + RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("Cancel assoc_timer\n")); } else{ RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("rtw_joinbss_event_callback err: fw_state:%x", get_fwstate(pmlmepriv))); @@ -1817,7 +1817,7 @@ void rtw_wmm_event_callback(struct adapter *padapter, u8 *pbuf) } /* -* _rtw_join_timeout_handler - Timeout/faliure handler for CMD JoinBss +* _rtw_join_timeout_handler - Timeout/failure handler for CMD JoinBss * @adapter: pointer to struct adapter structure */ void _rtw_join_timeout_handler (struct adapter *adapter) @@ -1870,7 +1870,7 @@ void _rtw_join_timeout_handler (struct adapter *adapter) } /* -* rtw_scan_timeout_handler - Timeout/Faliure handler for CMD SiteSurvey +* rtw_scan_timeout_handler - Timeout/Failure handler for CMD SiteSurvey * @adapter: pointer to struct adapter structure */ void rtw_scan_timeout_handler (struct adapter *adapter) @@ -2622,7 +2622,7 @@ void rtw_get_encrypt_decrypt_from_registrypriv(struct adapter *adapter) { } -/* the fucntion is at passive_level */ +/* the function is at passive_level */ void rtw_joinbss_reset(struct adapter *padapter) { u8 threshold; @@ -2727,7 +2727,7 @@ void rtw_build_wmm_ie_ht(struct adapter *padapter, u8 *out_ie, uint *pout_len) } } -/* the fucntion is >= passive_level */ +/* the function is >= passive_level */ unsigned int rtw_restructure_ht_ie(struct adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, u8 channel) { u32 ielen, out_len; @@ -2879,7 +2879,7 @@ unsigned int rtw_restructure_ht_ie(struct adapter *padapter, u8 *in_ie, u8 *out_ } -/* the fucntion is > passive_level (in critical_section) */ +/* the function is > passive_level (in critical_section) */ void rtw_update_ht_cap(struct adapter *padapter, u8 *pie, uint ie_len, u8 channel) { u8 *p, max_ampdu_sz; diff --git a/drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.c b/drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.c index 86040adb436c..37f42bfc55ed 100644 --- a/drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.c +++ b/drivers/staging/rtl8723bs/hal/HalBtc8723b1Ant.c @@ -404,7 +404,7 @@ static void halbtc8723b1ant_MonitorWiFiCtr(PBTC_COEXIST pBtCoexist) { s32 wifiRssi = 0; bool bWifiBusy = false, bWifiUnderBMode = false; - static u8 nCCKLockCounter = 0; + static u8 nCCKLockCounter; pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); @@ -488,7 +488,7 @@ static void halbtc8723b1ant_MonitorWiFiCtr(PBTC_COEXIST pBtCoexist) static bool halbtc8723b1ant_IsWifiStatusChanged(PBTC_COEXIST pBtCoexist) { - static bool bPreWifiBusy = false, bPreUnder4way = false, bPreBtHsOn = false; + static bool bPreWifiBusy, bPreUnder4way, bPreBtHsOn; bool bWifiBusy = false, bUnder4way = false, bBtHsOn = false; bool bWifiConnected = false; @@ -2754,7 +2754,7 @@ void EXhalbtc8723b1ant_DisplayCoexInfo(PBTC_COEXIST pBtCoexist) u32 wifiBw, wifiTrafficDir, faOfdm, faCck, wifiLinkStatus; u8 wifiDot11Chnl, wifiHsChnl; u32 fwVer = 0, btPatchVer = 0; - static u8 PopReportIn10s = 0; + static u8 PopReportIn10s; CL_SPRINTF( cliBuf, @@ -3751,7 +3751,7 @@ void EXhalbtc8723b1ant_PnpNotify(PBTC_COEXIST pBtCoexist, u8 pnpState) void EXhalbtc8723b1ant_Periodical(PBTC_COEXIST pBtCoexist) { - static u8 disVerInfoCnt = 0; + static u8 disVerInfoCnt; u32 fwVer = 0, btPatchVer = 0; BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], ==========================Periodical ===========================\n")); diff --git a/drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.c b/drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.c index f5bc511d02f2..33610d39333f 100644 --- a/drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.c +++ b/drivers/staging/rtl8723bs/hal/HalBtc8723b2Ant.c @@ -282,7 +282,7 @@ static void halbtc8723b2ant_QueryBtInfo(PBTC_COEXIST pBtCoexist) static bool halbtc8723b2ant_IsWifiStatusChanged(PBTC_COEXIST pBtCoexist) { - static bool bPreWifiBusy = false, bPreUnder4way = false, bPreBtHsOn = false; + static bool bPreWifiBusy, bPreUnder4way, bPreBtHsOn; bool bWifiBusy = false, bUnder4way = false, bBtHsOn = false; bool bWifiConnected = false; @@ -3706,7 +3706,7 @@ void EXhalbtc8723b2ant_PnpNotify(PBTC_COEXIST pBtCoexist, u8 pnpState) void EXhalbtc8723b2ant_Periodical(PBTC_COEXIST pBtCoexist) { - static u8 disVerInfoCnt = 0; + static u8 disVerInfoCnt; u32 fwVer = 0, btPatchVer = 0; BTC_PRINT(BTC_MSG_ALGORITHM, ALGO_TRACE, ("[BTCoex], ==========================Periodical ===========================\n")); diff --git a/drivers/staging/rtl8723bs/hal/hal_btcoex.c b/drivers/staging/rtl8723bs/hal/hal_btcoex.c index cc7e0903ee9d..9e08a4de4895 100644 --- a/drivers/staging/rtl8723bs/hal/hal_btcoex.c +++ b/drivers/staging/rtl8723bs/hal/hal_btcoex.c @@ -385,7 +385,7 @@ static s32 halbtcoutsrc_GetWifiRssi(struct adapter *padapter) static u8 halbtcoutsrc_GetWifiScanAPNum(struct adapter *padapter) { struct mlme_ext_priv *pmlmeext; - static u8 scan_AP_num = 0; + static u8 scan_AP_num; pmlmeext = &padapter->mlmeextpriv; diff --git a/drivers/staging/rtl8723bs/hal/hal_com.c b/drivers/staging/rtl8723bs/hal/hal_com.c index 1880d4140bee..e3a98322f475 100644 --- a/drivers/staging/rtl8723bs/hal/hal_com.c +++ b/drivers/staging/rtl8723bs/hal/hal_com.c @@ -26,7 +26,7 @@ u8 rtw_hal_data_init(struct adapter *padapter) padapter->hal_data_sz = sizeof(struct hal_com_data); padapter->HalData = vzalloc(padapter->hal_data_sz); if (padapter->HalData == NULL) { - DBG_8192C("cant not alloc memory for HAL DATA\n"); + DBG_8192C("cannot alloc memory for HAL DATA\n"); return _FAIL; } } @@ -1415,7 +1415,8 @@ bool GetHexValueFromString(char *szStr, u32 *pu4bVal, u32 *pu4bMove) /* Check input parameter. */ if (szStr == NULL || pu4bVal == NULL || pu4bMove == NULL) { - DBG_871X("GetHexValueFromString(): Invalid inpur argumetns! szStr: %p, pu4bVal: %p, pu4bMove: %p\n", szStr, pu4bVal, pu4bMove); + DBG_871X("GetHexValueFromString(): Invalid input arguments! szStr: %p, pu4bVal: %p, pu4bMove: %p\n", + szStr, pu4bVal, pu4bMove); return false; } diff --git a/drivers/staging/rtl8723bs/hal/odm.h b/drivers/staging/rtl8723bs/hal/odm.h index 0b3541a91548..87a76bafecb3 100644 --- a/drivers/staging/rtl8723bs/hal/odm.h +++ b/drivers/staging/rtl8723bs/hal/odm.h @@ -209,7 +209,10 @@ typedef struct _ODM_RATE_ADAPTIVE { #define AVG_THERMAL_NUM 8 #define IQK_Matrix_REG_NUM 8 -#define IQK_Matrix_Settings_NUM 14+24+21 /* Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G */ +#define IQK_Matrix_Settings_NUM (14 + 24 + 21) /* Channels_2_4G_NUM + * + Channels_5G_20M_NUM + * + Channels_5G + */ #define DM_Type_ByFW 0 #define DM_Type_ByDriver 1 diff --git a/drivers/staging/rtl8723bs/hal/odm_DIG.c b/drivers/staging/rtl8723bs/hal/odm_DIG.c index ba8e8eb534ef..0bde9444471d 100644 --- a/drivers/staging/rtl8723bs/hal/odm_DIG.c +++ b/drivers/staging/rtl8723bs/hal/odm_DIG.c @@ -278,11 +278,11 @@ void odm_Adaptivity(void *pDM_VOID, u8 IGI) if (!pDM_Odm->ForceEDCCA) { if (pDM_Odm->RSSI_Min > pDM_Odm->AdapEn_RSSI) - EDCCA_State = 1; + EDCCA_State = true; else if (pDM_Odm->RSSI_Min < (pDM_Odm->AdapEn_RSSI - 5)) - EDCCA_State = 0; + EDCCA_State = false; } else - EDCCA_State = 1; + EDCCA_State = true; if ( pDM_Odm->bLinked && @@ -305,7 +305,7 @@ void odm_Adaptivity(void *pDM_VOID, u8 IGI) ) ); - if (EDCCA_State == 1) { + if (EDCCA_State) { Diff = IGI_target-(s8)IGI; TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff; if (TH_L2H_dmc > 10) @@ -372,7 +372,7 @@ void odm_PauseDIG( { PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; - static bool bPaused = false; + static bool bPaused; ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG() =========>\n")); diff --git a/drivers/staging/rtl8723bs/hal/odm_debug.h b/drivers/staging/rtl8723bs/hal/odm_debug.h index 2ec4baf57464..ff131361248c 100644 --- a/drivers/staging/rtl8723bs/hal/odm_debug.h +++ b/drivers/staging/rtl8723bs/hal/odm_debug.h @@ -105,51 +105,60 @@ #if DBG #define ODM_RT_TRACE(pDM_Odm, comp, level, fmt)\ - if (\ - (comp & pDM_Odm->DebugComponents) &&\ - (level <= pDM_Odm->DebugLevel || level == ODM_DBG_SERIOUS)\ - ) {\ - RT_PRINTK fmt;\ - } + do {\ + if (\ + (comp & pDM_Odm->DebugComponents) &&\ + (level <= pDM_Odm->DebugLevel ||\ + level == ODM_DBG_SERIOUS)\ + ) {\ + RT_PRINTK fmt;\ + } \ + } while (0) #define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt)\ - if (\ - (comp & pDM_Odm->DebugComponents) &&\ - (level <= pDM_Odm->DebugLevel)\ - ) {\ - RT_PRINTK fmt;\ - } + do {\ + if (\ + (comp & pDM_Odm->DebugComponents) &&\ + (level <= pDM_Odm->DebugLevel)\ + ) {\ + RT_PRINTK fmt;\ + } \ + } while (0) #define ODM_RT_ASSERT(pDM_Odm, expr, fmt)\ - if (!expr) {\ - DbgPrint("Assertion failed! %s at ......\n", #expr);\ - DbgPrint(\ - " ......%s,%s, line =%d\n",\ - __FILE__,\ - __func__,\ - __LINE__\ - );\ - RT_PRINTK fmt;\ - ASSERT(false);\ - } + do {\ + if (!expr) {\ + DbgPrint("Assertion failed! %s at ......\n", #expr);\ + DbgPrint(\ + " ......%s,%s, line =%d\n",\ + __FILE__,\ + __func__,\ + __LINE__\ + );\ + RT_PRINTK fmt;\ + ASSERT(false);\ + } \ + } while (0) #define ODM_dbg_enter() { DbgPrint("==> %s\n", __func__); } #define ODM_dbg_exit() { DbgPrint("<== %s\n", __func__); } #define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __func__, str); } #define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr)\ - if (\ - (comp & pDM_Odm->DebugComponents) &&\ - (level <= pDM_Odm->DebugLevel)\ - ) {\ - int __i;\ - u8 *__ptr = (u8 *)ptr;\ - DbgPrint("[ODM] ");\ - DbgPrint(title_str);\ - DbgPrint(" ");\ - for (__i = 0; __i < 6; __i++)\ - DbgPrint("%02X%s", __ptr[__i], (__i == 5) ? "" : "-");\ - DbgPrint("\n");\ - } + do {\ + if (\ + (comp & pDM_Odm->DebugComponents) &&\ + (level <= pDM_Odm->DebugLevel)\ + ) {\ + int __i;\ + u8 *__ptr = (u8 *)ptr;\ + DbgPrint("[ODM] ");\ + DbgPrint(title_str);\ + DbgPrint(" ");\ + for (__i = 0; __i < 6; __i++)\ + DbgPrint("%02X%s", __ptr[__i], (__i == 5) ? "" : "-");\ + DbgPrint("\n");\ + } \ + } while (0) #else #define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) no_printk fmt #define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) no_printk fmt diff --git a/drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c b/drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c index 163537faefd9..84a89ef74169 100644 --- a/drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c +++ b/drivers/staging/rtl8723bs/hal/rtl8723b_hal_init.c @@ -1741,7 +1741,8 @@ static u8 hal_EfusePgPacketWrite2ByteHeader( efuse_addr = *pAddr; if (efuse_addr >= efuse_max_available_len) { - DBG_8192C("%s: addr(%d) over avaliable(%d)!!\n", __func__, efuse_addr, efuse_max_available_len); + DBG_8192C("%s: addr(%d) over available (%d)!!\n", __func__, + efuse_addr, efuse_max_available_len); return false; } diff --git a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c index 28d1a229c3a6..21ec890fd60c 100644 --- a/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c +++ b/drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c @@ -385,8 +385,7 @@ s32 PHY_MACConfig8723B(struct adapter *Adapter) /* Config MAC */ /* */ rtStatus = phy_ConfigMACWithParaFile(Adapter, pszMACRegFile); - if (rtStatus == _FAIL) - { + if (rtStatus == _FAIL) { ODM_ConfigMACWithHeaderFile(&pHalData->odmpriv); rtStatus = _SUCCESS; } @@ -459,8 +458,7 @@ static int phy_BB8723b_Config_ParaFile(struct adapter *Adapter) Adapter->registrypriv.RegEnableTxPowerLimit == 1 || (Adapter->registrypriv.RegEnableTxPowerLimit == 2 && pHalData->EEPROMRegulatory == 1) ) { - if (PHY_ConfigRFWithPowerLimitTableParaFile(Adapter, pszRFTxPwrLmtFile) == _FAIL) - { + if (PHY_ConfigRFWithPowerLimitTableParaFile(Adapter, pszRFTxPwrLmtFile) == _FAIL) { if (HAL_STATUS_SUCCESS != ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, CONFIG_RF_TXPWR_LMT, (ODM_RF_RADIO_PATH_E)0)) rtStatus = _FAIL; } @@ -474,8 +472,8 @@ static int phy_BB8723b_Config_ParaFile(struct adapter *Adapter) /* */ /* 1. Read PHY_REG.TXT BB INIT!! */ /* */ - if (phy_ConfigBBWithParaFile(Adapter, pszBBRegFile, CONFIG_BB_PHY_REG) == _FAIL) - { + if (phy_ConfigBBWithParaFile(Adapter, pszBBRegFile, CONFIG_BB_PHY_REG) == + _FAIL) { if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG)) rtStatus = _FAIL; } @@ -491,8 +489,8 @@ static int phy_BB8723b_Config_ParaFile(struct adapter *Adapter) Adapter->registrypriv.RegEnableTxPowerByRate == 1 || (Adapter->registrypriv.RegEnableTxPowerByRate == 2 && pHalData->EEPROMRegulatory != 2) ) { - if (phy_ConfigBBWithPgParaFile(Adapter, pszBBRegPgFile) == _FAIL) - { + if (phy_ConfigBBWithPgParaFile(Adapter, pszBBRegPgFile) == + _FAIL) { if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_PG)) rtStatus = _FAIL; } @@ -514,8 +512,8 @@ static int phy_BB8723b_Config_ParaFile(struct adapter *Adapter) /* */ /* 2. Read BB AGC table Initialization */ /* */ - if (phy_ConfigBBWithParaFile(Adapter, pszAGCTableFile, CONFIG_BB_AGC_TAB) == _FAIL) - { + if (phy_ConfigBBWithParaFile(Adapter, pszAGCTableFile, + CONFIG_BB_AGC_TAB) == _FAIL) { if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB)) rtStatus = _FAIL; } diff --git a/drivers/staging/rtl8723bs/hal/rtl8723b_rf6052.c b/drivers/staging/rtl8723bs/hal/rtl8723b_rf6052.c index 3a85d0cddfda..a71b552eca9a 100644 --- a/drivers/staging/rtl8723bs/hal/rtl8723b_rf6052.c +++ b/drivers/staging/rtl8723bs/hal/rtl8723b_rf6052.c @@ -144,15 +144,15 @@ static int phy_RF6052_Config_ParaFile(struct adapter *Adapter) /*----Initialize RF fom connfiguration file----*/ switch (eRFPath) { case RF_PATH_A: - if (PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, eRFPath) == _FAIL) - { + if (PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, + eRFPath) == _FAIL) { if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, CONFIG_RF_RADIO, (ODM_RF_RADIO_PATH_E)eRFPath)) rtStatus = _FAIL; } break; case RF_PATH_B: - if (PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, eRFPath) == _FAIL) - { + if (PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, + eRFPath) == _FAIL) { if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, CONFIG_RF_RADIO, (ODM_RF_RADIO_PATH_E)eRFPath)) rtStatus = _FAIL; } @@ -186,8 +186,8 @@ static int phy_RF6052_Config_ParaFile(struct adapter *Adapter) /* 3 Configuration of Tx Power Tracking */ /* 3 ----------------------------------------------------------------- */ - if (PHY_ConfigRFWithTxPwrTrackParaFile(Adapter, pszTxPwrTrackFile) == _FAIL) - { + if (PHY_ConfigRFWithTxPwrTrackParaFile(Adapter, pszTxPwrTrackFile) == + _FAIL) { ODM_ConfigRFWithTxPwrTrackHeaderFile(&pHalData->odmpriv); } diff --git a/drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c b/drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c index ca6ad9659b09..9bee2e40be32 100644 --- a/drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c +++ b/drivers/staging/rtl8723bs/hal/rtl8723bs_xmit.c @@ -23,8 +23,7 @@ static u8 rtw_sdio_wait_enough_TxOQT_space(struct adapter *padapter, u8 agg_num) u32 n = 0; struct hal_com_data *pHalData = GET_HAL_DATA(padapter); - while (pHalData->SdioTxOQTFreeSpace < agg_num) - { + while (pHalData->SdioTxOQTFreeSpace < agg_num) { if ( (padapter->bSurpriseRemoved == true) || (padapter->bDriverStopped == true) @@ -59,7 +58,7 @@ static s32 rtl8723_dequeue_writeport(struct adapter *padapter) struct xmit_priv *pxmitpriv = &padapter->xmitpriv; struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); struct xmit_buf *pxmitbuf; - struct adapter * pri_padapter = padapter; + struct adapter *pri_padapter = padapter; s32 ret = 0; u8 PageIdx = 0; u32 deviceId; @@ -231,7 +230,7 @@ static s32 xmit_xmitframes(struct adapter *padapter, struct xmit_priv *pxmitpriv pxmitbuf = NULL; if (padapter->registrypriv.wifi_spec == 1) { - for (idx = 0; idx<4; idx++) + for (idx = 0; idx < 4; idx++) inx[idx] = pxmitpriv->wmm_para_seq[idx]; } else { inx[0] = 0; @@ -299,9 +298,10 @@ static s32 xmit_xmitframes(struct adapter *padapter, struct xmit_priv *pxmitpriv ) { if (pxmitbuf) { /* pxmitbuf->priv_data will be NULL, and will crash here */ - if (pxmitbuf->len > 0 && pxmitbuf->priv_data) { + if (pxmitbuf->len > 0 && + pxmitbuf->priv_data) { struct xmit_frame *pframe; - pframe = (struct xmit_frame*)pxmitbuf->priv_data; + pframe = (struct xmit_frame *)pxmitbuf->priv_data; pframe->agg_num = k; pxmitbuf->agg_num = k; rtl8723b_update_txdesc(pframe, pframe->buf_addr); @@ -392,7 +392,7 @@ static s32 xmit_xmitframes(struct adapter *padapter, struct xmit_priv *pxmitpriv if (pxmitbuf->len > 0) { struct xmit_frame *pframe; - pframe = (struct xmit_frame*)pxmitbuf->priv_data; + pframe = (struct xmit_frame *)pxmitbuf->priv_data; pframe->agg_num = k; pxmitbuf->agg_num = k; rtl8723b_update_txdesc(pframe, pframe->buf_addr); @@ -400,8 +400,7 @@ static s32 xmit_xmitframes(struct adapter *padapter, struct xmit_priv *pxmitpriv pxmitbuf->priv_data = NULL; enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf); yield(); - } - else + } else rtw_free_xmitbuf(pxmitpriv, pxmitbuf); pxmitbuf = NULL; } @@ -611,7 +610,8 @@ s32 rtl8723bs_hal_xmitframe_enqueue( struct xmit_priv *pxmitpriv = &padapter->xmitpriv; s32 err; - if ((err = rtw_xmitframe_enqueue(padapter, pxmitframe)) != _SUCCESS) { + err = rtw_xmitframe_enqueue(padapter, pxmitframe); + if (err != _SUCCESS) { rtw_free_xmitframe(pxmitpriv, pxmitframe); pxmitpriv->tx_drop++; diff --git a/drivers/staging/rtl8723bs/include/ieee80211.h b/drivers/staging/rtl8723bs/include/ieee80211.h index 6dc6dc73d72f..73ce63770c3c 100644 --- a/drivers/staging/rtl8723bs/include/ieee80211.h +++ b/drivers/staging/rtl8723bs/include/ieee80211.h @@ -1003,10 +1003,10 @@ enum ieee80211_state { #define DEFAULT_MAX_SCAN_AGE (15 * HZ) #define DEFAULT_FTS 2346 -#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" -#define MAC_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5] -#define IP_FMT "%d.%d.%d.%d" -#define IP_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3] +#define MAC_FMT "%pM" +#define MAC_ARG(x) (x) +#define IP_FMT "%pI4" +#define IP_ARG(x) (x) extern __inline int is_multicast_mac_addr(const u8 *addr) { diff --git a/drivers/staging/rtl8723bs/include/osdep_service.h b/drivers/staging/rtl8723bs/include/osdep_service.h index fdeabc1daeca..ac9ffe0e3b84 100644 --- a/drivers/staging/rtl8723bs/include/osdep_service.h +++ b/drivers/staging/rtl8723bs/include/osdep_service.h @@ -169,10 +169,10 @@ __inline static u32 _RND8(u32 sz) } #ifndef MAC_FMT -#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" +#define MAC_FMT "%pM" #endif #ifndef MAC_ARG -#define MAC_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5] +#define MAC_ARG(x) (x) #endif diff --git a/drivers/staging/rtl8723bs/include/osdep_service_linux.h b/drivers/staging/rtl8723bs/include/osdep_service_linux.h index 486e8184b0b2..0c9b4f622fee 100644 --- a/drivers/staging/rtl8723bs/include/osdep_service_linux.h +++ b/drivers/staging/rtl8723bs/include/osdep_service_linux.h @@ -26,10 +26,10 @@ /* include <linux/smp_lock.h> */ #include <linux/netdevice.h> #include <linux/skbuff.h> - #include <asm/uaccess.h> + #include <linux/uaccess.h> #include <asm/byteorder.h> - #include <asm/atomic.h> - #include <asm/io.h> + #include <linux/atomic.h> + #include <linux/io.h> #include <linux/semaphore.h> #include <linux/sem.h> #include <linux/sched.h> diff --git a/drivers/staging/rtl8723bs/include/rtl8192c_rf.h b/drivers/staging/rtl8723bs/include/rtl8192c_rf.h index 0dbee562d19b..97900a31b326 100644 --- a/drivers/staging/rtl8723bs/include/rtl8192c_rf.h +++ b/drivers/staging/rtl8723bs/include/rtl8192c_rf.h @@ -19,19 +19,16 @@ /* */ /* RF RL6052 Series API */ /* */ -void rtl8192c_RF_ChangeTxPath(struct adapter *Adapter, - u16 DataRate); -void rtl8192c_PHY_RF6052SetBandwidth( - struct adapter * Adapter, - enum CHANNEL_WIDTH Bandwidth); -void rtl8192c_PHY_RF6052SetCckTxPower( - struct adapter *Adapter, - u8* pPowerlevel); -void rtl8192c_PHY_RF6052SetOFDMTxPower( - struct adapter *Adapter, - u8* pPowerLevel, - u8 Channel); -int PHY_RF6052_Config8192C(struct adapter * Adapter ); +void rtl8192c_RF_ChangeTxPath(struct adapter *Adapter, + u16 DataRate); +void rtl8192c_PHY_RF6052SetBandwidth(struct adapter *Adapter, + enum CHANNEL_WIDTH Bandwidth); +void rtl8192c_PHY_RF6052SetCckTxPower(struct adapter *Adapter, + u8 *pPowerlevel); +void rtl8192c_PHY_RF6052SetOFDMTxPower(struct adapter *Adapter, + u8 *pPowerLevel, + u8 Channel); +int PHY_RF6052_Config8192C(struct adapter *Adapter); /*--------------------------Exported Function prototype---------------------*/ diff --git a/drivers/staging/rtl8723bs/include/rtl8723b_spec.h b/drivers/staging/rtl8723bs/include/rtl8723b_spec.h index 8d78f4ef5438..1906ff2038f5 100644 --- a/drivers/staging/rtl8723bs/include/rtl8723b_spec.h +++ b/drivers/staging/rtl8723bs/include/rtl8723b_spec.h @@ -17,12 +17,11 @@ #include <autoconf.h> - #define HAL_NAV_UPPER_UNIT_8723B 128 /* micro-second */ /* */ /* */ -/* 0x0000h ~ 0x00FFh System Configuration */ +/* 0x0000h ~ 0x00FFh System Configuration */ /* */ /* */ #define REG_RSV_CTRL_8723B 0x001C /* 3 Byte */ @@ -42,7 +41,7 @@ /* */ /* */ -/* 0x0100h ~ 0x01FFh MACTOP General Configuration */ +/* 0x0100h ~ 0x01FFh MACTOP General Configuration */ /* */ /* */ #define REG_C2HEVT_CMD_ID_8723B 0x01A0 @@ -58,13 +57,13 @@ /* */ /* */ -/* 0x0200h ~ 0x027Fh TXDMA Configuration */ +/* 0x0200h ~ 0x027Fh TXDMA Configuration */ /* */ /* */ /* */ /* */ -/* 0x0280h ~ 0x02FFh RXDMA Configuration */ +/* 0x0280h ~ 0x02FFh RXDMA Configuration */ /* */ /* */ #define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */ @@ -72,7 +71,7 @@ /* */ /* */ -/* 0x0300h ~ 0x03FFh PCIe */ +/* 0x0300h ~ 0x03FFh PCIe */ /* */ /* */ #define REG_PCIE_CTRL_REG_8723B 0x0300 @@ -99,7 +98,7 @@ /* */ /* */ -/* 0x0400h ~ 0x047Fh Protocol Configuration */ +/* 0x0400h ~ 0x047Fh Protocol Configuration */ /* */ /* */ #define REG_TXPKTBUF_BCNQ_BDNY_8723B 0x0424 @@ -113,18 +112,17 @@ /* */ /* */ -/* 0x0500h ~ 0x05FFh EDCA Configuration */ +/* 0x0500h ~ 0x05FFh EDCA Configuration */ /* */ /* */ #define REG_SECONDARY_CCA_CTRL_8723B 0x0577 /* */ /* */ -/* 0x0600h ~ 0x07FFh WMAC Configuration */ +/* 0x0600h ~ 0x07FFh WMAC Configuration */ /* */ /* */ - /* */ /* SDIO Bus Specification */ /* */ @@ -142,9 +140,8 @@ /* */ #define SDIO_REG_HCPWM1_8723B 0x025 /* HCI Current Power Mode 1 */ - /* */ -/* 8723 Regsiter Bit and Content definition */ +/* 8723 Register Bit and Content definition */ /* */ /* 2 HSISR */ @@ -157,20 +154,19 @@ /* */ /* */ -/* 0x0100h ~ 0x01FFh MACTOP General Configuration */ +/* 0x0100h ~ 0x01FFh MACTOP General Configuration */ /* */ /* */ - /* */ /* */ -/* 0x0200h ~ 0x027Fh TXDMA Configuration */ +/* 0x0200h ~ 0x027Fh TXDMA Configuration */ /* */ /* */ /* */ /* */ -/* 0x0280h ~ 0x02FFh RXDMA Configuration */ +/* 0x0280h ~ 0x02FFh RXDMA Configuration */ /* */ /* */ #define BIT_USB_RXDMA_AGG_EN BIT(31) @@ -184,7 +180,7 @@ /* */ /* */ -/* 0x0400h ~ 0x047Fh Protocol Configuration */ +/* 0x0400h ~ 0x047Fh Protocol Configuration */ /* */ /* */ @@ -195,19 +191,18 @@ /* */ /* */ -/* 0x0500h ~ 0x05FFh EDCA Configuration */ +/* 0x0500h ~ 0x05FFh EDCA Configuration */ /* */ /* */ /* */ /* */ -/* 0x0600h ~ 0x07FFh WMAC Configuration */ +/* 0x0600h ~ 0x07FFh WMAC Configuration */ /* */ /* */ #define EEPROM_RF_GAIN_OFFSET 0xC1 #define EEPROM_RF_GAIN_VAL 0x1F6 - /* */ /* 8195 IMR/ISR bits (offset 0xB0, 8bits) */ /* */ @@ -246,13 +241,13 @@ #define IMR_BCNDMAINT3_8723B BIT23 /* Beacon DMA Interrupt 3 */ #define IMR_BCNDMAINT2_8723B BIT22 /* Beacon DMA Interrupt 2 */ #define IMR_BCNDMAINT1_8723B BIT21 /* Beacon DMA Interrupt 1 */ -#define IMR_BCNDOK7_8723B BIT20 /* Beacon Queue DMA OK Interrup 7 */ -#define IMR_BCNDOK6_8723B BIT19 /* Beacon Queue DMA OK Interrup 6 */ -#define IMR_BCNDOK5_8723B BIT18 /* Beacon Queue DMA OK Interrup 5 */ -#define IMR_BCNDOK4_8723B BIT17 /* Beacon Queue DMA OK Interrup 4 */ -#define IMR_BCNDOK3_8723B BIT16 /* Beacon Queue DMA OK Interrup 3 */ -#define IMR_BCNDOK2_8723B BIT15 /* Beacon Queue DMA OK Interrup 2 */ -#define IMR_BCNDOK1_8723B BIT14 /* Beacon Queue DMA OK Interrup 1 */ +#define IMR_BCNDOK7_8723B BIT20 /* Beacon Queue DMA OK Interrupt 7 */ +#define IMR_BCNDOK6_8723B BIT19 /* Beacon Queue DMA OK Interrupt 6 */ +#define IMR_BCNDOK5_8723B BIT18 /* Beacon Queue DMA OK Interrupt 5 */ +#define IMR_BCNDOK4_8723B BIT17 /* Beacon Queue DMA OK Interrupt 4 */ +#define IMR_BCNDOK3_8723B BIT16 /* Beacon Queue DMA OK Interrupt 3 */ +#define IMR_BCNDOK2_8723B BIT15 /* Beacon Queue DMA OK Interrupt 2 */ +#define IMR_BCNDOK1_8723B BIT14 /* Beacon Queue DMA OK Interrupt 1 */ #define IMR_ATIMEND_E_8723B BIT13 /* ATIM Window End Extension for Win7 */ #define IMR_TXERR_8723B BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ #define IMR_RXERR_8723B BIT10 /* Rx Error Flag INT Status, Write 1 clear */ diff --git a/drivers/staging/rtl8723bs/os_dep/ioctl_linux.c b/drivers/staging/rtl8723bs/os_dep/ioctl_linux.c index 916741371bee..79d8383d4b9b 100644 --- a/drivers/staging/rtl8723bs/os_dep/ioctl_linux.c +++ b/drivers/staging/rtl8723bs/os_dep/ioctl_linux.c @@ -766,7 +766,7 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, exit: - kfree((u8 *)pwep); + kfree(pwep); return ret; } @@ -2500,7 +2500,7 @@ static int rtw_wx_set_enc_ext(struct net_device *dev, ret = wpa_set_encryption(dev, param, param_len); exit: - kfree((u8 *)param); + kfree(param); return ret; } @@ -3767,7 +3767,7 @@ static int wpa_supplicant_ioctl(struct net_device *dev, struct iw_point *p) if (copy_from_user(param, p->pointer, p->length)) { - kfree((u8 *)param); + kfree(param); ret = -EFAULT; goto out; } @@ -3801,7 +3801,7 @@ static int wpa_supplicant_ioctl(struct net_device *dev, struct iw_point *p) if (ret == 0 && copy_to_user(p->pointer, param, p->length)) ret = -EFAULT; - kfree((u8 *)param); + kfree(param); out: @@ -4130,7 +4130,7 @@ static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, } exit: - kfree((u8 *)pwep); + kfree(pwep); return ret; @@ -4713,7 +4713,7 @@ static int rtw_hostapd_ioctl(struct net_device *dev, struct iw_point *p) if (copy_from_user(param, p->pointer, p->length)) { - kfree((u8 *)param); + kfree(param); ret = -EFAULT; goto out; } @@ -4817,7 +4817,7 @@ static int rtw_hostapd_ioctl(struct net_device *dev, struct iw_point *p) ret = -EFAULT; - kfree((u8 *)param); + kfree(param); out: diff --git a/drivers/staging/rtl8723bs/os_dep/sdio_ops_linux.c b/drivers/staging/rtl8723bs/os_dep/sdio_ops_linux.c index 33f0f83b002d..3aa3e6548fd5 100644 --- a/drivers/staging/rtl8723bs/os_dep/sdio_ops_linux.c +++ b/drivers/staging/rtl8723bs/os_dep/sdio_ops_linux.c @@ -272,7 +272,7 @@ u32 sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err) DBG_871X(KERN_ERR "%s: (%d) addr = 0x%05x, val = 0x%x\n", __func__, *err, addr, v); *err = 0; - for (i = 0; i<SD_IO_TRY_CNT; i++) + for (i = 0; i < SD_IO_TRY_CNT; i++) { if (claim_needed) sdio_claim_host(func); v = sdio_readl(func, addr, err); @@ -294,7 +294,7 @@ u32 sd_read32(struct intf_hdl *pintfhdl, u32 addr, s32 *err) } } - if (i ==SD_IO_TRY_CNT) + if (i == SD_IO_TRY_CNT) DBG_871X(KERN_ERR "%s: FAIL!(%d) addr = 0x%05x, val = 0x%x, try_cnt =%d\n", __func__, *err, addr, v, i); else DBG_871X(KERN_ERR "%s: (%d) addr = 0x%05x, val = 0x%x, try_cnt =%d\n", __func__, *err, addr, v, i); @@ -317,7 +317,7 @@ void sd_write8(struct intf_hdl *pintfhdl, u32 addr, u8 v, s32 *err) if (padapter->bSurpriseRemoved) { /* DBG_871X(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n", __func__); */ - return ; + return; } func = psdio->func; @@ -346,7 +346,7 @@ void sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err) if (padapter->bSurpriseRemoved) { /* DBG_871X(" %s (padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n", __func__); */ - return ; + return; } func = psdio->func; @@ -365,7 +365,7 @@ void sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err) DBG_871X(KERN_ERR "%s: (%d) addr = 0x%05x val = 0x%08x\n", __func__, *err, addr, v); *err = 0; - for (i = 0; i<SD_IO_TRY_CNT; i++) + for (i = 0; i < SD_IO_TRY_CNT; i++) { if (claim_needed) sdio_claim_host(func); sdio_writel(func, v, addr, err); @@ -386,7 +386,7 @@ void sd_write32(struct intf_hdl *pintfhdl, u32 addr, u32 v, s32 *err) } } - if (i ==SD_IO_TRY_CNT) + if (i == SD_IO_TRY_CNT) DBG_871X(KERN_ERR "%s: FAIL!(%d) addr = 0x%05x val = 0x%08x, try_cnt =%d\n", __func__, *err, addr, v, i); else DBG_871X(KERN_ERR "%s: (%d) addr = 0x%05x val = 0x%08x, try_cnt =%d\n", __func__, *err, addr, v, i); @@ -428,7 +428,7 @@ s32 _sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata) func = psdio->func; - if (unlikely((cnt == 1) || (cnt ==2))) + if (unlikely((cnt == 1) || (cnt == 2))) { int i; u8 *pbuf = (u8 *)pdata; @@ -465,7 +465,7 @@ s32 _sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata) *0 Success *others Fail */ -s32 sd_read(struct intf_hdl * pintfhdl, u32 addr, u32 cnt, void *pdata) +s32 sd_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata) { struct adapter *padapter; struct dvobj_priv *psdiodev; @@ -517,7 +517,7 @@ s32 _sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata) struct sdio_func *func; u32 size; - s32 err =-EPERM; + s32 err = -EPERM; padapter = pintfhdl->padapter; psdiodev = pintfhdl->pintf_dev; @@ -529,9 +529,9 @@ s32 _sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata) } func = psdio->func; -/* size = sdio_align_size(func, cnt); */ +/* size = sdio_align_size(func, cnt); */ - if (unlikely((cnt == 1) || (cnt ==2))) + if (unlikely((cnt == 1) || (cnt == 2))) { int i; u8 *pbuf = (u8 *)pdata; @@ -576,7 +576,7 @@ s32 sd_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, void *pdata) PSDIO_DATA psdio; struct sdio_func *func; bool claim_needed; - s32 err =-EPERM; + s32 err = -EPERM; padapter = pintfhdl->padapter; psdiodev = pintfhdl->pintf_dev; diff --git a/drivers/staging/rtl8723bs/os_dep/wifi_regd.c b/drivers/staging/rtl8723bs/os_dep/wifi_regd.c index 9c61125f5910..305e88a6b2ca 100644 --- a/drivers/staging/rtl8723bs/os_dep/wifi_regd.c +++ b/drivers/staging/rtl8723bs/os_dep/wifi_regd.c @@ -14,42 +14,43 @@ */ /* - *Only these channels all allow active - *scan on all world regulatory domains + * Only these channels all allow active + * scan on all world regulatory domains */ /* 2G chan 01 - chan 11 */ #define RTW_2GHZ_CH01_11 \ - REG_RULE(2412-10, 2462+10, 40, 0, 20, 0) + REG_RULE(2412 - 10, 2462 + 10, 40, 0, 20, 0) /* - *We enable active scan on these a case - *by case basis by regulatory domain + * We enable active scan on these a case + * by case basis by regulatory domain */ /* 2G chan 12 - chan 13, PASSIV SCAN */ #define RTW_2GHZ_CH12_13 \ - REG_RULE(2467-10, 2472+10, 40, 0, 20, \ + REG_RULE(2467 - 10, 2472 + 10, 40, 0, 20, \ NL80211_RRF_PASSIVE_SCAN) /* 2G chan 14, PASSIVS SCAN, NO OFDM (B only) */ #define RTW_2GHZ_CH14 \ - REG_RULE(2484-10, 2484+10, 40, 0, 20, \ + REG_RULE(2484 - 10, 2484 + 10, 40, 0, 20, \ NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_OFDM) static const struct ieee80211_regdomain rtw_regdom_rd = { .n_reg_rules = 3, .alpha2 = "99", .reg_rules = { - RTW_2GHZ_CH01_11, - RTW_2GHZ_CH12_13, - } + RTW_2GHZ_CH01_11, + RTW_2GHZ_CH12_13, + } }; static int rtw_ieee80211_channel_to_frequency(int chan, int band) { /* see 802.11 17.3.8.3.2 and Annex J - * there are overlapping channel numbers in 5GHz and 2GHz bands */ + * there are overlapping channel numbers in 5GHz and 2GHz bands + */ /* NL80211_BAND_2GHZ */ if (chan == 14) @@ -73,7 +74,7 @@ static void _rtw_reg_apply_flags(struct wiphy *wiphy) u16 channel; u32 freq; - /* all channels disable */ + /* all channels disable */ for (i = 0; i < NUM_NL80211_BANDS; i++) { sband = wiphy->bands[i]; @@ -87,7 +88,7 @@ static void _rtw_reg_apply_flags(struct wiphy *wiphy) } } - /* channels apply by channel plans. */ + /* channels apply by channel plans. */ for (i = 0; i < max_chan_nums; i++) { channel = channel_set[i].ChannelNum; freq = @@ -96,12 +97,10 @@ static void _rtw_reg_apply_flags(struct wiphy *wiphy) ch = ieee80211_get_channel(wiphy, freq); if (ch) { - if (channel_set[i].ScanType == SCAN_PASSIVE) { + if (channel_set[i].ScanType == SCAN_PASSIVE) ch->flags = IEEE80211_CHAN_NO_IR; - } - else { + else ch->flags = 0; - } } } } @@ -123,10 +122,11 @@ static const struct ieee80211_regdomain *_rtw_regdomain_select(struct } static void _rtw_regd_init_wiphy(struct rtw_regulatory *reg, - struct wiphy *wiphy, - void (*reg_notifier) (struct wiphy * wiphy, - struct regulatory_request * - request)) + struct wiphy *wiphy, + void (*reg_notifier)(struct wiphy *wiphy, + struct + regulatory_request * + request)) { const struct ieee80211_regdomain *regd; @@ -144,11 +144,11 @@ static void _rtw_regd_init_wiphy(struct rtw_regulatory *reg, } int rtw_regd_init(struct adapter *padapter, - void (*reg_notifier) (struct wiphy * wiphy, + void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)) { - /* struct registry_priv *registrypriv = &padapter->registrypriv; */ struct wiphy *wiphy = padapter->rtw_wdev->wiphy; + _rtw_regd_init_wiphy(NULL, wiphy, reg_notifier); return 0; diff --git a/drivers/staging/rts5208/rtsx_scsi.c b/drivers/staging/rts5208/rtsx_scsi.c index a95c5de1aa00..36b5a11f21d2 100644 --- a/drivers/staging/rts5208/rtsx_scsi.c +++ b/drivers/staging/rts5208/rtsx_scsi.c @@ -536,7 +536,7 @@ static int inquiry(struct scsi_cmnd *srb, struct rtsx_chip *chip) if (sendbytes > 8) { memcpy(buf, inquiry_buf, 8); - memcpy(buf + 8, inquiry_string, sendbytes - 8); + strncpy(buf + 8, inquiry_string, sendbytes - 8); if (pro_formatter_flag) { /* Additional Length */ buf[4] = 0x33; diff --git a/drivers/staging/rts5208/sd.c b/drivers/staging/rts5208/sd.c index bdd35b611f27..c2eb072cbe1d 100644 --- a/drivers/staging/rts5208/sd.c +++ b/drivers/staging/rts5208/sd.c @@ -1057,7 +1057,7 @@ fail: rtsx_write_register(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0); rtsx_write_register(chip, SD_VP_CTL, PHASE_CHANGE, 0); - wait_timeout(10); + mdelay(10); sd_reset_dcm(chip, tune_dir); return STATUS_FAIL; } @@ -5231,7 +5231,7 @@ int sd_power_off_card3v3(struct rtsx_chip *chip) return STATUS_FAIL; } - wait_timeout(50); + mdelay(50); } if (chip->asic_code) { diff --git a/drivers/staging/rts5208/xd.c b/drivers/staging/rts5208/xd.c index 85aba05acbc1..74d36f9a4c1d 100644 --- a/drivers/staging/rts5208/xd.c +++ b/drivers/staging/rts5208/xd.c @@ -1268,7 +1268,7 @@ static int xd_copy_page(struct rtsx_chip *chip, u32 old_blk, u32 new_blk, reg = 0; rtsx_read_register(chip, XD_CTL, ®); if (reg & (XD_ECC1_ERROR | XD_ECC2_ERROR)) { - wait_timeout(100); + mdelay(100); if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { diff --git a/drivers/staging/sm750fb/ddk750_chip.c b/drivers/staging/sm750fb/ddk750_chip.c index 5e4bfb601cea..944dd25924be 100644 --- a/drivers/staging/sm750fb/ddk750_chip.c +++ b/drivers/staging/sm750fb/ddk750_chip.c @@ -175,7 +175,7 @@ static void set_master_clock(unsigned int frequency) } sm750_set_current_gate(reg); - } + } } unsigned int ddk750_get_vm_size(void) @@ -224,7 +224,7 @@ int ddk750_init_hw(struct initchip_param *pInitParam) sm750_set_current_gate(reg); if (sm750_get_chip_type() != SM750LE) { - /* set panel pll and graphic mode via mmio_88 */ + /* set panel pll and graphic mode via mmio_88 */ reg = peek32(VGA_CONFIGURATION); reg |= (VGA_CONFIGURATION_PLL | VGA_CONFIGURATION_MODE); poke32(VGA_CONFIGURATION, reg); @@ -309,7 +309,8 @@ int ddk750_init_hw(struct initchip_param *pInitParam) * M = {1,...,255} * N = {2,...,15} */ -unsigned int sm750_calc_pll_value(unsigned int request_orig, struct pll_value *pll) +unsigned int sm750_calc_pll_value(unsigned int request_orig, + struct pll_value *pll) { /* * as sm750 register definition, diff --git a/drivers/staging/sm750fb/ddk750_dvi.c b/drivers/staging/sm750fb/ddk750_dvi.c index 171ae063f06f..87a199d6cdaf 100644 --- a/drivers/staging/sm750fb/ddk750_dvi.c +++ b/drivers/staging/sm750fb/ddk750_dvi.c @@ -29,26 +29,31 @@ static dvi_ctrl_device_t g_dcftSupportedDviController[] = { #endif }; -int dviInit( - unsigned char edgeSelect, - unsigned char busSelect, - unsigned char dualEdgeClkSelect, - unsigned char hsyncEnable, - unsigned char vsyncEnable, - unsigned char deskewEnable, - unsigned char deskewSetting, - unsigned char continuousSyncEnable, - unsigned char pllFilterEnable, - unsigned char pllFilterValue - ) +int dviInit(unsigned char edgeSelect, + unsigned char busSelect, + unsigned char dualEdgeClkSelect, + unsigned char hsyncEnable, + unsigned char vsyncEnable, + unsigned char deskewEnable, + unsigned char deskewSetting, + unsigned char continuousSyncEnable, + unsigned char pllFilterEnable, + unsigned char pllFilterValue) { dvi_ctrl_device_t *pCurrentDviCtrl; pCurrentDviCtrl = g_dcftSupportedDviController; if (pCurrentDviCtrl->pfnInit) { - return pCurrentDviCtrl->pfnInit(edgeSelect, busSelect, dualEdgeClkSelect, hsyncEnable, - vsyncEnable, deskewEnable, deskewSetting, continuousSyncEnable, - pllFilterEnable, pllFilterValue); + return pCurrentDviCtrl->pfnInit(edgeSelect, + busSelect, + dualEdgeClkSelect, + hsyncEnable, + vsyncEnable, + deskewEnable, + deskewSetting, + continuousSyncEnable, + pllFilterEnable, + pllFilterValue); } return -1; /* error */ } diff --git a/drivers/staging/sm750fb/ddk750_dvi.h b/drivers/staging/sm750fb/ddk750_dvi.h index 677939cb5130..4a8394561f76 100644 --- a/drivers/staging/sm750fb/ddk750_dvi.h +++ b/drivers/staging/sm750fb/ddk750_dvi.h @@ -3,17 +3,16 @@ /* dvi chip stuffs structros */ -typedef long (*PFN_DVICTRL_INIT)( - unsigned char edgeSelect, - unsigned char busSelect, - unsigned char dualEdgeClkSelect, - unsigned char hsyncEnable, - unsigned char vsyncEnable, - unsigned char deskewEnable, - unsigned char deskewSetting, - unsigned char continuousSyncEnable, - unsigned char pllFilterEnable, - unsigned char pllFilterValue); +typedef long (*PFN_DVICTRL_INIT)(unsigned char edgeSelect, + unsigned char busSelect, + unsigned char dualEdgeClkSelect, + unsigned char hsyncEnable, + unsigned char vsyncEnable, + unsigned char deskewEnable, + unsigned char deskewSetting, + unsigned char continuousSyncEnable, + unsigned char pllFilterEnable, + unsigned char pllFilterValue); typedef void (*PFN_DVICTRL_RESETCHIP)(void); typedef char* (*PFN_DVICTRL_GETCHIPSTRING)(void); @@ -42,18 +41,16 @@ typedef struct _dvi_ctrl_device_t { #define DVI_CTRL_SII164 /* dvi functions prototype */ -int dviInit( - unsigned char edgeSelect, - unsigned char busSelect, - unsigned char dualEdgeClkSelect, - unsigned char hsyncEnable, - unsigned char vsyncEnable, - unsigned char deskewEnable, - unsigned char deskewSetting, - unsigned char continuousSyncEnable, - unsigned char pllFilterEnable, - unsigned char pllFilterValue -); +int dviInit(unsigned char edgeSelect, + unsigned char busSelect, + unsigned char dualEdgeClkSelect, + unsigned char hsyncEnable, + unsigned char vsyncEnable, + unsigned char deskewEnable, + unsigned char deskewSetting, + unsigned char continuousSyncEnable, + unsigned char pllFilterEnable, + unsigned char pllFilterValue); #endif diff --git a/drivers/staging/sm750fb/ddk750_hwi2c.c b/drivers/staging/sm750fb/ddk750_hwi2c.c index fe814e4881f9..ec556a978a98 100644 --- a/drivers/staging/sm750fb/ddk750_hwi2c.c +++ b/drivers/staging/sm750fb/ddk750_hwi2c.c @@ -8,9 +8,7 @@ #define MAX_HWI2C_FIFO 16 #define HWI2C_WAIT_TIMEOUT 0xF0000 -int sm750_hw_i2c_init( -unsigned char bus_speed_mode -) +int sm750_hw_i2c_init(unsigned char bus_speed_mode) { unsigned int value; @@ -81,11 +79,9 @@ static long hw_i2c_wait_tx_done(void) * Return Value: * Total number of bytes those are actually written. */ -static unsigned int hw_i2c_write_data( - unsigned char addr, - unsigned int length, - unsigned char *buf -) +static unsigned int hw_i2c_write_data(unsigned char addr, + unsigned int length, + unsigned char *buf) { unsigned char count, i; unsigned int total_bytes = 0; @@ -148,11 +144,9 @@ static unsigned int hw_i2c_write_data( * Return Value: * Total number of actual bytes read from the slave device */ -static unsigned int hw_i2c_read_data( - unsigned char addr, - unsigned int length, - unsigned char *buf -) +static unsigned int hw_i2c_read_data(unsigned char addr, + unsigned int length, + unsigned char *buf) { unsigned char count, i; unsigned int total_bytes = 0; @@ -212,10 +206,7 @@ static unsigned int hw_i2c_read_data( * Return Value: * Register value */ -unsigned char sm750_hw_i2c_read_reg( - unsigned char addr, - unsigned char reg -) +unsigned char sm750_hw_i2c_read_reg(unsigned char addr, unsigned char reg) { unsigned char value = 0xFF; @@ -238,11 +229,9 @@ unsigned char sm750_hw_i2c_read_reg( * 0 - Success * -1 - Fail */ -int sm750_hw_i2c_write_reg( - unsigned char addr, - unsigned char reg, - unsigned char data -) +int sm750_hw_i2c_write_reg(unsigned char addr, + unsigned char reg, + unsigned char data) { unsigned char value[2]; diff --git a/drivers/staging/sm750fb/ddk750_sii164.c b/drivers/staging/sm750fb/ddk750_sii164.c index 259006ace219..0431833de781 100644 --- a/drivers/staging/sm750fb/ddk750_sii164.c +++ b/drivers/staging/sm750fb/ddk750_sii164.c @@ -112,18 +112,16 @@ unsigned short sii164GetDeviceID(void) * 0 - Success * -1 - Fail. */ -long sii164InitChip( - unsigned char edgeSelect, - unsigned char busSelect, - unsigned char dualEdgeClkSelect, - unsigned char hsyncEnable, - unsigned char vsyncEnable, - unsigned char deskewEnable, - unsigned char deskewSetting, - unsigned char continuousSyncEnable, - unsigned char pllFilterEnable, - unsigned char pllFilterValue -) +long sii164InitChip(unsigned char edgeSelect, + unsigned char busSelect, + unsigned char dualEdgeClkSelect, + unsigned char hsyncEnable, + unsigned char vsyncEnable, + unsigned char deskewEnable, + unsigned char deskewSetting, + unsigned char continuousSyncEnable, + unsigned char pllFilterEnable, + unsigned char pllFilterValue) { unsigned char config; @@ -259,7 +257,6 @@ void sii164ResetChip(void) sii164SetPower(1); } - /* * sii164GetChipString * This function returns a char string name of the current DVI Controller chip. @@ -270,7 +267,6 @@ char *sii164GetChipString(void) return gDviCtrlChipName; } - /* * sii164SetPower * This function sets the power configuration of the DVI Controller Chip. @@ -278,9 +274,7 @@ char *sii164GetChipString(void) * Input: * powerUp - Flag to set the power down or up */ -void sii164SetPower( - unsigned char powerUp -) +void sii164SetPower(unsigned char powerUp) { unsigned char config; @@ -298,18 +292,16 @@ void sii164SetPower( } } - /* * sii164SelectHotPlugDetectionMode * This function selects the mode of the hot plug detection. */ -static void sii164SelectHotPlugDetectionMode( - sii164_hot_plug_mode_t hotPlugMode -) +static void sii164SelectHotPlugDetectionMode(sii164_hot_plug_mode_t hotPlugMode) { unsigned char detectReg; - detectReg = i2cReadReg(SII164_I2C_ADDRESS, SII164_DETECT) & ~SII164_DETECT_MONITOR_SENSE_OUTPUT_FLAG; + detectReg = i2cReadReg(SII164_I2C_ADDRESS, SII164_DETECT) & + ~SII164_DETECT_MONITOR_SENSE_OUTPUT_FLAG; switch (hotPlugMode) { case SII164_HOTPLUG_DISABLE: detectReg |= SII164_DETECT_MONITOR_SENSE_OUTPUT_HIGH; @@ -336,9 +328,7 @@ static void sii164SelectHotPlugDetectionMode( * * enableHotPlug - Enable (=1) / disable (=0) Hot Plug detection */ -void sii164EnableHotPlugDetection( - unsigned char enableHotPlug -) +void sii164EnableHotPlugDetection(unsigned char enableHotPlug) { unsigned char detectReg; @@ -365,7 +355,8 @@ unsigned char sii164IsConnected(void) { unsigned char hotPlugValue; - hotPlugValue = i2cReadReg(SII164_I2C_ADDRESS, SII164_DETECT) & SII164_DETECT_HOT_PLUG_STATUS_MASK; + hotPlugValue = i2cReadReg(SII164_I2C_ADDRESS, SII164_DETECT) & + SII164_DETECT_HOT_PLUG_STATUS_MASK; if (hotPlugValue == SII164_DETECT_HOT_PLUG_STATUS_ON) return 1; else @@ -384,7 +375,8 @@ unsigned char sii164CheckInterrupt(void) { unsigned char detectReg; - detectReg = i2cReadReg(SII164_I2C_ADDRESS, SII164_DETECT) & SII164_DETECT_MONITOR_STATE_MASK; + detectReg = i2cReadReg(SII164_I2C_ADDRESS, SII164_DETECT) & + SII164_DETECT_MONITOR_STATE_MASK; if (detectReg == SII164_DETECT_MONITOR_STATE_CHANGE) return 1; else @@ -401,7 +393,8 @@ void sii164ClearInterrupt(void) /* Clear the MDI interrupt */ detectReg = i2cReadReg(SII164_I2C_ADDRESS, SII164_DETECT); - i2cWriteReg(SII164_I2C_ADDRESS, SII164_DETECT, detectReg | SII164_DETECT_MONITOR_STATE_CLEAR); + i2cWriteReg(SII164_I2C_ADDRESS, SII164_DETECT, + detectReg | SII164_DETECT_MONITOR_STATE_CLEAR); } #endif diff --git a/drivers/staging/sm750fb/ddk750_sii164.h b/drivers/staging/sm750fb/ddk750_sii164.h index 664ad089f753..6968cf532f16 100644 --- a/drivers/staging/sm750fb/ddk750_sii164.h +++ b/drivers/staging/sm750fb/ddk750_sii164.h @@ -13,18 +13,16 @@ typedef enum _sii164_hot_plug_mode_t { /* Silicon Image SiI164 chip prototype */ -long sii164InitChip( - unsigned char edgeSelect, - unsigned char busSelect, - unsigned char dualEdgeClkSelect, - unsigned char hsyncEnable, - unsigned char vsyncEnable, - unsigned char deskewEnable, - unsigned char deskewSetting, - unsigned char continuousSyncEnable, - unsigned char pllFilterEnable, - unsigned char pllFilterValue -); +long sii164InitChip(unsigned char edgeSelect, + unsigned char busSelect, + unsigned char dualEdgeClkSelect, + unsigned char hsyncEnable, + unsigned char vsyncEnable, + unsigned char deskewEnable, + unsigned char deskewSetting, + unsigned char continuousSyncEnable, + unsigned char pllFilterEnable, + unsigned char pllFilterValue); unsigned short sii164GetVendorID(void); unsigned short sii164GetDeviceID(void); diff --git a/drivers/staging/sm750fb/ddk750_swi2c.c b/drivers/staging/sm750fb/ddk750_swi2c.c index a4ac07cd50cb..19c5ffc72b16 100644 --- a/drivers/staging/sm750fb/ddk750_swi2c.c +++ b/drivers/staging/sm750fb/ddk750_swi2c.c @@ -349,8 +349,7 @@ static unsigned char sw_i2c_read_byte(unsigned char ack) * -1 - Fail to initialize the i2c * 0 - Success */ -static long sm750le_i2c_init(unsigned char clk_gpio, - unsigned char data_gpio) +static long sm750le_i2c_init(unsigned char clk_gpio, unsigned char data_gpio) { int i; @@ -388,10 +387,7 @@ static long sm750le_i2c_init(unsigned char clk_gpio, * -1 - Fail to initialize the i2c * 0 - Success */ -long sm750_sw_i2c_init( - unsigned char clk_gpio, - unsigned char data_gpio -) +long sm750_sw_i2c_init(unsigned char clk_gpio, unsigned char data_gpio) { int i; @@ -448,10 +444,7 @@ long sm750_sw_i2c_init( * Return Value: * Register value */ -unsigned char sm750_sw_i2c_read_reg( - unsigned char addr, - unsigned char reg -) +unsigned char sm750_sw_i2c_read_reg(unsigned char addr, unsigned char reg) { unsigned char data; @@ -488,11 +481,9 @@ unsigned char sm750_sw_i2c_read_reg( * 0 - Success * -1 - Fail */ -long sm750_sw_i2c_write_reg( - unsigned char addr, - unsigned char reg, - unsigned char data -) +long sm750_sw_i2c_write_reg(unsigned char addr, + unsigned char reg, + unsigned char data) { long ret = 0; diff --git a/drivers/staging/sm750fb/ddk750_swi2c.h b/drivers/staging/sm750fb/ddk750_swi2c.h index 5a9466efc7bd..3b8a96d6d25a 100644 --- a/drivers/staging/sm750fb/ddk750_swi2c.h +++ b/drivers/staging/sm750fb/ddk750_swi2c.h @@ -28,10 +28,7 @@ * -1 - Fail to initialize the i2c * 0 - Success */ -long sm750_sw_i2c_init( - unsigned char clk_gpio, - unsigned char data_gpio -); +long sm750_sw_i2c_init(unsigned char clk_gpio, unsigned char data_gpio); /* * This function reads the slave device's register @@ -44,10 +41,7 @@ long sm750_sw_i2c_init( * Return Value: * Register value */ -unsigned char sm750_sw_i2c_read_reg( - unsigned char addr, - unsigned char reg -); +unsigned char sm750_sw_i2c_read_reg(unsigned char addr, unsigned char reg); /* * This function writes a value to the slave device's register @@ -62,10 +56,8 @@ unsigned char sm750_sw_i2c_read_reg( * 0 - Success * -1 - Fail */ -long sm750_sw_i2c_write_reg( - unsigned char addr, - unsigned char reg, - unsigned char data -); +long sm750_sw_i2c_write_reg(unsigned char addr, + unsigned char reg, + unsigned char data); #endif /* _SWI2C_H_ */ diff --git a/drivers/staging/sm750fb/sm750.c b/drivers/staging/sm750fb/sm750.c index 386d4adcd91d..3aa4128703d5 100644 --- a/drivers/staging/sm750fb/sm750.c +++ b/drivers/staging/sm750fb/sm750.c @@ -33,7 +33,7 @@ static int g_hwcursor = 1; static int g_noaccel; static int g_nomtrr; static const char *g_fbmode[] = {NULL, NULL}; -static const char *g_def_fbmode = "800x600-16@60"; +static const char *g_def_fbmode = "1024x768-32@60"; static char *g_settings; static int g_dualview; static char *g_option; @@ -112,42 +112,42 @@ static int lynxfb_ops_cursor(struct fb_info *info, struct fb_cursor *fbcursor) cursor = &crtc->cursor; if (fbcursor->image.width > cursor->maxW || - fbcursor->image.height > cursor->maxH || - fbcursor->image.depth > 1) { + fbcursor->image.height > cursor->maxH || + fbcursor->image.depth > 1) { return -ENXIO; } sm750_hw_cursor_disable(cursor); if (fbcursor->set & FB_CUR_SETSIZE) sm750_hw_cursor_setSize(cursor, - fbcursor->image.width, - fbcursor->image.height); + fbcursor->image.width, + fbcursor->image.height); if (fbcursor->set & FB_CUR_SETPOS) sm750_hw_cursor_setPos(cursor, - fbcursor->image.dx - info->var.xoffset, - fbcursor->image.dy - info->var.yoffset); + fbcursor->image.dx - info->var.xoffset, + fbcursor->image.dy - info->var.yoffset); if (fbcursor->set & FB_CUR_SETCMAP) { /* get the 16bit color of kernel means */ u16 fg, bg; fg = ((info->cmap.red[fbcursor->image.fg_color] & 0xf800)) | - ((info->cmap.green[fbcursor->image.fg_color] & 0xfc00) >> 5) | - ((info->cmap.blue[fbcursor->image.fg_color] & 0xf800) >> 11); + ((info->cmap.green[fbcursor->image.fg_color] & 0xfc00) >> 5) | + ((info->cmap.blue[fbcursor->image.fg_color] & 0xf800) >> 11); bg = ((info->cmap.red[fbcursor->image.bg_color] & 0xf800)) | - ((info->cmap.green[fbcursor->image.bg_color] & 0xfc00) >> 5) | - ((info->cmap.blue[fbcursor->image.bg_color] & 0xf800) >> 11); + ((info->cmap.green[fbcursor->image.bg_color] & 0xfc00) >> 5) | + ((info->cmap.blue[fbcursor->image.bg_color] & 0xf800) >> 11); sm750_hw_cursor_setColor(cursor, fg, bg); } if (fbcursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) { sm750_hw_cursor_setData(cursor, - fbcursor->rop, - fbcursor->image.data, - fbcursor->mask); + fbcursor->rop, + fbcursor->image.data, + fbcursor->mask); } if (fbcursor->enable) @@ -183,19 +183,19 @@ static void lynxfb_ops_fillrect(struct fb_info *info, rop = (region->rop != ROP_COPY) ? HW_ROP2_XOR : HW_ROP2_COPY; /* - * If not use spin_lock,system will die if user load driver + * If not use spin_lock, system will die if user load driver * and immediately unload driver frequently (dual) + * since they fb_count could change during the lifetime of + * this lock, we are holding it for all cases. */ - if (sm750_dev->fb_count > 1) - spin_lock(&sm750_dev->slock); + spin_lock(&sm750_dev->slock); sm750_dev->accel.de_fillrect(&sm750_dev->accel, base, pitch, Bpp, region->dx, region->dy, region->width, region->height, color, rop); - if (sm750_dev->fb_count > 1) - spin_unlock(&sm750_dev->slock); + spin_unlock(&sm750_dev->slock); } static void lynxfb_ops_copyarea(struct fb_info *info, @@ -219,17 +219,17 @@ static void lynxfb_ops_copyarea(struct fb_info *info, /* * If not use spin_lock, system will die if user load driver * and immediately unload driver frequently (dual) + * since they fb_count could change during the lifetime of + * this lock, we are holding it for all cases. */ - if (sm750_dev->fb_count > 1) - spin_lock(&sm750_dev->slock); + spin_lock(&sm750_dev->slock); sm750_dev->accel.de_copyarea(&sm750_dev->accel, base, pitch, region->sx, region->sy, base, pitch, Bpp, region->dx, region->dy, region->width, region->height, HW_ROP2_COPY); - if (sm750_dev->fb_count > 1) - spin_unlock(&sm750_dev->slock); + spin_unlock(&sm750_dev->slock); } static void lynxfb_ops_imageblit(struct fb_info *info, @@ -268,9 +268,10 @@ static void lynxfb_ops_imageblit(struct fb_info *info, /* * If not use spin_lock, system will die if user load driver * and immediately unload driver frequently (dual) + * since they fb_count could change during the lifetime of + * this lock, we are holding it for all cases. */ - if (sm750_dev->fb_count > 1) - spin_lock(&sm750_dev->slock); + spin_lock(&sm750_dev->slock); sm750_dev->accel.de_imageblit(&sm750_dev->accel, image->data, image->width >> 3, 0, @@ -278,8 +279,7 @@ static void lynxfb_ops_imageblit(struct fb_info *info, image->dx, image->dy, image->width, image->height, fgcol, bgcol, HW_ROP2_COPY); - if (sm750_dev->fb_count > 1) - spin_unlock(&sm750_dev->slock); + spin_unlock(&sm750_dev->slock); } static int lynxfb_ops_pan_display(struct fb_var_screeninfo *var, diff --git a/drivers/staging/sm750fb/sm750.h b/drivers/staging/sm750fb/sm750.h index 5b186dafedec..4386122799b2 100644 --- a/drivers/staging/sm750fb/sm750.h +++ b/drivers/staging/sm750fb/sm750.h @@ -189,14 +189,22 @@ void hw_sm750_initAccel(struct sm750_dev *sm750_dev); int hw_sm750_deWait(void); int hw_sm750le_deWait(void); -int hw_sm750_output_setMode(struct lynxfb_output*, struct fb_var_screeninfo*, - struct fb_fix_screeninfo*); -int hw_sm750_crtc_checkMode(struct lynxfb_crtc*, struct fb_var_screeninfo*); -int hw_sm750_crtc_setMode(struct lynxfb_crtc*, struct fb_var_screeninfo*, - struct fb_fix_screeninfo*); -int hw_sm750_setColReg(struct lynxfb_crtc*, ushort, ushort, ushort, ushort); -int hw_sm750_setBLANK(struct lynxfb_output*, int); -int hw_sm750le_setBLANK(struct lynxfb_output*, int); +int hw_sm750_output_setMode(struct lynxfb_output *output, + struct fb_var_screeninfo *var, + struct fb_fix_screeninfo *fix); + +int hw_sm750_crtc_checkMode(struct lynxfb_crtc *crtc, + struct fb_var_screeninfo *var); + +int hw_sm750_crtc_setMode(struct lynxfb_crtc *crtc, + struct fb_var_screeninfo *var, + struct fb_fix_screeninfo *fix); + +int hw_sm750_setColReg(struct lynxfb_crtc *crtc, ushort index, + ushort red, ushort green, ushort blue); + +int hw_sm750_setBLANK(struct lynxfb_output *output, int blank); +int hw_sm750le_setBLANK(struct lynxfb_output *output, int blank); int hw_sm750_pan_display(struct lynxfb_crtc *crtc, const struct fb_var_screeninfo *var, const struct fb_info *info); diff --git a/drivers/staging/sm750fb/sm750_accel.c b/drivers/staging/sm750fb/sm750_accel.c index 6be86e4963be..4b720cfa05de 100644 --- a/drivers/staging/sm750fb/sm750_accel.c +++ b/drivers/staging/sm750fb/sm750_accel.c @@ -42,10 +42,11 @@ void sm750_hw_de_init(struct lynx_accel *accel) /* dpr1c */ reg = 0x3; - clr = DE_STRETCH_FORMAT_PATTERN_XY | DE_STRETCH_FORMAT_PATTERN_Y_MASK | - DE_STRETCH_FORMAT_PATTERN_X_MASK | - DE_STRETCH_FORMAT_ADDRESSING_MASK | - DE_STRETCH_FORMAT_SOURCE_HEIGHT_MASK; + clr = DE_STRETCH_FORMAT_PATTERN_XY | + DE_STRETCH_FORMAT_PATTERN_Y_MASK | + DE_STRETCH_FORMAT_PATTERN_X_MASK | + DE_STRETCH_FORMAT_ADDRESSING_MASK | + DE_STRETCH_FORMAT_SOURCE_HEIGHT_MASK; /* DE_STRETCH bpp format need be initialized in setMode routine */ write_dpr(accel, DE_STRETCH_FORMAT, @@ -84,9 +85,9 @@ void sm750_hw_set2dformat(struct lynx_accel *accel, int fmt) } int sm750_hw_fillrect(struct lynx_accel *accel, - u32 base, u32 pitch, u32 Bpp, - u32 x, u32 y, u32 width, u32 height, - u32 color, u32 rop) + u32 base, u32 pitch, u32 Bpp, + u32 x, u32 y, u32 width, u32 height, + u32 color, u32 rop) { u32 deCtrl; diff --git a/drivers/staging/sm750fb/sm750_cursor.c b/drivers/staging/sm750fb/sm750_cursor.c index b64dc8a4a8fb..aa47a16ac75c 100644 --- a/drivers/staging/sm750fb/sm750_cursor.c +++ b/drivers/staging/sm750fb/sm750_cursor.c @@ -60,15 +60,13 @@ void sm750_hw_cursor_disable(struct lynx_cursor *cursor) poke32(HWC_ADDRESS, 0); } -void sm750_hw_cursor_setSize(struct lynx_cursor *cursor, - int w, int h) +void sm750_hw_cursor_setSize(struct lynx_cursor *cursor, int w, int h) { cursor->w = w; cursor->h = h; } -void sm750_hw_cursor_setPos(struct lynx_cursor *cursor, - int x, int y) +void sm750_hw_cursor_setPos(struct lynx_cursor *cursor, int x, int y) { u32 reg; @@ -77,8 +75,7 @@ void sm750_hw_cursor_setPos(struct lynx_cursor *cursor, poke32(HWC_LOCATION, reg); } -void sm750_hw_cursor_setColor(struct lynx_cursor *cursor, - u32 fg, u32 bg) +void sm750_hw_cursor_setColor(struct lynx_cursor *cursor, u32 fg, u32 bg) { u32 reg = (fg << HWC_COLOR_12_2_RGB565_SHIFT) & HWC_COLOR_12_2_RGB565_MASK; @@ -87,8 +84,8 @@ void sm750_hw_cursor_setColor(struct lynx_cursor *cursor, poke32(HWC_COLOR_3, 0xffe0); } -void sm750_hw_cursor_setData(struct lynx_cursor *cursor, - u16 rop, const u8 *pcol, const u8 *pmsk) +void sm750_hw_cursor_setData(struct lynx_cursor *cursor, u16 rop, + const u8 *pcol, const u8 *pmsk) { int i, j, count, pitch, offset; u8 color, mask, opr; @@ -138,8 +135,8 @@ void sm750_hw_cursor_setData(struct lynx_cursor *cursor, } -void sm750_hw_cursor_setData2(struct lynx_cursor *cursor, - u16 rop, const u8 *pcol, const u8 *pmsk) +void sm750_hw_cursor_setData2(struct lynx_cursor *cursor, u16 rop, + const u8 *pcol, const u8 *pmsk) { int i, j, count, pitch, offset; u8 color, mask; diff --git a/drivers/staging/speakup/Makefile b/drivers/staging/speakup/Makefile index c5e43a59822f..c864ea69c40d 100644 --- a/drivers/staging/speakup/Makefile +++ b/drivers/staging/speakup/Makefile @@ -25,6 +25,7 @@ speakup-y := \ kobjects.o \ selection.o \ serialio.o \ + spk_ttyio.o \ synth.o \ thread.o \ varhandlers.o diff --git a/drivers/staging/speakup/main.c b/drivers/staging/speakup/main.c index d2ad596850f3..82e5de248947 100644 --- a/drivers/staging/speakup/main.c +++ b/drivers/staging/speakup/main.c @@ -1945,6 +1945,7 @@ static int handle_goto(struct vc_data *vc, u_char type, u_char ch, u_short key) goto oops; if (ch == 8) { u16 wch; + if (num == 0) return -1; wch = goto_buf[--num]; @@ -2287,6 +2288,7 @@ static int vt_notifier_call(struct notifier_block *nb, speakup_bs(vc); } else { u16 d = param->c; + speakup_con_write(vc, &d, 1); } break; diff --git a/drivers/staging/speakup/serialio.c b/drivers/staging/speakup/serialio.c index ba060d0ceca2..9cfc8142a318 100644 --- a/drivers/staging/speakup/serialio.c +++ b/drivers/staging/speakup/serialio.c @@ -28,11 +28,17 @@ static int timeouts; static int spk_serial_out(struct spk_synth *in_synth, const char ch); static void spk_serial_send_xchar(char ch); static void spk_serial_tiocmset(unsigned int set, unsigned int clear); +static unsigned char spk_serial_in(void); +static unsigned char spk_serial_in_nowait(void); +static void spk_serial_flush_buffer(void); struct spk_io_ops spk_serial_io_ops = { .synth_out = spk_serial_out, .send_xchar = spk_serial_send_xchar, .tiocmset = spk_serial_tiocmset, + .synth_in = spk_serial_in, + .synth_in_nowait = spk_serial_in_nowait, + .flush_buffer = spk_serial_flush_buffer, }; EXPORT_SYMBOL_GPL(spk_serial_io_ops); @@ -132,8 +138,8 @@ static void start_serial_interrupt(int irq) outb(UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2, speakup_info.port_tts + UART_MCR); /* Turn on Interrupts */ - outb(UART_IER_MSI|UART_IER_RLSI|UART_IER_RDI, - speakup_info.port_tts + UART_IER); + outb(UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI, + speakup_info.port_tts + UART_IER); inb(speakup_info.port_tts + UART_LSR); inb(speakup_info.port_tts + UART_RX); inb(speakup_info.port_tts + UART_IIR); @@ -156,6 +162,7 @@ static void spk_serial_send_xchar(char ch) static void spk_serial_tiocmset(unsigned int set, unsigned int clear) { int old = inb(speakup_info.port_tts + UART_MCR); + outb((old & ~clear) | set, speakup_info.port_tts + UART_MCR); } @@ -221,7 +228,8 @@ int spk_wait_for_xmitr(struct spk_synth *in_synth) } while (spk_serial_tx_busy()) { if (--tmout == 0) { - pr_warn("%s: timed out (tx busy)\n", in_synth->long_name); + pr_warn("%s: timed out (tx busy)\n", + in_synth->long_name); timeouts++; return 0; } @@ -240,7 +248,7 @@ int spk_wait_for_xmitr(struct spk_synth *in_synth) return 1; } -unsigned char spk_serial_in(void) +static unsigned char spk_serial_in(void) { int tmout = SPK_SERIAL_TIMEOUT; @@ -253,9 +261,8 @@ unsigned char spk_serial_in(void) } return inb_p(speakup_info.port_tts + UART_RX); } -EXPORT_SYMBOL_GPL(spk_serial_in); -unsigned char spk_serial_in_nowait(void) +static unsigned char spk_serial_in_nowait(void) { unsigned char lsr; @@ -264,7 +271,11 @@ unsigned char spk_serial_in_nowait(void) return 0; return inb_p(speakup_info.port_tts + UART_RX); } -EXPORT_SYMBOL_GPL(spk_serial_in_nowait); + +static void spk_serial_flush_buffer(void) +{ + /* TODO: flush the UART 16550 buffer */ +} static int spk_serial_out(struct spk_synth *in_synth, const char ch) { @@ -275,7 +286,8 @@ static int spk_serial_out(struct spk_synth *in_synth, const char ch) return 0; } -const char *spk_serial_synth_immediate(struct spk_synth *synth, const char *buff) +const char *spk_serial_synth_immediate(struct spk_synth *synth, + const char *buff) { u_char ch; diff --git a/drivers/staging/speakup/serialio.h b/drivers/staging/speakup/serialio.h index 3ad7ff0bc3c3..89de6fff9cb2 100644 --- a/drivers/staging/speakup/serialio.h +++ b/drivers/staging/speakup/serialio.h @@ -8,6 +8,8 @@ #endif #include <linux/serial_core.h> +#include "spk_priv.h" + /* * this is cut&paste from 8250.h. Get rid of the structure, the definitions * and this whole broken driver. @@ -21,7 +23,7 @@ struct old_serial_port { }; /* countdown values for serial timeouts in us */ -#define SPK_SERIAL_TIMEOUT 100000 +#define SPK_SERIAL_TIMEOUT SPK_SYNTH_TIMEOUT /* countdown values transmitter/dsr timeouts in us */ #define SPK_XMITR_TIMEOUT 100000 /* countdown values cts timeouts in us */ diff --git a/drivers/staging/speakup/speakup_acntsa.c b/drivers/staging/speakup/speakup_acntsa.c index de67ffda7d45..0e10404e2e8c 100644 --- a/drivers/staging/speakup/speakup_acntsa.c +++ b/drivers/staging/speakup/speakup_acntsa.c @@ -96,13 +96,14 @@ static struct spk_synth synth_acntsa = { .trigger = 50, .jiffies = 30, .full = 40000, + .dev_name = SYNTH_DEFAULT_DEV, .startup = SYNTH_START, .checkval = SYNTH_CHECK, .vars = vars, - .io_ops = &spk_serial_io_ops, + .io_ops = &spk_ttyio_ops, .probe = synth_probe, - .release = spk_serial_release, - .synth_immediate = spk_serial_synth_immediate, + .release = spk_ttyio_release, + .synth_immediate = spk_ttyio_synth_immediate, .catch_up = spk_do_catch_up, .flush = spk_synth_flush, .is_alive = spk_synth_is_alive_restart, @@ -125,7 +126,7 @@ static int synth_probe(struct spk_synth *synth) { int failed; - failed = spk_serial_synth_probe(synth); + failed = spk_ttyio_synth_probe(synth); if (failed == 0) { synth->synth_immediate(synth, "\033=R\r"); mdelay(100); @@ -135,9 +136,11 @@ static int synth_probe(struct spk_synth *synth) } module_param_named(ser, synth_acntsa.ser, int, 0444); +module_param_named(dev, synth_acntsa.dev_name, charp, S_IRUGO); module_param_named(start, synth_acntsa.startup, short, 0444); MODULE_PARM_DESC(ser, "Set the serial port for the synthesizer (0-based)."); +MODULE_PARM_DESC(dev, "Set the device e.g. ttyUSB0, for the synthesizer."); MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded."); module_spk_synth(synth_acntsa); diff --git a/drivers/staging/speakup/speakup_apollo.c b/drivers/staging/speakup/speakup_apollo.c index cead8b1b1bfc..2edb56c8a559 100644 --- a/drivers/staging/speakup/speakup_apollo.c +++ b/drivers/staging/speakup/speakup_apollo.c @@ -22,9 +22,9 @@ #include <linux/sched.h> #include <linux/timer.h> #include <linux/kthread.h> +#include <linux/serial_reg.h> /* for UART_MCR* constants */ #include "spk_priv.h" -#include "serialio.h" #include "speakup.h" #define DRV_VERSION "2.21" @@ -105,13 +105,14 @@ static struct spk_synth synth_apollo = { .trigger = 50, .jiffies = 50, .full = 40000, + .dev_name = SYNTH_DEFAULT_DEV, .startup = SYNTH_START, .checkval = SYNTH_CHECK, .vars = vars, - .io_ops = &spk_serial_io_ops, - .probe = spk_serial_synth_probe, - .release = spk_serial_release, - .synth_immediate = spk_serial_synth_immediate, + .io_ops = &spk_ttyio_ops, + .probe = spk_ttyio_synth_probe, + .release = spk_ttyio_release, + .synth_immediate = spk_ttyio_synth_immediate, .catch_up = do_catch_up, .flush = spk_synth_flush, .is_alive = spk_synth_is_alive_restart, @@ -199,9 +200,11 @@ static void do_catch_up(struct spk_synth *synth) } module_param_named(ser, synth_apollo.ser, int, 0444); +module_param_named(dev, synth_apollo.dev_name, charp, S_IRUGO); module_param_named(start, synth_apollo.startup, short, 0444); MODULE_PARM_DESC(ser, "Set the serial port for the synthesizer (0-based)."); +MODULE_PARM_DESC(dev, "Set the device e.g. ttyUSB0, for the synthesizer."); MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded."); module_spk_synth(synth_apollo); diff --git a/drivers/staging/speakup/speakup_audptr.c b/drivers/staging/speakup/speakup_audptr.c index 6880352a7b74..8ae826eba71c 100644 --- a/drivers/staging/speakup/speakup_audptr.c +++ b/drivers/staging/speakup/speakup_audptr.c @@ -20,7 +20,6 @@ */ #include "spk_priv.h" #include "speakup.h" -#include "serialio.h" #define DRV_VERSION "2.11" #define SYNTH_CLEAR 0x18 /* flush synth buffer */ @@ -101,13 +100,14 @@ static struct spk_synth synth_audptr = { .trigger = 50, .jiffies = 30, .full = 18000, + .dev_name = SYNTH_DEFAULT_DEV, .startup = SYNTH_START, .checkval = SYNTH_CHECK, .vars = vars, - .io_ops = &spk_serial_io_ops, + .io_ops = &spk_ttyio_ops, .probe = synth_probe, - .release = spk_serial_release, - .synth_immediate = spk_serial_synth_immediate, + .release = spk_ttyio_release, + .synth_immediate = spk_ttyio_synth_immediate, .catch_up = spk_do_catch_up, .flush = synth_flush, .is_alive = spk_synth_is_alive_restart, @@ -128,6 +128,7 @@ static struct spk_synth synth_audptr = { static void synth_flush(struct spk_synth *synth) { + synth->io_ops->flush_buffer(); synth->io_ops->send_xchar(SYNTH_CLEAR); synth->io_ops->synth_out(synth, PROCSPEECH); } @@ -138,11 +139,11 @@ static void synth_version(struct spk_synth *synth) char synth_id[40] = ""; synth->synth_immediate(synth, "\x05[Q]"); - synth_id[test] = spk_serial_in(); + synth_id[test] = synth->io_ops->synth_in(); if (synth_id[test] == 'A') { do { /* read version string from synth */ - synth_id[++test] = spk_serial_in(); + synth_id[++test] = synth->io_ops->synth_in(); } while (synth_id[test] != '\n' && test < 32); synth_id[++test] = 0x00; } @@ -154,7 +155,7 @@ static int synth_probe(struct spk_synth *synth) { int failed; - failed = spk_serial_synth_probe(synth); + failed = spk_ttyio_synth_probe(synth); if (failed == 0) synth_version(synth); synth->alive = !failed; @@ -162,9 +163,11 @@ static int synth_probe(struct spk_synth *synth) } module_param_named(ser, synth_audptr.ser, int, 0444); +module_param_named(dev, synth_audptr.dev_name, charp, S_IRUGO); module_param_named(start, synth_audptr.startup, short, 0444); MODULE_PARM_DESC(ser, "Set the serial port for the synthesizer (0-based)."); +MODULE_PARM_DESC(dev, "Set the device e.g. ttyUSB0, for the synthesizer."); MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded."); module_spk_synth(synth_audptr); diff --git a/drivers/staging/speakup/speakup_bns.c b/drivers/staging/speakup/speakup_bns.c index a972a5147c6b..60bcf0df8123 100644 --- a/drivers/staging/speakup/speakup_bns.c +++ b/drivers/staging/speakup/speakup_bns.c @@ -93,13 +93,14 @@ static struct spk_synth synth_bns = { .trigger = 50, .jiffies = 50, .full = 40000, + .dev_name = SYNTH_DEFAULT_DEV, .startup = SYNTH_START, .checkval = SYNTH_CHECK, .vars = vars, - .io_ops = &spk_serial_io_ops, - .probe = spk_serial_synth_probe, - .release = spk_serial_release, - .synth_immediate = spk_serial_synth_immediate, + .io_ops = &spk_ttyio_ops, + .probe = spk_ttyio_synth_probe, + .release = spk_ttyio_release, + .synth_immediate = spk_ttyio_synth_immediate, .catch_up = spk_do_catch_up, .flush = spk_synth_flush, .is_alive = spk_synth_is_alive_restart, @@ -119,9 +120,11 @@ static struct spk_synth synth_bns = { }; module_param_named(ser, synth_bns.ser, int, 0444); +module_param_named(dev, synth_bns.dev_name, charp, S_IRUGO); module_param_named(start, synth_bns.startup, short, 0444); MODULE_PARM_DESC(ser, "Set the serial port for the synthesizer (0-based)."); +MODULE_PARM_DESC(dev, "Set the device e.g. ttyUSB0, for the synthesizer."); MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded."); module_spk_synth(synth_bns); diff --git a/drivers/staging/speakup/speakup_decext.c b/drivers/staging/speakup/speakup_decext.c index c564bf8e1531..95f4b2116d0c 100644 --- a/drivers/staging/speakup/speakup_decext.c +++ b/drivers/staging/speakup/speakup_decext.c @@ -24,26 +24,22 @@ #include <linux/kthread.h> #include "spk_priv.h" -#include "serialio.h" #include "speakup.h" #define DRV_VERSION "2.14" #define SYNTH_CLEAR 0x03 #define PROCSPEECH 0x0b -static unsigned char last_char; -static inline u_char get_last_char(void) -{ - u_char avail = inb_p(speakup_info.port_tts + UART_LSR) & UART_LSR_DR; +static volatile unsigned char last_char; - if (avail) - last_char = inb_p(speakup_info.port_tts + UART_RX); - return last_char; +static void read_buff_add(u_char ch) +{ + last_char = ch; } static inline bool synth_full(void) { - return get_last_char() == 0x13; + return last_char == 0x13; } static void do_catch_up(struct spk_synth *synth); @@ -124,18 +120,19 @@ static struct spk_synth synth_decext = { .jiffies = 50, .full = 40000, .flags = SF_DEC, + .dev_name = SYNTH_DEFAULT_DEV, .startup = SYNTH_START, .checkval = SYNTH_CHECK, .vars = vars, - .io_ops = &spk_serial_io_ops, - .probe = spk_serial_synth_probe, - .release = spk_serial_release, - .synth_immediate = spk_serial_synth_immediate, + .io_ops = &spk_ttyio_ops, + .probe = spk_ttyio_synth_probe, + .release = spk_ttyio_release, + .synth_immediate = spk_ttyio_synth_immediate, .catch_up = do_catch_up, .flush = synth_flush, .is_alive = spk_synth_is_alive_restart, .synth_adjust = NULL, - .read_buff_add = NULL, + .read_buff_add = read_buff_add, .get_index = NULL, .indexing = { .command = NULL, @@ -225,13 +222,16 @@ static void do_catch_up(struct spk_synth *synth) static void synth_flush(struct spk_synth *synth) { in_escape = 0; + synth->io_ops->flush_buffer(); synth->synth_immediate(synth, "\033P;10z\033\\"); } module_param_named(ser, synth_decext.ser, int, 0444); +module_param_named(dev, synth_decext.dev_name, charp, S_IRUGO); module_param_named(start, synth_decext.startup, short, 0444); MODULE_PARM_DESC(ser, "Set the serial port for the synthesizer (0-based)."); +MODULE_PARM_DESC(dev, "Set the device e.g. ttyUSB0, for the synthesizer."); MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded."); module_spk_synth(synth_decext); diff --git a/drivers/staging/speakup/speakup_decpc.c b/drivers/staging/speakup/speakup_decpc.c index 5d22c3b7edd4..7a8df7dc1e38 100644 --- a/drivers/staging/speakup/speakup_decpc.c +++ b/drivers/staging/speakup/speakup_decpc.c @@ -84,7 +84,7 @@ #define CTRL_last_index 0x0b00 /* get last index spoken */ #define CTRL_io_priority 0x0c00 /* change i/o priority */ #define CTRL_free_mem 0x0d00 /* get free paragraphs on module */ -#define CTRL_get_lang 0x0e00 /* return bit mask of loaded languages */ +#define CTRL_get_lang 0x0e00 /* return bitmask of loaded languages */ #define CMD_test 0x2000 /* self-test request */ #define TEST_mask 0x0F00 /* isolate test field */ #define TEST_null 0x0000 /* no test requested */ diff --git a/drivers/staging/speakup/speakup_dectlk.c b/drivers/staging/speakup/speakup_dectlk.c index 0cdbd5e9b36b..f06995480022 100644 --- a/drivers/staging/speakup/speakup_dectlk.c +++ b/drivers/staging/speakup/speakup_dectlk.c @@ -27,7 +27,6 @@ #include <linux/kthread.h> #include "speakup.h" #include "spk_priv.h" -#include "serialio.h" #define DRV_VERSION "2.20" #define SYNTH_CLEAR 0x03 @@ -42,7 +41,7 @@ static inline int synth_full(void) static void do_catch_up(struct spk_synth *synth); static void synth_flush(struct spk_synth *synth); static void read_buff_add(u_char c); -static unsigned char get_index(void); +static unsigned char get_index(struct spk_synth *synth); static int in_escape; static int is_flushing; @@ -125,15 +124,16 @@ static struct spk_synth synth_dectlk = { .trigger = 50, .jiffies = 50, .full = 40000, + .dev_name = SYNTH_DEFAULT_DEV, .startup = SYNTH_START, .checkval = SYNTH_CHECK, .vars = vars, .default_pitch = ap_defaults, .default_vol = g5_defaults, - .io_ops = &spk_serial_io_ops, - .probe = spk_serial_synth_probe, - .release = spk_serial_release, - .synth_immediate = spk_serial_synth_immediate, + .io_ops = &spk_ttyio_ops, + .probe = spk_ttyio_synth_probe, + .release = spk_ttyio_release, + .synth_immediate = spk_ttyio_synth_immediate, .catch_up = do_catch_up, .flush = synth_flush, .is_alive = spk_synth_is_alive_restart, @@ -163,7 +163,7 @@ static int is_indnum(u_char *ch) static u_char lastind; -static unsigned char get_index(void) +static unsigned char get_index(struct spk_synth *synth) { u_char rv; @@ -294,13 +294,16 @@ static void synth_flush(struct spk_synth *synth) synth->io_ops->synth_out(synth, ']'); in_escape = 0; is_flushing = 1; + synth->io_ops->flush_buffer(); synth->io_ops->synth_out(synth, SYNTH_CLEAR); } module_param_named(ser, synth_dectlk.ser, int, 0444); +module_param_named(dev, synth_dectlk.dev_name, charp, S_IRUGO); module_param_named(start, synth_dectlk.startup, short, 0444); MODULE_PARM_DESC(ser, "Set the serial port for the synthesizer (0-based)."); +MODULE_PARM_DESC(dev, "Set the device e.g. ttyUSB0, for the synthesizer."); MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded."); module_spk_synth(synth_dectlk); diff --git a/drivers/staging/speakup/speakup_dtlk.c b/drivers/staging/speakup/speakup_dtlk.c index 33180937222d..8999e3eb5c26 100644 --- a/drivers/staging/speakup/speakup_dtlk.c +++ b/drivers/staging/speakup/speakup_dtlk.c @@ -138,7 +138,7 @@ static struct spk_synth synth_dtlk = { .is_alive = spk_synth_is_alive_nop, .synth_adjust = NULL, .read_buff_add = NULL, - .get_index = spk_serial_in_nowait, + .get_index = spk_synth_get_index, .indexing = { .command = "\x01%di", .lowindex = 1, diff --git a/drivers/staging/speakup/speakup_dtlk.h b/drivers/staging/speakup/speakup_dtlk.h index 46d885fcfb20..51ac0f2fcded 100644 --- a/drivers/staging/speakup/speakup_dtlk.h +++ b/drivers/staging/speakup/speakup_dtlk.h @@ -24,11 +24,11 @@ * usec later. */ #define TTS_ALMOST_FULL 0x08 /* mask for AF bit: When set to 1, - * indicates that less than 300 bytes - * are available in the TTS input - * buffer. AF is always 0 in the PCM, - * TGN and CVSD modes. - */ + * indicates that less than 300 bytes + * are available in the TTS input + * buffer. AF is always 0 in the PCM, + * TGN and CVSD modes. + */ #define TTS_ALMOST_EMPTY 0x04 /* mask for AE bit: When set to 1, * indicates that less than 300 bytes * are remaining in DoubleTalk's input diff --git a/drivers/staging/speakup/speakup_dummy.c b/drivers/staging/speakup/speakup_dummy.c index 8db7aa358f31..851953d5eefb 100644 --- a/drivers/staging/speakup/speakup_dummy.c +++ b/drivers/staging/speakup/speakup_dummy.c @@ -95,13 +95,14 @@ static struct spk_synth synth_dummy = { .trigger = 50, .jiffies = 50, .full = 40000, + .dev_name = SYNTH_DEFAULT_DEV, .startup = SYNTH_START, .checkval = SYNTH_CHECK, .vars = vars, - .io_ops = &spk_serial_io_ops, - .probe = spk_serial_synth_probe, - .release = spk_serial_release, - .synth_immediate = spk_serial_synth_immediate, + .io_ops = &spk_ttyio_ops, + .probe = spk_ttyio_synth_probe, + .release = spk_ttyio_release, + .synth_immediate = spk_ttyio_synth_immediate, .catch_up = spk_do_catch_up, .flush = spk_synth_flush, .is_alive = spk_synth_is_alive_restart, @@ -121,9 +122,11 @@ static struct spk_synth synth_dummy = { }; module_param_named(ser, synth_dummy.ser, int, 0444); +module_param_named(dev, synth_dummy.dev_name, charp, S_IRUGO); module_param_named(start, synth_dummy.startup, short, 0444); MODULE_PARM_DESC(ser, "Set the serial port for the synthesizer (0-based)."); +MODULE_PARM_DESC(dev, "Set the device e.g. ttyUSB0, for the synthesizer."); MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded."); module_spk_synth(synth_dummy); diff --git a/drivers/staging/speakup/speakup_ltlk.c b/drivers/staging/speakup/speakup_ltlk.c index 11275f49bea4..423795f88f53 100644 --- a/drivers/staging/speakup/speakup_ltlk.c +++ b/drivers/staging/speakup/speakup_ltlk.c @@ -20,7 +20,6 @@ */ #include "speakup.h" #include "spk_priv.h" -#include "serialio.h" #include "speakup_dtlk.h" /* local header file for LiteTalk values */ #define DRV_VERSION "2.11" @@ -108,19 +107,20 @@ static struct spk_synth synth_ltlk = { .trigger = 50, .jiffies = 50, .full = 40000, + .dev_name = SYNTH_DEFAULT_DEV, .startup = SYNTH_START, .checkval = SYNTH_CHECK, .vars = vars, - .io_ops = &spk_serial_io_ops, + .io_ops = &spk_ttyio_ops, .probe = synth_probe, - .release = spk_serial_release, - .synth_immediate = spk_serial_synth_immediate, + .release = spk_ttyio_release, + .synth_immediate = spk_ttyio_synth_immediate, .catch_up = spk_do_catch_up, .flush = spk_synth_flush, .is_alive = spk_synth_is_alive_restart, .synth_adjust = NULL, .read_buff_add = NULL, - .get_index = spk_serial_in_nowait, + .get_index = spk_synth_get_index, .indexing = { .command = "\x01%di", .lowindex = 1, @@ -141,7 +141,7 @@ static void synth_interrogate(struct spk_synth *synth) synth->synth_immediate(synth, "\x18\x01?"); for (i = 0; i < 50; i++) { - buf[i] = spk_serial_in(); + buf[i] = synth->io_ops->synth_in(); if (i > 2 && buf[i] == 0x7f) break; } @@ -159,7 +159,7 @@ static int synth_probe(struct spk_synth *synth) { int failed = 0; - failed = spk_serial_synth_probe(synth); + failed = spk_ttyio_synth_probe(synth); if (failed == 0) synth_interrogate(synth); synth->alive = !failed; @@ -167,9 +167,11 @@ static int synth_probe(struct spk_synth *synth) } module_param_named(ser, synth_ltlk.ser, int, 0444); +module_param_named(dev, synth_ltlk.dev_name, charp, S_IRUGO); module_param_named(start, synth_ltlk.startup, short, 0444); MODULE_PARM_DESC(ser, "Set the serial port for the synthesizer (0-based)."); +MODULE_PARM_DESC(dev, "Set the device e.g. ttyUSB0, for the synthesizer."); MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded."); module_spk_synth(synth_ltlk); diff --git a/drivers/staging/speakup/speakup_soft.c b/drivers/staging/speakup/speakup_soft.c index e454f5685f70..d99daf69e501 100644 --- a/drivers/staging/speakup/speakup_soft.c +++ b/drivers/staging/speakup/speakup_soft.c @@ -36,7 +36,7 @@ static int softsynth_probe(struct spk_synth *synth); static void softsynth_release(void); static int softsynth_is_alive(struct spk_synth *synth); -static unsigned char get_index(void); +static unsigned char get_index(struct spk_synth *synth); static struct miscdevice synth_device, synthu_device; static int init_pos; @@ -340,7 +340,7 @@ static unsigned int softsynth_poll(struct file *fp, struct poll_table_struct *wa return ret; } -static unsigned char get_index(void) +static unsigned char get_index(struct spk_synth *synth) { int rv; diff --git a/drivers/staging/speakup/speakup_spkout.c b/drivers/staging/speakup/speakup_spkout.c index d95c375a0736..9ca21edc42ce 100644 --- a/drivers/staging/speakup/speakup_spkout.c +++ b/drivers/staging/speakup/speakup_spkout.c @@ -20,7 +20,6 @@ */ #include "spk_priv.h" #include "speakup.h" -#include "serialio.h" #define DRV_VERSION "2.11" #define SYNTH_CLEAR 0x18 @@ -99,19 +98,20 @@ static struct spk_synth synth_spkout = { .trigger = 50, .jiffies = 50, .full = 40000, + .dev_name = SYNTH_DEFAULT_DEV, .startup = SYNTH_START, .checkval = SYNTH_CHECK, .vars = vars, - .io_ops = &spk_serial_io_ops, - .probe = spk_serial_synth_probe, - .release = spk_serial_release, - .synth_immediate = spk_serial_synth_immediate, + .io_ops = &spk_ttyio_ops, + .probe = spk_ttyio_synth_probe, + .release = spk_ttyio_release, + .synth_immediate = spk_ttyio_synth_immediate, .catch_up = spk_do_catch_up, .flush = synth_flush, .is_alive = spk_synth_is_alive_restart, .synth_adjust = NULL, .read_buff_add = NULL, - .get_index = spk_serial_in_nowait, + .get_index = spk_synth_get_index, .indexing = { .command = "\x05[%c", .lowindex = 1, @@ -126,13 +126,16 @@ static struct spk_synth synth_spkout = { static void synth_flush(struct spk_synth *synth) { + synth->io_ops->flush_buffer(); synth->io_ops->send_xchar(SYNTH_CLEAR); } module_param_named(ser, synth_spkout.ser, int, 0444); +module_param_named(dev, synth_spkout.dev_name, charp, S_IRUGO); module_param_named(start, synth_spkout.startup, short, 0444); MODULE_PARM_DESC(ser, "Set the serial port for the synthesizer (0-based)."); +MODULE_PARM_DESC(dev, "Set the device e.g. ttyUSB0, for the synthesizer."); MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded."); module_spk_synth(synth_spkout); diff --git a/drivers/staging/speakup/speakup_txprt.c b/drivers/staging/speakup/speakup_txprt.c index 3f531fb99fd3..831ee404e7a1 100644 --- a/drivers/staging/speakup/speakup_txprt.c +++ b/drivers/staging/speakup/speakup_txprt.c @@ -92,13 +92,14 @@ static struct spk_synth synth_txprt = { .trigger = 50, .jiffies = 50, .full = 40000, + .dev_name = SYNTH_DEFAULT_DEV, .startup = SYNTH_START, .checkval = SYNTH_CHECK, .vars = vars, - .io_ops = &spk_serial_io_ops, - .probe = spk_serial_synth_probe, - .release = spk_serial_release, - .synth_immediate = spk_serial_synth_immediate, + .io_ops = &spk_ttyio_ops, + .probe = spk_ttyio_synth_probe, + .release = spk_ttyio_release, + .synth_immediate = spk_ttyio_synth_immediate, .catch_up = spk_do_catch_up, .flush = spk_synth_flush, .is_alive = spk_synth_is_alive_restart, @@ -118,9 +119,11 @@ static struct spk_synth synth_txprt = { }; module_param_named(ser, synth_txprt.ser, int, 0444); +module_param_named(dev, synth_txprt.dev_name, charp, S_IRUGO); module_param_named(start, synth_txprt.startup, short, 0444); MODULE_PARM_DESC(ser, "Set the serial port for the synthesizer (0-based)."); +MODULE_PARM_DESC(dev, "Set the device e.g. ttyUSB0, for the synthesizer."); MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded."); module_spk_synth(synth_txprt); diff --git a/drivers/staging/speakup/spk_priv.h b/drivers/staging/speakup/spk_priv.h index 995f586bddcd..87b6a0a4c54d 100644 --- a/drivers/staging/speakup/spk_priv.h +++ b/drivers/staging/speakup/spk_priv.h @@ -39,13 +39,15 @@ #endif #define KT_SPKUP 15 +#define SPK_SYNTH_TIMEOUT 100000 /* in micro-seconds */ +#define SYNTH_DEFAULT_DEV "ttyS0" +#define SYNTH_DEFAULT_SER 0 const struct old_serial_port *spk_serial_init(int index); void spk_stop_serial_interrupt(void); int spk_wait_for_xmitr(struct spk_synth *in_synth); -unsigned char spk_serial_in(void); -unsigned char spk_serial_in_nowait(void); void spk_serial_release(void); +void spk_ttyio_release(void); void synth_buffer_skip_nonlatin1(void); u16 synth_buffer_getc(void); @@ -58,9 +60,12 @@ ssize_t spk_var_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count); int spk_serial_synth_probe(struct spk_synth *synth); +int spk_ttyio_synth_probe(struct spk_synth *synth); const char *spk_serial_synth_immediate(struct spk_synth *synth, const char *buff); +const char *spk_ttyio_synth_immediate(struct spk_synth *synth, const char *buff); void spk_do_catch_up(struct spk_synth *synth); void spk_synth_flush(struct spk_synth *synth); +unsigned char spk_synth_get_index(struct spk_synth *synth); int spk_synth_is_alive_nop(struct spk_synth *synth); int spk_synth_is_alive_restart(struct spk_synth *synth); __printf(1, 2) @@ -79,5 +84,6 @@ extern struct speakup_info_t speakup_info; extern struct var_t synth_time_vars[]; extern struct spk_io_ops spk_serial_io_ops; +extern struct spk_io_ops spk_ttyio_ops; #endif diff --git a/drivers/staging/speakup/spk_ttyio.c b/drivers/staging/speakup/spk_ttyio.c new file mode 100644 index 000000000000..ed8e96b06ead --- /dev/null +++ b/drivers/staging/speakup/spk_ttyio.c @@ -0,0 +1,320 @@ +#include <linux/types.h> +#include <linux/tty.h> +#include <linux/tty_flip.h> +#include <linux/slab.h> + +#include "speakup.h" +#include "spk_types.h" +#include "spk_priv.h" + +#define DEV_PREFIX_LP "lp" + +static const char * const lp_supported[] = { "acntsa", "bns", "dummy", + "txprt" }; + +struct spk_ldisc_data { + char buf; + struct semaphore sem; + bool buf_free; +}; + +static struct spk_synth *spk_ttyio_synth; +static struct tty_struct *speakup_tty; + +static int ser_to_dev(int ser, dev_t *dev_no) +{ + if (ser < 0 || ser > (255 - 64)) { + pr_err("speakup: Invalid ser param. Must be between 0 and 191 inclusive.\n"); + return -EINVAL; + } + + *dev_no = MKDEV(4, (64 + ser)); + return 0; +} + +static int get_dev_to_use(struct spk_synth *synth, dev_t *dev_no) +{ + /* use ser only when dev is not specified */ + if (strcmp(synth->dev_name, SYNTH_DEFAULT_DEV) || + synth->ser == SYNTH_DEFAULT_SER) { + /* for /dev/lp* check if synth is supported */ + if (strncmp(synth->dev_name, DEV_PREFIX_LP, + strlen(DEV_PREFIX_LP)) == 0) + if (match_string(lp_supported, ARRAY_SIZE(lp_supported), + synth->name) < 0) { + int i; + + pr_err("speakup: lp* is only supported on:"); + for (i = 0; i < ARRAY_SIZE(lp_supported); i++) + pr_cont(" %s", lp_supported[i]); + pr_cont("\n"); + + return -ENOTSUPP; + } + + return tty_dev_name_to_number(synth->dev_name, dev_no); + } + + return ser_to_dev(synth->ser, dev_no); +} + +static int spk_ttyio_ldisc_open(struct tty_struct *tty) +{ + struct spk_ldisc_data *ldisc_data; + + if (tty->ops->write == NULL) + return -EOPNOTSUPP; + speakup_tty = tty; + + ldisc_data = kmalloc(sizeof(struct spk_ldisc_data), GFP_KERNEL); + if (!ldisc_data) { + pr_err("speakup: Failed to allocate ldisc_data.\n"); + return -ENOMEM; + } + + sema_init(&ldisc_data->sem, 0); + ldisc_data->buf_free = true; + speakup_tty->disc_data = ldisc_data; + + return 0; +} + +static void spk_ttyio_ldisc_close(struct tty_struct *tty) +{ + kfree(speakup_tty->disc_data); + speakup_tty = NULL; +} + +static int spk_ttyio_receive_buf2(struct tty_struct *tty, + const unsigned char *cp, char *fp, int count) +{ + struct spk_ldisc_data *ldisc_data = tty->disc_data; + + if (spk_ttyio_synth->read_buff_add) { + int i; + + for (i = 0; i < count; i++) + spk_ttyio_synth->read_buff_add(cp[i]); + + return count; + } + + if (!ldisc_data->buf_free) + /* ttyio_in will tty_schedule_flip */ + return 0; + + /* Make sure the consumer has read buf before we have seen + * buf_free == true and overwrite buf */ + mb(); + + ldisc_data->buf = cp[0]; + ldisc_data->buf_free = false; + up(&ldisc_data->sem); + + return 1; +} + +static struct tty_ldisc_ops spk_ttyio_ldisc_ops = { + .owner = THIS_MODULE, + .magic = TTY_LDISC_MAGIC, + .name = "speakup_ldisc", + .open = spk_ttyio_ldisc_open, + .close = spk_ttyio_ldisc_close, + .receive_buf2 = spk_ttyio_receive_buf2, +}; + +static int spk_ttyio_out(struct spk_synth *in_synth, const char ch); +static void spk_ttyio_send_xchar(char ch); +static void spk_ttyio_tiocmset(unsigned int set, unsigned int clear); +static unsigned char spk_ttyio_in(void); +static unsigned char spk_ttyio_in_nowait(void); +static void spk_ttyio_flush_buffer(void); + +struct spk_io_ops spk_ttyio_ops = { + .synth_out = spk_ttyio_out, + .send_xchar = spk_ttyio_send_xchar, + .tiocmset = spk_ttyio_tiocmset, + .synth_in = spk_ttyio_in, + .synth_in_nowait = spk_ttyio_in_nowait, + .flush_buffer = spk_ttyio_flush_buffer, +}; +EXPORT_SYMBOL_GPL(spk_ttyio_ops); + +static inline void get_termios(struct tty_struct *tty, struct ktermios *out_termios) +{ + down_read(&tty->termios_rwsem); + *out_termios = tty->termios; + up_read(&tty->termios_rwsem); +} + +static int spk_ttyio_initialise_ldisc(struct spk_synth *synth) +{ + int ret = 0; + struct tty_struct *tty; + struct ktermios tmp_termios; + dev_t dev; + + ret = tty_register_ldisc(N_SPEAKUP, &spk_ttyio_ldisc_ops); + if (ret) { + pr_err("Error registering line discipline.\n"); + return ret; + } + + ret = get_dev_to_use(synth, &dev); + if (ret) + return ret; + + tty = tty_open_by_driver(dev, NULL, NULL); + if (IS_ERR(tty)) + return PTR_ERR(tty); + + if (tty->ops->open) + ret = tty->ops->open(tty, NULL); + else + ret = -ENODEV; + + if (ret) { + tty_unlock(tty); + return ret; + } + + clear_bit(TTY_HUPPED, &tty->flags); + /* ensure hardware flow control is enabled */ + get_termios(tty, &tmp_termios); + if (!(tmp_termios.c_cflag & CRTSCTS)) { + tmp_termios.c_cflag |= CRTSCTS; + tty_set_termios(tty, &tmp_termios); + /* + * check c_cflag to see if it's updated as tty_set_termios may not return + * error even when no tty bits are changed by the request. + */ + get_termios(tty, &tmp_termios); + if (!(tmp_termios.c_cflag & CRTSCTS)) + pr_warn("speakup: Failed to set hardware flow control\n"); + } + + tty_unlock(tty); + + ret = tty_set_ldisc(tty, N_SPEAKUP); + + return ret; +} + +static int spk_ttyio_out(struct spk_synth *in_synth, const char ch) +{ + if (in_synth->alive && speakup_tty && speakup_tty->ops->write) { + int ret = speakup_tty->ops->write(speakup_tty, &ch, 1); + + if (ret == 0) + /* No room */ + return 0; + if (ret < 0) { + pr_warn("%s: I/O error, deactivating speakup\n", in_synth->long_name); + /* No synth any more, so nobody will restart TTYs, and we thus + * need to do it ourselves. Now that there is no synth we can + * let application flood anyway + */ + in_synth->alive = 0; + speakup_start_ttys(); + return 0; + } + return 1; + } + return 0; +} + +static void spk_ttyio_send_xchar(char ch) +{ + speakup_tty->ops->send_xchar(speakup_tty, ch); +} + +static void spk_ttyio_tiocmset(unsigned int set, unsigned int clear) +{ + speakup_tty->ops->tiocmset(speakup_tty, set, clear); +} + +static unsigned char ttyio_in(int timeout) +{ + struct spk_ldisc_data *ldisc_data = speakup_tty->disc_data; + char rv; + + if (down_timeout(&ldisc_data->sem, usecs_to_jiffies(timeout)) == -ETIME) { + if (timeout) + pr_warn("spk_ttyio: timeout (%d) while waiting for input\n", + timeout); + return 0xff; + } + + rv = ldisc_data->buf; + /* Make sure we have read buf before we set buf_free to let + * the producer overwrite it */ + mb(); + ldisc_data->buf_free = true; + /* Let TTY push more characters */ + tty_schedule_flip(speakup_tty->port); + + return rv; +} + +static unsigned char spk_ttyio_in(void) +{ + return ttyio_in(SPK_SYNTH_TIMEOUT); +} + +static unsigned char spk_ttyio_in_nowait(void) +{ + u8 rv = ttyio_in(0); + + return (rv == 0xff) ? 0 : rv; +} + +static void spk_ttyio_flush_buffer(void) +{ + if (speakup_tty->ops->flush_buffer) + speakup_tty->ops->flush_buffer(speakup_tty); +} + +int spk_ttyio_synth_probe(struct spk_synth *synth) +{ + int rv = spk_ttyio_initialise_ldisc(synth); + + if (rv) + return rv; + + synth->alive = 1; + spk_ttyio_synth = synth; + + return 0; +} +EXPORT_SYMBOL_GPL(spk_ttyio_synth_probe); + +void spk_ttyio_release(void) +{ + if (!speakup_tty) + return; + + tty_lock(speakup_tty); + + if (speakup_tty->ops->close) + speakup_tty->ops->close(speakup_tty, NULL); + + tty_ldisc_flush(speakup_tty); + tty_unlock(speakup_tty); + tty_ldisc_release(speakup_tty); +} +EXPORT_SYMBOL_GPL(spk_ttyio_release); + +const char *spk_ttyio_synth_immediate(struct spk_synth *synth, const char *buff) +{ + u_char ch; + + while ((ch = *buff)) { + if (ch == '\n') + ch = synth->procspeech; + if (tty_write_room(speakup_tty) < 1 || !synth->io_ops->synth_out(synth, ch)) + return buff; + buff++; + } + return NULL; +} +EXPORT_SYMBOL_GPL(spk_ttyio_synth_immediate); diff --git a/drivers/staging/speakup/spk_types.h b/drivers/staging/speakup/spk_types.h index c156975392c8..22f657d45e46 100644 --- a/drivers/staging/speakup/spk_types.h +++ b/drivers/staging/speakup/spk_types.h @@ -152,6 +152,9 @@ struct spk_io_ops { int (*synth_out)(struct spk_synth *synth, const char ch); void (*send_xchar)(char ch); void (*tiocmset)(unsigned int set, unsigned int clear); + unsigned char (*synth_in)(void); + unsigned char (*synth_in_nowait)(void); + void (*flush_buffer)(void); }; struct spk_synth { @@ -166,6 +169,7 @@ struct spk_synth { int jiffies; int full; int ser; + char *dev_name; short flags; short startup; const int checkval; /* for validating a proper synth module */ @@ -182,7 +186,7 @@ struct spk_synth { int (*is_alive)(struct spk_synth *synth); int (*synth_adjust)(struct st_var_header *var); void (*read_buff_add)(u_char); - unsigned char (*get_index)(void); + unsigned char (*get_index)(struct spk_synth *synth); struct synth_indexing indexing; int alive; struct attribute_group attributes; diff --git a/drivers/staging/speakup/synth.c b/drivers/staging/speakup/synth.c index 352e9eebc3de..a1ca68c76579 100644 --- a/drivers/staging/speakup/synth.c +++ b/drivers/staging/speakup/synth.c @@ -120,10 +120,17 @@ EXPORT_SYMBOL_GPL(spk_do_catch_up); void spk_synth_flush(struct spk_synth *synth) { + synth->io_ops->flush_buffer(); synth->io_ops->synth_out(synth, synth->clear); } EXPORT_SYMBOL_GPL(spk_synth_flush); +unsigned char spk_synth_get_index(struct spk_synth *synth) +{ + return synth->io_ops->synth_in_nowait(); +} +EXPORT_SYMBOL_GPL(spk_synth_get_index); + int spk_synth_is_alive_nop(struct spk_synth *synth) { synth->alive = 1; @@ -249,7 +256,7 @@ void spk_reset_index_count(int sc) if (first) first = 0; else - synth->get_index(); + synth->get_index(synth); index_count = 0; sentence_count = sc; } @@ -282,7 +289,7 @@ void synth_insert_next_index(int sent_num) void spk_get_index_count(int *linecount, int *sentcount) { - int ind = synth->get_index(); + int ind = synth->get_index(synth); if (ind) { sentence_count = ind % 10; @@ -438,10 +445,15 @@ int synth_add(struct spk_synth *in_synth) mutex_unlock(&spk_mutex); return -1; } - synths[i++] = in_synth; - synths[i] = NULL; + if (in_synth->startup) status = do_synth_init(in_synth); + + if (!status) { + synths[i++] = in_synth; + synths[i] = NULL; + } + mutex_unlock(&spk_mutex); return status; } diff --git a/drivers/staging/typec/fusb302/fusb302.c b/drivers/staging/typec/fusb302/fusb302.c index 4a356e509fe4..03a3809d18f0 100644 --- a/drivers/staging/typec/fusb302/fusb302.c +++ b/drivers/staging/typec/fusb302/fusb302.c @@ -1039,8 +1039,8 @@ static int fusb302_pd_send_message(struct fusb302_chip *chip, } /* packsym tells the FUSB302 chip that the next X bytes are payload */ buf[pos++] = FUSB302_TKN_PACKSYM | (len & 0x1F); - buf[pos++] = msg->header & 0xFF; - buf[pos++] = (msg->header >> 8) & 0xFF; + memcpy(&buf[pos], &msg->header, sizeof(msg->header)); + pos += sizeof(msg->header); len -= 2; memcpy(&buf[pos], msg->payload, len); diff --git a/drivers/staging/unisys/Documentation/overview.txt b/drivers/staging/unisys/Documentation/overview.txt index 1146c1cf5c2a..e0466bfada2f 100644 --- a/drivers/staging/unisys/Documentation/overview.txt +++ b/drivers/staging/unisys/Documentation/overview.txt @@ -221,7 +221,7 @@ The following files exist under /sys/devices/visorbus<x>/vbus<x>:dev<y>: The visorhba driver registers with visorbus as the function driver to handle virtual scsi disk devices, specified using the -SPAR_VHBA_CHANNEL_PROTOCOL_UUID type in the visorbus_register_visor_driver() +VISOR_VHBA_CHANNEL_UUID type in the visorbus_register_visor_driver() call. visorhba uses scsi_add_host() to expose a Linux block device (e.g., /sys/block/) in the guest environment for each s-Par virtual device. @@ -240,7 +240,7 @@ When compiled as a module, visorhba can be autoloaded by visorbus in standard udev/systemd environments, as it includes the modules.alias definition: - "visorbus:"+SPAR_VHBA_CHANNEL_PROTOCOL_UUID_STR + "visorbus:"+VISOR_VHBA_CHANNEL_UUID_STR i.e.: @@ -252,7 +252,7 @@ i.e.: The visornic driver registers with visorbus as the function driver to handle virtual network devices, specified using the -SPAR_VNIC_CHANNEL_PROTOCOL_UUID type in the visorbus_register_visor_driver() +VISOR_VNIC_CHANNEL_UUID type in the visorbus_register_visor_driver() call. visornic uses register_netdev() to expose a Linux device of class net (e.g., /sys/class/net/) in the guest environment for each s-Par virtual device. @@ -270,7 +270,7 @@ When compiled as a module, visornic can be autoloaded by visorbus in standard udev/systemd environments, as it includes the modules.alias definition: - "visorbus:"+SPAR_VNIC_CHANNEL_PROTOCOL_UUID_STR + "visorbus:"+VISOR_VNIC_CHANNEL_UUID_STR i.e.: @@ -282,7 +282,7 @@ i.e.: The visorinput driver registers with visorbus as the function driver to handle human input devices, specified using the -SPAR_KEYBOARD_CHANNEL_PROTOCOL_UUID and SPAR_MOUSE_CHANNEL_PROTOCOL_UUID +VISOR_KEYBOARD_CHANNEL_UUID and VISOR_MOUSE_CHANNEL_UUID types in the visorbus_register_visor_driver() call. visorinput uses input_register_device() to expose devices of class input (e.g., /sys/class/input/) for virtual keyboard and virtual mouse devices. @@ -307,8 +307,8 @@ When compiled as a module, visorinput can be autoloaded by visorbus in standard udev/systemd environments, as it includes the modules.alias definition: - "visorbus:"+SPAR_MOUSE_CHANNEL_PROTOCOL_UUID_STR - "visorbus:"+SPAR_KEYBOARD_CHANNEL_PROTOCOL_UUID_STR + "visorbus:"+VISOR_MOUSE_CHANNEL_UUID_STR + "visorbus:"+VISOR_KEYBOARD_CHANNEL_UUID_STR i.e.: diff --git a/drivers/staging/unisys/include/channel.h b/drivers/staging/unisys/include/channel.h index 057421eeb1ae..692efcb38245 100644 --- a/drivers/staging/unisys/include/channel.h +++ b/drivers/staging/unisys/include/channel.h @@ -32,7 +32,7 @@ #define COVER(v, d) ((d) * DIV_ROUND_UP(v, d)) #endif -#define ULTRA_CHANNEL_PROTOCOL_SIGNATURE SIGNATURE_32('E', 'C', 'N', 'L') +#define VISOR_CHANNEL_SIGNATURE SIGNATURE_32('E', 'C', 'N', 'L') enum channel_serverstate { CHANNELSRV_UNINITIALIZED = 0, /* channel is in an undefined state */ @@ -59,10 +59,10 @@ enum channel_clientstate { /* access channel anytime */ }; -#define SPAR_CHANNEL_SERVER_READY(ch) \ +#define VISOR_CHANNEL_SERVER_READY(ch) \ (readl(&(ch)->srv_state) == CHANNELSRV_READY) -#define ULTRA_VALID_CHANNELCLI_TRANSITION(o, n) \ +#define VISOR_VALID_CHANNELCLI_TRANSITION(o, n) \ (((((o) == CHANNELCLI_DETACHED) && ((n) == CHANNELCLI_DISABLED)) || \ (((o) == CHANNELCLI_ATTACHING) && ((n) == CHANNELCLI_DISABLED)) || \ (((o) == CHANNELCLI_ATTACHED) && ((n) == CHANNELCLI_DISABLED)) || \ @@ -80,33 +80,33 @@ enum channel_clientstate { (((o) == CHANNELCLI_BUSY) && ((n) == CHANNELCLI_OWNED)) || (0)) \ ? (1) : (0)) -/* Values for ULTRA_CHANNEL_PROTOCOL.CliErrorBoot: */ +/* Values for VISORA_CHANNEL_PROTOCOL.CliErrorBoot: */ /* throttling invalid boot channel statetransition error due to client * disabled */ -#define ULTRA_CLIERRORBOOT_THROTTLEMSG_DISABLED 0x01 +#define VISOR_CLIERRORBOOT_THROTTLEMSG_DISABLED 0x01 /* throttling invalid boot channel statetransition error due to client * not attached */ -#define ULTRA_CLIERRORBOOT_THROTTLEMSG_NOTATTACHED 0x02 +#define VISOR_CLIERRORBOOT_THROTTLEMSG_NOTATTACHED 0x02 /* throttling invalid boot channel statetransition error due to busy channel */ -#define ULTRA_CLIERRORBOOT_THROTTLEMSG_BUSY 0x04 +#define VISOR_CLIERRORBOOT_THROTTLEMSG_BUSY 0x04 -/* Values for ULTRA_CHANNEL_PROTOCOL.Features: This define exists so +/* Values for VISOR_CHANNEL_PROTOCOL.Features: This define exists so * that windows guest can look at the FeatureFlags in the io channel, * and configure the windows driver to use interrupts or not based on * this setting. This flag is set in uislib after the - * ULTRA_VHBA_init_channel is called. All feature bits for all + * VISOR_VHBA_init_channel is called. All feature bits for all * channels should be defined here. The io channel feature bits are * defined right here */ -#define ULTRA_IO_DRIVER_ENABLES_INTS (0x1ULL << 1) -#define ULTRA_IO_CHANNEL_IS_POLLING (0x1ULL << 3) -#define ULTRA_IO_IOVM_IS_OK_WITH_DRIVER_DISABLING_INTS (0x1ULL << 4) -#define ULTRA_IO_DRIVER_DISABLES_INTS (0x1ULL << 5) -#define ULTRA_IO_DRIVER_SUPPORTS_ENHANCED_RCVBUF_CHECKING (0x1ULL << 6) +#define VISOR_DRIVER_ENABLES_INTS (0x1ULL << 1) +#define VISOR_CHANNEL_IS_POLLING (0x1ULL << 3) +#define VISOR_IOVM_OK_DRIVER_DISABLING_INTS (0x1ULL << 4) +#define VISOR_DRIVER_DISABLES_INTS (0x1ULL << 5) +#define VISOR_DRIVER_ENHANCED_RCVBUF_CHECKING (0x1ULL << 6) /* Common Channel Header */ struct channel_header { @@ -156,7 +156,7 @@ struct channel_header { u8 recover_channel; } __packed; -#define ULTRA_CHANNEL_ENABLE_INTS (0x1ULL << 0) +#define VISOR_CHANNEL_ENABLE_INTS (0x1ULL << 0) /* Subheader for the Signal Type variation of the Common Channel */ struct signal_queue_header { @@ -204,12 +204,12 @@ struct signal_queue_header { * is used to pass the EFI_DIAG_CAPTURE_PROTOCOL needed to log messages. */ static inline int -spar_check_channel(struct channel_header *ch, - uuid_le expected_uuid, - char *chname, - u64 expected_min_bytes, - u32 expected_version, - u64 expected_signature) +visor_check_channel(struct channel_header *ch, + uuid_le expected_uuid, + char *chname, + u64 expected_min_bytes, + u32 expected_version, + u64 expected_signature) { if (uuid_le_cmp(expected_uuid, NULL_UUID_LE) != 0) { /* caller wants us to verify type GUID */ @@ -254,27 +254,25 @@ spar_check_channel(struct channel_header *ch, */ /* {414815ed-c58c-11da-95a9-00e08161165f} */ -#define SPAR_VHBA_CHANNEL_PROTOCOL_UUID \ +#define VISOR_VHBA_CHANNEL_UUID \ UUID_LE(0x414815ed, 0xc58c, 0x11da, \ 0x95, 0xa9, 0x0, 0xe0, 0x81, 0x61, 0x16, 0x5f) -static const uuid_le spar_vhba_channel_protocol_uuid = - SPAR_VHBA_CHANNEL_PROTOCOL_UUID; -#define SPAR_VHBA_CHANNEL_PROTOCOL_UUID_STR \ +static const uuid_le visor_vhba_channel_uuid = VISOR_VHBA_CHANNEL_UUID; +#define VISOR_VHBA_CHANNEL_UUID_STR \ "414815ed-c58c-11da-95a9-00e08161165f" /* {8cd5994d-c58e-11da-95a9-00e08161165f} */ -#define SPAR_VNIC_CHANNEL_PROTOCOL_UUID \ +#define VISOR_VNIC_CHANNEL_UUID \ UUID_LE(0x8cd5994d, 0xc58e, 0x11da, \ 0x95, 0xa9, 0x0, 0xe0, 0x81, 0x61, 0x16, 0x5f) -static const uuid_le spar_vnic_channel_protocol_uuid = - SPAR_VNIC_CHANNEL_PROTOCOL_UUID; -#define SPAR_VNIC_CHANNEL_PROTOCOL_UUID_STR \ +static const uuid_le visor_vnic_channel_uuid = VISOR_VNIC_CHANNEL_UUID; +#define VISOR_VNIC_CHANNEL_UUID_STR \ "8cd5994d-c58e-11da-95a9-00e08161165f" /* {72120008-4AAB-11DC-8530-444553544200} */ -#define SPAR_SIOVM_UUID \ +#define VISOR_SIOVM_UUID \ UUID_LE(0x72120008, 0x4AAB, 0x11DC, \ 0x85, 0x30, 0x44, 0x45, 0x53, 0x54, 0x42, 0x00) -static const uuid_le spar_siovm_uuid = SPAR_SIOVM_UUID; +static const uuid_le visor_siovm_uuid = VISOR_SIOVM_UUID; #endif diff --git a/drivers/staging/unisys/include/iochannel.h b/drivers/staging/unisys/include/iochannel.h index 9bde848a321c..c7cb3fbde7b2 100644 --- a/drivers/staging/unisys/include/iochannel.h +++ b/drivers/staging/unisys/include/iochannel.h @@ -34,10 +34,9 @@ #include <linux/dma-direction.h> #include "channel.h" -#define ULTRA_VHBA_CHANNEL_PROTOCOL_SIGNATURE ULTRA_CHANNEL_PROTOCOL_SIGNATURE -#define ULTRA_VNIC_CHANNEL_PROTOCOL_SIGNATURE ULTRA_CHANNEL_PROTOCOL_SIGNATURE -#define ULTRA_VSWITCH_CHANNEL_PROTOCOL_SIGNATURE \ - ULTRA_CHANNEL_PROTOCOL_SIGNATURE +#define VISOR_VHBA_CHANNEL_SIGNATURE VISOR_CHANNEL_SIGNATURE +#define VISOR_VNIC_CHANNEL_SIGNATURE VISOR_CHANNEL_SIGNATURE +#define VISOR_VSWITCH_CHANNEL_SIGNATURE VISOR_CHANNEL_SIGNATURE /* * Must increment these whenever you insert or delete fields within this channel @@ -46,21 +45,21 @@ * usually add fields to the END of the channel struct without needing to * increment this. */ -#define ULTRA_VHBA_CHANNEL_PROTOCOL_VERSIONID 2 -#define ULTRA_VNIC_CHANNEL_PROTOCOL_VERSIONID 2 -#define ULTRA_VSWITCH_CHANNEL_PROTOCOL_VERSIONID 1 - -#define SPAR_VHBA_CHANNEL_OK_CLIENT(ch) \ - (spar_check_channel(ch, spar_vhba_channel_protocol_uuid, \ - "vhba", MIN_IO_CHANNEL_SIZE, \ - ULTRA_VHBA_CHANNEL_PROTOCOL_VERSIONID, \ - ULTRA_VHBA_CHANNEL_PROTOCOL_SIGNATURE)) - -#define SPAR_VNIC_CHANNEL_OK_CLIENT(ch) \ - (spar_check_channel(ch, spar_vnic_channel_protocol_uuid, \ - "vnic", MIN_IO_CHANNEL_SIZE, \ - ULTRA_VNIC_CHANNEL_PROTOCOL_VERSIONID, \ - ULTRA_VNIC_CHANNEL_PROTOCOL_SIGNATURE)) +#define VISOR_VHBA_CHANNEL_VERSIONID 2 +#define VISOR_VNIC_CHANNEL_VERSIONID 2 +#define VISOR_VSWITCH_CHANNEL_VERSIONID 1 + +#define VISOR_VHBA_CHANNEL_OK_CLIENT(ch) \ + (visor_check_channel(ch, visor_vhba_channel_uuid, \ + "vhba", MIN_IO_CHANNEL_SIZE, \ + VISOR_VHBA_CHANNEL_VERSIONID, \ + VISOR_VHBA_CHANNEL_SIGNATURE)) + +#define VISOR_VNIC_CHANNEL_OK_CLIENT(ch) \ + (visor_check_channel(ch, visor_vnic_channel_uuid, \ + "vnic", MIN_IO_CHANNEL_SIZE, \ + VISOR_VNIC_CHANNEL_VERSIONID, \ + VISOR_VNIC_CHANNEL_SIGNATURE)) /* * Everything necessary to handle SCSI & NIC traffic between Guest Partition and @@ -530,7 +529,7 @@ struct iochannel_vnic { * this header there is a large region of memory which contains the command and * response queues as specified in cmd_q and rsp_q SIGNAL_QUEUE_HEADERS. */ -struct spar_io_channel_protocol { +struct visor_io_channel { struct channel_header channel_header; struct signal_queue_header cmd_q; struct signal_queue_header rsp_q; diff --git a/drivers/staging/unisys/visorbus/controlvmchannel.h b/drivers/staging/unisys/visorbus/controlvmchannel.h index 274f72422166..ed045eff0e33 100644 --- a/drivers/staging/unisys/visorbus/controlvmchannel.h +++ b/drivers/staging/unisys/visorbus/controlvmchannel.h @@ -19,12 +19,11 @@ #include "channel.h" /* {2B3C2D10-7EF5-4ad8-B966-3448B7386B3D} */ -#define SPAR_CONTROLVM_CHANNEL_PROTOCOL_UUID \ +#define VISOR_CONTROLVM_CHANNEL_UUID \ UUID_LE(0x2b3c2d10, 0x7ef5, 0x4ad8, \ 0xb9, 0x66, 0x34, 0x48, 0xb7, 0x38, 0x6b, 0x3d) -#define ULTRA_CONTROLVM_CHANNEL_PROTOCOL_SIGNATURE \ - ULTRA_CHANNEL_PROTOCOL_SIGNATURE +#define VISOR_CONTROLVM_CHANNEL_SIGNATURE VISOR_CHANNEL_SIGNATURE #define CONTROLVM_MESSAGE_MAX 64 /* Must increment this whenever you insert or delete fields within @@ -33,15 +32,15 @@ * software. Note that you can usually add fields to the END of the * channel struct withOUT needing to increment this. */ -#define ULTRA_CONTROLVM_CHANNEL_PROTOCOL_VERSIONID 1 +#define VISOR_CONTROLVM_CHANNEL_VERSIONID 1 -#define SPAR_CONTROLVM_CHANNEL_OK_CLIENT(ch) \ - (spar_check_channel(ch, \ - SPAR_CONTROLVM_CHANNEL_PROTOCOL_UUID, \ - "controlvm", \ - sizeof(struct spar_controlvm_channel_protocol), \ - ULTRA_CONTROLVM_CHANNEL_PROTOCOL_VERSIONID, \ - ULTRA_CONTROLVM_CHANNEL_PROTOCOL_SIGNATURE)) +#define VISOR_CONTROLVM_CHANNEL_OK_CLIENT(ch) \ + (visor_check_channel(ch, \ + VISOR_CONTROLVM_CHANNEL_UUID, \ + "controlvm", \ + sizeof(struct visor_controlvm_channel), \ + VISOR_CONTROLVM_CHANNEL_VERSIONID, \ + VISOR_CONTROLVM_CHANNEL_SIGNATURE)) /* Defines for various channel queues */ #define CONTROLVM_QUEUE_REQUEST 0 @@ -52,7 +51,7 @@ /* Max num of messages stored during IOVM creation to be reused after crash */ #define CONTROLVM_CRASHMSG_MAX 2 -struct spar_segment_state { +struct visor_segment_state { /* Bit 0: May enter other states */ u16 enabled:1; /* Bit 1: Assigned to active partition */ @@ -76,15 +75,15 @@ struct spar_segment_state { */ } __packed; -static const struct spar_segment_state segment_state_running = { +static const struct visor_segment_state segment_state_running = { 1, 1, 1, 0, 1, 1, 1, 1 }; -static const struct spar_segment_state segment_state_paused = { +static const struct visor_segment_state segment_state_paused = { 1, 1, 1, 0, 1, 1, 1, 0 }; -static const struct spar_segment_state segment_state_standby = { +static const struct visor_segment_state segment_state_standby = { 1, 1, 0, 0, 1, 1, 1, 0 }; @@ -149,7 +148,7 @@ struct irq_info { u8 reserved[3]; /* Natural alignment purposes */ } __packed; -struct efi_spar_indication { +struct efi_visor_indication { u64 boot_to_fw_ui:1; /* Bit 0: Stop in uefi ui */ u64 clear_nvram:1; /* Bit 1: Clear NVRAM */ u64 clear_cmos:1; /* Bit 2: Clear CMOS */ @@ -158,9 +157,9 @@ struct efi_spar_indication { u64 reserved:60; /* Natural alignment */ } __packed; -enum ultra_chipset_feature { - ULTRA_CHIPSET_FEATURE_REPLY = 0x00000001, - ULTRA_CHIPSET_FEATURE_PARA_HOTPLUG = 0x00000002, +enum visor_chipset_feature { + VISOR_CHIPSET_FEATURE_REPLY = 0x00000001, + VISOR_CHIPSET_FEATURE_PARA_HOTPLUG = 0x00000002, }; /* This is the common structure that is at the beginning of every @@ -298,13 +297,13 @@ struct controlvm_message_packet { /* for CONTROLVM_DEVICE_RECONFIGURE */ struct { u32 bus_no; - struct spar_segment_state state; + struct visor_segment_state state; u8 reserved[2]; /* Natural alignment purposes */ } __packed bus_change_state; /* for CONTROLVM_BUS_CHANGESTATE */ struct { u32 bus_no; u32 dev_no; - struct spar_segment_state state; + struct visor_segment_state state; struct { /* =1 if message is for a physical device */ u32 phys_device:1; @@ -317,7 +316,7 @@ struct controlvm_message_packet { struct { u32 bus_no; u32 dev_no; - struct spar_segment_state state; + struct visor_segment_state state; u8 reserved[6]; /* Natural alignment purposes */ } __packed device_change_state_event; /* for CONTROLVM_DEVICE_CHANGESTATE_EVENT */ @@ -326,7 +325,7 @@ struct controlvm_message_packet { u32 bus_count; /* indicates the max number of switches */ u32 switch_count; - enum ultra_chipset_feature features; + enum visor_chipset_feature features; u32 platform_number; /* Platform Number */ } __packed init_chipset; /* for CONTROLVM_CHIPSET_INIT */ struct { @@ -349,7 +348,7 @@ struct controlvm_message { struct controlvm_message_packet cmd; } __packed; -struct spar_controlvm_channel_protocol { +struct visor_controlvm_channel { struct channel_header header; u64 gp_controlvm; /* guest phys addr of this channel */ u64 gp_partition_tables;/* guest phys addr of partition tables */ @@ -371,7 +370,7 @@ struct spar_controlvm_channel_protocol { u32 message_count; /* CONTROLVM_MESSAGE_MAX */ u64 gp_smbios_table; /* guest phys addr of SMBIOS tables */ u64 gp_physical_smbios_table; /* guest phys addr of SMBIOS table */ - /* ULTRA_MAX_GUESTS_PER_SERVICE */ + /* VISOR_MAX_GUESTS_PER_SERVICE */ char gp_reserved[2688]; /* guest physical address of EFI firmware image base */ @@ -402,11 +401,10 @@ struct spar_controlvm_channel_protocol { u32 installation_text_id; /* Id of string to display */ /* Number of remaining installation steps (for progress bars) */ u16 installation_remaining_steps; - /* ULTRA_TOOL_ACTIONS Installation Action field */ + /* VISOR_TOOL_ACTIONS Installation Action field */ u8 tool_action; u8 reserved; /* alignment */ - struct efi_spar_indication efi_spar_ind; - struct efi_spar_indication efi_spar_ind_supported; + struct efi_visor_indication efi_visor_ind; u32 sp_reserved; /* Force signals to begin on 128-byte cache line */ u8 reserved2[28]; @@ -444,7 +442,7 @@ struct spar_controlvm_channel_protocol { * of total_length should equal PayloadBytes. The format of the strings at * PayloadVmOffset will take different forms depending on the message. */ -struct spar_controlvm_parameters_header { +struct visor_controlvm_parameters_header { u32 total_length; u32 header_length; u32 connection_offset; diff --git a/drivers/staging/unisys/visorbus/vbuschannel.h b/drivers/staging/unisys/visorbus/vbuschannel.h index f0ef5ecf3d7d..01d7d517dba7 100644 --- a/drivers/staging/unisys/visorbus/vbuschannel.h +++ b/drivers/staging/unisys/visorbus/vbuschannel.h @@ -27,13 +27,12 @@ #include "channel.h" /* {193b331b-c58f-11da-95a9-00e08161165f} */ -#define SPAR_VBUS_CHANNEL_PROTOCOL_UUID \ +#define VISOR_VBUS_CHANNEL_UUID \ UUID_LE(0x193b331b, 0xc58f, 0x11da, \ 0x95, 0xa9, 0x0, 0xe0, 0x81, 0x61, 0x16, 0x5f) -static const uuid_le spar_vbus_channel_protocol_uuid = - SPAR_VBUS_CHANNEL_PROTOCOL_UUID; +static const uuid_le visor_vbus_channel_uuid = VISOR_VBUS_CHANNEL_UUID; -#define SPAR_VBUS_CHANNEL_PROTOCOL_SIGNATURE ULTRA_CHANNEL_PROTOCOL_SIGNATURE +#define VISOR_VBUS_CHANNEL_SIGNATURE VISOR_CHANNEL_SIGNATURE /* Must increment this whenever you insert or delete fields within this channel * struct. Also increment whenever you change the meaning of fields within this @@ -41,7 +40,7 @@ static const uuid_le spar_vbus_channel_protocol_uuid = * usually add fields to the END of the channel struct withOUT needing to * increment this. */ -#define SPAR_VBUS_CHANNEL_PROTOCOL_VERSIONID 1 +#define VISOR_VBUS_CHANNEL_VERSIONID 1 /* * An array of this struct is present in the channel area for each vbus. @@ -49,16 +48,16 @@ static const uuid_le spar_vbus_channel_protocol_uuid = * It is filled in by the client side to provide info about the device * and driver from the client's perspective. */ -struct ultra_vbus_deviceinfo { +struct visor_vbus_deviceinfo { u8 devtype[16]; /* short string identifying the device type */ u8 drvname[16]; /* driver .sys file name */ u8 infostrs[96]; /* kernel version */ u8 reserved[128]; /* pad size to 256 bytes */ } __packed; -struct spar_vbus_headerinfo { +struct visor_vbus_headerinfo { u32 struct_bytes; /* size of this struct in bytes */ - u32 device_info_struct_bytes; /* sizeof(ULTRA_VBUS_DEVICEINFO) */ + u32 device_info_struct_bytes; /* sizeof(VISOR_VBUS_DEVICEINFO) */ u32 dev_info_count; /* num of items in DevInfo member */ /* (this is the allocated size) */ u32 chp_info_offset; /* byte offset from beginning of this struct */ @@ -70,15 +69,15 @@ struct spar_vbus_headerinfo { u8 reserved[104]; } __packed; -struct spar_vbus_channel_protocol { +struct visor_vbus_channel { struct channel_header channel_header; /* initialized by server */ - struct spar_vbus_headerinfo hdr_info; /* initialized by server */ + struct visor_vbus_headerinfo hdr_info; /* initialized by server */ /* the remainder of this channel is filled in by the client */ - struct ultra_vbus_deviceinfo chp_info; + struct visor_vbus_deviceinfo chp_info; /* describes client chipset device and driver */ - struct ultra_vbus_deviceinfo bus_info; + struct visor_vbus_deviceinfo bus_info; /* describes client bus device and driver */ - struct ultra_vbus_deviceinfo dev_info[0]; + struct visor_vbus_deviceinfo dev_info[0]; /* describes client device and driver for each device on the bus */ } __packed; diff --git a/drivers/staging/unisys/visorbus/visorbus_main.c b/drivers/staging/unisys/visorbus/visorbus_main.c index a692561c81c8..1c785dd19ddd 100644 --- a/drivers/staging/unisys/visorbus/visorbus_main.c +++ b/drivers/staging/unisys/visorbus/visorbus_main.c @@ -64,9 +64,9 @@ static const struct attribute_group *visorbus_dev_groups[] = { }; /* filled in with info about parent chipset driver when we register with it */ -static struct ultra_vbus_deviceinfo chipset_driverinfo; +static struct visor_vbus_deviceinfo chipset_driverinfo; /* filled in with info about this driver, wrt it servicing client busses */ -static struct ultra_vbus_deviceinfo clientbus_driverinfo; +static struct visor_vbus_deviceinfo clientbus_driverinfo; /* list of visor_device structs, linked via .list_all */ static LIST_HEAD(list_all_bus_instances); @@ -356,9 +356,9 @@ static const struct attribute_group *visorbus_groups[] = { * /sys/kernel/debug/visorbus/visorbus<n>. */ /* - * vbuschannel_print_devinfo() - format a struct ultra_vbus_deviceinfo + * vbuschannel_print_devinfo() - format a struct visor_vbus_deviceinfo * and write it to a seq_file - * @devinfo: the struct ultra_vbus_deviceinfo to format + * @devinfo: the struct visor_vbus_deviceinfo to format * @seq: seq_file to write to * @devix: the device index to be included in the output data, or -1 if no * device index is to be included @@ -366,7 +366,7 @@ static const struct attribute_group *visorbus_groups[] = { * Reads @devInfo, and writes it in human-readable notation to @seq. */ static void -vbuschannel_print_devinfo(struct ultra_vbus_deviceinfo *devinfo, +vbuschannel_print_devinfo(struct visor_vbus_deviceinfo *devinfo, struct seq_file *seq, int devix) { if (!isprint(devinfo->devtype[0])) @@ -397,7 +397,7 @@ static int client_bus_info_debugfs_show(struct seq_file *seq, void *v) int i; unsigned long off; - struct ultra_vbus_deviceinfo dev_info; + struct visor_vbus_deviceinfo dev_info; if (!channel) return 0; @@ -407,16 +407,14 @@ static int client_bus_info_debugfs_show(struct seq_file *seq, void *v) ((vdev->name) ? (char *)(vdev->name) : ""), vdev->chipset_bus_no); if (visorchannel_read(channel, - offsetof(struct spar_vbus_channel_protocol, - chp_info), + offsetof(struct visor_vbus_channel, chp_info), &dev_info, sizeof(dev_info)) >= 0) vbuschannel_print_devinfo(&dev_info, seq, -1); if (visorchannel_read(channel, - offsetof(struct spar_vbus_channel_protocol, - bus_info), + offsetof(struct visor_vbus_channel, bus_info), &dev_info, sizeof(dev_info)) >= 0) vbuschannel_print_devinfo(&dev_info, seq, -1); - off = offsetof(struct spar_vbus_channel_protocol, dev_info); + off = offsetof(struct visor_vbus_channel, dev_info); i = 0; while (off + sizeof(dev_info) <= visorchannel_get_nbytes(channel)) { if (visorchannel_read(channel, off, &dev_info, @@ -684,16 +682,16 @@ remove_visor_device(struct visor_device *dev) static int get_vbus_header_info(struct visorchannel *chan, - struct spar_vbus_headerinfo *hdr_info) + struct visor_vbus_headerinfo *hdr_info) { int err; - if (!spar_check_channel(visorchannel_get_header(chan), - spar_vbus_channel_protocol_uuid, - "vbus", - sizeof(struct spar_vbus_channel_protocol), - SPAR_VBUS_CHANNEL_PROTOCOL_VERSIONID, - SPAR_VBUS_CHANNEL_PROTOCOL_SIGNATURE)) + if (!visor_check_channel(visorchannel_get_header(chan), + visor_vbus_channel_uuid, + "vbus", + sizeof(struct visor_vbus_channel), + VISOR_VBUS_CHANNEL_VERSIONID, + VISOR_VBUS_CHANNEL_SIGNATURE)) return -EINVAL; err = visorchannel_read(chan, sizeof(struct channel_header), hdr_info, @@ -701,11 +699,11 @@ get_vbus_header_info(struct visorchannel *chan, if (err < 0) return err; - if (hdr_info->struct_bytes < sizeof(struct spar_vbus_headerinfo)) + if (hdr_info->struct_bytes < sizeof(struct visor_vbus_headerinfo)) return -EINVAL; if (hdr_info->device_info_struct_bytes < - sizeof(struct ultra_vbus_deviceinfo)) + sizeof(struct visor_vbus_deviceinfo)) return -EINVAL; return 0; @@ -713,7 +711,7 @@ get_vbus_header_info(struct visorchannel *chan, /* * write_vbus_chp_info() - write the contents of <info> to the struct - * spar_vbus_channel_protocol.chp_info + * visor_vbus_channel.chp_info * @chan: indentifies the s-Par channel that will be updated * @hdr_info: used to find appropriate channel offset to write data * @info: contains the information to write @@ -726,8 +724,8 @@ get_vbus_header_info(struct visorchannel *chan, */ static void write_vbus_chp_info(struct visorchannel *chan, - struct spar_vbus_headerinfo *hdr_info, - struct ultra_vbus_deviceinfo *info) + struct visor_vbus_headerinfo *hdr_info, + struct visor_vbus_deviceinfo *info) { int off = sizeof(struct channel_header) + hdr_info->chp_info_offset; @@ -739,7 +737,7 @@ write_vbus_chp_info(struct visorchannel *chan, /* * write_vbus_bus_info() - write the contents of <info> to the struct - * spar_vbus_channel_protocol.bus_info + * visor_vbus_channel.bus_info * @chan: indentifies the s-Par channel that will be updated * @hdr_info: used to find appropriate channel offset to write data * @info: contains the information to write @@ -752,8 +750,8 @@ write_vbus_chp_info(struct visorchannel *chan, */ static void write_vbus_bus_info(struct visorchannel *chan, - struct spar_vbus_headerinfo *hdr_info, - struct ultra_vbus_deviceinfo *info) + struct visor_vbus_headerinfo *hdr_info, + struct visor_vbus_deviceinfo *info) { int off = sizeof(struct channel_header) + hdr_info->bus_info_offset; @@ -765,7 +763,7 @@ write_vbus_bus_info(struct visorchannel *chan, /* * write_vbus_dev_info() - write the contents of <info> to the struct - * spar_vbus_channel_protocol.dev_info[<devix>] + * visor_vbus_channel.dev_info[<devix>] * @chan: indentifies the s-Par channel that will be updated * @hdr_info: used to find appropriate channel offset to write data * @info: contains the information to write @@ -779,8 +777,8 @@ write_vbus_bus_info(struct visorchannel *chan, */ static void write_vbus_dev_info(struct visorchannel *chan, - struct spar_vbus_headerinfo *hdr_info, - struct ultra_vbus_deviceinfo *info, unsigned int devix) + struct visor_vbus_headerinfo *hdr_info, + struct visor_vbus_deviceinfo *info, unsigned int devix) { int off = (sizeof(struct channel_header) + hdr_info->dev_info_offset) + @@ -793,10 +791,10 @@ write_vbus_dev_info(struct visorchannel *chan, } static void bus_device_info_init( - struct ultra_vbus_deviceinfo *bus_device_info_ptr, + struct visor_vbus_deviceinfo *bus_device_info_ptr, const char *dev_type, const char *drv_name) { - memset(bus_device_info_ptr, 0, sizeof(struct ultra_vbus_deviceinfo)); + memset(bus_device_info_ptr, 0, sizeof(struct visor_vbus_deviceinfo)); snprintf(bus_device_info_ptr->devtype, sizeof(bus_device_info_ptr->devtype), "%s", (dev_type) ? dev_type : "unknownType"); @@ -823,9 +821,9 @@ fix_vbus_dev_info(struct visor_device *visordev) struct visor_driver *visordrv; u32 bus_no = visordev->chipset_bus_no; u32 dev_no = visordev->chipset_dev_no; - struct ultra_vbus_deviceinfo dev_info; + struct visor_vbus_deviceinfo dev_info; const char *chan_type_name = NULL; - struct spar_vbus_headerinfo *hdr_info; + struct visor_vbus_headerinfo *hdr_info; if (!visordev->device.driver) return; @@ -833,7 +831,7 @@ fix_vbus_dev_info(struct visor_device *visordev) bdev = visorbus_get_device_by_id(bus_no, BUS_ROOT_DEVICE, NULL); if (!bdev) return; - hdr_info = (struct spar_vbus_headerinfo *)bdev->vbus_hdr_info; + hdr_info = (struct visor_vbus_headerinfo *)bdev->vbus_hdr_info; if (!hdr_info) return; visordrv = to_visor_driver(visordev->device.driver); @@ -981,18 +979,18 @@ int visorbus_register_visor_driver(struct visor_driver *drv) EXPORT_SYMBOL_GPL(visorbus_register_visor_driver); /* - * create_bus_instance() - create a device instance for the visor bus itself + * visorbus_create_instance() - create a device instance for the visorbus itself * @dev: struct visor_device indicating the bus instance * * Return: 0 for success, otherwise negative errno value indicating reason for * failure */ static int -create_bus_instance(struct visor_device *dev) +visorbus_create_instance(struct visor_device *dev) { int id = dev->chipset_bus_no; int err; - struct spar_vbus_headerinfo *hdr_info; + struct visor_vbus_headerinfo *hdr_info; hdr_info = kzalloc(sizeof(*hdr_info), GFP_KERNEL); if (!hdr_info) @@ -1032,16 +1030,16 @@ create_bus_instance(struct visor_device *dev) err_debugfs_dir: debugfs_remove_recursive(dev->debugfs_dir); kfree(hdr_info); - dev_err(&dev->device, "create_bus_instance failed: %d\n", err); + dev_err(&dev->device, "visorbus_create_instance failed: %d\n", err); return err; } /* - * remove_bus_instance() - remove a device instance for the visor bus itself + * visorbus_remove_instance() - remove a device instance for the visorbus itself * @dev: struct visor_device indentifying the bus to remove */ static void -remove_bus_instance(struct visor_device *dev) +visorbus_remove_instance(struct visor_device *dev) { /* * Note that this will result in the release method for @@ -1061,7 +1059,7 @@ remove_bus_instance(struct visor_device *dev) } /* - * remove_all_visor_devices() - remove all child visor bus device instances + * remove_all_visor_devices() - remove all child visorbus device instances */ static void remove_all_visor_devices(void) @@ -1077,29 +1075,29 @@ remove_all_visor_devices(void) } int -chipset_bus_create(struct visor_device *dev) +visorchipset_bus_create(struct visor_device *dev) { int err; - err = create_bus_instance(dev); + err = visorbus_create_instance(dev); if (err < 0) return err; - bus_create_response(dev, err); + visorbus_create_response(dev, err); return 0; } void -chipset_bus_destroy(struct visor_device *dev) +visorchipset_bus_destroy(struct visor_device *dev) { - remove_bus_instance(dev); - bus_destroy_response(dev, 0); + visorbus_remove_instance(dev); + visorbus_destroy_response(dev, 0); } int -chipset_device_create(struct visor_device *dev_info) +visorchipset_device_create(struct visor_device *dev_info) { int err; @@ -1107,17 +1105,17 @@ chipset_device_create(struct visor_device *dev_info) if (err < 0) return err; - device_create_response(dev_info, err); + visorbus_device_create_response(dev_info, err); return 0; } void -chipset_device_destroy(struct visor_device *dev_info) +visorchipset_device_destroy(struct visor_device *dev_info) { remove_visor_device(dev_info); - device_destroy_response(dev_info, 0); + visorbus_device_destroy_response(dev_info, 0); } /* @@ -1137,7 +1135,7 @@ pause_state_change_complete(struct visor_device *dev, int status) dev->pausing = false; - device_pause_response(dev, status); + visorbus_device_pause_response(dev, status); } /* @@ -1162,12 +1160,12 @@ resume_state_change_complete(struct visor_device *dev, int status) * which will presumably want to send some sort of response to * the initiator. */ - device_resume_response(dev, status); + visorbus_device_resume_response(dev, status); } /* - * initiate_chipset_device_pause_resume() - start a pause or resume operation - * for a visor device + * visorchipset_initiate_device_pause_resume() - start a pause or resume + * operation for a visor device * @dev: struct visor_device identifying the device being paused or resumed * @is_pause: true to indicate pause operation, false to indicate resume * @@ -1177,7 +1175,8 @@ resume_state_change_complete(struct visor_device *dev, int status) * resume_state_change_complete(). */ static int -initiate_chipset_device_pause_resume(struct visor_device *dev, bool is_pause) +visorchipset_initiate_device_pause_resume(struct visor_device *dev, + bool is_pause) { int err; struct visor_driver *drv = NULL; @@ -1211,7 +1210,7 @@ initiate_chipset_device_pause_resume(struct visor_device *dev, bool is_pause) } /** - * chipset_device_pause() - start a pause operation for a visor device + * visorchipset_device_pause() - start a pause operation for a visor device * @dev_info: struct visor_device identifying the device being paused * * Tell the subordinate function driver for a specific device to pause @@ -1219,11 +1218,11 @@ initiate_chipset_device_pause_resume(struct visor_device *dev, bool is_pause) * via a callback function; see pause_state_change_complete(). */ int -chipset_device_pause(struct visor_device *dev_info) +visorchipset_device_pause(struct visor_device *dev_info) { int err; - err = initiate_chipset_device_pause_resume(dev_info, true); + err = visorchipset_initiate_device_pause_resume(dev_info, true); if (err < 0) { dev_info->pausing = false; @@ -1234,7 +1233,7 @@ chipset_device_pause(struct visor_device *dev_info) } /** - * chipset_device_resume() - start a resume operation for a visor device + * visorchipset_device_resume() - start a resume operation for a visor device * @dev_info: struct visor_device identifying the device being resumed * * Tell the subordinate function driver for a specific device to resume @@ -1242,11 +1241,11 @@ chipset_device_pause(struct visor_device *dev_info) * via a callback function; see resume_state_change_complete(). */ int -chipset_device_resume(struct visor_device *dev_info) +visorchipset_device_resume(struct visor_device *dev_info) { int err; - err = initiate_chipset_device_pause_resume(dev_info, false); + err = visorchipset_initiate_device_pause_resume(dev_info, false); if (err < 0) { dev_info->resuming = false; @@ -1289,7 +1288,7 @@ visorbus_exit(void) struct visor_device *dev = list_entry(listentry, struct visor_device, list_all); - remove_bus_instance(dev); + visorbus_remove_instance(dev); } bus_unregister(&visorbus_type); diff --git a/drivers/staging/unisys/visorbus/visorbus_private.h b/drivers/staging/unisys/visorbus/visorbus_private.h index 9f030b1f589f..98a5af19189d 100644 --- a/drivers/staging/unisys/visorbus/visorbus_private.h +++ b/drivers/staging/unisys/visorbus/visorbus_private.h @@ -27,19 +27,19 @@ * command line */ -int chipset_bus_create(struct visor_device *bus_info); -void chipset_bus_destroy(struct visor_device *bus_info); -int chipset_device_create(struct visor_device *dev_info); -void chipset_device_destroy(struct visor_device *dev_info); -int chipset_device_pause(struct visor_device *dev_info); -int chipset_device_resume(struct visor_device *dev_info); +int visorchipset_bus_create(struct visor_device *bus_info); +void visorchipset_bus_destroy(struct visor_device *bus_info); +int visorchipset_device_create(struct visor_device *dev_info); +void visorchipset_device_destroy(struct visor_device *dev_info); +int visorchipset_device_pause(struct visor_device *dev_info); +int visorchipset_device_resume(struct visor_device *dev_info); -void bus_create_response(struct visor_device *p, int response); -void bus_destroy_response(struct visor_device *p, int response); -void device_create_response(struct visor_device *p, int response); -void device_destroy_response(struct visor_device *p, int response); -void device_resume_response(struct visor_device *p, int response); -void device_pause_response(struct visor_device *p, int response); +void visorbus_create_response(struct visor_device *p, int response); +void visorbus_destroy_response(struct visor_device *p, int response); +void visorbus_device_create_response(struct visor_device *p, int response); +void visorbus_device_destroy_response(struct visor_device *p, int response); +void visorbus_device_resume_response(struct visor_device *p, int response); +void visorbus_device_pause_response(struct visor_device *p, int response); int visorbus_init(void); void visorbus_exit(void); diff --git a/drivers/staging/unisys/visorbus/visorchannel.c b/drivers/staging/unisys/visorbus/visorchannel.c index 9e1cea22ce68..6885c2cb7135 100644 --- a/drivers/staging/unisys/visorbus/visorchannel.c +++ b/drivers/staging/unisys/visorbus/visorchannel.c @@ -28,11 +28,11 @@ #define MYDRVNAME "visorchannel" -#define SPAR_CONSOLEVIDEO_CHANNEL_PROTOCOL_GUID \ +#define VISOR_CONSOLEVIDEO_CHANNEL_GUID \ UUID_LE(0x3cd6e705, 0xd6a2, 0x4aa5, \ 0xad, 0x5c, 0x7b, 0x8, 0x88, 0x9d, 0xff, 0xe2) -static const uuid_le spar_video_guid = SPAR_CONSOLEVIDEO_CHANNEL_PROTOCOL_GUID; +static const uuid_le visor_video_guid = VISOR_CONSOLEVIDEO_CHANNEL_GUID; struct visorchannel { u64 physaddr; @@ -415,7 +415,7 @@ visorchannel_create_guts(u64 physaddr, unsigned long channel_bytes, * release later on. */ channel->requested = request_mem_region(physaddr, size, MYDRVNAME); - if (!channel->requested && uuid_le_cmp(guid, spar_video_guid)) + if (!channel->requested && uuid_le_cmp(guid, visor_video_guid)) /* we only care about errors if this is not the video channel */ goto err_destroy_channel; @@ -445,7 +445,7 @@ visorchannel_create_guts(u64 physaddr, unsigned long channel_bytes, channel->mapped = NULL; channel->requested = request_mem_region(channel->physaddr, channel_bytes, MYDRVNAME); - if (!channel->requested && uuid_le_cmp(guid, spar_video_guid)) + if (!channel->requested && uuid_le_cmp(guid, visor_video_guid)) /* we only care about errors if this is not the video channel */ goto err_destroy_channel; diff --git a/drivers/staging/unisys/visorbus/visorchipset.c b/drivers/staging/unisys/visorbus/visorchipset.c index 4cfd0fae9bd5..22150564b4fb 100644 --- a/drivers/staging/unisys/visorbus/visorchipset.c +++ b/drivers/staging/unisys/visorbus/visorchipset.c @@ -34,12 +34,12 @@ #define MAX_CONTROLVM_PAYLOAD_BYTES (1024 * 128) -#define UNISYS_SPAR_LEAF_ID 0x40000000 +#define UNISYS_VISOR_LEAF_ID 0x40000000 /* The s-Par leaf ID returns "UnisysSpar64" encoded across ebx, ecx, edx */ -#define UNISYS_SPAR_ID_EBX 0x73696e55 -#define UNISYS_SPAR_ID_ECX 0x70537379 -#define UNISYS_SPAR_ID_EDX 0x34367261 +#define UNISYS_VISOR_ID_EBX 0x73696e55 +#define UNISYS_VISOR_ID_ECX 0x70537379 +#define UNISYS_VISOR_ID_EDX 0x34367261 /* * When the controlvm channel is idle for at least MIN_IDLE_SECONDS, @@ -101,7 +101,7 @@ static ssize_t toolaction_show(struct device *dev, int err; err = visorchannel_read(chipset_dev->controlvm_channel, - offsetof(struct spar_controlvm_channel_protocol, + offsetof(struct visor_controlvm_channel, tool_action), &tool_action, sizeof(u8)); if (err) @@ -120,11 +120,10 @@ static ssize_t toolaction_store(struct device *dev, if (kstrtou8(buf, 10, &tool_action)) return -EINVAL; - err = visorchannel_write - (chipset_dev->controlvm_channel, - offsetof(struct spar_controlvm_channel_protocol, - tool_action), - &tool_action, sizeof(u8)); + err = visorchannel_write(chipset_dev->controlvm_channel, + offsetof(struct visor_controlvm_channel, + tool_action), + &tool_action, sizeof(u8)); if (err) return err; @@ -136,18 +135,18 @@ static ssize_t boottotool_show(struct device *dev, struct device_attribute *attr, char *buf) { - struct efi_spar_indication efi_spar_indication; + struct efi_visor_indication efi_visor_indication; int err; err = visorchannel_read(chipset_dev->controlvm_channel, - offsetof(struct spar_controlvm_channel_protocol, - efi_spar_ind), - &efi_spar_indication, - sizeof(struct efi_spar_indication)); + offsetof(struct visor_controlvm_channel, + efi_visor_ind), + &efi_visor_indication, + sizeof(struct efi_visor_indication)); if (err) return err; - return sprintf(buf, "%u\n", efi_spar_indication.boot_to_tool); + return sprintf(buf, "%u\n", efi_visor_indication.boot_to_tool); } static ssize_t boottotool_store(struct device *dev, @@ -155,17 +154,17 @@ static ssize_t boottotool_store(struct device *dev, const char *buf, size_t count) { int val, err; - struct efi_spar_indication efi_spar_indication; + struct efi_visor_indication efi_visor_indication; if (kstrtoint(buf, 10, &val)) return -EINVAL; - efi_spar_indication.boot_to_tool = val; - err = visorchannel_write - (chipset_dev->controlvm_channel, - offsetof(struct spar_controlvm_channel_protocol, - efi_spar_ind), &(efi_spar_indication), - sizeof(struct efi_spar_indication)); + efi_visor_indication.boot_to_tool = val; + err = visorchannel_write(chipset_dev->controlvm_channel, + offsetof(struct visor_controlvm_channel, + efi_visor_ind), + &(efi_visor_indication), + sizeof(struct efi_visor_indication)); if (err) return err; @@ -180,7 +179,7 @@ static ssize_t error_show(struct device *dev, struct device_attribute *attr, int err; err = visorchannel_read(chipset_dev->controlvm_channel, - offsetof(struct spar_controlvm_channel_protocol, + offsetof(struct visor_controlvm_channel, installation_error), &error, sizeof(u32)); if (err) @@ -197,11 +196,10 @@ static ssize_t error_store(struct device *dev, struct device_attribute *attr, if (kstrtou32(buf, 10, &error)) return -EINVAL; - err = visorchannel_write - (chipset_dev->controlvm_channel, - offsetof(struct spar_controlvm_channel_protocol, - installation_error), - &error, sizeof(u32)); + err = visorchannel_write(chipset_dev->controlvm_channel, + offsetof(struct visor_controlvm_channel, + installation_error), + &error, sizeof(u32)); if (err) return err; return count; @@ -214,11 +212,10 @@ static ssize_t textid_show(struct device *dev, struct device_attribute *attr, u32 text_id = 0; int err; - err = visorchannel_read - (chipset_dev->controlvm_channel, - offsetof(struct spar_controlvm_channel_protocol, - installation_text_id), - &text_id, sizeof(u32)); + err = visorchannel_read(chipset_dev->controlvm_channel, + offsetof(struct visor_controlvm_channel, + installation_text_id), + &text_id, sizeof(u32)); if (err) return err; @@ -234,11 +231,10 @@ static ssize_t textid_store(struct device *dev, struct device_attribute *attr, if (kstrtou32(buf, 10, &text_id)) return -EINVAL; - err = visorchannel_write - (chipset_dev->controlvm_channel, - offsetof(struct spar_controlvm_channel_protocol, - installation_text_id), - &text_id, sizeof(u32)); + err = visorchannel_write(chipset_dev->controlvm_channel, + offsetof(struct visor_controlvm_channel, + installation_text_id), + &text_id, sizeof(u32)); if (err) return err; return count; @@ -252,7 +248,7 @@ static ssize_t remaining_steps_show(struct device *dev, int err; err = visorchannel_read(chipset_dev->controlvm_channel, - offsetof(struct spar_controlvm_channel_protocol, + offsetof(struct visor_controlvm_channel, installation_remaining_steps), &remaining_steps, sizeof(u16)); if (err) @@ -271,11 +267,10 @@ static ssize_t remaining_steps_store(struct device *dev, if (kstrtou16(buf, 10, &remaining_steps)) return -EINVAL; - err = visorchannel_write - (chipset_dev->controlvm_channel, - offsetof(struct spar_controlvm_channel_protocol, - installation_remaining_steps), - &remaining_steps, sizeof(u16)); + err = visorchannel_write(chipset_dev->controlvm_channel, + offsetof(struct visor_controlvm_channel, + installation_remaining_steps), + &remaining_steps, sizeof(u16)); if (err) return err; return count; @@ -285,9 +280,9 @@ static DEVICE_ATTR_RW(remaining_steps); static uuid_le parser_id_get(struct parser_context *ctx) { - struct spar_controlvm_parameters_header *phdr = NULL; + struct visor_controlvm_parameters_header *phdr = NULL; - phdr = (struct spar_controlvm_parameters_header *)(ctx->data); + phdr = (struct visor_controlvm_parameters_header *)(ctx->data); return phdr->id; } @@ -331,9 +326,9 @@ parser_string_get(struct parser_context *ctx) static void * parser_name_get(struct parser_context *ctx) { - struct spar_controlvm_parameters_header *phdr = NULL; + struct visor_controlvm_parameters_header *phdr = NULL; - phdr = (struct spar_controlvm_parameters_header *)(ctx->data); + phdr = (struct visor_controlvm_parameters_header *)(ctx->data); if (phdr->name_offset + phdr->name_length > ctx->param_bytes) return NULL; @@ -400,7 +395,7 @@ controlvm_init_response(struct controlvm_message *msg, static int controlvm_respond_chipset_init(struct controlvm_message_header *msg_hdr, int response, - enum ultra_chipset_feature features) + enum visor_chipset_feature features) { struct controlvm_message outmsg; @@ -414,7 +409,7 @@ static int chipset_init(struct controlvm_message *inmsg) { static int chipset_inited; - enum ultra_chipset_feature features = 0; + enum visor_chipset_feature features = 0; int rc = CONTROLVM_RESP_SUCCESS; int res = 0; @@ -430,13 +425,13 @@ chipset_init(struct controlvm_message *inmsg) * also supports it). */ features = inmsg->cmd.init_chipset.features & - ULTRA_CHIPSET_FEATURE_PARA_HOTPLUG; + VISOR_CHIPSET_FEATURE_PARA_HOTPLUG; /* * Set the "reply" bit so Command knows this is a * features-aware driver. */ - features |= ULTRA_CHIPSET_FEATURE_REPLY; + features |= VISOR_CHIPSET_FEATURE_REPLY; out_respond: if (inmsg->hdr.flags.response_expected) @@ -447,7 +442,7 @@ out_respond: static int controlvm_respond(struct controlvm_message_header *msg_hdr, int response, - struct spar_segment_state *state) + struct visor_segment_state *state) { struct controlvm_message outmsg; @@ -470,14 +465,14 @@ enum crash_obj_type { }; static int -save_crash_message(struct controlvm_message *msg, enum crash_obj_type typ) +save_crash_message(struct controlvm_message *msg, enum crash_obj_type cr_type) { u32 local_crash_msg_offset; u16 local_crash_msg_count; int err; err = visorchannel_read(chipset_dev->controlvm_channel, - offsetof(struct spar_controlvm_channel_protocol, + offsetof(struct visor_controlvm_channel, saved_crash_message_count), &local_crash_msg_count, sizeof(u16)); if (err) { @@ -493,7 +488,7 @@ save_crash_message(struct controlvm_message *msg, enum crash_obj_type typ) } err = visorchannel_read(chipset_dev->controlvm_channel, - offsetof(struct spar_controlvm_channel_protocol, + offsetof(struct visor_controlvm_channel, saved_crash_message_offset), &local_crash_msg_offset, sizeof(u32)); if (err) { @@ -502,7 +497,7 @@ save_crash_message(struct controlvm_message *msg, enum crash_obj_type typ) return err; } - switch (typ) { + switch (cr_type) { case CRASH_DEV: local_crash_msg_offset += sizeof(struct controlvm_message); err = visorchannel_write(chipset_dev->controlvm_channel, @@ -551,7 +546,7 @@ controlvm_responder(enum controlvm_id cmd_id, static int device_changestate_responder(enum controlvm_id cmd_id, struct visor_device *p, int response, - struct spar_segment_state response_state) + struct visor_segment_state response_state) { struct controlvm_message outmsg; u32 bus_no = p->chipset_bus_no; @@ -573,7 +568,7 @@ device_changestate_responder(enum controlvm_id cmd_id, } static int -bus_create(struct controlvm_message *inmsg) +visorbus_create(struct controlvm_message *inmsg) { struct controlvm_message_packet *cmd = &inmsg->cmd; struct controlvm_message_header *pmsg_hdr = NULL; @@ -585,7 +580,7 @@ bus_create(struct controlvm_message *inmsg) bus_info = visorbus_get_device_by_id(bus_no, BUS_ROOT_DEVICE, NULL); if (bus_info && (bus_info->state.created == 1)) { dev_err(&chipset_dev->acpi_device->dev, - "failed bus_create: already exists\n"); + "failed visorbus_create: already exists\n"); err = -EEXIST; goto err_respond; } @@ -600,7 +595,7 @@ bus_create(struct controlvm_message *inmsg) bus_info->chipset_bus_no = bus_no; bus_info->chipset_dev_no = BUS_ROOT_DEVICE; - if (uuid_le_cmp(cmd->create_bus.bus_inst_uuid, spar_siovm_uuid) == 0) { + if (uuid_le_cmp(cmd->create_bus.bus_inst_uuid, visor_siovm_uuid) == 0) { err = save_crash_message(inmsg, CRASH_BUS); if (err) goto err_free_bus_info; @@ -630,9 +625,9 @@ bus_create(struct controlvm_message *inmsg) } bus_info->visorchannel = visorchannel; - /* Response will be handled by chipset_bus_create */ - err = chipset_bus_create(bus_info); - /* If error chipset_bus_create didn't respond, need to respond here */ + /* Response will be handled by visorchipset_bus_create */ + err = visorchipset_bus_create(bus_info); + /* If visorchipset_bus_create didn't respond, need to respond here */ if (err) goto err_destroy_channel; @@ -654,7 +649,7 @@ err_respond: } static int -bus_destroy(struct controlvm_message *inmsg) +visorbus_destroy(struct controlvm_message *inmsg) { struct controlvm_message_packet *cmd = &inmsg->cmd; struct controlvm_message_header *pmsg_hdr = NULL; @@ -688,8 +683,8 @@ bus_destroy(struct controlvm_message *inmsg) bus_info->pending_msg_hdr = pmsg_hdr; } - /* Response will be handled by chipset_bus_destroy */ - chipset_bus_destroy(bus_info); + /* Response will be handled by visorchipset_bus_destroy */ + visorchipset_bus_destroy(bus_info); return 0; err_respond: @@ -699,8 +694,8 @@ err_respond: } static int -bus_configure(struct controlvm_message *inmsg, - struct parser_context *parser_ctx) +visorbus_configure(struct controlvm_message *inmsg, + struct parser_context *parser_ctx) { struct controlvm_message_packet *cmd = &inmsg->cmd; u32 bus_no; @@ -737,14 +732,14 @@ bus_configure(struct controlvm_message *inmsg, err_respond: dev_err(&chipset_dev->acpi_device->dev, - "bus_configured exited with err: %d\n", err); + "visorbus_configure exited with err: %d\n", err); if (inmsg->hdr.flags.response_expected == 1) controlvm_responder(inmsg->hdr.id, &inmsg->hdr, err); return err; } static int -my_device_create(struct controlvm_message *inmsg) +visorbus_device_create(struct controlvm_message *inmsg) { struct controlvm_message_packet *cmd = &inmsg->cmd; struct controlvm_message_header *pmsg_hdr = NULL; @@ -807,7 +802,7 @@ my_device_create(struct controlvm_message *inmsg) dev_info->visorchannel = visorchannel; dev_info->channel_type_guid = cmd->create_device.data_type_uuid; if (uuid_le_cmp(cmd->create_device.data_type_uuid, - spar_vhba_channel_protocol_uuid) == 0) { + visor_vhba_channel_uuid) == 0) { err = save_crash_message(inmsg, CRASH_DEV); if (err) goto err_destroy_visorchannel; @@ -824,8 +819,8 @@ my_device_create(struct controlvm_message *inmsg) sizeof(struct controlvm_message_header)); dev_info->pending_msg_hdr = pmsg_hdr; } - /* Chipset_device_create will send response */ - err = chipset_device_create(dev_info); + /* visorchipset_device_create will send response */ + err = visorchipset_device_create(dev_info); if (err) goto err_destroy_visorchannel; @@ -844,13 +839,13 @@ err_respond: } static int -my_device_changestate(struct controlvm_message *inmsg) +visorbus_device_changestate(struct controlvm_message *inmsg) { struct controlvm_message_packet *cmd = &inmsg->cmd; struct controlvm_message_header *pmsg_hdr = NULL; u32 bus_no = cmd->device_change_state.bus_no; u32 dev_no = cmd->device_change_state.dev_no; - struct spar_segment_state state = cmd->device_change_state.state; + struct visor_segment_state state = cmd->device_change_state.state; struct visor_device *dev_info; int err = 0; @@ -882,16 +877,16 @@ my_device_changestate(struct controlvm_message *inmsg) if (state.alive == segment_state_running.alive && state.operating == segment_state_running.operating) - /* Response will be sent from chipset_device_resume */ - err = chipset_device_resume(dev_info); + /* Response will be sent from visorchipset_device_resume */ + err = visorchipset_device_resume(dev_info); /* ServerNotReady / ServerLost / SegmentStateStandby */ else if (state.alive == segment_state_standby.alive && state.operating == segment_state_standby.operating) /* * technically this is standby case where server is lost. - * Response will be sent from chipset_device_pause. + * Response will be sent from visorchipset_device_pause. */ - err = chipset_device_pause(dev_info); + err = visorchipset_device_pause(dev_info); if (err) goto err_respond; @@ -905,7 +900,7 @@ err_respond: } static int -my_device_destroy(struct controlvm_message *inmsg) +visorbus_device_destroy(struct controlvm_message *inmsg) { struct controlvm_message_packet *cmd = &inmsg->cmd; struct controlvm_message_header *pmsg_hdr = NULL; @@ -941,7 +936,7 @@ my_device_destroy(struct controlvm_message *inmsg) dev_info->pending_msg_hdr = pmsg_hdr; } - chipset_device_destroy(dev_info); + visorchipset_device_destroy(dev_info); return 0; err_respond: @@ -1179,15 +1174,15 @@ parahotplug_request_kickoff(struct parahotplug_request *req) env_cmd, env_id, env_state, env_bus, env_dev, env_func, NULL }; - sprintf(env_cmd, "SPAR_PARAHOTPLUG=1"); - sprintf(env_id, "SPAR_PARAHOTPLUG_ID=%d", req->id); - sprintf(env_state, "SPAR_PARAHOTPLUG_STATE=%d", + sprintf(env_cmd, "VISOR_PARAHOTPLUG=1"); + sprintf(env_id, "VISOR_PARAHOTPLUG_ID=%d", req->id); + sprintf(env_state, "VISOR_PARAHOTPLUG_STATE=%d", cmd->device_change_state.state.active); - sprintf(env_bus, "SPAR_PARAHOTPLUG_BUS=%d", + sprintf(env_bus, "VISOR_PARAHOTPLUG_BUS=%d", cmd->device_change_state.bus_no); - sprintf(env_dev, "SPAR_PARAHOTPLUG_DEVICE=%d", + sprintf(env_dev, "VISOR_PARAHOTPLUG_DEVICE=%d", cmd->device_change_state.dev_no >> 3); - sprintf(env_func, "SPAR_PARAHOTPLUG_FUNCTION=%d", + sprintf(env_func, "VISOR_PARAHOTPLUG_FUNCTION=%d", cmd->device_change_state.dev_no & 0x7); return kobject_uevent_env(&chipset_dev->acpi_device->dev.kobj, @@ -1387,7 +1382,7 @@ setup_crash_devices_work_queue(struct work_struct *work) /* get saved message count */ if (visorchannel_read(chipset_dev->controlvm_channel, - offsetof(struct spar_controlvm_channel_protocol, + offsetof(struct visor_controlvm_channel, saved_crash_message_count), &local_crash_msg_count, sizeof(u16)) < 0) { dev_err(&chipset_dev->acpi_device->dev, @@ -1403,7 +1398,7 @@ setup_crash_devices_work_queue(struct work_struct *work) /* get saved crash message offset */ if (visorchannel_read(chipset_dev->controlvm_channel, - offsetof(struct spar_controlvm_channel_protocol, + offsetof(struct visor_controlvm_channel, saved_crash_message_offset), &local_crash_msg_offset, sizeof(u32)) < 0) { dev_err(&chipset_dev->acpi_device->dev, @@ -1438,7 +1433,7 @@ setup_crash_devices_work_queue(struct work_struct *work) "no valid create_bus message\n"); return; } - bus_create(&local_crash_bus_msg); + visorbus_create(&local_crash_bus_msg); /* reuse create device message for storage device */ if (!local_crash_dev_msg.cmd.create_device.channel_addr) { @@ -1446,11 +1441,11 @@ setup_crash_devices_work_queue(struct work_struct *work) "no valid create_device message\n"); return; } - my_device_create(&local_crash_dev_msg); + visorbus_device_create(&local_crash_dev_msg); } void -bus_create_response(struct visor_device *bus_info, int response) +visorbus_create_response(struct visor_device *bus_info, int response) { if (response >= 0) bus_info->state.created = 1; @@ -1463,7 +1458,7 @@ bus_create_response(struct visor_device *bus_info, int response) } void -bus_destroy_response(struct visor_device *bus_info, int response) +visorbus_destroy_response(struct visor_device *bus_info, int response) { controlvm_responder(CONTROLVM_BUS_DESTROY, bus_info->pending_msg_hdr, response); @@ -1473,7 +1468,7 @@ bus_destroy_response(struct visor_device *bus_info, int response) } void -device_create_response(struct visor_device *dev_info, int response) +visorbus_device_create_response(struct visor_device *dev_info, int response) { if (response >= 0) dev_info->state.created = 1; @@ -1486,7 +1481,7 @@ device_create_response(struct visor_device *dev_info, int response) } void -device_destroy_response(struct visor_device *dev_info, int response) +visorbus_device_destroy_response(struct visor_device *dev_info, int response) { controlvm_responder(CONTROLVM_DEVICE_DESTROY, dev_info->pending_msg_hdr, response); @@ -1496,8 +1491,7 @@ device_destroy_response(struct visor_device *dev_info, int response) } void -device_pause_response(struct visor_device *dev_info, - int response) +visorbus_device_pause_response(struct visor_device *dev_info, int response) { device_changestate_responder(CONTROLVM_DEVICE_CHANGESTATE, dev_info, response, @@ -1508,7 +1502,7 @@ device_pause_response(struct visor_device *dev_info, } void -device_resume_response(struct visor_device *dev_info, int response) +visorbus_device_resume_response(struct visor_device *dev_info, int response) { device_changestate_responder(CONTROLVM_DEVICE_CHANGESTATE, dev_info, response, @@ -1599,9 +1593,6 @@ handle_command(struct controlvm_message inmsg, u64 channel_addr) /* create parsing context if necessary */ local_addr = (inmsg.hdr.flags.test_message == 1); - if (channel_addr == 0) - return -EINVAL; - parm_addr = channel_addr + inmsg.hdr.payload_vm_offset; parm_bytes = inmsg.hdr.payload_bytes; @@ -1634,16 +1625,16 @@ handle_command(struct controlvm_message inmsg, u64 channel_addr) err = chipset_init(&inmsg); break; case CONTROLVM_BUS_CREATE: - err = bus_create(&inmsg); + err = visorbus_create(&inmsg); break; case CONTROLVM_BUS_DESTROY: - err = bus_destroy(&inmsg); + err = visorbus_destroy(&inmsg); break; case CONTROLVM_BUS_CONFIGURE: - err = bus_configure(&inmsg, parser_ctx); + err = visorbus_configure(&inmsg, parser_ctx); break; case CONTROLVM_DEVICE_CREATE: - err = my_device_create(&inmsg); + err = visorbus_device_create(&inmsg); break; case CONTROLVM_DEVICE_CHANGESTATE: if (cmd->device_change_state.flags.phys_device) { @@ -1653,12 +1644,12 @@ handle_command(struct controlvm_message inmsg, u64 channel_addr) * save the hdr and cmd structures for later use * when sending back the response to Command */ - err = my_device_changestate(&inmsg); + err = visorbus_device_changestate(&inmsg); break; } break; case CONTROLVM_DEVICE_DESTROY: - err = my_device_destroy(&inmsg); + err = visorbus_device_destroy(&inmsg); break; case CONTROLVM_DEVICE_CONFIGURE: /* no op just send a respond that we passed */ @@ -1793,6 +1784,11 @@ controlvm_periodic_work(struct work_struct *work) /* parahotplug_worker */ parahotplug_process_list(); +/* + * The controlvm messages are sent in a bulk. If we start receiving messages, we + * want the polling to be fast. If we do not receive any message for + * MIN_IDLE_SECONDS, we can slow down the polling. + */ schedule_out: if (time_after(jiffies, chipset_dev->most_recent_message_jiffies + (HZ * MIN_IDLE_SECONDS))) { @@ -1821,7 +1817,7 @@ visorchipset_init(struct acpi_device *acpi_device) { int err = -ENODEV; u64 addr; - uuid_le uuid = SPAR_CONTROLVM_CHANNEL_PROTOCOL_UUID; + uuid_le uuid = VISOR_CONTROLVM_CHANNEL_UUID; struct visorchannel *controlvm_channel; chipset_dev = kzalloc(sizeof(*chipset_dev), GFP_KERNEL); @@ -1849,7 +1845,7 @@ visorchipset_init(struct acpi_device *acpi_device) if (err < 0) goto error_destroy_channel; - if (!SPAR_CONTROLVM_CHANNEL_OK_CLIENT( + if (!VISOR_CONTROLVM_CHANNEL_OK_CLIENT( visorchannel_get_header(controlvm_channel))) goto error_delete_groups; @@ -1928,10 +1924,10 @@ static __init int visorutil_spar_detect(void) if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { /* check the ID */ - cpuid(UNISYS_SPAR_LEAF_ID, &eax, &ebx, &ecx, &edx); - return (ebx == UNISYS_SPAR_ID_EBX) && - (ecx == UNISYS_SPAR_ID_ECX) && - (edx == UNISYS_SPAR_ID_EDX); + cpuid(UNISYS_VISOR_LEAF_ID, &eax, &ebx, &ecx, &edx); + return (ebx == UNISYS_VISOR_ID_EBX) && + (ecx == UNISYS_VISOR_ID_ECX) && + (edx == UNISYS_VISOR_ID_EDX); } else { return 0; } diff --git a/drivers/staging/unisys/visorhba/visorhba_main.c b/drivers/staging/unisys/visorhba/visorhba_main.c index 6997b16b4dcd..a6e7a6bbc428 100644 --- a/drivers/staging/unisys/visorhba/visorhba_main.c +++ b/drivers/staging/unisys/visorhba/visorhba_main.c @@ -37,14 +37,14 @@ static struct dentry *visorhba_debugfs_dir; /* GUIDS for HBA channel type supported by this driver */ static struct visor_channeltype_descriptor visorhba_channel_types[] = { /* Note that the only channel type we expect to be reported by the - * bus driver is the SPAR_VHBA channel. + * bus driver is the VISOR_VHBA channel. */ - { SPAR_VHBA_CHANNEL_PROTOCOL_UUID, "sparvhba" }, + { VISOR_VHBA_CHANNEL_UUID, "sparvhba" }, { NULL_UUID_LE, NULL } }; MODULE_DEVICE_TABLE(visorbus, visorhba_channel_types); -MODULE_ALIAS("visorbus:" SPAR_VHBA_CHANNEL_PROTOCOL_UUID_STR); +MODULE_ALIAS("visorbus:" VISOR_VHBA_CHANNEL_UUID_STR); struct visordisk_info { u32 valid; @@ -657,7 +657,7 @@ static int info_debugfs_show(struct seq_file *seq, void *v) seq_printf(seq, "phys_flags_addr = 0x%016llx\n", phys_flags_addr); seq_printf(seq, "FeatureFlags = %llu\n", - (__le64)readq(devdata->flags_addr)); + (u64)readq(devdata->flags_addr)); } seq_printf(seq, "acquire_failed_cnt = %llu\n", devdata->acquire_failed_cnt); @@ -1060,8 +1060,7 @@ static int visorhba_probe(struct visor_device *dev) if (!scsihost) return -ENODEV; - channel_offset = offsetof(struct spar_io_channel_protocol, - vhba.max); + channel_offset = offsetof(struct visor_io_channel, vhba.max); err = visorbus_read_channel(dev, channel_offset, &max, sizeof(struct vhba_config_max)); if (err < 0) @@ -1091,7 +1090,7 @@ static int visorhba_probe(struct visor_device *dev) goto err_scsi_remove_host; } devdata->debugfs_info = - debugfs_create_file("info", S_IRUSR | S_IRGRP, + debugfs_create_file("info", 0440, devdata->debugfs_dir, devdata, &info_debugfs_fops); if (!devdata->debugfs_info) { @@ -1105,12 +1104,12 @@ static int visorhba_probe(struct visor_device *dev) devdata->serverchangingstate = false; devdata->scsihost = scsihost; - channel_offset = offsetof(struct spar_io_channel_protocol, + channel_offset = offsetof(struct visor_io_channel, channel_header.features); err = visorbus_read_channel(dev, channel_offset, &features, 8); if (err) goto err_debugfs_info; - features |= ULTRA_IO_CHANNEL_IS_POLLING; + features |= VISOR_CHANNEL_IS_POLLING; err = visorbus_write_channel(dev, channel_offset, &features, 8); if (err) goto err_debugfs_info; @@ -1166,7 +1165,7 @@ static void visorhba_remove(struct visor_device *dev) debugfs_remove_recursive(devdata->debugfs_dir); } -/* This is used to tell the visor bus driver which types of visor devices +/* This is used to tell the visorbus driver which types of visor devices * we support, and what functions to call when a visor device that we support * is attached or removed. */ diff --git a/drivers/staging/unisys/visorinput/ultrainputreport.h b/drivers/staging/unisys/visorinput/ultrainputreport.h index 53dde7c53809..a4baea53c518 100644 --- a/drivers/staging/unisys/visorinput/ultrainputreport.h +++ b/drivers/staging/unisys/visorinput/ultrainputreport.h @@ -17,26 +17,23 @@ #include <linux/types.h> -/* Identifies mouse and keyboard activity which is specified by the firmware to - * the host using the cmsimpleinput protocol. @ingroup coretypes +/* These defines identify mouse and keyboard activity which is specified by the + * firmware to the host using the cmsimpleinput protocol. @ingroup coretypes */ -enum ultra_inputaction { - inputaction_none = 0, - inputaction_xy_motion = 1, /* only motion; arg1=x, arg2=y */ - inputaction_mouse_button_down = 2, /* arg1: 1=left,2=center,3=right */ - inputaction_mouse_button_up = 3, /* arg1: 1=left,2=center,3=right */ - inputaction_mouse_button_click = 4, /* arg1: 1=left,2=center,3=right */ - inputaction_mouse_button_dclick = 5, /* arg1: 1=left,2=center, - * 3=right - */ - inputaction_wheel_rotate_away = 6, /* arg1: wheel rotation away from - * user - */ - inputaction_wheel_rotate_toward = 7, /* arg1: wheel rotation toward - * user - */ - inputaction_set_max_xy = 8, /* set screen maxXY; arg1=x, arg2=y */ - inputaction_key_down = 64, /* arg1: scancode, as follows: +#define INPUTACTION_XY_MOTION 1 /* only motion; arg1=x, arg2=y */ +#define INPUTACTION_MOUSE_BUTTON_DOWN 2 /* arg1: 1=left,2=center,3=right */ +#define INPUTACTION_MOUSE_BUTTON_UP 3 /* arg1: 1=left,2=center,3=right */ +#define INPUTACTION_MOUSE_BUTTON_CLICK 4 /* arg1: 1=left,2=center,3=right */ +#define INPUTACTION_MOUSE_BUTTON_DCLICK 5 /* arg1: 1=left,2=center, + * 3=right + */ +#define INPUTACTION_WHEEL_ROTATE_AWAY 6 /* arg1: wheel rotation away from + * user + */ +#define INPUTACTION_WHEEL_ROTATE_TOWARD 7 /* arg1: wheel rotation toward + * user + */ +#define INPUTACTION_KEY_DOWN 64 /* arg1: scancode, as follows: * If arg1 <= 0xff, it's a 1-byte * scancode and arg1 is that scancode. * If arg1 > 0xff, it's a 2-byte @@ -45,10 +42,10 @@ enum ultra_inputaction { * high 8 bits. E.g., the right ALT key * would appear as x'38e0'. */ - inputaction_key_up = 65, /* arg1: scancode (in same format as +#define INPUTACTION_KEY_UP 65 /* arg1: scancode (in same format as * inputaction_keyDown) */ - inputaction_set_locking_key_state = 66, +#define INPUTACTION_SET_LOCKING_KEY_STATE 66 /* arg1: scancode (in same format * as inputaction_keyDown); * MUST refer to one of the @@ -58,22 +55,20 @@ enum ultra_inputaction { * in the LOCKED position * (e.g., light is ON) */ - inputaction_key_down_up = 67, /* arg1: scancode (in same format +#define INPUTACTION_KEY_DOWN_UP 67 /* arg1: scancode (in same format * as inputaction_keyDown) */ - inputaction_last -}; -struct ultra_inputactivity { +struct visor_inputactivity { u16 action; u16 arg1; u16 arg2; u16 arg3; } __packed; -struct ultra_inputreport { +struct visor_inputreport { u64 seq_no; - struct ultra_inputactivity activity; + struct visor_inputactivity activity; } __packed; #endif diff --git a/drivers/staging/unisys/visorinput/visorinput.c b/drivers/staging/unisys/visorinput/visorinput.c index cdd35437f0a0..45bc340d4e9d 100644 --- a/drivers/staging/unisys/visorinput/visorinput.c +++ b/drivers/staging/unisys/visorinput/visorinput.c @@ -33,17 +33,16 @@ #include "ultrainputreport.h" /* Keyboard channel {c73416d0-b0b8-44af-b304-9d2ae99f1b3d} */ -#define SPAR_KEYBOARD_CHANNEL_PROTOCOL_UUID \ +#define VISOR_KEYBOARD_CHANNEL_UUID \ UUID_LE(0xc73416d0, 0xb0b8, 0x44af, \ 0xb3, 0x4, 0x9d, 0x2a, 0xe9, 0x9f, 0x1b, 0x3d) -#define SPAR_KEYBOARD_CHANNEL_PROTOCOL_UUID_STR "c73416d0-b0b8-44af-b304-9d2ae99f1b3d" +#define VISOR_KEYBOARD_CHANNEL_UUID_STR "c73416d0-b0b8-44af-b304-9d2ae99f1b3d" /* Mouse channel {addf07d4-94a9-46e2-81c3-61abcdbdbd87} */ -#define SPAR_MOUSE_CHANNEL_PROTOCOL_UUID \ +#define VISOR_MOUSE_CHANNEL_UUID \ UUID_LE(0xaddf07d4, 0x94a9, 0x46e2, \ 0x81, 0xc3, 0x61, 0xab, 0xcd, 0xbd, 0xbd, 0x87) -#define SPAR_MOUSE_CHANNEL_PROTOCOL_UUID_STR \ - "addf07d4-94a9-46e2-81c3-61abcdbdbd87" +#define VISOR_MOUSE_CHANNEL_UUID_STR "addf07d4-94a9-46e2-81c3-61abcdbdbd87" #define PIXELS_ACROSS_DEFAULT 800 #define PIXELS_DOWN_DEFAULT 600 @@ -70,10 +69,8 @@ struct visorinput_devdata { unsigned char keycode_table[0]; }; -static const uuid_le spar_keyboard_channel_protocol_uuid = - SPAR_KEYBOARD_CHANNEL_PROTOCOL_UUID; -static const uuid_le spar_mouse_channel_protocol_uuid = - SPAR_MOUSE_CHANNEL_PROTOCOL_UUID; +static const uuid_le visor_keyboard_channel_uuid = VISOR_KEYBOARD_CHANNEL_UUID; +static const uuid_le visor_mouse_channel_uuid = VISOR_MOUSE_CHANNEL_UUID; /* * Borrowed from drivers/input/keyboard/atakbd.c @@ -456,9 +453,9 @@ visorinput_probe(struct visor_device *dev) enum visorinput_device_type devtype; guid = visorchannel_get_uuid(dev->visorchannel); - if (uuid_le_cmp(guid, spar_mouse_channel_protocol_uuid) == 0) + if (uuid_le_cmp(guid, visor_mouse_channel_uuid) == 0) devtype = visorinput_mouse; - else if (uuid_le_cmp(guid, spar_keyboard_channel_protocol_uuid) == 0) + else if (uuid_le_cmp(guid, visor_keyboard_channel_uuid) == 0) devtype = visorinput_keyboard; else return -ENODEV; @@ -568,7 +565,7 @@ calc_button(int x) static void visorinput_channel_interrupt(struct visor_device *dev) { - struct ultra_inputreport r; + struct visor_inputreport r; int scancode, keycode; struct input_dev *visorinput_dev; int xmotion, ymotion, button; @@ -585,46 +582,46 @@ visorinput_channel_interrupt(struct visor_device *dev) scancode = r.activity.arg1; keycode = scancode_to_keycode(scancode); switch (r.activity.action) { - case inputaction_key_down: + case INPUTACTION_KEY_DOWN: input_report_key(visorinput_dev, keycode, 1); input_sync(visorinput_dev); break; - case inputaction_key_up: + case INPUTACTION_KEY_UP: input_report_key(visorinput_dev, keycode, 0); input_sync(visorinput_dev); break; - case inputaction_key_down_up: + case INPUTACTION_KEY_DOWN_UP: input_report_key(visorinput_dev, keycode, 1); input_sync(visorinput_dev); input_report_key(visorinput_dev, keycode, 0); input_sync(visorinput_dev); break; - case inputaction_set_locking_key_state: + case INPUTACTION_SET_LOCKING_KEY_STATE: handle_locking_key(visorinput_dev, keycode, r.activity.arg2); break; - case inputaction_xy_motion: + case INPUTACTION_XY_MOTION: xmotion = r.activity.arg1; ymotion = r.activity.arg2; input_report_abs(visorinput_dev, ABS_X, xmotion); input_report_abs(visorinput_dev, ABS_Y, ymotion); input_sync(visorinput_dev); break; - case inputaction_mouse_button_down: + case INPUTACTION_MOUSE_BUTTON_DOWN: button = calc_button(r.activity.arg1); if (button < 0) break; input_report_key(visorinput_dev, button, 1); input_sync(visorinput_dev); break; - case inputaction_mouse_button_up: + case INPUTACTION_MOUSE_BUTTON_UP: button = calc_button(r.activity.arg1); if (button < 0) break; input_report_key(visorinput_dev, button, 0); input_sync(visorinput_dev); break; - case inputaction_mouse_button_click: + case INPUTACTION_MOUSE_BUTTON_CLICK: button = calc_button(r.activity.arg1); if (button < 0) break; @@ -634,7 +631,7 @@ visorinput_channel_interrupt(struct visor_device *dev) input_report_key(visorinput_dev, button, 0); input_sync(visorinput_dev); break; - case inputaction_mouse_button_dclick: + case INPUTACTION_MOUSE_BUTTON_DCLICK: button = calc_button(r.activity.arg1); if (button < 0) break; @@ -645,11 +642,11 @@ visorinput_channel_interrupt(struct visor_device *dev) input_sync(visorinput_dev); } break; - case inputaction_wheel_rotate_away: + case INPUTACTION_WHEEL_ROTATE_AWAY: input_report_rel(visorinput_dev, REL_WHEEL, 1); input_sync(visorinput_dev); break; - case inputaction_wheel_rotate_toward: + case INPUTACTION_WHEEL_ROTATE_TOWARD: input_report_rel(visorinput_dev, REL_WHEEL, -1); input_sync(visorinput_dev); break; @@ -730,8 +727,8 @@ out: /* GUIDS for all channel types supported by this driver. */ static struct visor_channeltype_descriptor visorinput_channel_types[] = { - { SPAR_KEYBOARD_CHANNEL_PROTOCOL_UUID, "keyboard"}, - { SPAR_MOUSE_CHANNEL_PROTOCOL_UUID, "mouse"}, + { VISOR_KEYBOARD_CHANNEL_UUID, "keyboard"}, + { VISOR_MOUSE_CHANNEL_UUID, "mouse"}, { NULL_UUID_LE, NULL } }; @@ -767,5 +764,5 @@ MODULE_AUTHOR("Unisys"); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("s-Par human input driver for virtual keyboard/mouse"); -MODULE_ALIAS("visorbus:" SPAR_MOUSE_CHANNEL_PROTOCOL_UUID_STR); -MODULE_ALIAS("visorbus:" SPAR_KEYBOARD_CHANNEL_PROTOCOL_UUID_STR); +MODULE_ALIAS("visorbus:" VISOR_MOUSE_CHANNEL_UUID_STR); +MODULE_ALIAS("visorbus:" VISOR_KEYBOARD_CHANNEL_UUID_STR); diff --git a/drivers/staging/unisys/visornic/visornic_main.c b/drivers/staging/unisys/visornic/visornic_main.c index adebf224f73a..2891622eef18 100644 --- a/drivers/staging/unisys/visornic/visornic_main.c +++ b/drivers/staging/unisys/visornic/visornic_main.c @@ -39,9 +39,9 @@ /* GUIDS for director channel type supported by this driver. */ static struct visor_channeltype_descriptor visornic_channel_types[] = { /* Note that the only channel type we expect to be reported by the - * bus driver is the SPAR_VNIC channel. + * bus driver is the VISOR_VNIC channel. */ - { SPAR_VNIC_CHANNEL_PROTOCOL_UUID, "ultravnic" }, + { VISOR_VNIC_CHANNEL_UUID, "ultravnic" }, { NULL_UUID_LE, NULL } }; MODULE_DEVICE_TABLE(visorbus, visornic_channel_types); @@ -52,7 +52,7 @@ MODULE_DEVICE_TABLE(visorbus, visornic_channel_types); * must be added to scripts/mode/file2alias.c, etc., to get this working * properly. */ -MODULE_ALIAS("visorbus:" SPAR_VNIC_CHANNEL_PROTOCOL_UUID_STR); +MODULE_ALIAS("visorbus:" VISOR_VNIC_CHANNEL_UUID_STR); struct chanstat { unsigned long got_rcv; @@ -1807,8 +1807,7 @@ static int visornic_probe(struct visor_device *dev) /* Get MAC address from channel and read it into the device. */ netdev->addr_len = ETH_ALEN; - channel_offset = offsetof(struct spar_io_channel_protocol, - vnic.macaddr); + channel_offset = offsetof(struct visor_io_channel, vnic.macaddr); err = visorbus_read_channel(dev, channel_offset, netdev->dev_addr, ETH_ALEN); if (err < 0) { @@ -1836,8 +1835,7 @@ static int visornic_probe(struct visor_device *dev) atomic_set(&devdata->usage, 1); /* Setup rcv bufs */ - channel_offset = offsetof(struct spar_io_channel_protocol, - vnic.num_rcv_bufs); + channel_offset = offsetof(struct visor_io_channel, vnic.num_rcv_bufs); err = visorbus_read_channel(dev, channel_offset, &devdata->num_rcv_bufs, 4); if (err) { @@ -1884,8 +1882,7 @@ static int visornic_probe(struct visor_device *dev) devdata->server_change_state = false; /*set the default mtu */ - channel_offset = offsetof(struct spar_io_channel_protocol, - vnic.mtu); + channel_offset = offsetof(struct visor_io_channel, vnic.mtu); err = visorbus_read_channel(dev, channel_offset, &netdev->mtu, 4); if (err) { dev_err(&dev->device, @@ -1906,7 +1903,7 @@ static int visornic_probe(struct visor_device *dev) */ mod_timer(&devdata->irq_poll_timer, msecs_to_jiffies(2)); - channel_offset = offsetof(struct spar_io_channel_protocol, + channel_offset = offsetof(struct visor_io_channel, channel_header.features); err = visorbus_read_channel(dev, channel_offset, &features, 8); if (err) { @@ -1916,8 +1913,8 @@ static int visornic_probe(struct visor_device *dev) goto cleanup_napi_add; } - features |= ULTRA_IO_CHANNEL_IS_POLLING; - features |= ULTRA_IO_DRIVER_SUPPORTS_ENHANCED_RCVBUF_CHECKING; + features |= VISOR_CHANNEL_IS_POLLING; + features |= VISOR_DRIVER_ENHANCED_RCVBUF_CHECKING; err = visorbus_write_channel(dev, channel_offset, &features, 8); if (err) { dev_err(&dev->device, @@ -2115,7 +2112,7 @@ static int visornic_resume(struct visor_device *dev, return 0; } -/* This is used to tell the visor bus driver which types of visor devices +/* This is used to tell the visorbus driver which types of visor devices * we support, and what functions to call when a visor device that we support * is attached or removed. */ diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c index d04db3f55519..0159ca4407d8 100644 --- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c +++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c @@ -153,7 +153,6 @@ int vchiq_platform_init(struct platform_device *pdev, VCHIQ_STATE_T *state) MAX_FRAGMENTS; g_fragments_base = (char *)slot_mem + slot_mem_size; - slot_mem_size += frag_mem_size; g_free_fragments = g_fragments_base; for (i = 0; i < (MAX_FRAGMENTS - 1); i++) { @@ -365,7 +364,7 @@ vchiq_doorbell_irq(int irq, void *dev_id) } static void -cleaup_pagelistinfo(struct vchiq_pagelist_info *pagelistinfo) +cleanup_pagelistinfo(struct vchiq_pagelist_info *pagelistinfo) { if (pagelistinfo->scatterlist_mapped) { dma_unmap_sg(g_dev, pagelistinfo->scatterlist, @@ -460,6 +459,11 @@ create_pagelist(char __user *buf, size_t count, unsigned short type, PAGE_SIZE)); size_t bytes = PAGE_SIZE - off; + if (!pg) { + cleanup_pagelistinfo(pagelistinfo); + return NULL; + } + if (bytes > length) bytes = length; pages[actual_pages] = pg; @@ -470,7 +474,7 @@ create_pagelist(char __user *buf, size_t count, unsigned short type, } else { down_read(&task->mm->mmap_sem); actual_pages = get_user_pages( - (unsigned long)buf & ~(PAGE_SIZE - 1), + (unsigned long)buf & PAGE_MASK, num_pages, (type == PAGELIST_READ) ? FOLL_WRITE : 0, pages, @@ -489,7 +493,7 @@ create_pagelist(char __user *buf, size_t count, unsigned short type, actual_pages--; put_page(pages[actual_pages]); } - cleaup_pagelistinfo(pagelistinfo); + cleanup_pagelistinfo(pagelistinfo); return NULL; } /* release user pages */ @@ -518,7 +522,7 @@ create_pagelist(char __user *buf, size_t count, unsigned short type, pagelistinfo->dma_dir); if (dma_buffers == 0) { - cleaup_pagelistinfo(pagelistinfo); + cleanup_pagelistinfo(pagelistinfo); return NULL; } @@ -555,7 +559,7 @@ create_pagelist(char __user *buf, size_t count, unsigned short type, char *fragments; if (down_interruptible(&g_free_fragments_sema) != 0) { - cleaup_pagelistinfo(pagelistinfo); + cleanup_pagelistinfo(pagelistinfo); return NULL; } @@ -577,7 +581,6 @@ static void free_pagelist(struct vchiq_pagelist_info *pagelistinfo, int actual) { - unsigned int i; PAGELIST_T *pagelist = pagelistinfo->pagelist; struct page **pages = pagelistinfo->pages; unsigned int num_pages = pagelistinfo->num_pages; @@ -633,9 +636,11 @@ free_pagelist(struct vchiq_pagelist_info *pagelistinfo, /* Need to mark all the pages dirty. */ if (pagelist->type != PAGELIST_WRITE && pagelistinfo->pages_need_release) { + unsigned int i; + for (i = 0; i < num_pages; i++) set_page_dirty(pages[i]); } - cleaup_pagelistinfo(pagelistinfo); + cleanup_pagelistinfo(pagelistinfo); } diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c index e823f1d5d177..030bec855d86 100644 --- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c +++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_arm.c @@ -2070,7 +2070,7 @@ dump_phys_mem(void *virt_addr, u32 num_bytes) struct page **pages; u8 *kmapped_virt_ptr; - /* Align virtAddr and endVirtAddr to 16 byte boundaries. */ + /* Align virt_addr and end_virt_addr to 16 byte boundaries. */ virt_addr = (void *)((unsigned long)virt_addr & ~0x0fuL); end_virt_addr = (void *)(((unsigned long)end_virt_addr + 15uL) & @@ -3276,12 +3276,12 @@ vchiq_dump_service_use_state(VCHIQ_STATE_T *state) if (only_nonzero && !service_ptr->service_use_count) continue; - if (service_ptr->srvstate != VCHIQ_SRVSTATE_FREE) { - service_data[j].fourcc = service_ptr->base.fourcc; - service_data[j].clientid = service_ptr->client_id; - service_data[j++].use_count = service_ptr-> - service_use_count; - } + if (service_ptr->srvstate == VCHIQ_SRVSTATE_FREE) + continue; + + service_data[j].fourcc = service_ptr->base.fourcc; + service_data[j].clientid = service_ptr->client_id; + service_data[j++].use_count = service_ptr->service_use_count; } read_unlock_bh(&arm_state->susp_res_lock); diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c index 4f9e738abddf..486be990d7fc 100644 --- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c +++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_core.c @@ -175,7 +175,7 @@ find_service_by_handle(VCHIQ_SERVICE_HANDLE_T handle) service = handle_to_service(handle); if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE) && (service->handle == handle)) { - BUG_ON(service->ref_count == 0); + WARN_ON(service->ref_count == 0); service->ref_count++; } else service = NULL; @@ -197,7 +197,7 @@ find_service_by_port(VCHIQ_STATE_T *state, int localport) spin_lock(&service_spinlock); service = state->services[localport]; if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE)) { - BUG_ON(service->ref_count == 0); + WARN_ON(service->ref_count == 0); service->ref_count++; } else service = NULL; @@ -221,7 +221,7 @@ find_service_for_instance(VCHIQ_INSTANCE_T instance, if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE) && (service->handle == handle) && (service->instance == instance)) { - BUG_ON(service->ref_count == 0); + WARN_ON(service->ref_count == 0); service->ref_count++; } else service = NULL; @@ -246,7 +246,7 @@ find_closed_service_for_instance(VCHIQ_INSTANCE_T instance, (service->srvstate == VCHIQ_SRVSTATE_CLOSED)) && (service->handle == handle) && (service->instance == instance)) { - BUG_ON(service->ref_count == 0); + WARN_ON(service->ref_count == 0); service->ref_count++; } else service = NULL; @@ -273,7 +273,7 @@ next_service_by_instance(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance, if (srv && (srv->srvstate != VCHIQ_SRVSTATE_FREE) && (srv->instance == instance)) { service = srv; - BUG_ON(service->ref_count == 0); + WARN_ON(service->ref_count == 0); service->ref_count++; break; } @@ -289,9 +289,11 @@ void lock_service(VCHIQ_SERVICE_T *service) { spin_lock(&service_spinlock); - BUG_ON(!service || (service->ref_count == 0)); - if (service) + WARN_ON(!service); + if (service) { + WARN_ON(service->ref_count == 0); service->ref_count++; + } spin_unlock(&service_spinlock); } @@ -299,17 +301,24 @@ void unlock_service(VCHIQ_SERVICE_T *service) { spin_lock(&service_spinlock); - BUG_ON(!service || (service->ref_count == 0)); - if (service && service->ref_count) { - service->ref_count--; - if (!service->ref_count) { - VCHIQ_STATE_T *state = service->state; - - BUG_ON(service->srvstate != VCHIQ_SRVSTATE_FREE); - state->services[service->localport] = NULL; - } else - service = NULL; + if (!service) { + WARN(1, "%s: service is NULL\n", __func__); + goto unlock; + } + if (!service->ref_count) { + WARN(1, "%s: ref_count is zero\n", __func__); + goto unlock; } + service->ref_count--; + if (!service->ref_count) { + VCHIQ_STATE_T *state = service->state; + + WARN_ON(service->srvstate != VCHIQ_SRVSTATE_FREE); + state->services[service->localport] = NULL; + } else { + service = NULL; + } +unlock: spin_unlock(&service_spinlock); if (service && service->userdata_term) @@ -591,8 +600,10 @@ reserve_space(VCHIQ_STATE_T *state, size_t space, int is_blocking) return NULL; /* No space available */ } - BUG_ON(tx_pos == - (state->slot_queue_available * VCHIQ_SLOT_SIZE)); + if (tx_pos == (state->slot_queue_available * VCHIQ_SLOT_SIZE)) { + pr_warn("%s: invalid tx_pos: %d\n", __func__, tx_pos); + return NULL; + } slot_index = local->slot_queue[ SLOT_QUEUE_INDEX_FROM_POS(tx_pos) & @@ -822,9 +833,14 @@ queue_message(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, if (type == VCHIQ_MSG_DATA) { int tx_end_index; - BUG_ON(!service); - BUG_ON((flags & (QMFLAGS_NO_MUTEX_LOCK | - QMFLAGS_NO_MUTEX_UNLOCK)) != 0); + if (!service) { + WARN(1, "%s: service is NULL\n", __func__); + mutex_unlock(&state->slot_mutex); + return VCHIQ_ERROR; + } + + WARN_ON((flags & (QMFLAGS_NO_MUTEX_LOCK | + QMFLAGS_NO_MUTEX_UNLOCK)) != 0); if (service->closing) { /* The service has been closed */ @@ -923,9 +939,8 @@ queue_message(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, header, size, VCHIQ_MSG_SRCPORT(msgid), VCHIQ_MSG_DSTPORT(msgid)); - BUG_ON(!service); - BUG_ON((flags & (QMFLAGS_NO_MUTEX_LOCK | - QMFLAGS_NO_MUTEX_UNLOCK)) != 0); + WARN_ON((flags & (QMFLAGS_NO_MUTEX_LOCK | + QMFLAGS_NO_MUTEX_UNLOCK)) != 0); callback_result = copy_message_data(copy_callback, context, @@ -1376,7 +1391,6 @@ resolve_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue) { VCHIQ_STATE_T *state = service->state; int resolved = 0; - int rc; while ((queue->process != queue->local_insert) && (queue->process != queue->remote_insert)) { @@ -1392,8 +1406,7 @@ resolve_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue) WARN_ON(!((int)(queue->local_insert - queue->process) > 0)); WARN_ON(!((int)(queue->remote_insert - queue->process) > 0)); - rc = mutex_lock_killable(&state->bulk_transfer_mutex); - if (rc != 0) + if (mutex_lock_killable(&state->bulk_transfer_mutex)) break; vchiq_transfer_bulk(bulk); @@ -1952,9 +1965,14 @@ parse_rx_slots(VCHIQ_STATE_T *state) mutex_unlock(&service->bulk_mutex); break; } - - BUG_ON(queue->process == queue->local_insert); - BUG_ON(queue->process != queue->remote_insert); + if (queue->process != queue->remote_insert) { + pr_err("%s: p %x != ri %x\n", + __func__, + queue->process, + queue->remote_insert); + mutex_unlock(&service->bulk_mutex); + goto bail_not_ready; + } bulk = &queue->bulks[ BULK_INDEX(queue->remote_insert)]; @@ -2139,7 +2157,6 @@ slot_handler_func(void *v) vchiq_log_error(vchiq_core_log_level, "Failed to send RESUME " "message"); - BUG(); } break; @@ -2351,13 +2368,17 @@ vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero, VCHIQ_SHARED_STATE_T *remote; VCHIQ_STATUS_T status; char threadname[16]; - static int id; int i; vchiq_log_warning(vchiq_core_log_level, "%s: slot_zero = %pK, is_master = %d", __func__, slot_zero, is_master); + if (vchiq_states[0]) { + pr_err("%s: VCHIQ state already initialized\n", __func__); + return VCHIQ_ERROR; + } + /* Check the input configuration */ if (slot_zero->magic != VCHIQ_MAGIC) { @@ -2439,7 +2460,6 @@ vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero, memset(state, 0, sizeof(VCHIQ_STATE_T)); - state->id = id++; state->is_master = is_master; /* @@ -2558,8 +2578,7 @@ vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero, set_user_nice(state->sync_thread, -20); wake_up_process(state->sync_thread); - BUG_ON(state->id >= VCHIQ_MAX_STATES); - vchiq_states[state->id] = state; + vchiq_states[0] = state; /* Indicate readiness to the other side */ local->initialised = 1; @@ -3185,7 +3204,7 @@ vchiq_close_service(VCHIQ_SERVICE_HANDLE_T handle) if (current == service->state->slot_handler_thread) { status = vchiq_close_service_internal(service, 0/*!close_recvd*/); - BUG_ON(status == VCHIQ_RETRY); + WARN_ON(status == VCHIQ_RETRY); } else { /* Mark the service for termination by the slot handler */ request_poll(service->state, service, VCHIQ_POLL_TERMINATE); @@ -3247,7 +3266,7 @@ vchiq_remove_service(VCHIQ_SERVICE_HANDLE_T handle) status = vchiq_close_service_internal(service, 0/*!close_recvd*/); - BUG_ON(status == VCHIQ_RETRY); + WARN_ON(status == VCHIQ_RETRY); } else { /* Mark the service for removal by the slot handler */ request_poll(service->state, service, VCHIQ_POLL_REMOVE); diff --git a/drivers/staging/vme/devices/vme_pio2.h b/drivers/staging/vme/devices/vme_pio2.h index 5577df3199e7..ac4a4bad4091 100644 --- a/drivers/staging/vme/devices/vme_pio2.h +++ b/drivers/staging/vme/devices/vme_pio2.h @@ -68,38 +68,38 @@ static const int PIO2_CHANNEL_BANK[32] = { 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3 }; -#define PIO2_CHANNEL0_BIT (1 << 0) -#define PIO2_CHANNEL1_BIT (1 << 1) -#define PIO2_CHANNEL2_BIT (1 << 2) -#define PIO2_CHANNEL3_BIT (1 << 3) -#define PIO2_CHANNEL4_BIT (1 << 4) -#define PIO2_CHANNEL5_BIT (1 << 5) -#define PIO2_CHANNEL6_BIT (1 << 6) -#define PIO2_CHANNEL7_BIT (1 << 7) -#define PIO2_CHANNEL8_BIT (1 << 0) -#define PIO2_CHANNEL9_BIT (1 << 1) -#define PIO2_CHANNEL10_BIT (1 << 2) -#define PIO2_CHANNEL11_BIT (1 << 3) -#define PIO2_CHANNEL12_BIT (1 << 4) -#define PIO2_CHANNEL13_BIT (1 << 5) -#define PIO2_CHANNEL14_BIT (1 << 6) -#define PIO2_CHANNEL15_BIT (1 << 7) -#define PIO2_CHANNEL16_BIT (1 << 0) -#define PIO2_CHANNEL17_BIT (1 << 1) -#define PIO2_CHANNEL18_BIT (1 << 2) -#define PIO2_CHANNEL19_BIT (1 << 3) -#define PIO2_CHANNEL20_BIT (1 << 4) -#define PIO2_CHANNEL21_BIT (1 << 5) -#define PIO2_CHANNEL22_BIT (1 << 6) -#define PIO2_CHANNEL23_BIT (1 << 7) -#define PIO2_CHANNEL24_BIT (1 << 0) -#define PIO2_CHANNEL25_BIT (1 << 1) -#define PIO2_CHANNEL26_BIT (1 << 2) -#define PIO2_CHANNEL27_BIT (1 << 3) -#define PIO2_CHANNEL28_BIT (1 << 4) -#define PIO2_CHANNEL29_BIT (1 << 5) -#define PIO2_CHANNEL30_BIT (1 << 6) -#define PIO2_CHANNEL31_BIT (1 << 7) +#define PIO2_CHANNEL0_BIT BIT(0) +#define PIO2_CHANNEL1_BIT BIT(1) +#define PIO2_CHANNEL2_BIT BIT(2) +#define PIO2_CHANNEL3_BIT BIT(3) +#define PIO2_CHANNEL4_BIT BIT(4) +#define PIO2_CHANNEL5_BIT BIT(5) +#define PIO2_CHANNEL6_BIT BIT(6) +#define PIO2_CHANNEL7_BIT BIT(7) +#define PIO2_CHANNEL8_BIT BIT(0) +#define PIO2_CHANNEL9_BIT BIT(1) +#define PIO2_CHANNEL10_BIT BIT(2) +#define PIO2_CHANNEL11_BIT BIT(3) +#define PIO2_CHANNEL12_BIT BIT(4) +#define PIO2_CHANNEL13_BIT BIT(5) +#define PIO2_CHANNEL14_BIT BIT(6) +#define PIO2_CHANNEL15_BIT BIT(7) +#define PIO2_CHANNEL16_BIT BIT(0) +#define PIO2_CHANNEL17_BIT BIT(1) +#define PIO2_CHANNEL18_BIT BIT(2) +#define PIO2_CHANNEL19_BIT BIT(3) +#define PIO2_CHANNEL20_BIT BIT(4) +#define PIO2_CHANNEL21_BIT BIT(5) +#define PIO2_CHANNEL22_BIT BIT(6) +#define PIO2_CHANNEL23_BIT BIT(7) +#define PIO2_CHANNEL24_BIT BIT(0) +#define PIO2_CHANNEL25_BIT BIT(1) +#define PIO2_CHANNEL26_BIT BIT(2) +#define PIO2_CHANNEL27_BIT BIT(3) +#define PIO2_CHANNEL28_BIT BIT(4) +#define PIO2_CHANNEL29_BIT BIT(5) +#define PIO2_CHANNEL30_BIT BIT(6) +#define PIO2_CHANNEL31_BIT BIT(7) static const int PIO2_CHANNEL_BIT[32] = { PIO2_CHANNEL0_BIT, PIO2_CHANNEL1_BIT, PIO2_CHANNEL2_BIT, PIO2_CHANNEL3_BIT, @@ -120,12 +120,12 @@ static const int PIO2_CHANNEL_BIT[32] = { PIO2_CHANNEL0_BIT, PIO2_CHANNEL1_BIT, }; /* PIO2_REGS_INT_STAT_CNTR (0xc) */ -#define PIO2_COUNTER0 (1 << 0) -#define PIO2_COUNTER1 (1 << 1) -#define PIO2_COUNTER2 (1 << 2) -#define PIO2_COUNTER3 (1 << 3) -#define PIO2_COUNTER4 (1 << 4) -#define PIO2_COUNTER5 (1 << 5) +#define PIO2_COUNTER0 BIT(0) +#define PIO2_COUNTER1 BIT(1) +#define PIO2_COUNTER2 BIT(2) +#define PIO2_COUNTER3 BIT(3) +#define PIO2_COUNTER4 BIT(4) +#define PIO2_COUNTER5 BIT(5) static const int PIO2_COUNTER[6] = { PIO2_COUNTER0, PIO2_COUNTER1, PIO2_COUNTER2, PIO2_COUNTER3, @@ -133,8 +133,8 @@ static const int PIO2_COUNTER[6] = { PIO2_COUNTER0, PIO2_COUNTER1, /* PIO2_REGS_CTRL (0x18) */ #define PIO2_VME_INT_MASK 0x7 -#define PIO2_LED (1 << 6) -#define PIO2_LOOP (1 << 7) +#define PIO2_LED BIT(6) +#define PIO2_LOOP BIT(7) /* PIO2_REGS_VME_VECTOR (0x19) */ #define PIO2_VME_VECTOR_SPUR 0x0 diff --git a/drivers/staging/vt6655/card.c b/drivers/staging/vt6655/card.c index 5463cf869d1b..f5db2b3d9045 100644 --- a/drivers/staging/vt6655/card.c +++ b/drivers/staging/vt6655/card.c @@ -913,7 +913,7 @@ u64 CARDqGetTSFOffset(unsigned char byRxRate, u64 qwTSF1, u64 qwTSF2) { unsigned short wRxBcnTSFOffst; - wRxBcnTSFOffst = cwRXBCNTSFOff[byRxRate%MAX_RATE]; + wRxBcnTSFOffst = cwRXBCNTSFOff[byRxRate % MAX_RATE]; qwTSF2 += (u64)wRxBcnTSFOffst; diff --git a/drivers/staging/vt6655/card.h b/drivers/staging/vt6655/card.h index 44420b5a445f..1a04dbb57d42 100644 --- a/drivers/staging/vt6655/card.h +++ b/drivers/staging/vt6655/card.h @@ -63,26 +63,26 @@ typedef enum _CARD_STATUS_TYPE { struct vnt_private; -void CARDvSetRSPINF(struct vnt_private *, u8); -void CARDvUpdateBasicTopRate(struct vnt_private *); -bool CARDbIsOFDMinBasicRate(struct vnt_private *); -void CARDvSetLoopbackMode(struct vnt_private *, unsigned short wLoopbackMode); -bool CARDbSoftwareReset(struct vnt_private *); -void CARDvSetFirstNextTBTT(struct vnt_private *, +void CARDvSetRSPINF(struct vnt_private *priv, u8 bb_type); +void CARDvUpdateBasicTopRate(struct vnt_private *priv); +bool CARDbIsOFDMinBasicRate(struct vnt_private *priv); +void CARDvSetLoopbackMode(struct vnt_private *priv, unsigned short wLoopbackMode); +bool CARDbSoftwareReset(struct vnt_private *priv); +void CARDvSetFirstNextTBTT(struct vnt_private *priv, unsigned short wBeaconInterval); -void CARDvUpdateNextTBTT(struct vnt_private *, u64 qwTSF, +void CARDvUpdateNextTBTT(struct vnt_private *priv, u64 qwTSF, unsigned short wBeaconInterval); -bool CARDbGetCurrentTSF(struct vnt_private *, u64 *pqwCurrTSF); +bool CARDbGetCurrentTSF(struct vnt_private *priv, u64 *pqwCurrTSF); u64 CARDqGetNextTBTT(u64 qwTSF, unsigned short wBeaconInterval); u64 CARDqGetTSFOffset(unsigned char byRxRate, u64 qwTSF1, u64 qwTSF2); -unsigned char CARDbyGetPktType(struct vnt_private *); -void CARDvSafeResetTx(struct vnt_private *); -void CARDvSafeResetRx(struct vnt_private *); -bool CARDbRadioPowerOff(struct vnt_private *); -bool CARDbRadioPowerOn(struct vnt_private *); -bool CARDbSetPhyParameter(struct vnt_private *, u8); -bool CARDbUpdateTSF(struct vnt_private *, unsigned char byRxRate, +unsigned char CARDbyGetPktType(struct vnt_private *priv); +void CARDvSafeResetTx(struct vnt_private *priv); +void CARDvSafeResetRx(struct vnt_private *priv); +bool CARDbRadioPowerOff(struct vnt_private *priv); +bool CARDbRadioPowerOn(struct vnt_private *priv); +bool CARDbSetPhyParameter(struct vnt_private *priv, u8 bb_type); +bool CARDbUpdateTSF(struct vnt_private *priv, unsigned char byRxRate, u64 qwBSSTimestamp); -bool CARDbSetBeaconPeriod(struct vnt_private *, unsigned short wBeaconInterval); +bool CARDbSetBeaconPeriod(struct vnt_private *priv, unsigned short wBeaconInterval); #endif /* __CARD_H__ */ diff --git a/drivers/staging/vt6655/channel.h b/drivers/staging/vt6655/channel.h index 2621dfabff06..8fe70760e548 100644 --- a/drivers/staging/vt6655/channel.h +++ b/drivers/staging/vt6655/channel.h @@ -21,8 +21,8 @@ #include "card.h" -void vnt_init_bands(struct vnt_private *); +void vnt_init_bands(struct vnt_private *priv); -bool set_channel(struct vnt_private *, struct ieee80211_channel *); +bool set_channel(struct vnt_private *priv, struct ieee80211_channel *ch); #endif /* _CHANNEL_H_ */ diff --git a/drivers/staging/vt6655/device_main.c b/drivers/staging/vt6655/device_main.c index da0f71191009..9fcf2e223f71 100644 --- a/drivers/staging/vt6655/device_main.c +++ b/drivers/staging/vt6655/device_main.c @@ -157,7 +157,7 @@ static void vt6655_remove(struct pci_dev *pcid) { struct vnt_private *priv = pci_get_drvdata(pcid); - if (priv == NULL) + if (!priv) return; device_free_info(priv); } @@ -453,7 +453,7 @@ static bool device_init_rings(struct vnt_private *priv) priv->opts.tx_descs[0] * sizeof(struct vnt_tx_desc) + priv->opts.tx_descs[1] * sizeof(struct vnt_tx_desc), &priv->pool_dma, GFP_ATOMIC); - if (vir_pool == NULL) { + if (!vir_pool) { dev_err(&priv->pcid->dev, "allocate desc dma memory failed\n"); return false; } @@ -1018,7 +1018,6 @@ static void vnt_interrupt_process(struct vnt_private *priv) } /* TODO: adhoc PS mode */ - } if (isr & ISR_BNTX) { @@ -1311,8 +1310,8 @@ static int vnt_config(struct ieee80211_hw *hw, u32 changed) } static void vnt_bss_info_changed(struct ieee80211_hw *hw, - struct ieee80211_vif *vif, struct ieee80211_bss_conf *conf, - u32 changed) + struct ieee80211_vif *vif, + struct ieee80211_bss_conf *conf, u32 changed) { struct vnt_private *priv = hw->priv; @@ -1402,7 +1401,7 @@ static void vnt_bss_info_changed(struct ieee80211_hw *hw, } static u64 vnt_prepare_multicast(struct ieee80211_hw *hw, - struct netdev_hw_addr_list *mc_list) + struct netdev_hw_addr_list *mc_list) { struct vnt_private *priv = hw->priv; struct netdev_hw_addr *ha; @@ -1421,7 +1420,8 @@ static u64 vnt_prepare_multicast(struct ieee80211_hw *hw, } static void vnt_configure(struct ieee80211_hw *hw, - unsigned int changed_flags, unsigned int *total_flags, u64 multicast) + unsigned int changed_flags, + unsigned int *total_flags, u64 multicast) { struct vnt_private *priv = hw->priv; u8 rx_mode = 0; @@ -1482,8 +1482,8 @@ static void vnt_configure(struct ieee80211_hw *hw, } static int vnt_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, - struct ieee80211_vif *vif, struct ieee80211_sta *sta, - struct ieee80211_key_conf *key) + struct ieee80211_vif *vif, struct ieee80211_sta *sta, + struct ieee80211_key_conf *key) { struct vnt_private *priv = hw->priv; @@ -1702,7 +1702,6 @@ static int vt6655_suspend(struct pci_dev *pcid, pm_message_t state) static int vt6655_resume(struct pci_dev *pcid) { - pci_set_power_state(pcid, PCI_D0); pci_enable_wake(pcid, PCI_D0, 0); pci_restore_state(pcid); diff --git a/drivers/staging/vt6655/key.c b/drivers/staging/vt6655/key.c index dad9e292d4da..d7ede73a1a01 100644 --- a/drivers/staging/vt6655/key.c +++ b/drivers/staging/vt6655/key.c @@ -27,8 +27,8 @@ #include "mac.h" static int vnt_set_keymode(struct ieee80211_hw *hw, u8 *mac_addr, - struct ieee80211_key_conf *key, u32 key_type, u32 mode, - bool onfly_latch) + struct ieee80211_key_conf *key, u32 key_type, + u32 mode, bool onfly_latch) { struct vnt_private *priv = hw->priv; u8 broadcast[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; diff --git a/drivers/staging/vt6655/mac.h b/drivers/staging/vt6655/mac.h index 33b758cb79d4..db401e32ae23 100644 --- a/drivers/staging/vt6655/mac.h +++ b/drivers/staging/vt6655/mac.h @@ -885,57 +885,57 @@ do { \ #define MACvSetRFLE_LatchBase(iobase) \ MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_RFLEOPT) -bool MACbIsRegBitsOn(struct vnt_private *, unsigned char byRegOfs, +bool MACbIsRegBitsOn(struct vnt_private *priv, unsigned char byRegOfs, unsigned char byTestBits); -bool MACbIsRegBitsOff(struct vnt_private *, unsigned char byRegOfs, +bool MACbIsRegBitsOff(struct vnt_private *priv, unsigned char byRegOfs, unsigned char byTestBits); -bool MACbIsIntDisable(struct vnt_private *); +bool MACbIsIntDisable(struct vnt_private *priv); -void MACvSetShortRetryLimit(struct vnt_private *, unsigned char byRetryLimit); +void MACvSetShortRetryLimit(struct vnt_private *priv, unsigned char byRetryLimit); -void MACvSetLongRetryLimit(struct vnt_private *, unsigned char byRetryLimit); -void MACvGetLongRetryLimit(struct vnt_private *, +void MACvSetLongRetryLimit(struct vnt_private *priv, unsigned char byRetryLimit); +void MACvGetLongRetryLimit(struct vnt_private *priv, unsigned char *pbyRetryLimit); -void MACvSetLoopbackMode(struct vnt_private *, unsigned char byLoopbackMode); +void MACvSetLoopbackMode(struct vnt_private *priv, unsigned char byLoopbackMode); -void MACvSaveContext(struct vnt_private *, unsigned char *pbyCxtBuf); -void MACvRestoreContext(struct vnt_private *, unsigned char *pbyCxtBuf); +void MACvSaveContext(struct vnt_private *priv, unsigned char *pbyCxtBuf); +void MACvRestoreContext(struct vnt_private *priv, unsigned char *pbyCxtBuf); -bool MACbSoftwareReset(struct vnt_private *); -bool MACbSafeSoftwareReset(struct vnt_private *); -bool MACbSafeRxOff(struct vnt_private *); -bool MACbSafeTxOff(struct vnt_private *); -bool MACbSafeStop(struct vnt_private *); -bool MACbShutdown(struct vnt_private *); -void MACvInitialize(struct vnt_private *); -void MACvSetCurrRx0DescAddr(struct vnt_private *, +bool MACbSoftwareReset(struct vnt_private *priv); +bool MACbSafeSoftwareReset(struct vnt_private *priv); +bool MACbSafeRxOff(struct vnt_private *priv); +bool MACbSafeTxOff(struct vnt_private *priv); +bool MACbSafeStop(struct vnt_private *priv); +bool MACbShutdown(struct vnt_private *priv); +void MACvInitialize(struct vnt_private *priv); +void MACvSetCurrRx0DescAddr(struct vnt_private *priv, u32 curr_desc_addr); -void MACvSetCurrRx1DescAddr(struct vnt_private *, +void MACvSetCurrRx1DescAddr(struct vnt_private *priv, u32 curr_desc_addr); -void MACvSetCurrTXDescAddr(int iTxType, struct vnt_private *, +void MACvSetCurrTXDescAddr(int iTxType, struct vnt_private *priv, u32 curr_desc_addr); -void MACvSetCurrTx0DescAddrEx(struct vnt_private *, +void MACvSetCurrTx0DescAddrEx(struct vnt_private *priv, u32 curr_desc_addr); -void MACvSetCurrAC0DescAddrEx(struct vnt_private *, +void MACvSetCurrAC0DescAddrEx(struct vnt_private *priv, u32 curr_desc_addr); -void MACvSetCurrSyncDescAddrEx(struct vnt_private *, +void MACvSetCurrSyncDescAddrEx(struct vnt_private *priv, u32 curr_desc_addr); -void MACvSetCurrATIMDescAddrEx(struct vnt_private *, +void MACvSetCurrATIMDescAddrEx(struct vnt_private *priv, u32 curr_desc_addr); -void MACvTimer0MicroSDelay(struct vnt_private *, unsigned int uDelay); -void MACvOneShotTimer1MicroSec(struct vnt_private *, unsigned int uDelayTime); +void MACvTimer0MicroSDelay(struct vnt_private *priv, unsigned int uDelay); +void MACvOneShotTimer1MicroSec(struct vnt_private *priv, unsigned int uDelayTime); -void MACvSetMISCFifo(struct vnt_private *, unsigned short wOffset, +void MACvSetMISCFifo(struct vnt_private *priv, unsigned short wOffset, u32 dwData); -bool MACbPSWakeup(struct vnt_private *); +bool MACbPSWakeup(struct vnt_private *priv); -void MACvSetKeyEntry(struct vnt_private *, unsigned short wKeyCtl, +void MACvSetKeyEntry(struct vnt_private *priv, unsigned short wKeyCtl, unsigned int uEntryIdx, unsigned int uKeyIdx, unsigned char *pbyAddr, u32 *pdwKey, unsigned char byLocalID); -void MACvDisableKeyEntry(struct vnt_private *, unsigned int uEntryIdx); +void MACvDisableKeyEntry(struct vnt_private *priv, unsigned int uEntryIdx); #endif /* __MAC_H__ */ diff --git a/drivers/staging/vt6655/power.h b/drivers/staging/vt6655/power.h index dfcb0ca8b448..f360c5966523 100644 --- a/drivers/staging/vt6655/power.h +++ b/drivers/staging/vt6655/power.h @@ -31,20 +31,10 @@ #define PS_FAST_INTERVAL 1 /* Fast power saving listen interval */ #define PS_MAX_INTERVAL 4 /* MAX power saving listen interval */ -void -PSvDisablePowerSaving( - struct vnt_private * -); +void PSvDisablePowerSaving(struct vnt_private *priv); -void -PSvEnablePowerSaving( - struct vnt_private *, - unsigned short wListenInterval -); +void PSvEnablePowerSaving(struct vnt_private *priv, unsigned short wListenInterval); -bool -PSbIsNextTBTTWakeUp( - struct vnt_private * -); +bool PSbIsNextTBTTWakeUp(struct vnt_private *priv); #endif /* __POWER_H__ */ diff --git a/drivers/staging/vt6655/rf.h b/drivers/staging/vt6655/rf.h index 37600093cab2..ba222301d49d 100644 --- a/drivers/staging/vt6655/rf.h +++ b/drivers/staging/vt6655/rf.h @@ -68,28 +68,28 @@ /*--------------------- Export Functions --------------------------*/ -bool IFRFbWriteEmbedded(struct vnt_private *, unsigned long dwData); -bool RFbSelectChannel(struct vnt_private *, unsigned char byRFType, u16); +bool IFRFbWriteEmbedded(struct vnt_private *priv, unsigned long dwData); +bool RFbSelectChannel(struct vnt_private *priv, unsigned char byRFType, u16 byChannel); bool RFbInit( - struct vnt_private * + struct vnt_private *priv ); -bool RFvWriteWakeProgSyn(struct vnt_private *, unsigned char byRFType, u16); -bool RFbSetPower(struct vnt_private *, unsigned int rate, u16); +bool RFvWriteWakeProgSyn(struct vnt_private *priv, unsigned char byRFType, u16 uChannel); +bool RFbSetPower(struct vnt_private *priv, unsigned int rate, u16 uCH); bool RFbRawSetPower( - struct vnt_private *, + struct vnt_private *priv, unsigned char byPwr, unsigned int rate ); void RFvRSSITodBm( - struct vnt_private *, + struct vnt_private *priv, unsigned char byCurrRSSI, long *pldBm ); /* {{ RobertYu: 20050104 */ -bool RFbAL7230SelectChannelPostProcess(struct vnt_private *, u16, u16); +bool RFbAL7230SelectChannelPostProcess(struct vnt_private *priv, u16 byOldChannel, u16 byNewChannel); /* }} RobertYu */ #endif /* __RF_H__ */ diff --git a/drivers/staging/vt6656/card.c b/drivers/staging/vt6656/card.c index 0e5a99375099..c61422ea8846 100644 --- a/drivers/staging/vt6656/card.c +++ b/drivers/staging/vt6656/card.c @@ -359,35 +359,18 @@ void vnt_update_ifs(struct vnt_private *priv) priv->sifs = C_SIFS_A; priv->difs = C_SIFS_A + 2 * C_SLOT_SHORT; max_min = 4; - } else if (priv->packet_type == PK_TYPE_11B) { - priv->slot = C_SLOT_LONG; - priv->sifs = C_SIFS_BG; - priv->difs = C_SIFS_BG + 2 * C_SLOT_LONG; - max_min = 5; - } else {/* PK_TYPE_11GA & PK_TYPE_11GB */ - bool ofdm_rate = false; - unsigned int ii = 0; - + } else { priv->sifs = C_SIFS_BG; - if (priv->short_slot_time) + if (priv->short_slot_time) { priv->slot = C_SLOT_SHORT; - else + max_min = 4; + } else { priv->slot = C_SLOT_LONG; - - priv->difs = C_SIFS_BG + 2 * priv->slot; - - for (ii = RATE_54M; ii >= RATE_6M; ii--) { - if (priv->basic_rates & ((u32)(0x1 << ii))) { - ofdm_rate = true; - break; - } + max_min = 5; } - if (ofdm_rate) - max_min = 4; - else - max_min = 5; + priv->difs = C_SIFS_BG + 2 * priv->slot; } priv->eifs = C_EIFS; diff --git a/drivers/staging/vt6656/main_usb.c b/drivers/staging/vt6656/main_usb.c index 028f54b453d0..095b85567306 100644 --- a/drivers/staging/vt6656/main_usb.c +++ b/drivers/staging/vt6656/main_usb.c @@ -513,6 +513,9 @@ static int vnt_start(struct ieee80211_hw *hw) goto free_all; } + if (vnt_key_init_table(priv)) + goto free_all; + priv->int_interval = 1; /* bInterval is set to 1 */ vnt_int_start_interrupt(priv); @@ -634,7 +637,6 @@ static int vnt_config(struct ieee80211_hw *hw, u32 changed) { struct vnt_private *priv = hw->priv; struct ieee80211_conf *conf = &hw->conf; - u8 bb_type; if (changed & IEEE80211_CONF_CHANGE_PS) { if (conf->flags & IEEE80211_CONF_PS) @@ -648,15 +650,9 @@ static int vnt_config(struct ieee80211_hw *hw, u32 changed) vnt_set_channel(priv, conf->chandef.chan->hw_value); if (conf->chandef.chan->band == NL80211_BAND_5GHZ) - bb_type = BB_TYPE_11A; + priv->bb_type = BB_TYPE_11A; else - bb_type = BB_TYPE_11G; - - if (priv->bb_type != bb_type) { - priv->bb_type = bb_type; - - vnt_set_bss_mode(priv); - } + priv->bb_type = BB_TYPE_11G; } if (changed & IEEE80211_CONF_CHANGE_POWER) { @@ -687,6 +683,7 @@ static void vnt_bss_info_changed(struct ieee80211_hw *hw, priv->basic_rates = conf->basic_rates; vnt_update_top_rates(priv); + vnt_set_bss_mode(priv); dev_dbg(&priv->usb->dev, "basic rates %x\n", conf->basic_rates); } @@ -715,6 +712,7 @@ static void vnt_bss_info_changed(struct ieee80211_hw *hw, priv->short_slot_time = false; vnt_set_short_slot_time(priv); + vnt_update_ifs(priv); vnt_set_vga_gain_offset(priv, priv->bb_vga[0]); vnt_update_pre_ed_threshold(priv, false); } @@ -846,7 +844,6 @@ static void vnt_sw_scan_start(struct ieee80211_hw *hw, { struct vnt_private *priv = hw->priv; - vnt_set_bss_mode(priv); /* Set max sensitivity*/ vnt_update_pre_ed_threshold(priv, true); } diff --git a/drivers/staging/vt6656/rxtx.c b/drivers/staging/vt6656/rxtx.c index 63413492e61d..a44abcce6fb4 100644 --- a/drivers/staging/vt6656/rxtx.c +++ b/drivers/staging/vt6656/rxtx.c @@ -114,7 +114,7 @@ static __le16 vnt_time_stamp_off(struct vnt_private *priv, u16 rate) } static u32 vnt_get_rsvtime(struct vnt_private *priv, u8 pkt_type, - u32 frame_length, u16 rate, int need_ack) + u32 frame_length, u16 rate, int need_ack) { u32 data_time, ack_time; @@ -135,30 +135,37 @@ static u32 vnt_get_rsvtime(struct vnt_private *priv, u8 pkt_type, } static __le16 vnt_rxtx_rsvtime_le16(struct vnt_private *priv, u8 pkt_type, - u32 frame_length, u16 rate, int need_ack) + u32 frame_length, u16 rate, int need_ack) { return cpu_to_le16((u16)vnt_get_rsvtime(priv, pkt_type, frame_length, rate, need_ack)); } -static __le16 vnt_get_rtscts_rsvtime_le(struct vnt_private *priv, - u8 rsv_type, u8 pkt_type, u32 frame_length, u16 current_rate) +static __le16 vnt_get_rtscts_rsvtime_le(struct vnt_private *priv, u8 rsv_type, + u8 pkt_type, u32 frame_length, + u16 current_rate) { u32 rrv_time, rts_time, cts_time, ack_time, data_time; - rrv_time = rts_time = cts_time = ack_time = data_time = 0; + rrv_time = 0; + rts_time = 0; + cts_time = 0; + ack_time = 0; data_time = vnt_get_frame_time(priv->preamble_type, pkt_type, frame_length, current_rate); if (rsv_type == 0) { - rts_time = vnt_get_frame_time(priv->preamble_type, - pkt_type, 20, priv->top_cck_basic_rate); - cts_time = ack_time = vnt_get_frame_time(priv->preamble_type, - pkt_type, 14, priv->top_cck_basic_rate); + rts_time = vnt_get_frame_time(priv->preamble_type, pkt_type, + 20, priv->top_cck_basic_rate); + ack_time = vnt_get_frame_time(priv->preamble_type, + pkt_type, 14, + priv->top_cck_basic_rate); + cts_time = ack_time; + } else if (rsv_type == 1) { - rts_time = vnt_get_frame_time(priv->preamble_type, - pkt_type, 20, priv->top_cck_basic_rate); + rts_time = vnt_get_frame_time(priv->preamble_type, pkt_type, + 20, priv->top_cck_basic_rate); cts_time = vnt_get_frame_time(priv->preamble_type, pkt_type, 14, priv->top_cck_basic_rate); ack_time = vnt_get_frame_time(priv->preamble_type, pkt_type, @@ -166,8 +173,11 @@ static __le16 vnt_get_rtscts_rsvtime_le(struct vnt_private *priv, } else if (rsv_type == 2) { rts_time = vnt_get_frame_time(priv->preamble_type, pkt_type, 20, priv->top_ofdm_basic_rate); - cts_time = ack_time = vnt_get_frame_time(priv->preamble_type, - pkt_type, 14, priv->top_ofdm_basic_rate); + ack_time = vnt_get_frame_time(priv->preamble_type, + pkt_type, 14, + priv->top_ofdm_basic_rate); + cts_time = ack_time; + } else if (rsv_type == 3) { cts_time = vnt_get_frame_time(priv->preamble_type, pkt_type, 14, priv->top_cck_basic_rate); @@ -184,18 +194,20 @@ static __le16 vnt_get_rtscts_rsvtime_le(struct vnt_private *priv, return cpu_to_le16((u16)rrv_time); } -static __le16 vnt_get_duration_le(struct vnt_private *priv, - u8 pkt_type, int need_ack) +static __le16 vnt_get_duration_le(struct vnt_private *priv, u8 pkt_type, + int need_ack) { u32 ack_time = 0; if (need_ack) { if (pkt_type == PK_TYPE_11B) ack_time = vnt_get_frame_time(priv->preamble_type, - pkt_type, 14, priv->top_cck_basic_rate); + pkt_type, 14, + priv->top_cck_basic_rate); else ack_time = vnt_get_frame_time(priv->preamble_type, - pkt_type, 14, priv->top_ofdm_basic_rate); + pkt_type, 14, + priv->top_ofdm_basic_rate); return cpu_to_le16((u16)(priv->sifs + ack_time)); } @@ -216,8 +228,8 @@ static __le16 vnt_get_rtscts_duration_le(struct vnt_usb_send_context *context, case RTSDUR_BA: case RTSDUR_BA_F0: case RTSDUR_BA_F1: - cts_time = vnt_get_frame_time(priv->preamble_type, - pkt_type, 14, priv->top_cck_basic_rate); + cts_time = vnt_get_frame_time(priv->preamble_type, pkt_type, + 14, priv->top_cck_basic_rate); dur_time = cts_time + 2 * priv->sifs + vnt_get_rsvtime(priv, pkt_type, frame_length, rate, need_ack); @@ -226,8 +238,8 @@ static __le16 vnt_get_rtscts_duration_le(struct vnt_usb_send_context *context, case RTSDUR_AA: case RTSDUR_AA_F0: case RTSDUR_AA_F1: - cts_time = vnt_get_frame_time(priv->preamble_type, - pkt_type, 14, priv->top_ofdm_basic_rate); + cts_time = vnt_get_frame_time(priv->preamble_type, pkt_type, + 14, priv->top_ofdm_basic_rate); dur_time = cts_time + 2 * priv->sifs + vnt_get_rsvtime(priv, pkt_type, frame_length, rate, need_ack); @@ -248,7 +260,7 @@ static __le16 vnt_get_rtscts_duration_le(struct vnt_usb_send_context *context, } static u16 vnt_mac_hdr_pos(struct vnt_usb_send_context *tx_context, - struct ieee80211_hdr *hdr) + struct ieee80211_hdr *hdr) { u8 *head = tx_context->data + offsetof(struct vnt_tx_buffer, fifo_head); u8 *hdr_pos = (u8 *)hdr; @@ -263,7 +275,6 @@ static u16 vnt_mac_hdr_pos(struct vnt_usb_send_context *tx_context, static u16 vnt_rxtx_datahead_g(struct vnt_usb_send_context *tx_context, struct vnt_tx_datahead_g *buf) { - struct vnt_private *priv = tx_context->priv; struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_context->skb->data; @@ -274,7 +285,7 @@ static u16 vnt_rxtx_datahead_g(struct vnt_usb_send_context *tx_context, /* Get SignalField,ServiceField,Length */ vnt_get_phy_field(priv, frame_len, rate, tx_context->pkt_type, &buf->a); vnt_get_phy_field(priv, frame_len, priv->top_cck_basic_rate, - PK_TYPE_11B, &buf->b); + PK_TYPE_11B, &buf->b); /* Get Duration and TimeStamp */ if (ieee80211_is_pspoll(hdr->frame_control)) { @@ -310,7 +321,7 @@ static u16 vnt_rxtx_datahead_g_fb(struct vnt_usb_send_context *tx_context, vnt_get_phy_field(priv, frame_len, rate, tx_context->pkt_type, &buf->a); vnt_get_phy_field(priv, frame_len, priv->top_cck_basic_rate, - PK_TYPE_11B, &buf->b); + PK_TYPE_11B, &buf->b); /* Get Duration and TimeStamp */ buf->duration_a = vnt_get_duration_le(priv, tx_context->pkt_type, @@ -387,7 +398,7 @@ static u16 vnt_rxtx_datahead_ab(struct vnt_usb_send_context *tx_context, } static int vnt_fill_ieee80211_rts(struct vnt_usb_send_context *tx_context, - struct ieee80211_rts *rts, __le16 duration) + struct ieee80211_rts *rts, __le16 duration) { struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_context->skb->data; @@ -499,8 +510,8 @@ static u16 vnt_rxtx_rts_a_fb_head(struct vnt_usb_send_context *tx_context, u16 current_rate = tx_context->tx_rate; u16 rts_frame_len = 20; - vnt_get_phy_field(priv, rts_frame_len, - priv->top_ofdm_basic_rate, tx_context->pkt_type, &buf->a); + vnt_get_phy_field(priv, rts_frame_len, priv->top_ofdm_basic_rate, + tx_context->pkt_type, &buf->a); buf->duration = vnt_get_rtscts_duration_le(tx_context, RTSDUR_AA, tx_context->pkt_type, @@ -683,11 +694,10 @@ static u16 vnt_rxtx_ab(struct vnt_usb_send_context *tx_context, } static u16 vnt_generate_tx_parameter(struct vnt_usb_send_context *tx_context, - struct vnt_tx_buffer *tx_buffer, - struct vnt_mic_hdr **mic_hdr, u32 need_mic, - bool need_rts) + struct vnt_tx_buffer *tx_buffer, + struct vnt_mic_hdr **mic_hdr, u32 need_mic, + bool need_rts) { - if (tx_context->pkt_type == PK_TYPE_11GB || tx_context->pkt_type == PK_TYPE_11GA) { if (need_rts) { @@ -712,8 +722,9 @@ static u16 vnt_generate_tx_parameter(struct vnt_usb_send_context *tx_context, } static void vnt_fill_txkey(struct vnt_usb_send_context *tx_context, - u8 *key_buffer, struct ieee80211_key_conf *tx_key, struct sk_buff *skb, - u16 payload_len, struct vnt_mic_hdr *mic_hdr) + u8 *key_buffer, struct ieee80211_key_conf *tx_key, + struct sk_buff *skb, u16 payload_len, + struct vnt_mic_hdr *mic_hdr) { struct ieee80211_hdr *hdr = tx_context->hdr; u64 pn64; @@ -774,14 +785,12 @@ static void vnt_fill_txkey(struct vnt_usb_send_context *tx_context, if (ieee80211_has_a4(hdr->frame_control)) ether_addr_copy(mic_hdr->addr4, hdr->addr4); - memcpy(key_buffer, tx_key->key, WLAN_KEY_LEN_CCMP); break; default: break; } - } int vnt_tx_packet(struct vnt_private *priv, struct sk_buff *skb) @@ -807,7 +816,7 @@ int vnt_tx_packet(struct vnt_private *priv, struct sk_buff *skb) current_rate = rate->hw_value; if (priv->current_rate != current_rate && - !(priv->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) { + !(priv->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) { priv->current_rate = current_rate; vnt_schedule_command(priv, WLAN_CMD_SETPOWER); } @@ -964,7 +973,7 @@ int vnt_tx_packet(struct vnt_private *priv, struct sk_buff *skb) tx_key = info->control.hw_key; if (tx_key->keylen > 0) vnt_fill_txkey(tx_context, tx_buffer_head->tx_key, - tx_key, skb, tx_body_size, mic_hdr); + tx_key, skb, tx_body_size, mic_hdr); } priv->seq_counter = (le16_to_cpu(hdr->seq_ctrl) & @@ -991,8 +1000,7 @@ int vnt_tx_packet(struct vnt_private *priv, struct sk_buff *skb) return 0; } -static int vnt_beacon_xmit(struct vnt_private *priv, - struct sk_buff *skb) +static int vnt_beacon_xmit(struct vnt_private *priv, struct sk_buff *skb) { struct vnt_beacon_buffer *beacon_buffer; struct vnt_tx_short_buf_head *short_head; @@ -1101,7 +1109,7 @@ int vnt_beacon_make(struct vnt_private *priv, struct ieee80211_vif *vif) } int vnt_beacon_enable(struct vnt_private *priv, struct ieee80211_vif *vif, - struct ieee80211_bss_conf *conf) + struct ieee80211_bss_conf *conf) { vnt_mac_reg_bits_off(priv, MAC_REG_TCR, TCR_AUTOBCNTX); diff --git a/drivers/staging/wilc1000/host_interface.c b/drivers/staging/wilc1000/host_interface.c index c3a8af081880..2568dfc15181 100644 --- a/drivers/staging/wilc1000/host_interface.c +++ b/drivers/staging/wilc1000/host_interface.c @@ -329,25 +329,53 @@ static void handle_set_channel(struct wilc_vif *vif, netdev_err(vif->ndev, "Failed to set channel\n"); } -static void handle_set_wfi_drv_handler(struct wilc_vif *vif, - struct drv_handler *hif_drv_handler) +static int handle_set_wfi_drv_handler(struct wilc_vif *vif, + struct drv_handler *hif_drv_handler) { int ret = 0; struct wid wid; + u8 *currbyte, *buffer; + struct host_if_drv *hif_drv = NULL; + + if (!vif->hif_drv) + return -EINVAL; + + if (!hif_drv_handler) + return -EINVAL; + + hif_drv = vif->hif_drv; + + buffer = kzalloc(DRV_HANDLER_SIZE, GFP_KERNEL); + if (!buffer) + return -ENOMEM; + + currbyte = buffer; + *currbyte = hif_drv->driver_handler_id & DRV_HANDLER_MASK; + currbyte++; + *currbyte = (u32)0 & DRV_HANDLER_MASK; + currbyte++; + *currbyte = (u32)0 & DRV_HANDLER_MASK; + currbyte++; + *currbyte = (u32)0 & DRV_HANDLER_MASK; + currbyte++; + *currbyte = (hif_drv_handler->name | (hif_drv_handler->mode << 1)); wid.id = (u16)WID_SET_DRV_HANDLER; wid.type = WID_STR; - wid.val = (s8 *)hif_drv_handler; - wid.size = sizeof(*hif_drv_handler); + wid.val = (s8 *)buffer; + wid.size = DRV_HANDLER_SIZE; ret = wilc_send_config_pkt(vif, SET_CFG, &wid, 1, - hif_drv_handler->handler); - - if (!hif_drv_handler->handler) - complete(&hif_driver_comp); - - if (ret) + hif_drv->driver_handler_id); + if (ret) { netdev_err(vif->ndev, "Failed to set driver handler\n"); + complete(&hif_driver_comp); + kfree(buffer); + return ret; + } + complete(&hif_driver_comp); + kfree(buffer); + return 0; } static void handle_set_operation_mode(struct wilc_vif *vif, @@ -1188,7 +1216,7 @@ static s32 Handle_ConnectTimeout(struct wilc_vif *vif) result = wilc_send_config_pkt(vif, SET_CFG, &wid, 1, wilc_get_vif_idx(vif)); if (result) - netdev_err(vif->ndev, "Failed to send dissconect\n"); + netdev_err(vif->ndev, "Failed to send disconnect\n"); hif_drv->usr_conn_req.ssid_len = 0; kfree(hif_drv->usr_conn_req.ssid); @@ -2052,23 +2080,9 @@ static u32 WILC_HostIf_PackStaParam(u8 *pu8Buffer, pu8CurrByte += pstrStationParam->rates_len; *pu8CurrByte++ = pstrStationParam->ht_supported; - *pu8CurrByte++ = pstrStationParam->ht_capa_info & 0xFF; - *pu8CurrByte++ = (pstrStationParam->ht_capa_info >> 8) & 0xFF; - - *pu8CurrByte++ = pstrStationParam->ht_ampdu_params; - memcpy(pu8CurrByte, pstrStationParam->ht_supp_mcs_set, - WILC_SUPP_MCS_SET_SIZE); - pu8CurrByte += WILC_SUPP_MCS_SET_SIZE; - - *pu8CurrByte++ = pstrStationParam->ht_ext_params & 0xFF; - *pu8CurrByte++ = (pstrStationParam->ht_ext_params >> 8) & 0xFF; - - *pu8CurrByte++ = pstrStationParam->ht_tx_bf_cap & 0xFF; - *pu8CurrByte++ = (pstrStationParam->ht_tx_bf_cap >> 8) & 0xFF; - *pu8CurrByte++ = (pstrStationParam->ht_tx_bf_cap >> 16) & 0xFF; - *pu8CurrByte++ = (pstrStationParam->ht_tx_bf_cap >> 24) & 0xFF; - - *pu8CurrByte++ = pstrStationParam->ht_ante_sel; + memcpy(pu8CurrByte, &pstrStationParam->ht_capa, + sizeof(struct ieee80211_ht_cap)); + pu8CurrByte += sizeof(struct ieee80211_ht_cap); *pu8CurrByte++ = pstrStationParam->flags_mask & 0xFF; *pu8CurrByte++ = (pstrStationParam->flags_mask >> 8) & 0xFF; @@ -2403,9 +2417,9 @@ static void Handle_SetMulticastFilter(struct wilc_vif *vif, pu8CurrByte = wid.val; *pu8CurrByte++ = (strHostIfSetMulti->enabled & 0xFF); - *pu8CurrByte++ = 0; - *pu8CurrByte++ = 0; - *pu8CurrByte++ = 0; + *pu8CurrByte++ = ((strHostIfSetMulti->enabled >> 8) & 0xFF); + *pu8CurrByte++ = ((strHostIfSetMulti->enabled >> 16) & 0xFF); + *pu8CurrByte++ = ((strHostIfSetMulti->enabled >> 24) & 0xFF); *pu8CurrByte++ = (strHostIfSetMulti->cnt & 0xFF); *pu8CurrByte++ = ((strHostIfSetMulti->cnt >> 8) & 0xFF); @@ -2463,6 +2477,7 @@ static void host_if_work(struct work_struct *work) { struct host_if_msg *msg; struct wilc *wilc; + int ret = 0; msg = container_of(work, struct host_if_msg, work); wilc = msg->vif->wilc; @@ -2568,7 +2583,7 @@ static void host_if_work(struct work_struct *work) break; case HOST_IF_MSG_SET_WFIDRV_HANDLER: - handle_set_wfi_drv_handler(msg->vif, &msg->body.drv); + ret = handle_set_wfi_drv_handler(msg->vif, &msg->body.drv); break; case HOST_IF_MSG_SET_OPERATION_MODE: @@ -2622,6 +2637,8 @@ static void host_if_work(struct work_struct *work) break; } free_msg: + if (ret) + netdev_err(msg->vif->ndev, "Host cmd %d failed\n", msg->id); kfree(msg); complete(&hif_thread_comp); } @@ -3099,7 +3116,8 @@ int wilc_set_mac_chnl_num(struct wilc_vif *vif, u8 channel) return 0; } -int wilc_set_wfi_drv_handler(struct wilc_vif *vif, int index, u8 mac_idx) +int wilc_set_wfi_drv_handler(struct wilc_vif *vif, int index, u8 mode, + u8 ifc_id) { int result = 0; struct host_if_msg msg; @@ -3107,7 +3125,8 @@ int wilc_set_wfi_drv_handler(struct wilc_vif *vif, int index, u8 mac_idx) memset(&msg, 0, sizeof(struct host_if_msg)); msg.id = HOST_IF_MSG_SET_WFIDRV_HANDLER; msg.body.drv.handler = index; - msg.body.drv.mac_idx = mac_idx; + msg.body.drv.mode = mode; + msg.body.drv.name = ifc_id; msg.vif = vif; result = wilc_enqueue_cmd(&msg); @@ -3330,6 +3349,7 @@ int wilc_init(struct net_device *dev, struct host_if_drv **hif_drv_handler) for (i = 0; i < wilc->vif_num; i++) if (dev == wilc->vif[i]->ndev) { wilc->vif[i]->hif_drv = hif_drv; + hif_drv->driver_handler_id = i + 1; break; } @@ -3403,7 +3423,7 @@ int wilc_deinit(struct wilc_vif *vif) del_timer_sync(&periodic_rssi); del_timer_sync(&hif_drv->remain_on_ch_timer); - wilc_set_wfi_drv_handler(vif, 0, 0); + wilc_set_wfi_drv_handler(vif, 0, 0, 0); wait_for_completion(&hif_driver_comp); if (hif_drv->usr_scan_req.scan_result) { diff --git a/drivers/staging/wilc1000/host_interface.h b/drivers/staging/wilc1000/host_interface.h index f36d3b5a0370..1ce5ead318c7 100644 --- a/drivers/staging/wilc1000/host_interface.h +++ b/drivers/staging/wilc1000/host_interface.h @@ -1,6 +1,6 @@ #ifndef HOST_INT_H #define HOST_INT_H - +#include <linux/ieee80211.h> #include "coreconfigurator.h" #define IP_ALEN 4 @@ -47,10 +47,11 @@ #define ETH_ALEN 6 #define PMKID_LEN 16 #define WILC_MAX_NUM_PMKIDS 16 -#define WILC_SUPP_MCS_SET_SIZE 16 #define WILC_ADD_STA_LENGTH 40 #define SCAN_EVENT_DONE_ABORTED #define NUM_CONCURRENT_IFC 2 +#define DRV_HANDLER_SIZE 5 +#define DRV_HANDLER_MASK 0x000000FF struct rf_info { u8 link_speed; @@ -217,7 +218,8 @@ struct user_conn_req { struct drv_handler { u32 handler; - u8 mac_idx; + u8 mode; + u8 name; }; struct op_mode { @@ -281,6 +283,7 @@ struct host_if_drv { struct timer_list remain_on_ch_timer; bool IFC_UP; + int driver_handler_id; }; struct add_sta_param { @@ -289,12 +292,7 @@ struct add_sta_param { u8 rates_len; const u8 *rates; bool ht_supported; - u16 ht_capa_info; - u8 ht_ampdu_params; - u8 ht_supp_mcs_set[16]; - u16 ht_ext_params; - u32 ht_tx_bf_cap; - u8 ht_ante_sel; + struct ieee80211_ht_cap ht_capa; u16 flags_mask; u16 flags_set; }; @@ -354,7 +352,8 @@ int wilc_remain_on_channel(struct wilc_vif *vif, u32 session_id, void *user_arg); int wilc_listen_state_expired(struct wilc_vif *vif, u32 session_id); int wilc_frame_register(struct wilc_vif *vif, u16 frame_type, bool reg); -int wilc_set_wfi_drv_handler(struct wilc_vif *vif, int index, u8 mac_idx); +int wilc_set_wfi_drv_handler(struct wilc_vif *vif, int index, u8 mode, + u8 ifc_id); int wilc_set_operation_mode(struct wilc_vif *vif, u32 mode); int wilc_get_statistics(struct wilc_vif *vif, struct rf_info *stats); void wilc_resolve_disconnect_aberration(struct wilc_vif *vif); diff --git a/drivers/staging/wilc1000/linux_wlan.c b/drivers/staging/wilc1000/linux_wlan.c index d6d803416be2..308708450830 100644 --- a/drivers/staging/wilc1000/linux_wlan.c +++ b/drivers/staging/wilc1000/linux_wlan.c @@ -858,34 +858,15 @@ static int wilc_mac_open(struct net_device *ndev) for (i = 0; i < wl->vif_num; i++) { if (ndev == wl->vif[i]->ndev) { - if (vif->iftype == AP_MODE) { - wilc_set_wfi_drv_handler(vif, - wilc_get_vif_idx(vif), - 0); - } else if (!wilc_wlan_get_num_conn_ifcs(wl)) { - wilc_set_wfi_drv_handler(vif, - wilc_get_vif_idx(vif), - wl->open_ifcs); - } else { - if (memcmp(wl->vif[i ^ 1]->bssid, - wl->vif[i ^ 1]->src_addr, 6)) - wilc_set_wfi_drv_handler(vif, - wilc_get_vif_idx(vif), - 0); - else - wilc_set_wfi_drv_handler(vif, - wilc_get_vif_idx(vif), - 1); - } + wilc_set_wfi_drv_handler(vif, wilc_get_vif_idx(vif), + vif->iftype, vif->ifc_id); wilc_set_operation_mode(vif, vif->iftype); - - wilc_get_mac_address(vif, mac_add); - netdev_dbg(ndev, "Mac address: %pM\n", mac_add); - memcpy(wl->vif[i]->src_addr, mac_add, ETH_ALEN); - break; } } + wilc_get_mac_address(vif, mac_add); + netdev_dbg(ndev, "Mac address: %pM\n", mac_add); + memcpy(wl->vif[i]->src_addr, mac_add, ETH_ALEN); memcpy(ndev->dev_addr, wl->vif[i]->src_addr, ETH_ALEN); @@ -1246,11 +1227,13 @@ int wilc_netdev_init(struct wilc **wilc, struct device *dev, int io_type, vif = netdev_priv(ndev); memset(vif, 0, sizeof(struct wilc_vif)); - if (i == 0) + if (i == 0) { strcpy(ndev->name, "wlan%d"); - else + vif->ifc_id = 1; + } else { strcpy(ndev->name, "p2p%d"); - + vif->ifc_id = 0; + } vif->wilc = *wilc; vif->ndev = ndev; wl->vif[i] = vif; diff --git a/drivers/staging/wilc1000/wilc_debugfs.c b/drivers/staging/wilc1000/wilc_debugfs.c index 7d32de930576..ce54864569c7 100644 --- a/drivers/staging/wilc1000/wilc_debugfs.c +++ b/drivers/staging/wilc1000/wilc_debugfs.c @@ -20,7 +20,7 @@ static struct dentry *wilc_dir; /* - * -------------------------------------------------------------------------------- + * ---------------------------------------------------------------------------- */ #define DEBUG BIT(0) #define INFO BIT(1) @@ -32,10 +32,11 @@ static atomic_t WILC_DEBUG_LEVEL = ATOMIC_INIT(ERR); EXPORT_SYMBOL_GPL(WILC_DEBUG_LEVEL); /* - * -------------------------------------------------------------------------------- + * ---------------------------------------------------------------------------- */ -static ssize_t wilc_debug_level_read(struct file *file, char __user *userbuf, size_t count, loff_t *ppos) +static ssize_t wilc_debug_level_read(struct file *file, char __user *userbuf, + size_t count, loff_t *ppos) { char buf[128]; int res = 0; @@ -44,13 +45,15 @@ static ssize_t wilc_debug_level_read(struct file *file, char __user *userbuf, si if (*ppos > 0) return 0; - res = scnprintf(buf, sizeof(buf), "Debug Level: %x\n", atomic_read(&WILC_DEBUG_LEVEL)); + res = scnprintf(buf, sizeof(buf), "Debug Level: %x\n", + atomic_read(&WILC_DEBUG_LEVEL)); return simple_read_from_buffer(userbuf, count, ppos, buf, res); } -static ssize_t wilc_debug_level_write(struct file *filp, const char __user *buf, - size_t count, loff_t *ppos) +static ssize_t wilc_debug_level_write(struct file *filp, + const char __user *buf, size_t count, + loff_t *ppos) { int flag = 0; int ret; @@ -60,7 +63,8 @@ static ssize_t wilc_debug_level_write(struct file *filp, const char __user *buf, return ret; if (flag > DBG_LEVEL_ALL) { - pr_info("%s, value (0x%08x) is out of range, stay previous flag (0x%08x)\n", __func__, flag, atomic_read(&WILC_DEBUG_LEVEL)); + pr_info("%s, value (0x%08x) is out of range, stay previous flag (0x%08x)\n", + __func__, flag, atomic_read(&WILC_DEBUG_LEVEL)); return -EINVAL; } @@ -75,7 +79,7 @@ static ssize_t wilc_debug_level_write(struct file *filp, const char __user *buf, } /* - * -------------------------------------------------------------------------------- + * ---------------------------------------------------------------------------- */ #define FOPS(_open, _read, _write, _poll) { \ @@ -94,7 +98,12 @@ struct wilc_debugfs_info_t { }; static struct wilc_debugfs_info_t debugfs_info[] = { - { "wilc_debug_level", 0666, (DEBUG | ERR), FOPS(NULL, wilc_debug_level_read, wilc_debug_level_write, NULL), }, + { + "wilc_debug_level", + 0666, + (DEBUG | ERR), + FOPS(NULL, wilc_debug_level_read, wilc_debug_level_write, NULL), + }, }; static int __init wilc_debugfs_init(void) @@ -122,4 +131,3 @@ static void __exit wilc_debugfs_remove(void) module_exit(wilc_debugfs_remove); #endif - diff --git a/drivers/staging/wilc1000/wilc_wfi_cfgoperations.c b/drivers/staging/wilc1000/wilc_wfi_cfgoperations.c index 44a12bdd6a46..68fd5b3b8b2d 100644 --- a/drivers/staging/wilc1000/wilc_wfi_cfgoperations.c +++ b/drivers/staging/wilc1000/wilc_wfi_cfgoperations.c @@ -84,7 +84,6 @@ static const struct wiphy_wowlan_support wowlan_support = { #define TCP_ACK_FILTER_LINK_SPEED_THRESH 54 #define DEFAULT_LINK_SPEED 72 - #define IS_MANAGMEMENT 0x100 #define IS_MANAGMEMENT_CALLBACK 0x080 #define IS_MGMT_STATUS_SUCCES 0x040 @@ -163,12 +162,12 @@ static struct ieee80211_supported_band WILC_WFI_band_2ghz = { .n_bitrates = ARRAY_SIZE(ieee80211_bitrates), }; - struct add_key_params { u8 key_idx; bool pairwise; u8 *mac_addr; }; + static struct add_key_params g_add_gtk_key_params; static struct wilc_wfi_key g_key_gtk_params; static struct add_key_params g_add_ptk_key_params; @@ -281,7 +280,6 @@ static void remove_network_from_shadow(unsigned long arg) unsigned long now = jiffies; int i, j; - for (i = 0; i < last_scanned_cnt; i++) { if (time_after(now, last_scanned_shadow[i].time_scan + (unsigned long)(SCAN_RESULT_EXPIRE))) { @@ -526,7 +524,6 @@ static void CfgConnectResult(enum conn_event enuConnDisconnEvent, memcpy(priv->au8AssociatedBss, pstrConnectInfo->bssid, ETH_ALEN); - for (i = 0; i < last_scanned_cnt; i++) { if (memcmp(last_scanned_shadow[i].bssid, pstrConnectInfo->bssid, @@ -626,7 +623,6 @@ static int scan(struct wiphy *wiphy, struct cfg80211_scan_request *request) return -ENOMEM; strHiddenNetwork.n_ssids = request->n_ssids; - for (i = 0; i < request->n_ssids; i++) { if (request->ssids[i].ssid_len != 0) { strHiddenNetwork.net_info[i].ssid = kmalloc(request->ssids[i].ssid_len, GFP_KERNEL); @@ -927,8 +923,6 @@ static int add_key(struct wiphy *wiphy, struct net_device *netdev, u8 key_index, priv->wilc_ptk[key_index]->seq = NULL; } - - if (!pairwise) { if (params->cipher == WLAN_CIPHER_SUITE_TKIP) u8gmode = ENCRYPT_ENABLED | WPA | TKIP; @@ -968,7 +962,6 @@ static int add_key(struct wiphy *wiphy, struct net_device *netdev, u8 key_index, else u8pmode = priv->wilc_groupkey | AES; - if (params->key_len > 16 && params->cipher == WLAN_CIPHER_SUITE_TKIP) { pu8TxMic = params->key + 24; pu8RxMic = params->key + 16; @@ -1153,7 +1146,6 @@ static int get_key(struct wiphy *wiphy, struct net_device *netdev, u8 key_index, priv = wiphy_priv(wiphy); - if (!pairwise) { key_params.key = priv->wilc_gtk[key_index]->key; key_params.cipher = priv->wilc_gtk[key_index]->cipher; @@ -1298,7 +1290,6 @@ static int set_pmksa(struct wiphy *wiphy, struct net_device *netdev, vif = netdev_priv(priv->dev); - for (i = 0; i < priv->pmkid_list.numpmkid; i++) { if (!memcmp(pmksa->bssid, priv->pmkid_list.pmkidlist[i].bssid, ETH_ALEN)) { @@ -1511,7 +1502,6 @@ void WILC_WFI_p2p_rx(struct net_device *dev, u8 *buff, u32 size) } } - if ((buff[P2P_PUB_ACTION_SUBTYPE] == GO_NEG_REQ || buff[P2P_PUB_ACTION_SUBTYPE] == GO_NEG_RSP) && (wilc_ie)) { cfg80211_rx_mgmt(priv->wdev, s32Freq, 0, buff, size - 7, 0); return; @@ -1533,7 +1523,6 @@ static void WILC_WFI_mgmt_tx_complete(void *priv, int status) { struct p2p_mgmt_data *pv_data = priv; - kfree(pv_data->buff); kfree(pv_data); } @@ -1653,7 +1642,6 @@ static int mgmt_tx(struct wiphy *wiphy, memcpy(mgmt_tx->buff, buf, len); mgmt_tx->size = len; - if (ieee80211_is_probe_resp(mgmt->frame_control)) { wilc_set_mac_chnl_num(vif, chan->hw_value); curr_channel = chan->hw_value; @@ -1832,7 +1820,6 @@ static int set_power_mgmt(struct wiphy *wiphy, struct net_device *dev, if (wilc_enable_ps) wilc_set_power_mgmt(vif, enabled, timeout); - return 0; } @@ -1887,7 +1874,7 @@ static int change_virtual_intf(struct wiphy *wiphy, struct net_device *dev, if (wl->initialized) { wilc_set_wfi_drv_handler(vif, wilc_get_vif_idx(vif), - 0); + 0, vif->ifc_id); wilc_set_operation_mode(vif, AP_MODE); wilc_set_power_mgmt(vif, 0, 0); } @@ -2003,14 +1990,7 @@ static int add_station(struct wiphy *wiphy, struct net_device *dev, strStaParams.ht_supported = false; } else { strStaParams.ht_supported = true; - strStaParams.ht_capa_info = params->ht_capa->cap_info; - strStaParams.ht_ampdu_params = params->ht_capa->ampdu_params_info; - memcpy(strStaParams.ht_supp_mcs_set, - ¶ms->ht_capa->mcs, - WILC_SUPP_MCS_SET_SIZE); - strStaParams.ht_ext_params = params->ht_capa->extended_ht_cap_info; - strStaParams.ht_tx_bf_cap = params->ht_capa->tx_BF_cap_info; - strStaParams.ht_ante_sel = params->ht_capa->antenna_selection_info; + strStaParams.ht_capa = *params->ht_capa; } strStaParams.flags_mask = params->sta_flags_mask; @@ -2075,14 +2055,7 @@ static int change_station(struct wiphy *wiphy, struct net_device *dev, strStaParams.ht_supported = false; } else { strStaParams.ht_supported = true; - strStaParams.ht_capa_info = params->ht_capa->cap_info; - strStaParams.ht_ampdu_params = params->ht_capa->ampdu_params_info; - memcpy(strStaParams.ht_supp_mcs_set, - ¶ms->ht_capa->mcs, - WILC_SUPP_MCS_SET_SIZE); - strStaParams.ht_ext_params = params->ht_capa->extended_ht_cap_info; - strStaParams.ht_tx_bf_cap = params->ht_capa->tx_BF_cap_info; - strStaParams.ht_ante_sel = params->ht_capa->antenna_selection_info; + strStaParams.ht_capa = *params->ht_capa; } strStaParams.flags_mask = params->sta_flags_mask; @@ -2108,7 +2081,6 @@ static struct wireless_dev *add_virtual_intf(struct wiphy *wiphy, priv = wiphy_priv(wiphy); vif = netdev_priv(priv->wdev->netdev); - if (type == NL80211_IFTYPE_MONITOR) { new_ifc = WILC_WFI_init_mon_interface(name, vif->ndev); if (new_ifc) { diff --git a/drivers/staging/wilc1000/wilc_wfi_netdevice.h b/drivers/staging/wilc1000/wilc_wfi_netdevice.h index d431673bc46c..c89bf4301096 100644 --- a/drivers/staging/wilc1000/wilc_wfi_netdevice.h +++ b/drivers/staging/wilc1000/wilc_wfi_netdevice.h @@ -158,6 +158,7 @@ struct wilc_vif { struct host_if_drv *hif_drv; struct net_device *ndev; u8 mode; + u8 ifc_id; }; struct wilc { diff --git a/drivers/staging/wilc1000/wilc_wlan_if.h b/drivers/staging/wilc1000/wilc_wlan_if.h index 439ac6f8d533..f4d60057a06e 100644 --- a/drivers/staging/wilc1000/wilc_wlan_if.h +++ b/drivers/staging/wilc1000/wilc_wlan_if.h @@ -845,7 +845,7 @@ typedef enum { WID_MODEL_NAME = 0x3027, /*Added for CAPI tool */ WID_MODEL_NUM = 0x3028, /*Added for CAPI tool */ WID_DEVICE_NAME = 0x3029, /*Added for CAPI tool */ - WID_SET_DRV_HANDLER = 0x3030, + WID_SET_DRV_HANDLER = 0x3079, /* NMAC String WID list */ WID_11N_P_ACTION_REQ = 0x3080, diff --git a/drivers/staging/wlan-ng/hfa384x.h b/drivers/staging/wlan-ng/hfa384x.h index 310e2c454590..018db2299d0c 100644 --- a/drivers/staging/wlan-ng/hfa384x.h +++ b/drivers/staging/wlan-ng/hfa384x.h @@ -353,12 +353,12 @@ /*-------------------------------------------------------------*/ /* Commonly used basic types */ struct hfa384x_bytestr { - u16 len; + __le16 len; u8 data[0]; } __packed; struct hfa384x_bytestr32 { - u16 len; + __le16 len; u8 data[32]; } __packed; @@ -399,8 +399,8 @@ struct hfa384x_caplevel { /*-- Configuration Record: HostScanRequest (data portion only) --*/ struct hfa384x_host_scan_request_data { - u16 channel_list; - u16 tx_rate; + __le16 channel_list; + __le16 tx_rate; struct hfa384x_bytestr32 ssid; } __packed; @@ -419,7 +419,7 @@ struct hfa384x_authenticate_station_data { /*-- Configuration Record: WPAData (data portion only) --*/ struct hfa384x_wpa_data { - u16 datalen; + __le16 datalen; u8 data[0]; /* max 80 */ } __packed; @@ -682,16 +682,16 @@ struct hfa384x_ch_info_result { /*-- Inquiry Frame, Diagnose: Host Scan Results & Subfields--*/ struct hfa384x_hscan_result_sub { - u16 chid; - u16 anl; - u16 sl; + __le16 chid; + __le16 anl; + __le16 sl; u8 bssid[WLAN_BSSID_LEN]; - u16 bcnint; - u16 capinfo; + __le16 bcnint; + __le16 capinfo; struct hfa384x_bytestr32 ssid; u8 supprates[10]; /* 802.11 info element */ u16 proberesp_rate; - u16 atim; + __le16 atim; } __packed; struct hfa384x_hscan_result { diff --git a/drivers/staging/wlan-ng/hfa384x_usb.c b/drivers/staging/wlan-ng/hfa384x_usb.c index a812e55ba1b0..d3d1958675ed 100644 --- a/drivers/staging/wlan-ng/hfa384x_usb.c +++ b/drivers/staging/wlan-ng/hfa384x_usb.c @@ -1840,15 +1840,15 @@ int hfa384x_drvr_flashdl_enable(struct hfa384x *hw) if (result) return result; - hw->bufinfo.page = le16_to_cpu(hw->bufinfo.page); - hw->bufinfo.offset = le16_to_cpu(hw->bufinfo.offset); - hw->bufinfo.len = le16_to_cpu(hw->bufinfo.len); + le16_to_cpus(&hw->bufinfo.page); + le16_to_cpus(&hw->bufinfo.offset); + le16_to_cpus(&hw->bufinfo.len); result = hfa384x_drvr_getconfig16(hw, HFA384x_RID_MAXLOADTIME, &hw->dltimeout); if (result) return result; - hw->dltimeout = le16_to_cpu(hw->dltimeout); + le16_to_cpus(&hw->dltimeout); pr_debug("flashdl_enable\n"); @@ -2644,8 +2644,7 @@ int hfa384x_drvr_txframe(struct hfa384x *hw, struct sk_buff *skb, HFA384x_TX_MACPORT_SET(0) | HFA384x_TX_STRUCTYPE_SET(1) | HFA384x_TX_TXEX_SET(0) | HFA384x_TX_TXOK_SET(0); #endif - hw->txbuff.txfrm.desc.tx_control = - cpu_to_le16(hw->txbuff.txfrm.desc.tx_control); + cpu_to_le16s(&hw->txbuff.txfrm.desc.tx_control); /* copy the header over to the txdesc */ memcpy(&hw->txbuff.txfrm.desc.frame_control, p80211_hdr, @@ -3380,8 +3379,8 @@ static void hfa384x_usbin_rx(struct wlandevice *wlandev, struct sk_buff *skb) u16 fc; /* Byte order convert once up front. */ - usbin->rxfrm.desc.status = le16_to_cpu(usbin->rxfrm.desc.status); - usbin->rxfrm.desc.time = le32_to_cpu(usbin->rxfrm.desc.time); + le16_to_cpus(&usbin->rxfrm.desc.status); + le32_to_cpus(&usbin->rxfrm.desc.time); /* Now handle frame based on port# */ switch (HFA384x_RXSTATUS_MACPORT_GET(usbin->rxfrm.desc.status)) { @@ -3576,8 +3575,7 @@ static void hfa384x_int_rxmonitor(struct wlandevice *wlandev, static void hfa384x_usbin_info(struct wlandevice *wlandev, union hfa384x_usbin *usbin) { - usbin->infofrm.info.framelen = - le16_to_cpu(usbin->infofrm.info.framelen); + le16_to_cpus(&usbin->infofrm.info.framelen); prism2sta_ev_info(wlandev, &usbin->infofrm.info); } diff --git a/drivers/staging/wlan-ng/prism2fw.c b/drivers/staging/wlan-ng/prism2fw.c index afd877fb4557..1a0c786c7616 100644 --- a/drivers/staging/wlan-ng/prism2fw.c +++ b/drivers/staging/wlan-ng/prism2fw.c @@ -617,28 +617,28 @@ static int mkpdrlist(struct pda *pda) HFA384x_PDR_NICID) { memcpy(&nicid, &pda->rec[pda->nrec]->data.nicid, sizeof(nicid)); - nicid.id = le16_to_cpu(nicid.id); - nicid.variant = le16_to_cpu(nicid.variant); - nicid.major = le16_to_cpu(nicid.major); - nicid.minor = le16_to_cpu(nicid.minor); + le16_to_cpus(&nicid.id); + le16_to_cpus(&nicid.variant); + le16_to_cpus(&nicid.major); + le16_to_cpus(&nicid.minor); } if (le16_to_cpu(pda->rec[pda->nrec]->code) == HFA384x_PDR_MFISUPRANGE) { memcpy(&rfid, &pda->rec[pda->nrec]->data.mfisuprange, sizeof(rfid)); - rfid.id = le16_to_cpu(rfid.id); - rfid.variant = le16_to_cpu(rfid.variant); - rfid.bottom = le16_to_cpu(rfid.bottom); - rfid.top = le16_to_cpu(rfid.top); + le16_to_cpus(&rfid.id); + le16_to_cpus(&rfid.variant); + le16_to_cpus(&rfid.bottom); + le16_to_cpus(&rfid.top); } if (le16_to_cpu(pda->rec[pda->nrec]->code) == HFA384x_PDR_CFISUPRANGE) { memcpy(&macid, &pda->rec[pda->nrec]->data.cfisuprange, sizeof(macid)); - macid.id = le16_to_cpu(macid.id); - macid.variant = le16_to_cpu(macid.variant); - macid.bottom = le16_to_cpu(macid.bottom); - macid.top = le16_to_cpu(macid.top); + le16_to_cpus(&macid.id); + le16_to_cpus(&macid.variant); + le16_to_cpus(&macid.bottom); + le16_to_cpus(&macid.top); } (pda->nrec)++; diff --git a/drivers/staging/wlan-ng/prism2mgmt.c b/drivers/staging/wlan-ng/prism2mgmt.c index e23a0d0e7b09..c4aa9e7e7003 100644 --- a/drivers/staging/wlan-ng/prism2mgmt.c +++ b/drivers/staging/wlan-ng/prism2mgmt.c @@ -170,7 +170,7 @@ int prism2mgmt_scan(struct wlandevice *wlandev, void *msgp) hw->ident_sta_fw.variant) > HFA384x_FIRMWARE_VERSION(1, 5, 0)) { if (msg->scantype.data != P80211ENUM_scantype_active) - word = cpu_to_le16(msg->maxchanneltime.data); + word = msg->maxchanneltime.data; else word = 0; @@ -213,7 +213,7 @@ int prism2mgmt_scan(struct wlandevice *wlandev, void *msgp) goto exit; } if (word == HFA384x_PORTSTATUS_DISABLED) { - u16 wordbuf[17]; + __le16 wordbuf[17]; result = hfa384x_drvr_setconfig16(hw, HFA384x_RID_CNFROAMINGMODE, diff --git a/drivers/staging/wlan-ng/prism2mib.c b/drivers/staging/wlan-ng/prism2mib.c index 28df1f3d6f4a..e41207d97309 100644 --- a/drivers/staging/wlan-ng/prism2mib.c +++ b/drivers/staging/wlan-ng/prism2mib.c @@ -774,7 +774,7 @@ void prism2mgmt_pstr2bytestr(struct hfa384x_bytestr *bytestr, void prism2mgmt_bytestr2pstr(struct hfa384x_bytestr *bytestr, struct p80211pstrd *pstr) { - pstr->len = (u8)(le16_to_cpu((u16)(bytestr->len))); + pstr->len = (u8)(le16_to_cpu(bytestr->len)); memcpy(pstr->data, bytestr->data, pstr->len); } diff --git a/drivers/staging/wlan-ng/prism2sta.c b/drivers/staging/wlan-ng/prism2sta.c index 9c2b4ef2de58..e16da34389cd 100644 --- a/drivers/staging/wlan-ng/prism2sta.c +++ b/drivers/staging/wlan-ng/prism2sta.c @@ -603,10 +603,10 @@ static int prism2sta_getcardinfo(struct wlandevice *wlandev) } /* get all the nic id fields in host byte order */ - hw->ident_nic.id = le16_to_cpu(hw->ident_nic.id); - hw->ident_nic.variant = le16_to_cpu(hw->ident_nic.variant); - hw->ident_nic.major = le16_to_cpu(hw->ident_nic.major); - hw->ident_nic.minor = le16_to_cpu(hw->ident_nic.minor); + le16_to_cpus(&hw->ident_nic.id); + le16_to_cpus(&hw->ident_nic.variant); + le16_to_cpus(&hw->ident_nic.major); + le16_to_cpus(&hw->ident_nic.minor); netdev_info(wlandev->netdev, "ident: nic h/w: id=0x%02x %d.%d.%d\n", hw->ident_nic.id, hw->ident_nic.major, @@ -622,10 +622,10 @@ static int prism2sta_getcardinfo(struct wlandevice *wlandev) } /* get all the private fw id fields in host byte order */ - hw->ident_pri_fw.id = le16_to_cpu(hw->ident_pri_fw.id); - hw->ident_pri_fw.variant = le16_to_cpu(hw->ident_pri_fw.variant); - hw->ident_pri_fw.major = le16_to_cpu(hw->ident_pri_fw.major); - hw->ident_pri_fw.minor = le16_to_cpu(hw->ident_pri_fw.minor); + le16_to_cpus(&hw->ident_pri_fw.id); + le16_to_cpus(&hw->ident_pri_fw.variant); + le16_to_cpus(&hw->ident_pri_fw.major); + le16_to_cpus(&hw->ident_pri_fw.minor); netdev_info(wlandev->netdev, "ident: pri f/w: id=0x%02x %d.%d.%d\n", hw->ident_pri_fw.id, hw->ident_pri_fw.major, @@ -648,10 +648,10 @@ static int prism2sta_getcardinfo(struct wlandevice *wlandev) } /* get all the station fw id fields in host byte order */ - hw->ident_sta_fw.id = le16_to_cpu(hw->ident_sta_fw.id); - hw->ident_sta_fw.variant = le16_to_cpu(hw->ident_sta_fw.variant); - hw->ident_sta_fw.major = le16_to_cpu(hw->ident_sta_fw.major); - hw->ident_sta_fw.minor = le16_to_cpu(hw->ident_sta_fw.minor); + le16_to_cpus(&hw->ident_sta_fw.id); + le16_to_cpus(&hw->ident_sta_fw.variant); + le16_to_cpus(&hw->ident_sta_fw.major); + le16_to_cpus(&hw->ident_sta_fw.minor); /* strip out the 'special' variant bits */ hw->mm_mods = hw->ident_sta_fw.variant & GENMASK(15, 14); @@ -683,11 +683,11 @@ static int prism2sta_getcardinfo(struct wlandevice *wlandev) /* get all the Compatibility range, modem interface supplier * fields in byte order */ - hw->cap_sup_mfi.role = le16_to_cpu(hw->cap_sup_mfi.role); - hw->cap_sup_mfi.id = le16_to_cpu(hw->cap_sup_mfi.id); - hw->cap_sup_mfi.variant = le16_to_cpu(hw->cap_sup_mfi.variant); - hw->cap_sup_mfi.bottom = le16_to_cpu(hw->cap_sup_mfi.bottom); - hw->cap_sup_mfi.top = le16_to_cpu(hw->cap_sup_mfi.top); + le16_to_cpus(&hw->cap_sup_mfi.role); + le16_to_cpus(&hw->cap_sup_mfi.id); + le16_to_cpus(&hw->cap_sup_mfi.variant); + le16_to_cpus(&hw->cap_sup_mfi.bottom); + le16_to_cpus(&hw->cap_sup_mfi.top); netdev_info(wlandev->netdev, "MFI:SUP:role=0x%02x:id=0x%02x:var=0x%02x:b/t=%d/%d\n", @@ -707,11 +707,11 @@ static int prism2sta_getcardinfo(struct wlandevice *wlandev) /* get all the Compatibility range, controller interface supplier * fields in byte order */ - hw->cap_sup_cfi.role = le16_to_cpu(hw->cap_sup_cfi.role); - hw->cap_sup_cfi.id = le16_to_cpu(hw->cap_sup_cfi.id); - hw->cap_sup_cfi.variant = le16_to_cpu(hw->cap_sup_cfi.variant); - hw->cap_sup_cfi.bottom = le16_to_cpu(hw->cap_sup_cfi.bottom); - hw->cap_sup_cfi.top = le16_to_cpu(hw->cap_sup_cfi.top); + le16_to_cpus(&hw->cap_sup_cfi.role); + le16_to_cpus(&hw->cap_sup_cfi.id); + le16_to_cpus(&hw->cap_sup_cfi.variant); + le16_to_cpus(&hw->cap_sup_cfi.bottom); + le16_to_cpus(&hw->cap_sup_cfi.top); netdev_info(wlandev->netdev, "CFI:SUP:role=0x%02x:id=0x%02x:var=0x%02x:b/t=%d/%d\n", @@ -731,11 +731,11 @@ static int prism2sta_getcardinfo(struct wlandevice *wlandev) /* get all the Compatibility range, primary firmware supplier * fields in byte order */ - hw->cap_sup_pri.role = le16_to_cpu(hw->cap_sup_pri.role); - hw->cap_sup_pri.id = le16_to_cpu(hw->cap_sup_pri.id); - hw->cap_sup_pri.variant = le16_to_cpu(hw->cap_sup_pri.variant); - hw->cap_sup_pri.bottom = le16_to_cpu(hw->cap_sup_pri.bottom); - hw->cap_sup_pri.top = le16_to_cpu(hw->cap_sup_pri.top); + le16_to_cpus(&hw->cap_sup_pri.role); + le16_to_cpus(&hw->cap_sup_pri.id); + le16_to_cpus(&hw->cap_sup_pri.variant); + le16_to_cpus(&hw->cap_sup_pri.bottom); + le16_to_cpus(&hw->cap_sup_pri.top); netdev_info(wlandev->netdev, "PRI:SUP:role=0x%02x:id=0x%02x:var=0x%02x:b/t=%d/%d\n", @@ -755,11 +755,11 @@ static int prism2sta_getcardinfo(struct wlandevice *wlandev) /* get all the Compatibility range, station firmware supplier * fields in byte order */ - hw->cap_sup_sta.role = le16_to_cpu(hw->cap_sup_sta.role); - hw->cap_sup_sta.id = le16_to_cpu(hw->cap_sup_sta.id); - hw->cap_sup_sta.variant = le16_to_cpu(hw->cap_sup_sta.variant); - hw->cap_sup_sta.bottom = le16_to_cpu(hw->cap_sup_sta.bottom); - hw->cap_sup_sta.top = le16_to_cpu(hw->cap_sup_sta.top); + le16_to_cpus(&hw->cap_sup_sta.role); + le16_to_cpus(&hw->cap_sup_sta.id); + le16_to_cpus(&hw->cap_sup_sta.variant); + le16_to_cpus(&hw->cap_sup_sta.bottom); + le16_to_cpus(&hw->cap_sup_sta.top); if (hw->cap_sup_sta.id == 0x04) { netdev_info(wlandev->netdev, @@ -787,11 +787,11 @@ static int prism2sta_getcardinfo(struct wlandevice *wlandev) /* get all the Compatibility range, primary f/w actor, CFI supplier * fields in byte order */ - hw->cap_act_pri_cfi.role = le16_to_cpu(hw->cap_act_pri_cfi.role); - hw->cap_act_pri_cfi.id = le16_to_cpu(hw->cap_act_pri_cfi.id); - hw->cap_act_pri_cfi.variant = le16_to_cpu(hw->cap_act_pri_cfi.variant); - hw->cap_act_pri_cfi.bottom = le16_to_cpu(hw->cap_act_pri_cfi.bottom); - hw->cap_act_pri_cfi.top = le16_to_cpu(hw->cap_act_pri_cfi.top); + le16_to_cpus(&hw->cap_act_pri_cfi.role); + le16_to_cpus(&hw->cap_act_pri_cfi.id); + le16_to_cpus(&hw->cap_act_pri_cfi.variant); + le16_to_cpus(&hw->cap_act_pri_cfi.bottom); + le16_to_cpus(&hw->cap_act_pri_cfi.top); netdev_info(wlandev->netdev, "PRI-CFI:ACT:role=0x%02x:id=0x%02x:var=0x%02x:b/t=%d/%d\n", @@ -811,11 +811,11 @@ static int prism2sta_getcardinfo(struct wlandevice *wlandev) /* get all the Compatibility range, station f/w actor, CFI supplier * fields in byte order */ - hw->cap_act_sta_cfi.role = le16_to_cpu(hw->cap_act_sta_cfi.role); - hw->cap_act_sta_cfi.id = le16_to_cpu(hw->cap_act_sta_cfi.id); - hw->cap_act_sta_cfi.variant = le16_to_cpu(hw->cap_act_sta_cfi.variant); - hw->cap_act_sta_cfi.bottom = le16_to_cpu(hw->cap_act_sta_cfi.bottom); - hw->cap_act_sta_cfi.top = le16_to_cpu(hw->cap_act_sta_cfi.top); + le16_to_cpus(&hw->cap_act_sta_cfi.role); + le16_to_cpus(&hw->cap_act_sta_cfi.id); + le16_to_cpus(&hw->cap_act_sta_cfi.variant); + le16_to_cpus(&hw->cap_act_sta_cfi.bottom); + le16_to_cpus(&hw->cap_act_sta_cfi.top); netdev_info(wlandev->netdev, "STA-CFI:ACT:role=0x%02x:id=0x%02x:var=0x%02x:b/t=%d/%d\n", @@ -835,11 +835,11 @@ static int prism2sta_getcardinfo(struct wlandevice *wlandev) /* get all the Compatibility range, station f/w actor, MFI supplier * fields in byte order */ - hw->cap_act_sta_mfi.role = le16_to_cpu(hw->cap_act_sta_mfi.role); - hw->cap_act_sta_mfi.id = le16_to_cpu(hw->cap_act_sta_mfi.id); - hw->cap_act_sta_mfi.variant = le16_to_cpu(hw->cap_act_sta_mfi.variant); - hw->cap_act_sta_mfi.bottom = le16_to_cpu(hw->cap_act_sta_mfi.bottom); - hw->cap_act_sta_mfi.top = le16_to_cpu(hw->cap_act_sta_mfi.top); + le16_to_cpus(&hw->cap_act_sta_mfi.role); + le16_to_cpus(&hw->cap_act_sta_mfi.id); + le16_to_cpus(&hw->cap_act_sta_mfi.variant); + le16_to_cpus(&hw->cap_act_sta_mfi.bottom); + le16_to_cpus(&hw->cap_act_sta_mfi.top); netdev_info(wlandev->netdev, "STA-MFI:ACT:role=0x%02x:id=0x%02x:var=0x%02x:b/t=%d/%d\n", @@ -1478,8 +1478,8 @@ static void prism2sta_inf_assocstatus(struct wlandevice *wlandev, int i; memcpy(&rec, &inf->info.assocstatus, sizeof(rec)); - rec.assocstatus = le16_to_cpu(rec.assocstatus); - rec.reason = le16_to_cpu(rec.reason); + le16_to_cpus(&rec.assocstatus); + le16_to_cpus(&rec.reason); /* * Find the address in the list of authenticated stations. @@ -1748,7 +1748,7 @@ static void prism2sta_inf_psusercnt(struct wlandevice *wlandev, void prism2sta_ev_info(struct wlandevice *wlandev, struct hfa384x_inf_frame *inf) { - inf->infotype = le16_to_cpu(inf->infotype); + le16_to_cpus(&inf->infotype); /* Dispatch */ switch (inf->infotype) { case HFA384x_IT_HANDOVERADDR: diff --git a/drivers/staging/xgifb/vb_table.h b/drivers/staging/xgifb/vb_table.h index f9f98e06e6d5..31dd52c513df 100644 --- a/drivers/staging/xgifb/vb_table.h +++ b/drivers/staging/xgifb/vb_table.h @@ -2448,15 +2448,15 @@ static const struct XGI301C_Tap4TimingStruct PALTap4Timing[] = { } }, {0xFFFF, { - 0x04, 0x1A, 0x04, 0x7E, 0x02, 0x1B, 0x05, 0x7E, /* ; C0-C7 */ - 0x01, 0x1A, 0x07, 0x7E, 0x00, 0x1A, 0x09, 0x7D, /* ; C8-CF */ - 0x7F, 0x19, 0x0B, 0x7D, 0x7E, 0x18, 0x0D, 0x7D, /* ; D0-D7 */ - 0x7D, 0x17, 0x10, 0x7C, 0x7D, 0x15, 0x12, 0x7C, /* ; D8-DF */ - 0x7C, 0x14, 0x14, 0x7C, 0x7C, 0x12, 0x15, 0x7D, /* ; E0-E7 */ - 0x7C, 0x10, 0x17, 0x7D, 0x7C, 0x0D, 0x18, 0x7F, /* ; EA-EF */ - 0x7D, 0x0B, 0x19, 0x7F, 0x7D, 0x09, 0x1A, 0x00, /* ; F0-F7 */ - 0x7D, 0x07, 0x1A, 0x02, 0x7E, 0x05, 0x1B, 0x02 /* ; F8-FF */ - } + 0x04, 0x1A, 0x04, 0x7E, 0x02, 0x1B, 0x05, 0x7E, /* ; C0-C7 */ + 0x01, 0x1A, 0x07, 0x7E, 0x00, 0x1A, 0x09, 0x7D, /* ; C8-CF */ + 0x7F, 0x19, 0x0B, 0x7D, 0x7E, 0x18, 0x0D, 0x7D, /* ; D0-D7 */ + 0x7D, 0x17, 0x10, 0x7C, 0x7D, 0x15, 0x12, 0x7C, /* ; D8-DF */ + 0x7C, 0x14, 0x14, 0x7C, 0x7C, 0x12, 0x15, 0x7D, /* ; E0-E7 */ + 0x7C, 0x10, 0x17, 0x7D, 0x7C, 0x0D, 0x18, 0x7F, /* ; EA-EF */ + 0x7D, 0x0B, 0x19, 0x7F, 0x7D, 0x09, 0x1A, 0x00, /* ; F0-F7 */ + 0x7D, 0x07, 0x1A, 0x02, 0x7E, 0x05, 0x1B, 0x02 /* ; F8-FF */ + } } }; diff --git a/drivers/tty/tty_io.c b/drivers/tty/tty_io.c index 0c150b5a9dd6..974b13d24401 100644 --- a/drivers/tty/tty_io.c +++ b/drivers/tty/tty_io.c @@ -325,6 +325,56 @@ static struct tty_driver *get_tty_driver(dev_t device, int *index) return NULL; } +/** + * tty_dev_name_to_number - return dev_t for device name + * @name: user space name of device under /dev + * @number: pointer to dev_t that this function will populate + * + * This function converts device names like ttyS0 or ttyUSB1 into dev_t + * like (4, 64) or (188, 1). If no corresponding driver is registered then + * the function returns -ENODEV. + * + * Locking: this acquires tty_mutex to protect the tty_drivers list from + * being modified while we are traversing it, and makes sure to + * release it before exiting. + */ +int tty_dev_name_to_number(const char *name, dev_t *number) +{ + struct tty_driver *p; + int ret; + int index, prefix_length = 0; + const char *str; + + for (str = name; *str && !isdigit(*str); str++) + ; + + if (!*str) + return -EINVAL; + + ret = kstrtoint(str, 10, &index); + if (ret) + return ret; + + prefix_length = str - name; + mutex_lock(&tty_mutex); + + list_for_each_entry(p, &tty_drivers, tty_drivers) + if (prefix_length == strlen(p->name) && strncmp(name, + p->name, prefix_length) == 0) { + if (index < p->num) { + *number = MKDEV(p->major, p->minor_start + index); + goto out; + } + } + + /* if here then driver wasn't found */ + ret = -ENODEV; +out: + mutex_unlock(&tty_mutex); + return ret; +} +EXPORT_SYMBOL_GPL(tty_dev_name_to_number); + #ifdef CONFIG_CONSOLE_POLL /** @@ -1083,7 +1133,10 @@ static struct tty_struct *tty_driver_lookup_tty(struct tty_driver *driver, struct tty_struct *tty; if (driver->ops->lookup) - tty = driver->ops->lookup(driver, file, idx); + if (!file) + tty = ERR_PTR(-EIO); + else + tty = driver->ops->lookup(driver, file, idx); else tty = driver->ttys[idx]; @@ -1715,7 +1768,7 @@ static struct tty_driver *tty_lookup_driver(dev_t device, struct file *filp, struct tty_driver *console_driver = console_device(index); if (console_driver) { driver = tty_driver_kref_get(console_driver); - if (driver) { + if (driver && filp) { /* Don't let /dev/console block */ filp->f_flags |= O_NONBLOCK; break; @@ -1748,7 +1801,7 @@ static struct tty_driver *tty_lookup_driver(dev_t device, struct file *filp, * - concurrent tty driver removal w/ lookup * - concurrent tty removal from driver table */ -static struct tty_struct *tty_open_by_driver(dev_t device, struct inode *inode, +struct tty_struct *tty_open_by_driver(dev_t device, struct inode *inode, struct file *filp) { struct tty_struct *tty; @@ -1793,6 +1846,7 @@ out: tty_driver_kref_put(driver); return tty; } +EXPORT_SYMBOL_GPL(tty_open_by_driver); /** * tty_open - open a tty device diff --git a/drivers/tty/tty_ldisc.c b/drivers/tty/tty_ldisc.c index e4603b09863a..f6ffe28b8a0d 100644 --- a/drivers/tty/tty_ldisc.c +++ b/drivers/tty/tty_ldisc.c @@ -605,6 +605,7 @@ err: tty_unlock(tty); return retval; } +EXPORT_SYMBOL_GPL(tty_set_ldisc); /** * tty_ldisc_kill - teardown ldisc @@ -797,6 +798,7 @@ void tty_ldisc_release(struct tty_struct *tty) tty_ldisc_debug(tty, "released\n"); } +EXPORT_SYMBOL_GPL(tty_ldisc_release); /** * tty_ldisc_init - ldisc setup for new tty diff --git a/include/linux/hid-sensor-hub.h b/include/linux/hid-sensor-hub.h index f32d7c392c1e..fc7aae64dcde 100644 --- a/include/linux/hid-sensor-hub.h +++ b/include/linux/hid-sensor-hub.h @@ -233,12 +233,14 @@ struct hid_sensor_common { atomic_t user_requested_state; int poll_interval; int raw_hystersis; + int latency_ms; struct iio_trigger *trigger; int timestamp_ns_scale; struct hid_sensor_hub_attribute_info poll; struct hid_sensor_hub_attribute_info report_state; struct hid_sensor_hub_attribute_info power_state; struct hid_sensor_hub_attribute_info sensitivity; + struct hid_sensor_hub_attribute_info report_latency; struct work_struct work; }; @@ -276,5 +278,8 @@ s32 hid_sensor_read_poll_value(struct hid_sensor_common *st); int64_t hid_sensor_convert_timestamp(struct hid_sensor_common *st, int64_t raw_value); +bool hid_sensor_batch_mode_supported(struct hid_sensor_common *st); +int hid_sensor_set_report_latency(struct hid_sensor_common *st, int latency); +int hid_sensor_get_report_latency(struct hid_sensor_common *st); #endif diff --git a/include/linux/hid-sensor-ids.h b/include/linux/hid-sensor-ids.h index 761f86242473..76033e0420a7 100644 --- a/include/linux/hid-sensor-ids.h +++ b/include/linux/hid-sensor-ids.h @@ -90,6 +90,8 @@ #define HID_USAGE_SENSOR_ORIENT_TILT_Z 0x200481 #define HID_USAGE_SENSOR_DEVICE_ORIENTATION 0x20008A +#define HID_USAGE_SENSOR_RELATIVE_ORIENTATION 0x20008E +#define HID_USAGE_SENSOR_GEOMAGNETIC_ORIENTATION 0x2000C1 #define HID_USAGE_SENSOR_ORIENT_ROTATION_MATRIX 0x200482 #define HID_USAGE_SENSOR_ORIENT_QUATERNION 0x200483 #define HID_USAGE_SENSOR_ORIENT_MAGN_FLUX 0x200484 @@ -150,6 +152,9 @@ #define HID_USAGE_SENSOR_PROP_REPORT_STATE 0x200316 #define HID_USAGE_SENSOR_PROY_POWER_STATE 0x200319 +/* Batch mode selectors */ +#define HID_USAGE_SENSOR_PROP_REPORT_LATENCY 0x20031B + /* Per data field properties */ #define HID_USAGE_SENSOR_DATA_MOD_NONE 0x00 #define HID_USAGE_SENSOR_DATA_MOD_CHANGE_SENSITIVITY_ABS 0x1000 diff --git a/include/linux/i2c/twl4030-madc.h b/include/linux/i2c/twl4030-madc.h deleted file mode 100644 index 1c0134dd3271..000000000000 --- a/include/linux/i2c/twl4030-madc.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * twl4030_madc.h - Header for TWL4030 MADC - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * J Keerthy <j-keerthy@ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA - * 02110-1301 USA - * - */ - -#ifndef _TWL4030_MADC_H -#define _TWL4030_MADC_H - -struct twl4030_madc_conversion_method { - u8 sel; - u8 avg; - u8 rbase; - u8 ctrl; -}; - -#define TWL4030_MADC_MAX_CHANNELS 16 - - -/* - * twl4030_madc_request- madc request packet for channel conversion - * @channels: 16 bit bitmap for individual channels - * @do_avgP: sample the input channel for 4 consecutive cycles - * @method: RT, SW1, SW2 - * @type: Polling or interrupt based method - * @raw: Return raw value, do not convert it - */ - -struct twl4030_madc_request { - unsigned long channels; - bool do_avg; - u16 method; - u16 type; - bool active; - bool result_pending; - bool raw; - int rbuf[TWL4030_MADC_MAX_CHANNELS]; - void (*func_cb)(int len, int channels, int *buf); -}; - -enum conversion_methods { - TWL4030_MADC_RT, - TWL4030_MADC_SW1, - TWL4030_MADC_SW2, - TWL4030_MADC_NUM_METHODS -}; - -enum sample_type { - TWL4030_MADC_WAIT, - TWL4030_MADC_IRQ_ONESHOT, - TWL4030_MADC_IRQ_REARM -}; - -#define TWL4030_MADC_CTRL1 0x00 -#define TWL4030_MADC_CTRL2 0x01 - -#define TWL4030_MADC_RTSELECT_LSB 0x02 -#define TWL4030_MADC_SW1SELECT_LSB 0x06 -#define TWL4030_MADC_SW2SELECT_LSB 0x0A - -#define TWL4030_MADC_RTAVERAGE_LSB 0x04 -#define TWL4030_MADC_SW1AVERAGE_LSB 0x08 -#define TWL4030_MADC_SW2AVERAGE_LSB 0x0C - -#define TWL4030_MADC_CTRL_SW1 0x12 -#define TWL4030_MADC_CTRL_SW2 0x13 - -#define TWL4030_MADC_RTCH0_LSB 0x17 -#define TWL4030_MADC_GPCH0_LSB 0x37 - -#define TWL4030_MADC_MADCON (1 << 0) /* MADC power on */ -#define TWL4030_MADC_BUSY (1 << 0) /* MADC busy */ -/* MADC conversion completion */ -#define TWL4030_MADC_EOC_SW (1 << 1) -/* MADC SWx start conversion */ -#define TWL4030_MADC_SW_START (1 << 5) -#define TWL4030_MADC_ADCIN0 (1 << 0) -#define TWL4030_MADC_ADCIN1 (1 << 1) -#define TWL4030_MADC_ADCIN2 (1 << 2) -#define TWL4030_MADC_ADCIN3 (1 << 3) -#define TWL4030_MADC_ADCIN4 (1 << 4) -#define TWL4030_MADC_ADCIN5 (1 << 5) -#define TWL4030_MADC_ADCIN6 (1 << 6) -#define TWL4030_MADC_ADCIN7 (1 << 7) -#define TWL4030_MADC_ADCIN8 (1 << 8) -#define TWL4030_MADC_ADCIN9 (1 << 9) -#define TWL4030_MADC_ADCIN10 (1 << 10) -#define TWL4030_MADC_ADCIN11 (1 << 11) -#define TWL4030_MADC_ADCIN12 (1 << 12) -#define TWL4030_MADC_ADCIN13 (1 << 13) -#define TWL4030_MADC_ADCIN14 (1 << 14) -#define TWL4030_MADC_ADCIN15 (1 << 15) - -/* Fixed channels */ -#define TWL4030_MADC_BTEMP TWL4030_MADC_ADCIN1 -#define TWL4030_MADC_VBUS TWL4030_MADC_ADCIN8 -#define TWL4030_MADC_VBKB TWL4030_MADC_ADCIN9 -#define TWL4030_MADC_ICHG TWL4030_MADC_ADCIN10 -#define TWL4030_MADC_VCHG TWL4030_MADC_ADCIN11 -#define TWL4030_MADC_VBAT TWL4030_MADC_ADCIN12 - -/* Step size and prescaler ratio */ -#define TEMP_STEP_SIZE 147 -#define TEMP_PSR_R 100 -#define CURR_STEP_SIZE 147 -#define CURR_PSR_R1 44 -#define CURR_PSR_R2 88 - -#define TWL4030_BCI_BCICTL1 0x23 -#define TWL4030_BCI_CGAIN 0x020 -#define TWL4030_BCI_MESBAT (1 << 1) -#define TWL4030_BCI_TYPEN (1 << 4) -#define TWL4030_BCI_ITHEN (1 << 3) - -#define REG_BCICTL2 0x024 -#define TWL4030_BCI_ITHSENS 0x007 - -/* Register and bits for GPBR1 register */ -#define TWL4030_REG_GPBR1 0x0c -#define TWL4030_GPBR1_MADC_HFCLK_EN (1 << 7) - -struct twl4030_madc_user_parms { - int channel; - int average; - int status; - u16 result; -}; - -int twl4030_madc_conversion(struct twl4030_madc_request *conv); -int twl4030_get_madc_conversion(int channel_no); -#endif diff --git a/include/linux/iio/iio.h b/include/linux/iio/iio.h index 3f5ea2e9a39e..d68bec297a45 100644 --- a/include/linux/iio/iio.h +++ b/include/linux/iio/iio.h @@ -352,10 +352,16 @@ unsigned int iio_get_time_res(const struct iio_dev *indio_dev); #define INDIO_BUFFER_SOFTWARE 0x04 #define INDIO_BUFFER_HARDWARE 0x08 #define INDIO_EVENT_TRIGGERED 0x10 +#define INDIO_HARDWARE_TRIGGERED 0x20 #define INDIO_ALL_BUFFER_MODES \ (INDIO_BUFFER_TRIGGERED | INDIO_BUFFER_HARDWARE | INDIO_BUFFER_SOFTWARE) +#define INDIO_ALL_TRIGGERED_MODES \ + (INDIO_BUFFER_TRIGGERED \ + | INDIO_EVENT_TRIGGERED \ + | INDIO_HARDWARE_TRIGGERED) + #define INDIO_MAX_RAW_ELEMENTS 4 struct iio_trigger; /* forward declaration */ diff --git a/include/linux/iio/timer/stm32-timer-trigger.h b/include/linux/iio/timer/stm32-timer-trigger.h index 55535aef2e6c..fa7d786ed99e 100644 --- a/include/linux/iio/timer/stm32-timer-trigger.h +++ b/include/linux/iio/timer/stm32-timer-trigger.h @@ -10,6 +10,7 @@ #define _STM32_TIMER_TRIGGER_H_ #define TIM1_TRGO "tim1_trgo" +#define TIM1_TRGO2 "tim1_trgo2" #define TIM1_CH1 "tim1_ch1" #define TIM1_CH2 "tim1_ch2" #define TIM1_CH3 "tim1_ch3" @@ -44,6 +45,7 @@ #define TIM7_TRGO "tim7_trgo" #define TIM8_TRGO "tim8_trgo" +#define TIM8_TRGO2 "tim8_trgo2" #define TIM8_CH1 "tim8_ch1" #define TIM8_CH2 "tim8_ch2" #define TIM8_CH3 "tim8_ch3" diff --git a/include/linux/mfd/stm32-timers.h b/include/linux/mfd/stm32-timers.h index 4a0abbc10ef6..ce7346e7f77a 100644 --- a/include/linux/mfd/stm32-timers.h +++ b/include/linux/mfd/stm32-timers.h @@ -34,6 +34,7 @@ #define TIM_CR1_DIR BIT(4) /* Counter Direction */ #define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */ #define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */ +#define TIM_CR2_MMS2 GENMASK(23, 20) /* Master mode selection 2 */ #define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */ #define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */ #define TIM_DIER_UIE BIT(0) /* Update interrupt */ @@ -60,6 +61,7 @@ #define MAX_TIM_PSC 0xFFFF #define TIM_CR2_MMS_SHIFT 4 +#define TIM_CR2_MMS2_SHIFT 20 #define TIM_SMCR_TS_SHIFT 4 #define TIM_BDTR_BKF_MASK 0xF #define TIM_BDTR_BKF_SHIFT 16 diff --git a/include/linux/tty.h b/include/linux/tty.h index eccb4ec30a8a..8156a9ee6fe6 100644 --- a/include/linux/tty.h +++ b/include/linux/tty.h @@ -400,6 +400,9 @@ extern struct tty_struct *get_current_tty(void); /* tty_io.c */ extern int __init tty_init(void); extern const char *tty_name(const struct tty_struct *tty); +extern struct tty_struct *tty_open_by_driver(dev_t device, struct inode *inode, + struct file *filp); +extern int tty_dev_name_to_number(const char *name, dev_t *number); #else static inline void tty_kref_put(struct tty_struct *tty) { } @@ -420,6 +423,11 @@ static inline int __init tty_init(void) { return 0; } static inline const char *tty_name(const struct tty_struct *tty) { return "(none)"; } +static inline struct tty_struct *tty_open_by_driver(dev_t device, + struct inode *inode, struct file *filp) +{ return NULL; } +static inline int tty_dev_name_to_number(const char *name, dev_t *number) +{ return -ENOTSUPP; } #endif extern struct ktermios tty_std_termios; diff --git a/include/uapi/linux/tty.h b/include/uapi/linux/tty.h index 01c4410352ff..e7855dffd592 100644 --- a/include/uapi/linux/tty.h +++ b/include/uapi/linux/tty.h @@ -35,5 +35,6 @@ #define N_TRACESINK 23 /* Trace data routing for MIPI P1149.7 */ #define N_TRACEROUTER 24 /* Trace data routing for MIPI P1149.7 */ #define N_NCI 25 /* NFC NCI UART */ +#define N_SPEAKUP 26 /* Speakup communication with synths */ #endif /* _UAPI_LINUX_TTY_H */ diff --git a/tools/iio/Makefile b/tools/iio/Makefile index 5446d625e17d..8f08e03a9a5e 100644 --- a/tools/iio/Makefile +++ b/tools/iio/Makefile @@ -1,5 +1,5 @@ CC = $(CROSS_COMPILE)gcc -CFLAGS += -Wall -g -D_GNU_SOURCE +CFLAGS += -Wall -g -D_GNU_SOURCE -D__EXPORTED_HEADERS__ -I../../include/uapi -I../../include BINDIR=usr/bin INSTALL_PROGRAM=install -m 755 -p diff --git a/tools/iio/iio_utils.h b/tools/iio/iio_utils.h index 780f2014f8fa..8b379da26e35 100644 --- a/tools/iio/iio_utils.h +++ b/tools/iio/iio_utils.h @@ -13,7 +13,7 @@ #include <stdint.h> /* Made up value to limit allocation sizes */ -#define IIO_MAX_NAME_LENGTH 30 +#define IIO_MAX_NAME_LENGTH 64 #define FORMAT_SCAN_ELEMENTS_DIR "%s/scan_elements" #define FORMAT_TYPE_FILE "%s_type" |