diff options
| author | LEROY Christophe <christophe.leroy@c-s.fr> | 2014-09-19 10:36:10 +0200 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2014-11-07 18:10:44 -0600 |
| commit | b0168eb97b8b02594f47ce44faf1502f79e540df (patch) | |
| tree | f71de298e449a605d41f04ed329c3fb069f5b8e4 | |
| parent | c9a803fb17bcec0e7527dc8fa055e56a9691abbb (diff) | |
powerpc/8xx: Don't restore regs to save them again.
There is not need to restore r10, r11 and cr registers at this end of ITLBmiss
handler as they are saved again to the same place in ITLBError handler we are
jumping to.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>
| -rw-r--r-- | arch/powerpc/kernel/head_8xx.S | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 46b47e1fe2a9..330d54418494 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -383,8 +383,7 @@ InstructionTLBMiss: lwz r3, 8(r0) #endif mfspr r10, SPRN_SPRG_SCRATCH2 - EXCEPTION_EPILOG_0 - b InstructionTLBError + b InstructionTLBError1 . = 0x1200 DataStoreTLBMiss: @@ -473,7 +472,10 @@ DataStoreTLBMiss: */ . = 0x1300 InstructionTLBError: - EXCEPTION_PROLOG + EXCEPTION_PROLOG_0 +InstructionTLBError1: + EXCEPTION_PROLOG_1 + EXCEPTION_PROLOG_2 mr r4,r12 mr r5,r9 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */ |