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authorJernej Skrabec <jernej.skrabec@siol.net>2020-01-25 00:20:10 +0100
committerChen-Yu Tsai <wens@csie.org>2020-03-12 00:24:39 +0800
commit3e9a1a8b7f811de3eb1445d72f68766b704ad17c (patch)
treeaea003701c083c8591a0554cb9e4dd05a00edae2
parentda180322582bd9db07f29e6d4a2d170afde0703f (diff)
arm64: dts: allwinner: a64: Fix display clock register range
Register range of display clocks is 0x10000, as it can be seen from DE2 documentation. Fix it. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Fixes: 2c796fc8f5dbd ("arm64: dts: allwinner: a64: add necessary device tree nodes for DE2 CCU") [wens@csie.org: added fixes tag] Signed-off-by: Chen-Yu Tsai <wens@csie.org>
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 990de71ca048..8571f4aeaeb8 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -264,7 +264,7 @@
display_clocks: clock@0 {
compatible = "allwinner,sun50i-a64-de2-clk";
- reg = <0x0 0x100000>;
+ reg = <0x0 0x10000>;
clocks = <&ccu CLK_BUS_DE>,
<&ccu CLK_DE>;
clock-names = "bus",