Documentation/devicetree/bindings/net/mediatek,star-emac.yaml


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/mediatek,star-emac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek STAR Ethernet MAC Controller

maintainers:
  - Bartosz Golaszewski <bgolaszewski@baylibre.com>

description:
  This Ethernet MAC is used on the MT8* family of SoCs from MediaTek.
  It's compliant with 802.3 standards and supports half- and full-duplex
  modes with flow-control as well as CRC offloading and VLAN tags.

allOf:
  - $ref: "ethernet-controller.yaml#"

properties:
  compatible:
    enum:
      - mediatek,mt8516-eth
      - mediatek,mt8518-eth
      - mediatek,mt8175-eth

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 3
    maxItems: 3

  clock-names:
    additionalItems: false
    items:
      - const: core
      - const: reg
      - const: trans

  mediatek,pericfg:
    $ref: /schemas/types.yaml#definitions/phandle
    description:
      Phandle to the device containing the PERICFG register range. This is used
      to control the MII mode.

  mdio:
    type: object
    description:
      Creates and registers an MDIO bus.

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names
  - mediatek,pericfg
  - phy-handle

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/mt8516-clk.h>

    ethernet: ethernet@11180000 {
        compatible = "mediatek,mt8516-eth";
        reg = <0x11180000 0x1000>;
        mediatek,pericfg = <&pericfg>;
        interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>;
        clocks = <&topckgen CLK_TOP_RG_ETH>,
                 <&topckgen CLK_TOP_66M_ETH>,
                 <&topckgen CLK_TOP_133M_ETH>;
        clock-names = "core", "reg", "trans";
        phy-handle = <&eth_phy>;
        phy-mode = "rmii";

        mdio {
            #address-cells = <1>;
            #size-cells = <0>;

            eth_phy: ethernet-phy@0 {
                reg = <0>;
            };
        };
    };