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path: root/drivers/spi/spi-dw-core.c
AgeCommit message (Expand)AuthorFilesLines
2023-03-11spi: Replace all spi->chip_select and spi->cs_gpiod references with function ...Amit Kumar Mahapatra via Alsa-devel1-1/+1
2023-01-27spi: dw: Fix wrong FIFO level setting for long xfersSerge Semin1-1/+1
2022-08-23spi: dw: Quite logging on deferred controller registrationSerge Semin1-1/+1
2022-07-13spi: dw: Add support for master mode selection for DWC SSI controllerNandhini Srikandan1-2/+3
2022-06-27spi: dw: Add deferred DMA-channels setup supportSerge Semin1-1/+4
2021-12-23spi: dw: Propagate firmware nodeAndy Shevchenko1-2/+2
2021-11-16spi: dw: Replace DWC_HSSI capability with IP-core version checkerSerge Semin1-4/+4
2021-11-16spi: dw: Introduce Synopsys IP-core versions interfaceSerge Semin1-0/+14
2021-11-16spi: dw: Convert to using the Bitfield access macrosSerge Semin1-12/+19
2021-11-16spi: dw: Put the driver entities naming in orderSerge Semin1-68/+70
2021-11-16spi: dw: Discard redundant DW SSI Frame Formats enumerationSerge Semin1-2/+2
2021-11-16spi: dw: Add a symbols namespace for the core moduleSerge Semin1-7/+7
2020-12-09spi: dw: Add support for 32-bits max xfer sizeDamien Le Moal1-7/+37
2020-11-25spi: dw: Fix spi registration for controllers overriding CSLars Povlsen1-1/+2
2020-11-17spi: dw: Set transfer handler before unmasking the IRQsSerge Semin1-2/+2
2020-10-08spi: dw: Add poll-based SPI transfers supportSerge Semin1-1/+39
2020-10-08spi: dw: Introduce max mem-ops SPI bus frequency settingSerge Semin1-1/+3
2020-10-08spi: dw: Add memory operations supportSerge Semin1-0/+301
2020-10-08spi: dw: Add generic DW SSI status-check methodSerge Semin1-9/+34
2020-10-08spi: dw: Explicitly de-assert CS on SPI transfer completionSerge Semin1-1/+1
2020-10-08spi: dw: Discard chip enabling on DMA setup errorSerge Semin1-3/+1
2020-10-08spi: dw: Unmask IRQs after enabling the chipSerge Semin1-2/+2
2020-10-08spi: dw: Perform IRQ setup in a dedicated functionSerge Semin1-18/+23
2020-10-08spi: dw: Refactor IRQ-based SPI transfer procedureSerge Semin1-9/+24
2020-10-08spi: dw: Refactor data IO procedureSerge Semin1-20/+17
2020-10-08spi: dw: Add DW SPI controller config structureSerge Semin1-12/+17
2020-10-08spi: dw: Update Rx sample delay in the config functionSerge Semin1-7/+6
2020-10-08spi: dw: Simplify the SPI bus speed config procedureSerge Semin1-13/+10
2020-10-08spi: dw: Update SPI bus speed in a config functionSerge Semin1-14/+14
2020-10-08spi: dw: Detach SPI device specific CR0 config methodSerge Semin1-13/+30
2020-10-08spi: dw: Add DWC SSI capabilitySerge Semin1-43/+37
2020-10-08spi: dw: Use an explicit set_cs assignmentSerge Semin1-4/+4
2020-09-29spi: spi-dw: Remove extraneous lockingSerge Semin1-12/+2
2020-09-29spi: dw: Add KeemBay Master capabilitySerge Semin1-0/+4
2020-09-29spi: dw: Convert CS-override to DW SPI capabilitiesSerge Semin1-2/+2
2020-09-29spi: dw: Discard DW SSI chip type storagesSerge Semin1-4/+2
2020-09-29spi: dw: Disable all IRQs when controller is unusedSerge Semin1-5/+5
2020-09-29spi: dw: Initialize n_bytes before the memory barrierSerge Semin1-1/+1
2020-09-08spi: dw: Add support for RX sample delay registerLars Povlsen1-0/+26
2020-05-30Merge remote-tracking branch 'spi/for-5.8' into spi-nextMark Brown1-0/+545
2020-05-29spi: dw: Use regset32 DebugFS method to create regdump fileSerge Semin1-60/+26
2020-05-29spi: dw: Add core suffix to the DW APB SSI core source fileSerge Semin1-0/+577
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