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path: root/drivers/cxl
AgeCommit message (Expand)AuthorFilesLines
2022-04-08cxl/pci: Drop shadowed variableDan Williams1-1/+0
2022-03-22cxl/core/port: Fix NULL but dereferenced coccicheck errorWan Jiabing1-1/+4
2022-02-17cxl/port: Hold port reference until decoder releaseDan Williams1-0/+4
2022-02-17cxl/port: Fix endpoint refcount leakDan Williams1-1/+2
2022-02-11cxl/core: Fix cxl_device_lock() class detectionDan Williams1-1/+1
2022-02-11cxl/core/port: Fix unregister_port() lock assertionDan Williams1-4/+20
2022-02-08cxl/regs: Fix size of CXL Capability Header RegisterJonathan Cameron1-2/+2
2022-02-08cxl/core/port: Handle invalid decodersDan Williams1-6/+30
2022-02-08cxl/core/port: Fix / relax decoder target enumerationDan Williams2-2/+5
2022-02-08cxl/core/port: Add endpoint decodersBen Widawsky4-16/+73
2022-02-08cxl/core: Move target_list out of base decoder attributesDan Williams1-1/+2
2022-02-08cxl/mem: Add the cxl_mem driverBen Widawsky9-5/+391
2022-02-08cxl/core/port: Add switch port enumerationDan Williams3-25/+438
2022-02-08cxl/memdev: Add numa_node attributeDan Williams1-0/+17
2022-02-08cxl/pci: Emit device serial numberDan Williams3-0/+14
2022-02-08cxl/pci: Implement wait for media activeBen Widawsky2-1/+50
2022-02-08cxl/pci: Retrieve CXL DVSEC memory infoBen Widawsky3-0/+146
2022-02-08cxl/pci: Cache device DVSEC offsetBen Widawsky2-0/+8
2022-02-08cxl/pci: Store component register base in cxldsBen Widawsky2-0/+14
2022-02-08cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams7-24/+24
2022-02-08cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky8-29/+108
2022-02-08cxl/core: Emit modalias for CXL devicesDan Williams1-9/+17
2022-02-08cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams8-49/+348
2022-02-08cxl/core: Generalize dport enumeration in the coreDan Williams6-110/+167
2022-02-08cxl/pci: Rename pci.h to cxlpci.hDan Williams4-3/+4
2022-02-08cxl/port: Up-level cxl_add_dport() locking requirements to the callerDan Williams2-2/+3
2022-02-08cxl/pmem: Introduce a find_cxl_root() helperDan Williams3-4/+60
2022-02-08cxl/port: Introduce cxl_port_to_pci_bus()Dan Williams3-5/+49
2022-02-08cxl/core/port: Use dedicated lock for decoder target listDan Williams2-7/+25
2022-02-08cxl: Prove CXL lockingDan Williams5-24/+130
2022-02-08cxl/core: Track port depthBen Widawsky2-0/+4
2022-02-08cxl/core/port: Make passthrough decoder init implicitBen Widawsky2-6/+8
2022-02-08cxl/core: Fix cxl_probe_component_regs() error messageDan Williams1-1/+1
2022-02-08cxl/core/port: Clarify decoder creationBen Widawsky3-11/+92
2022-02-08cxl/core: Convert decoder range to resourceBen Widawsky3-18/+35
2022-02-08cxl/decoder: Hide physical address information from non-rootDan Williams1-1/+1
2022-02-08cxl/core/port: Rename bus.c to port.cDan Williams2-1/+1
2022-02-08cxl: Introduce module_cxl_driverBen Widawsky1-0/+3
2022-02-08cxl/acpi: Map component registers for Root PortsBen Widawsky5-54/+80
2022-02-08cxl/pci: Add new DVSEC definitionsBen Widawsky1-0/+15
2022-02-08cxl: Flesh out register namesBen Widawsky2-16/+17
2022-02-08cxl/pci: Defer mailbox status checks to command timeoutsDan Williams1-101/+33
2022-02-08cxl/pci: Implement Interface Ready TimeoutBen Widawsky1-0/+35
2022-02-08cxl: Rename CXL_MEM to CXL_PCIBen Widawsky2-12/+13
2022-01-04cxl/core: Remove cxld_const_init in cxl_decoder_alloc()Nathan Chancellor2-5/+3
2021-11-15cxl/pmem: Fix module reload vs workqueue stateDan Williams3-3/+42
2021-11-15ACPI: NUMA: Add a node and memblk for each CFMWS not in SRATAlison Schofield1-1/+2
2021-11-15cxl/test: Mock acpi_table_parse_cedt()Dan Williams1-0/+2
2021-11-15cxl/acpi: Convert CFMWS parsing to ACPI sub-table helpersDan Williams2-147/+88
2021-11-15cxl/memdev: Remove unused cxlmd fieldIra Weiny1-2/+0
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