| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2017-11-14 | clk: hi3660: fix incorrect uart3 clock freqency | Zhong Kaihua | 1 | -1/+1 |
| 2017-06-19 | clk: hi3660: Set PPLL2 to 2880M | Zhong Kaihua | 1 | -2/+2 |
| 2017-06-19 | clk: hi3660: add clocks for video encoder, decoder and ISP | Chen Jun | 1 | -0/+40 |
| 2017-06-19 | clk: hi3660: fix wrong parent name of clk_mux_sysbus | Chen Jun | 1 | -2/+4 |
| 2017-06-19 | clk: Hi3660: register fixed_rate_clks with CLK_OF_DECLARE_DRIVER | Leo Yan | 1 | -10/+38 |
| 2017-01-09 | clk: hisilicon: Add clock driver for hi3660 SoC | Zhangfei Gao | 1 | -0/+567 |
 |
index : drm-misc | |
| Kernel DRM miscellaneous fixes and cross-tree changes | UNKNOWN |
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