summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Expand)AuthorFilesLines
2014-01-24MIPS: jz4740: update platform data for JZ4740 usb device controllerApelete Seketeli3-16/+26
2014-01-24MIPS: Kill CONFIG_MTD_PARTITIONSEunbong Song11-11/+0
2014-01-24MIPS: replace open-coded init_dspPaul Burton1-2/+1
2014-01-24MIPS: clean up resume declarationPaul Burton1-4/+12
2014-01-24MIPS: qi_lb60: add defconfig for Ben NanoNoteApelete Seketeli1-0/+188
2014-01-23MIPS: include linux/types.hQais Yousef1-0/+1
2014-01-23MIPS: sead3: use unflatten_and_copy_device_tree()Qais Yousef1-10/+1
2014-01-23MIPS: sead3: populate platform devices from device treeQais Yousef1-0/+7
2014-01-23MIPS: sead3: remove chosen nodeQais Yousef1-4/+0
2014-01-23MIPS: sead3: allow cmdline/env to change memory size using memsize paramQais Yousef3-0/+71
2014-01-23MIPS: BCM63XX: use linux/serial_bcm63xx.hFlorian Fainelli2-8/+1
2014-01-23MIPS: BCM63XX: move UART register definitionsFlorian Fainelli1-114/+1
2014-01-23MIPS: microMIPS: Remove unsupported compiler flag.Steven J. Hill1-1/+1
2014-01-23MIPS: OCTEON: Supply OCTEON+ USB nodes in internal device trees.David Daney4-0/+87
2014-01-23MIPS: Malta: use generic 8250 early consolePaul Burton4-75/+33
2014-01-23MIPS: Malta: mux & enable SERIRQ interruptPaul Burton2-0/+18
2014-01-23MIPS: Malta: initialise the RTC at bootPaul Burton1-0/+13
2014-01-23MIPS: sead3: remove unused cpu_khz variablePaul Burton1-4/+0
2014-01-23MIPS: Malta: remove unused cpu_khz variablePaul Burton1-3/+0
2014-01-23MIPS: cavium-octeon: export symbols needed by octeon-ethernetAaro Koskinen5-1/+16
2014-01-23MIPS: Fix build error seen in some configurationsGuenter Roeck1-1/+1
2014-01-23MIPS: cavium-octeon: fix early boot hang on EBH5600 boardAaro Koskinen1-3/+3
2014-01-23MIPS: cavium-octeon: fix out-of-bounds array accessAaro Koskinen1-1/+1
2014-01-23MIPS: JZ4740: reuse UART0 address macro for vmlinuz debug portAntony Pavlov1-2/+2
2014-01-22MIPS: improve checks for noncoherent DMAFelix Fietkau4-5/+16
2014-01-22MIPS: APRP: Code formatting clean-ups.Steven J. Hill9-320/+248
2014-01-22MIPS: APRP: Add support for Malta CMP platform.Deng-Cheng Zhu3-5/+35
2014-01-22MIPS: APRP: Add RTLX API support for CMP platforms.Deng-Cheng Zhu4-0/+123
2014-01-22MIPS: APRP: Split RTLX support into separate files.Deng-Cheng Zhu5-144/+195
2014-01-22MIPS: APRP: Add VPE loader support for CMP platforms.Deng-Cheng Zhu3-0/+186
2014-01-22MIPS: APRP: Split VPE loader into separate files.Deng-Cheng Zhu5-633/+660
2014-01-22MIPS: Clean up MIPS MT and CMP configuration options.Steven J. Hill2-40/+24
2014-01-22MIPS: kernel: cpu-probe: Add support for probing interAptiv coresLeonid Yegoshin1-0/+8
2014-01-22MIPS: Add support for interAptiv coresLeonid Yegoshin9-1/+12
2014-01-22MIPS: Add processor identifiers for the interAptiv processorsLeonid Yegoshin1-0/+2
2014-01-22MIPS: Add debugfs file to print the segmentation control registersSteven J. Hill2-0/+111
2014-01-22MIPS: Add support for FTLBsLeonid Yegoshin7-14/+155
2014-01-22MIPS: mm: Use the TLBINVF instruction to flush the VTLBLeonid Yegoshin1-6/+12
2014-01-22MIPS: Add function for flushing the TLB using the TLBINV instructionLeonid Yegoshin1-0/+13
2014-01-22MIPS: kernel: cpu-probe: Add support for probing proAptiv coresLeonid Yegoshin1-0/+8
2014-01-22MIPS: Add support for the proAptiv coresLeonid Yegoshin10-1/+13
2014-01-22MIPS: Add processor identifiers for the proAptiv processorsLeonid Yegoshin1-0/+2
2014-01-22MIPS: tlb: Set the EHINV bit for TLBINVF cores when invalidating the TLBLeonid Yegoshin1-1/+3
2014-01-22MIPS: features: Add initial support for Segmentation Control registersSteven J. Hill4-0/+36
2014-01-22MIPS: features: Add initial support for TLBINVF capable coresLeonid Yegoshin3-0/+9
2014-01-22MIPS: mm: Move UNIQUE_ENTRYHI macro to a header fileMarkos Chandras3-8/+3
2014-01-22MIPS: Add missing bits for Config registersLeonid Yegoshin1-2/+38
2014-01-22MIPS: MT: proc: Add support for printing VPE and TC idsMarkos Chandras1-1/+8
2014-01-22MIPS: Malta: Remove ttyS2 serial for CMP platformsLeonid Yegoshin1-0/+2
2014-01-22MIPS: Add printing of ES bit for Imgtec cores when cache error occurs.Leonid Yegoshin1-8/+21