diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c index e962821ae6a1..a766e2d90cd0 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c @@ -402,10 +402,21 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev) WREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2, data); break; } +} + +#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) - if (amdgpu_sriov_vf(adev)) - adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0, - regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; +static void nbio_v7_2_set_reg_remap(struct amdgpu_device *adev) +{ + if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) { + adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET; + adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET; + } else { + adev->rmmio_remap.reg_offset = + SOC15_REG_OFFSET(NBIO, 0, + regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2; + adev->rmmio_remap.bus_addr = 0; + } } const struct amdgpu_nbio_funcs nbio_v7_2_funcs = { @@ -429,4 +440,5 @@ const struct amdgpu_nbio_funcs nbio_v7_2_funcs = { .ih_control = nbio_v7_2_ih_control, .init_registers = nbio_v7_2_init_registers, .remap_hdp_registers = nbio_v7_2_remap_hdp_registers, + .set_reg_remap = nbio_v7_2_set_reg_remap, }; |