summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/exynos4.dtsi
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/boot/dts/exynos4.dtsi')
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi28
1 files changed, 14 insertions, 14 deletions
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 7863a21a7a64..1264cc431ff6 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -51,20 +51,6 @@
serial3 = &serial_3;
};
- gpu: gpu@13000000 {
- compatible = "samsung,exynos4210-mali", "arm,mali-400";
- reg = <0x13000000 0x10000>;
- /*
- * CLK_G3D is not actually bus clock but a IP-level clock.
- * The bus clock is not described in hardware manual.
- */
- clocks = <&clock CLK_G3D>,
- <&clock CLK_SCLK_G3D>;
- clock-names = "bus", "core";
- power-domains = <&pd_g3d>;
- status = "disabled";
- };
-
pmu: pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-parent = <&combiner>;
@@ -429,6 +415,20 @@
};
};
+ gpu: gpu@13000000 {
+ compatible = "samsung,exynos4210-mali", "arm,mali-400";
+ reg = <0x13000000 0x10000>;
+ /*
+ * CLK_G3D is not actually bus clock but a IP-level clock.
+ * The bus clock is not described in hardware manual.
+ */
+ clocks = <&clock CLK_G3D>,
+ <&clock CLK_SCLK_G3D>;
+ clock-names = "bus", "core";
+ power-domains = <&pd_g3d>;
+ status = "disabled";
+ };
+
i2s1: i2s@13960000 {
compatible = "samsung,s3c6410-i2s";
reg = <0x13960000 0x100>;