diff options
| author | Lin Huang <hl@rock-chips.com> | 2016-08-22 11:36:17 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2016-08-31 18:53:24 +0200 |
| commit | 97dd82682f1a6174698fbea149a04b4cabc58c4f (patch) | |
| tree | b8c6f2621de55f5f6cc500ac3489d82bc4562f54 /include/soc/rockchip | |
| parent | 29b4817d4018df78086157ea3a55c1d9424a7cfc (diff) | |
soc: rockchip: add header for ddr rate SIP interface
Add a header for the SIP interface defined to access the dcf controller
handling ddr rate changes on rk3399 (and most likely later socs).
This interface is shared between the clock driver as well as the
devfreq driver.
The SIP interface counterpart was merged from pull-request #684 [0]
into the upstream arm-trusted-firmware codebase.
[0] https://github.com/ARM-software/arm-trusted-firmware/pull/684
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'include/soc/rockchip')
| -rw-r--r-- | include/soc/rockchip/rockchip_sip.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/include/soc/rockchip/rockchip_sip.h b/include/soc/rockchip/rockchip_sip.h new file mode 100644 index 000000000000..7e28092c4d3d --- /dev/null +++ b/include/soc/rockchip/rockchip_sip.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd + * Author: Lin Huang <hl@rock-chips.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef __SOC_ROCKCHIP_SIP_H +#define __SOC_ROCKCHIP_SIP_H + +#define ROCKCHIP_SIP_DRAM_FREQ 0x82000008 +#define ROCKCHIP_SIP_CONFIG_DRAM_INIT 0x00 +#define ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE 0x01 +#define ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE 0x02 +#define ROCKCHIP_SIP_CONFIG_DRAM_SET_AT_SR 0x03 +#define ROCKCHIP_SIP_CONFIG_DRAM_GET_BW 0x04 +#define ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE 0x05 +#define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06 +#define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07 + +#endif |